Index: /trunk/INSTALL
===================================================================
--- /trunk/INSTALL	(revision 3)
+++ /trunk/INSTALL	(revision 3)
@@ -0,0 +1,39 @@
+--------------------------------------------------
+ install.txt
+--------------------------------------------------
+
+Follow this step to install the Morpheo Tools Chain
+
+1) Install GNU-Toolchain
+
+cf Tools-source/or1k_toolchain-build-instructions.txt
+
+2) Install newlib
+
+Now you can compile a software and use the libc and libm
+
+3) Install a simulator
+
+3a) systemC
+...
+
+3b) systemCASS
+
+4) Install soclib
+
+...
+
+5) Link
+
+This step consist at create all symbolik link
+ * Morpheo/Tools :
+   - newlib
+   - or1k
+   - soclib
+   - systemc (or systemcass)
+ * Morpheo/Software/*/src/sys/
+   - crt0.s           with $TOOLS/newlib/libgloss/or32/crt0.S
+ * Morpheo/IPs/systemC/shared/
+   - mapping_memory.h
+
+6) Enjoy
Index: /trunk/IPs/systemC/hierarchy_memory/Makefile
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/Makefile	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/Makefile	(revision 3)
@@ -0,0 +1,32 @@
+RM			= rm -f
+
+INCDIR			= -I. -I.. 				\
+			  -I$(IPS)  				\
+			  -I$(TOOLS)/systemc/include		\
+			  -I$(TOOLS)/soclib/include
+
+LIBDIR			= -L. -L.. 				\
+			  -L$(TOOLS)/or1k/lib 			\
+			  -L$(TOOLS)/soclib/lib-$(TARGET_ARCH)	\
+			  -L$(TOOLS)/systemc/lib-$(TARGET_ARCH)
+
+LIBS			= -lm -lsystemc -lsoclib -lbfd -liberty -ldl
+
+#DEBUG			= -DDEBUG
+
+CXX			= g++
+CXX_OPT			= -g3 -Wall $(INCDIR) $(LIBDIR) $(DEBUG)
+CXXFILT			= c++filt
+
+EXE			= $(patsubst %.cpp,%.x ,$(wildcard *.cpp) )
+HEADERS			= $(wildcard *.h)
+
+all			: $(EXE)
+			./$(EXE)
+
+%.x			: %.cpp $(HEADERS)
+			$(CXX) $(CXX_OPT) -o $@ $<  $(LIBS) 2>&1 | $(CXXFILT)
+#(TOOLS)/soclib/lib/loadexec.o
+
+clean			:
+			$(RM) $(EXE) *~ tty_*
Index: /trunk/IPs/systemC/hierarchy_memory/cache/Makefile
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/Makefile	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/Makefile	(revision 3)
@@ -0,0 +1,18 @@
+INCLUDE			= -I../../../
+# DEBUG			= -DDEBUG
+DEBUG			=
+CXX			= g++
+CXX_OPT			= -g3 -Wall -Werror -ansi $(INCLUDE) $(DEBUG)
+RM			= rm -f
+
+EXE			= $(patsubst %.cpp,%.x ,$(wildcard *.cpp) )
+HEADERS			= $(wildcard *.h)
+
+all			: $(EXE)
+			./$(EXE)
+
+%.x			: %.cpp $(HEADERS)
+			$(CXX) $(CXX_OPT) -o $@ $<
+
+clean			:
+			$(RM) $(EXE) *~
Index: /trunk/IPs/systemC/hierarchy_memory/cache/access_port.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/access_port.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/access_port.h	(revision 3)
@@ -0,0 +1,39 @@
+#ifndef ACCESS_PORT_H
+#define ACCESS_PORT_H
+
+#include "address.h"
+#include "type_rsp_cache.h"
+#include <iostream>
+using namespace std;
+
+namespace hierarchy_memory          {
+namespace cache                     {
+namespace cache_multilevel          {
+namespace cache_onelevel            {
+
+  class access_port_t
+    {
+    public    : bool             valid;
+    public    : address_t        address;
+    public    : uint32_t         trdid;
+    public    : type_rsp_cache_t hit;
+    public    : uint32_t         num_associativity; // on hit  : update lru
+    public    : uint32_t         latence;           // on miss : wait
+
+      friend ostream& operator<< (ostream& output_stream, const access_port_t &x)
+      {
+	output_stream << x.valid             << " "
+		      << x.hit               << " "
+		      << x.address           << " "
+		      << x.trdid             << " "
+		      << x.num_associativity << " "
+		      << x.latence;
+
+	return output_stream;
+      }
+
+    };
+
+};};};};
+
+#endif //!ACCESS_PORT_H
Index: /trunk/IPs/systemC/hierarchy_memory/cache/address.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/address.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/address.h	(revision 3)
@@ -0,0 +1,33 @@
+#ifndef ADDRESS_H
+#define ADDRESS_H
+
+#include <iomanip>
+#include <iostream>
+using namespace std;
+
+namespace hierarchy_memory          {
+  namespace cache                     {
+    namespace cache_multilevel          {
+      namespace cache_onelevel            {
+
+	class address_t
+	{
+	public    : uint32_t        tag;
+	public    : uint32_t        familly;
+	public    : uint32_t        offset;
+      
+	  friend ostream& operator<< (ostream& output_stream, const address_t &x)
+	  {
+	    output_stream << hex
+			  << setw(8) << setfill('0') << x.tag     << " "
+			  << setw(8) << setfill('0') << x.familly << " "
+			  << setw(8) << setfill('0') << x.offset 
+			  << dec;
+
+	    return output_stream;
+	  }
+	};
+
+      };};};};
+
+#endif //!ADDRESS_H
Index: /trunk/IPs/systemC/hierarchy_memory/cache/cache.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/cache.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/cache.h	(revision 3)
@@ -0,0 +1,239 @@
+#ifndef CACHE_H
+#define CACHE_H
+
+#include <stdint.h>
+#include <stdarg.h>
+#include <iostream>
+#include "cache_multilevel.h"
+#include "cache_onelevel.h"
+#include "type_req_cache.h"
+#include "type_rsp_cache.h"
+
+using namespace std;
+using namespace hierarchy_memory::cache::cache_multilevel;
+
+
+namespace hierarchy_memory          {
+  namespace cache                     {
+    typedef enum
+      {
+	INSTRUCTION_CACHE ,
+	DATA_CACHE 
+      } cache_t;
+
+    class param_t
+    {
+    public : const char                * name                  ;
+    public : uint32_t                    nb_entity             ;
+    public : cache_multilevel::param_t * param_icache_dedicated; // 1 each entity
+    public : cache_multilevel::param_t * param_dcache_dedicated; // 1 each entity
+    public : cache_multilevel::param_t   param_cache_shared    ; // 1 to all entity and I/D is unify
+  
+    public : param_t () {};
+
+    public : param_t (const char                * name                  ,
+		      uint32_t                    nb_entity             ,
+		      cache_multilevel::param_t * param_icache_dedicated,
+		      cache_multilevel::param_t * param_dcache_dedicated,
+		      cache_multilevel::param_t   param_cache_shared    
+		      ) :
+      name (name)
+      {
+	this->name                   = name                    ;
+	this->nb_entity              = nb_entity               ;
+	this->param_icache_dedicated = param_icache_dedicated  ;
+	this->param_dcache_dedicated = param_dcache_dedicated  ;
+	this->param_cache_shared     = param_cache_shared      ;
+      }
+    
+      friend ostream& operator<< (ostream& output_stream, const param_t & x)
+      {
+	output_stream << "<" << x.name << ">" << endl
+		      << "  * nb_entity : " << x.nb_entity << endl;
+
+	for (uint32_t it = 0; it < x.nb_entity; it ++)
+	  output_stream << x.param_icache_dedicated [it] << endl;
+	for (uint32_t it = 0; it < x.nb_entity; it ++)
+	  output_stream << x.param_dcache_dedicated [it] << endl;
+      
+	output_stream << x.param_cache_shared << endl;
+      
+	return output_stream;
+      }
+   
+    };//end param_t
+
+
+    class Cache
+    {
+    private  : char              * name            ;
+    protected: const uint32_t      nb_entity       ;
+    protected: uint32_t            nb_iport        ;
+    protected: uint32_t            nb_dport        ;
+
+    protected: Cache_Multilevel ** icache_dedicated;
+    protected: Cache_Multilevel ** dcache_dedicated;
+    protected: Cache_Multilevel  * cache_shared    ;
+
+      //*****[ constructor ]*****
+    public   : Cache (param_t param):
+      nb_entity (param.nb_entity)
+      {
+	uint32_t size_name = strlen(param.name)+1;
+	name               = new char [size_name];
+	strncpy(name,param.name,size_name);
+	
+	cache_shared     = new Cache_Multilevel (param.param_cache_shared);
+	icache_dedicated = new Cache_Multilevel * [nb_entity];
+	dcache_dedicated = new Cache_Multilevel * [nb_entity];
+      
+	nb_iport         = 0;
+	nb_dport         = 0;
+	for (uint32_t it = 0; it < nb_entity        ; it++)
+	  {
+	    icache_dedicated [it] = new Cache_Multilevel (param.param_icache_dedicated[it]); 
+	    dcache_dedicated [it] = new Cache_Multilevel (param.param_dcache_dedicated[it]); 
+	    nb_iport             += param.param_icache_dedicated[it].nb_port;
+	    nb_dport             += param.param_dcache_dedicated[it].nb_port;
+	  }
+
+	information();
+      };
+
+      //*****[ destructor ]*****
+    public   : ~Cache ()
+      {
+	for (uint32_t it = 0; it < nb_entity        ; it++)
+	  {
+	    delete icache_dedicated      [it];
+	    delete dcache_dedicated      [it];
+	  }
+	delete cache_shared          ;
+      };
+
+      //*****[ reset ]*****
+      void reset ()
+      {
+	cache_shared -> reset();
+	// Reset buffer of respons
+	for (uint32_t it = 0; it < nb_entity; it++)
+	  {
+	    icache_dedicated [it] ->reset();
+	    dcache_dedicated [it] ->reset();
+	  }
+      }//end reset
+
+      //*****[ transition ]*****
+      void transition()
+      {
+	cache_shared -> transition();
+	// Transition buffer of respons
+	for (uint32_t it = 0; it < nb_entity; it++)
+	  {
+	    icache_dedicated      [it] ->transition();
+	    dcache_dedicated      [it] ->transition();
+	  }
+      }//end transition
+
+      //*****[ range_port ]*****
+    public : uint32_t range_port (cache_t               type_cache, 
+				  uint32_t              num_entity)
+      {
+	uint32_t nb_port_dedicated = 0;
+      
+	if (type_cache == INSTRUCTION_CACHE)
+	  for (uint32_t it = 1; it < num_entity; it++ )
+	    nb_port_dedicated += icache_dedicated [it]->nb_port;
+	else
+	  {
+	    nb_port_dedicated = nb_iport;
+	    for (uint32_t it = 1; it < num_entity; it++)
+	      nb_port_dedicated += dcache_dedicated [it]->nb_port;
+	  }
+	return nb_port_dedicated;
+      }
+    
+      //*****[ latence ]*****
+      // Return the time to have the data
+      // latence is call on the same port in a single cycle, only the last access is save
+      // { NOTE } : type_cache = 0 : icache, 1 : dcache
+    public : uint32_t latence (cache_t               type_cache, 
+			       uint32_t              num_entity, 
+			       uint32_t              num_port  , 
+			       uint32_t              address   , 
+			       uint32_t              trdid     , 
+			       type_req_cache_t      type      ,
+			       direction_req_cache_t dir    )
+      {
+	if (num_entity >= nb_entity)
+	  {
+	    cerr << "<Cache.latence> {ERROR} num_entity ("<< num_entity << ") can be >= nb_entity (" << nb_entity << ")" << endl;
+	    exit (1);
+	  }
+
+	Cache_Multilevel * cache;
+	if (type_cache == INSTRUCTION_CACHE)
+	  cache = icache_dedicated [num_entity];
+	else
+	  cache = dcache_dedicated [num_entity];
+      
+	if (num_port >= cache->nb_port)
+	  {
+	    cerr << "<Cache.latence> {ERROR} num_port ("<< num_port << ") can be >= nb_port (" << cache->nb_port << ")" << endl;
+	    exit (1);
+	  }
+	// Make a access with this level "dedicated"
+
+	access_t access_dedicated = cache->access(num_port,address,trdid,type,dir);
+ 
+	// cout << "access_dedicated         : " << access_dedicated << endl;
+
+	if (access_dedicated.hit == MISS)
+	  {
+	    // Make a access with this level "shared"
+	    access_t access_shared  = cache_shared->access(range_port (type_cache,num_entity)+num_port,address,trdid,type,dir);
+	    // cout << "access_shared            : " << access_shared    << endl;
+
+	    cache_shared->update_access (access_shared);
+
+	    access_dedicated.last_nb_level = cache->nb_level; // Update all cache
+	    access_dedicated.latence += access_shared.latence;
+
+	    // cout << "access_dedicated (after) : " << access_dedicated << endl;
+	  }
+      
+	cache->update_access (access_dedicated);
+	return access_dedicated.latence;
+      }
+
+      //*****[ information ]*****
+    public : void information (void)
+      {
+	cout << "<" << name << ">" << endl;
+
+	for (uint32_t it = 0; it < nb_entity; it ++)
+	  icache_dedicated [it]->information();
+	for (uint32_t it = 0; it < nb_entity; it ++)
+	  dcache_dedicated [it]->information();
+	
+	cache_shared->information();
+      }
+      
+
+      friend ostream& operator<< (ostream& output_stream, const Cache & x)
+      {
+	output_stream << "<" << x.name << ">" << endl;
+	  
+	for (uint32_t it = 0; it < x.nb_entity; it ++)
+	  output_stream << *x.icache_dedicated [it] << endl;
+	for (uint32_t it = 0; it < x.nb_entity; it ++)
+	  output_stream << *x.dcache_dedicated [it] << endl;
+      
+	output_stream << *x.cache_shared << endl;
+      
+	return output_stream;
+      }
+
+    };//end Cache
+  };};
+#endif //!CACHE_H
Index: /trunk/IPs/systemC/hierarchy_memory/cache/cache_multilevel.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/cache_multilevel.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/cache_multilevel.h	(revision 3)
@@ -0,0 +1,186 @@
+#ifndef CACHE_MULTILEVEL_H
+#define CACHE_MULTILEVEL_H
+
+#include <stdint.h>
+#include <stdarg.h>
+#include <iostream>
+#include "cache_onelevel.h"
+#include "type_req_cache.h"
+#include "type_rsp_cache.h"
+
+using namespace std;
+using namespace hierarchy_memory::cache::cache_multilevel::cache_onelevel;
+
+namespace hierarchy_memory          {
+  namespace cache                     {
+    namespace cache_multilevel          {
+
+      class param_t
+      {
+      public : const char    * name         ;
+      public : uint32_t        nb_level     ;
+      public : uint32_t        nb_port      ;
+      public : param_cache_t * param_cache  ;
+  
+      public : param_t () {};
+
+      public : param_t (const char    * name        ,
+			uint32_t        nb_level    ,
+			uint32_t        nb_port     ,
+			param_cache_t * param_cache ) :
+	name (name)
+	{
+	  //this->name          = name         ;
+	  this->nb_level      = nb_level     ;
+	  this->nb_port       = nb_port      ;
+	  this->param_cache   = param_cache  ;
+	}
+    
+	friend ostream& operator<< (ostream& output_stream, const param_t & x)
+	{
+	  output_stream << "<" << x.name   << "> "
+			<< x.nb_level << " " 
+			<< x.nb_port;
+
+	  for (uint32_t it = 0; it < x.nb_level; it ++)
+	    output_stream << endl << x.param_cache [it];
+	  return output_stream;
+	}
+    
+      };//end param_t
+
+      class access_t
+      {
+      public : uint32_t         num_port     ;
+      public : type_rsp_cache_t hit          ; // result of access
+      public : uint32_t         latence      ; // Latence of access
+      public : uint32_t         last_nb_level; // if access is not a hit : last level of cache before a error
+	
+      public : access_t (uint32_t         num_port     ,
+			 type_rsp_cache_t hit          ,
+			 uint32_t         latence      ,
+			 uint32_t         last_nb_level)
+	{
+	  this->num_port      = num_port     ;
+	  this->hit           = hit          ;
+	  this->latence       = latence      ;
+	  this->last_nb_level = last_nb_level;
+	}
+
+	friend ostream& operator<< (ostream& output_stream, const access_t & x)
+	{
+	  output_stream << "["
+			<< x.num_port << "] "  
+			<< x.hit      << " " 
+			<< x.latence  << " " 
+			<< x.last_nb_level;
+	  return output_stream;
+	}
+      };//access_t
+  
+      class Cache_Multilevel
+      {
+      private   : char            * name;
+      protected : Cache_OneLevel ** hierarchy_cache;
+      public    : const uint32_t    nb_level;
+      public    : const uint32_t    nb_port ;
+
+	//*****[ constructor ]*****
+      public : Cache_Multilevel (param_t param) :
+	nb_level (param.nb_level),
+	nb_port  (param.nb_port )
+	{
+	  uint32_t size_name = strlen(param.name)+1;
+	  name               = new char [size_name];
+	  strncpy(name,param.name,size_name);
+
+	  hierarchy_cache = new Cache_OneLevel * [nb_level];
+
+	  // Creation of Cache hierarchy
+	  for (uint32_t it = 0; it < nb_level; it ++)
+	    hierarchy_cache [it] = new Cache_OneLevel (cache_onelevel::param_t(param.nb_port          ,
+									       param.param_cache  [it]));
+	}
+      
+	//*****[ destructor ]*****
+      public : ~Cache_Multilevel ()
+	{
+	  for (uint32_t it = 0; it < nb_level; it ++)
+	    delete hierarchy_cache [it];
+	};
+	//*****[ reset ]*****
+      public : void reset ()
+	{
+	  for (uint32_t it = 0; it < nb_level; it ++)
+	    hierarchy_cache [it]->reset();
+	}
+
+	//*****[ transition ]*****
+      public : void transition ()
+	{
+	  for (uint32_t it = 0; it < nb_level; it ++)
+	    hierarchy_cache [it]->transition();
+	}
+
+	//*****[ access ]*****
+      public : access_t access (uint32_t num_port, uint32_t address, uint32_t trdid, type_req_cache_t type, direction_req_cache_t dir)
+	{
+	  uint32_t         time          = 0;
+	  uint32_t         last_nb_level = (nb_level==0)?0:(nb_level-1);
+	  type_rsp_cache_t hit           = MISS;
+
+	  for (uint32_t it_nb_level = 0; it_nb_level < nb_level; it_nb_level ++)
+	    {
+	      hit = hierarchy_cache[it_nb_level]->access(num_port,address,trdid,type,dir);
+	      time += hierarchy_cache [it_nb_level]->latence (num_port);
+
+	      if ( (hit == HIT_CACHE)        || 
+		   (hit == HIT_WRITE_BUFFER) || 
+		   (hit == HIT_BYPASS)       )
+		{
+		  last_nb_level = it_nb_level;
+		  break;
+		}
+	    }
+	  return access_t (num_port,hit,time,last_nb_level);
+	}
+
+	//*****[ update_access ]*****
+      public : uint32_t update_access (access_t cur_access)
+	{
+	  for (uint32_t it = 0; it < cur_access.last_nb_level; it ++)
+	      hierarchy_cache [it]->update_latence (cur_access.num_port,cur_access.latence);
+
+	  return cur_access.latence;
+	}
+
+	//*****[ latence ]*****
+	// Return the time to have the data
+	// latence is call on the same port in a single cycle, only the last access is save
+      public : uint32_t latence (uint32_t num_port, uint32_t address, uint32_t trdid, type_req_cache_t type, direction_req_cache_t dir)
+	{
+	  return update_access (access (num_port, address, trdid, type, dir));
+	}
+
+	//*****[ information ]*****
+      public : void information (void)
+	{
+	  cout << "<" << name << ">" << endl;
+	  for (uint32_t it = 0; it < nb_level; it ++)
+	    hierarchy_cache [it]->information();
+	}
+
+	friend ostream& operator<< (ostream& output_stream, const Cache_Multilevel & x)
+	{
+	  output_stream << "<" << x.name << ">" << endl;
+	  
+	  for (uint32_t it = 0; it < x.nb_level; it ++)
+	    output_stream << *x.hierarchy_cache [it] << endl;
+
+	  return output_stream;
+	}
+      };
+  
+    };};};
+#endif //!CACHE_MULTILEVEL_H
+
Index: /trunk/IPs/systemC/hierarchy_memory/cache/cache_onelevel.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/cache_onelevel.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/cache_onelevel.h	(revision 3)
@@ -0,0 +1,523 @@
+#ifndef CACHE_ONELEVEL_H
+#define CACHE_ONELEVEL_H
+
+#include <stdint.h>
+#include <math.h>
+#include <iostream>
+#include <iomanip>
+#include "../file/sort_file_dynamic.h"
+#include "type_req_cache.h"
+#include "tag.h"
+#include "address.h"
+#include "access_port.h"
+#include "write_buffer.h"
+
+using namespace std;
+using namespace hierarchy_memory::sort_file;
+using namespace hierarchy_memory::cache::cache_multilevel;
+
+namespace hierarchy_memory          {
+namespace cache                     {
+namespace cache_multilevel          {
+namespace cache_onelevel            {
+
+  class param_cache_t
+  {
+  public : const char *   name         ;
+  public : uint32_t nb_line      ;
+  public : uint32_t size_line    ;
+  public : uint32_t size_word    ;
+  public : uint32_t associativity;
+  public : uint32_t hit_latence  ;
+  public : uint32_t miss_penality;
+    
+  public : param_cache_t () {};
+
+  public : param_cache_t (const char   * name         ,
+			  uint32_t nb_line      ,
+			  uint32_t size_line    ,
+			  uint32_t size_word    ,
+			  uint32_t associativity,
+			  uint32_t hit_latence  ,
+			  uint32_t miss_penality
+			  ) :
+    name (name)
+    {
+      //this->name          = name         ;
+      this->nb_line       = nb_line      ;
+      this->size_line     = size_line    ;
+      this->size_word     = size_word    ;
+      this->associativity = associativity;
+      this->hit_latence   = hit_latence  ;
+      this->miss_penality = miss_penality;
+    }
+
+    friend ostream& operator<< (ostream& output_stream, const param_cache_t & x)
+    {
+      output_stream << "<" << x.name   << "> "
+		    << x.nb_line       << " "
+		    << x.size_line     << " "
+		    << x.size_word     << " "
+		    << x.associativity << " "
+		    << x.hit_latence   << " "
+		    << x.miss_penality;
+    
+      return output_stream;
+    }
+  };//end param_cache_t
+ 
+  class param_t
+  {
+  public : uint32_t      nb_port    ;
+  public : param_cache_t param_cache;
+    
+  public : param_t (uint32_t      nb_port    ,
+		    param_cache_t param_cache)
+    {
+      this->nb_port     = nb_port      ;
+      this->param_cache = param_cache  ;
+    }
+
+    friend ostream& operator<< (ostream& output_stream, const param_t & x)
+    {
+      output_stream << x.nb_port << " " 
+		    << x.param_cache;
+      return output_stream;
+    }
+
+  };//end param_t
+
+  class Cache_OneLevel
+  {
+  protected : const uint32_t  nb_port       ;
+  protected : const uint32_t  nb_line       ;
+  protected : const uint32_t  size_line     ;
+  protected : const uint32_t  size_word     ;
+  protected : const uint32_t  associativity ;
+  protected : const uint32_t  hit_latence   ;
+  protected : const uint32_t  miss_penality ;
+    
+  private   : char          *  name;
+  private   : tag_t         ** tag;
+  private   : access_port_t *  access_port;
+  private   : address_t        size_address;
+  private   : Sort_File_Dynamic<write_buffer_t> * write_buffer;
+
+    //*****[ constructor ]*****
+  public : Cache_OneLevel (param_t param):
+      nb_port       (param.nb_port                  ),
+      nb_line       (param.param_cache.nb_line      ),
+      size_line     (param.param_cache.size_line    ),
+      size_word     (param.param_cache.size_word    ),
+      associativity (param.param_cache.associativity),
+      hit_latence   (param.param_cache.hit_latence  ),
+      miss_penality (param.param_cache.miss_penality)
+      {
+	uint32_t size_name = strlen(param.param_cache.name)+1;
+	name               = new char [size_name];
+	strncpy(name,param.param_cache.name,size_name);
+
+	if ((nb_line * size_line * associativity) == 0)
+	  {
+	    cerr << "<" << name << ".{Cache_OneLevel}> all parameter must be greater that 0" << endl;
+	    cerr << " nb_line       : " << nb_line       << endl;
+	    cerr << " size_line     : " << size_line     << endl;
+	    cerr << " associativity : " << associativity << endl;
+	    exit(1);
+	  }
+	if ((nb_line % associativity) != 0)
+	  {
+	    cerr << "<" << name << ".{Cache_OneLevel}> nb_line must be a mutiple of associativity" << endl;
+	    cerr << "  * nb_line       : " << nb_line       << endl;
+	    cerr << "  * associativity : " << associativity << endl;
+	    exit(1);
+	  }
+
+	if ((double)nb_line    != ::pow(2,::log2(nb_line)))
+	  {
+	    cerr << "<" << name << ".{Cache_OneLevel}> nb_line must be a mutiple of 2^n" << endl;
+	    cerr << "  * nb_line       : " << nb_line       << endl;
+	    exit(1);
+	  }
+
+	if ((double)size_line != ::pow(2,::log2(size_line)))
+	  {
+	    cerr << "<" << name << ".{Cache_OneLevel}> size_line must be a mutiple of 2^n" << endl;
+	    cerr << "  * size_line     : " << size_line     << endl;
+	    exit(1);
+	  }
+
+	if ((double)size_word != ::pow(2,::log2(size_word)))
+	  {
+	    cerr << "<" << name << ".{Cache_OneLevel}> size_word must be a mutiple of 2^n" << endl;
+	    cerr << "  * size_word     : " << size_word     << endl;
+	    exit(1);
+	  }
+	
+	write_buffer= new Sort_File_Dynamic<write_buffer_t> (sort_file::param_t("write_buffer",5));
+	access_port = new access_port_t [nb_port];
+	tag         = new tag_t *       [nb_line/associativity];
+	for (uint32_t it = 0; it < nb_line/associativity; it ++)
+	  tag [it] = new tag_t [associativity];
+
+	size_address.offset  = (uint32_t) log2(size_line * size_word);
+	size_address.familly = (uint32_t) log2(nb_line/associativity);
+	size_address.tag     = 32 - size_address.familly - size_address.offset;
+     }
+      
+      //*****[ destructor ]*****
+    public : ~Cache_OneLevel ()
+      {
+// 	delete tag;
+// 	delete access_port;
+      };
+
+      //*****[ reset ]*****
+    public : void reset ()
+      {
+	for (uint32_t x = 0; x < nb_port; x ++)
+	  access_port[x].valid = false;
+
+	for (uint32_t x = 0; x < nb_line/associativity; x ++)
+	  for (uint32_t y = 0; y < associativity; y ++)
+	    {
+	      tag[x][y].valid      = false;
+	      tag[x][y].index_lru  = y;
+	    }
+	write_buffer->reset();
+      }
+
+      //*****[ transition ]*****
+    public : void transition ()
+    {
+	// scan all port - test if have a transaction
+	for (int32_t x = nb_port-1; x >= 0; x --)
+	  {
+	    if (access_port[x].valid == true)
+	      {
+		access_port[x].valid = false;
+		
+		// Update LRU
+		//  * hit  : now
+		//  * miss : after the return of next cache
+		
+		if (access_port[x].hit == HIT_CACHE)
+		  {// Hit
+		    update_lru(access_port[x].address.familly,access_port[x].num_associativity);
+		  }
+
+		if (access_port[x].hit == MISS)
+		  {// Miss
+		    // Write in write_buffer
+		    write_buffer->push(access_port[x].latence,write_buffer_t(access_port[x].address,access_port[x].trdid));
+		  }
+	      }
+	  }
+	
+	// Test if a write_buffer have the result
+	while ((write_buffer->empty() == false) && (write_buffer->read(0).delay == 0))
+	  {
+	    // Save in the cache
+	    write_buffer_t val         = write_buffer->pop();
+	    
+	    uint32_t num_tag           = val.address.tag;
+	    uint32_t num_familly       = val.address.familly;
+	    uint32_t num_associativity = index_victim(num_familly);
+	    
+	    tag [num_familly][num_associativity].valid    = true;
+	    tag [num_familly][num_associativity].address  = num_tag;
+	    tag [num_familly][num_associativity].trdid    = val.trdid;
+	    
+	    update_lru(num_familly,num_associativity);
+	  }
+
+	write_buffer->transition();
+      }
+      //*****[ update_lru ]*****
+    private : void update_lru (uint32_t familly, uint32_t num_associativity)
+      {
+	uint32_t current_lru = tag [familly][num_associativity].index_lru;
+	
+	for (uint32_t k = 0; k < associativity; k ++)
+	  if (tag [familly][k].index_lru < current_lru)
+	    tag [familly][k].index_lru ++;
+	tag [familly][num_associativity].index_lru = 0;
+      }
+      
+    //*****[ index_victim ]*****
+    // return the index of the nex victim
+  public : uint32_t index_victim (uint32_t familly)
+    {
+      uint32_t victim = 0;
+      while (tag [familly][victim].index_lru != (associativity-1))
+	{
+	  victim ++;
+	}
+
+      return victim;
+    }
+
+      //*****[ translate_address ]*****
+    private : address_t translate_address (uint32_t address)
+      {
+ 	address_t address_translated;
+	uint32_t  shift;
+
+	address_translated.offset  = (address & ((uint32_t)-1 >> (32-(size_address.offset          ))));
+	address                   -= address_translated.offset;
+	shift                      = size_address.offset;
+	address_translated.familly = (address & ((uint32_t)-1 >> (32-(size_address.familly + shift))))>>shift;
+	address                   -= address_translated.familly;
+	shift                     += size_address.familly;
+	address_translated.tag     = (address & ((uint32_t)-1 >> (32-(size_address.tag     + shift))))>>shift;
+
+	return address_translated;
+      }
+
+    //********************
+    //********************
+
+    //*****[ access ]*****
+    // Return hit (true) 
+      // uncache is to stocke the address on the cache
+  public : type_rsp_cache_t access (uint32_t nb_port, uint32_t address, uint32_t trdid, type_req_cache_t type, direction_req_cache_t dir)
+    {
+      switch (type)
+	{
+	case UNCACHED   : return access_uncached   (nb_port,address,trdid    ); break;
+	case INVALIDATE : return access_invalidate (nb_port,address,trdid    ); break;
+	case FLUSH      : return access_flush      (nb_port,address,trdid    ); break;
+	case PREFETCH   : // no difference with the simple read cached (have no add a prefetch cache)
+	case CACHED     : return access_cached     (nb_port,address,trdid,dir); break;
+	default         : cout << "<Cache_Onelevel.access> unkonow type : " << endl; exit(1); break;
+	}
+    }
+
+    // *****[ access_cached ]*****
+  public : type_rsp_cache_t access_cached (uint32_t nb_port, uint32_t address, uint32_t trdid, direction_req_cache_t dir)
+    {
+	address_t        address_translate  = translate_address(address);
+	uint32_t         num_associativity  = hit_cache        (trdid, address_translate);
+	uint32_t         num_port           = hit_access_port  (trdid, address_translate);
+	uint32_t         num_write_buffer   = hit_write_buffer (trdid, address_translate);
+	      	
+	if (num_port == this->nb_port)
+	  num_port = nb_port;
+
+	uint32_t         latence            ;
+	type_rsp_cache_t res                = MISS;
+
+	bool             is_in_cache        = (num_associativity != associativity);
+	bool             is_in_access_port  = (num_port != nb_port);
+	bool             is_in_write_buffer = false;
+
+	if (is_in_access_port == true)
+	  {
+	    res     = HIT_BYPASS;
+	    latence = access_port[num_port].latence; //already compute
+	  }
+	else
+	  if (is_in_cache == true)
+	    {	
+	      res     = HIT_CACHE;
+	      latence = 0; // Hit !!!
+	    }
+	  else
+	    {
+	      // Search in the write buffer, and test if have a miss
+	      if ( num_write_buffer == write_buffer->nb_slot_use())
+		  {
+		    res     = MISS;
+		    latence = miss_penality; // miss -> access at down of cache,  + respons at the up of cache
+		  }
+	      else
+		{
+		  res                = HIT_WRITE_BUFFER;
+		  is_in_write_buffer = true;
+		  latence            = write_buffer->read(num_write_buffer).delay;
+		}
+	    }
+
+	// access_port valid = there are a new request to update
+	//  -> no previous request in the same     cycle (hit in a access port)
+	//  -> no previous request in the previous cycle (hit in the write buffer)
+	
+ 	access_port[nb_port].valid             = ((is_in_access_port || is_in_write_buffer) == false);
+	access_port[nb_port].address           = address_translate;
+	access_port[nb_port].trdid             = trdid;
+	access_port[nb_port].hit               = res;
+	access_port[nb_port].num_associativity = num_associativity;
+	access_port[nb_port].latence           = latence;
+
+	return res;
+    }
+
+    // *****[ access_uncached ]*****
+  public : type_rsp_cache_t access_uncached (uint32_t nb_port, uint32_t address, uint32_t trdid)
+    {
+      access_port[nb_port].valid             = false;
+      access_port[nb_port].trdid             = trdid;
+      access_port[nb_port].hit               = MISS;
+      access_port[nb_port].latence           = miss_penality;
+      
+      return MISS;
+    }
+    // *****[ access_invalidate ]*****
+  public : type_rsp_cache_t access_invalidate (uint32_t nb_port, uint32_t address, uint32_t trdid)
+    {
+      cerr << "<" << name << ".{Cache_OneLevel}.access_invalidate> Not implemented" << endl;
+      exit (0);
+      return MISS;
+    }
+
+    // *****[ access_flush ]*****
+  public : type_rsp_cache_t access_flush (uint32_t nb_port, uint32_t address, uint32_t trdid)
+    {
+      cerr << "<" << name << ".{Cache_OneLevel}.access_flush> Not implemented" << endl;
+      exit (0);
+      return MISS;
+    }
+
+    //******************************
+    //******************************
+
+    //*****[ hit_write_buffer ]*****
+
+    // If a instruction is in the write_buffer, return the position
+    // else, return the number of elt in the write_buffer
+  public : uint32_t hit_write_buffer (uint32_t trdid, address_t address)
+    {
+	uint32_t num_write_buffer = 0;
+	// Scan the write_buffer
+	for (num_write_buffer = 0; num_write_buffer < write_buffer->nb_slot_use(); num_write_buffer ++)
+	  {
+	    slot_t<write_buffer_t> val = write_buffer->read(num_write_buffer);
+
+	    if ( (val.data.trdid           == trdid          ) &&
+		 (val.data.address.tag     == address.tag    ) &&
+		 (val.data.address.familly == address.familly))
+	      break;
+	  }
+	
+	return num_write_buffer;
+    }
+
+    //*****[ hit_access_port ]*****
+    // return the number of associativity if hit
+    // return nb_accosiativity if miss
+  public : uint32_t hit_cache (uint32_t trdid, address_t address)
+      {
+	uint32_t num_associativity;
+	for (num_associativity = 0; num_associativity < associativity; num_associativity ++)
+	  // Hit if :
+	  //  * in the line
+	  //  * in a way associative
+	  //  -> there are the same tag 
+	  //               the same trdid
+	  //               is valid
+	  if ( (tag [address.familly][num_associativity].address == address.tag) && 
+	       (tag [address.familly][num_associativity].valid   == true       ) &&
+	       (tag [address.familly][num_associativity].trdid   == trdid      ) )
+	      break;
+
+	return num_associativity;
+      }
+
+    //*****[ hit_access_port ]*****
+    // Return the number of port if hit
+    // Return nb_port if miss
+  public : uint32_t hit_access_port (uint32_t trdid, address_t address)
+      {
+	uint32_t it_num_port = 0;
+
+	// scan all port - test if have a transaction
+	for (it_num_port = 0; it_num_port < nb_port; it_num_port ++)
+	  if ( (access_port[it_num_port].valid           == true           ) &&
+	       (access_port[it_num_port].trdid           == trdid          ) &&
+	       (access_port[it_num_port].address.tag     == address.tag    ) &&
+	       (access_port[it_num_port].address.familly == address.familly))
+	    break;
+
+	return it_num_port;
+      }
+
+      //*****[ need_slot ]*****
+    public : uint32_t need_slot ()
+      {
+	uint32_t res = 0;
+	// scan all port - test if have a transaction
+	for (uint32_t x = 0; x < nb_port; x ++)
+	  if (access_port[x].valid == true)
+	    res ++;
+
+	return res;
+      }
+
+      //*****[ latence ]*****
+      // Return the time to have the data
+      // uncache is to stocke the address on the cache
+    public : uint32_t latence (uint32_t num_port)
+      {
+	uint32_t res = hit_latence + access_port[num_port].latence;
+
+	return res;
+      }
+
+      //*****[ update_latence ]*****
+      // Return the time to have the data
+      // uncache is to stocke the address on the cache
+  public : bool update_latence (uint32_t nb_port, uint32_t latence)
+      {
+	access_port[nb_port].latence = latence-hit_latence;
+	return access_port[nb_port].valid;
+      }
+
+    //*****[ information ]*****
+  public : void information (void)
+    {
+      cout << "<" << name << ">"                                                      << endl
+	   << "  * Information"                                                       << endl
+	   << "  * Capacity        : " << nb_line * size_line * size_word << " bytes" << endl
+	   << "    * Nb line       : " << nb_line                                     << endl
+	   << "    * Size line     : " << size_line                                   << endl
+	   << "    * Size word     : " << size_word                                   << endl
+	   << "    * Associativity : " << associativity                               << endl
+	   << "  * Timing          : "                                                << endl
+	   << "    * Hit  latence  : " << hit_latence                                 << endl
+	   << "    * Miss penality : " << miss_penality                               << endl
+	   << "    * Nb port       : " << nb_port                                     << endl
+	   << endl;
+    }
+    
+      friend ostream& operator<< (ostream& output_stream, const Cache_OneLevel & x)
+      {
+	output_stream << "<" << x.name << ">"                                                          << endl
+		      << "  * Capacity        : " << x.nb_line * x.size_line * x.size_word << " bytes" << endl
+		      << "    * Nb line       : " << x.nb_line                                         << endl
+		      << "    * Size line     : " << x.size_line                                       << endl
+		      << "    * Size word     : " << x.size_word                                       << endl
+		      << "    * Associativity : " << x.associativity                                   << endl
+	              << "  * Timing          : "                                                      << endl
+		      << "    * Hit  latence  : " << x.hit_latence                                     << endl
+		      << "    * Miss penality : " << x.miss_penality                                   << endl
+	              << "    * Nb port       : " << x.nb_port                                         << endl
+		      << endl;
+
+	output_stream << "  * Tag"                                                                     << endl;
+	for (uint32_t i = 0; i < x.nb_line / x.associativity; i ++)
+	  {
+	    for (uint32_t j = 0; j < x.associativity; j ++)
+		output_stream << x.tag [i][j] << " | ";
+	    output_stream << endl;
+	  }
+	
+	output_stream << endl;
+	output_stream << *x.write_buffer << endl;
+
+	return output_stream;
+      }
+
+    };
+};};};};
+#endif //!CACHE_ONELEVEL_H
+
Index: /trunk/IPs/systemC/hierarchy_memory/cache/main.cpp
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/main.cpp	(revision 3)
@@ -0,0 +1,760 @@
+#include "cache.h"
+#include "type_req_cache.h"
+#include <iostream>
+using namespace hierarchy_memory;
+using namespace hierarchy_memory::cache;
+using namespace std;
+
+//-----[ Routine de test ]---------------------------------------
+
+void test_ko (char * file, uint32_t line)
+{
+  cerr << "***** Test KO *****" << endl
+       << " - File : " << file << endl
+       << " - Line : " << line << endl;
+  exit (line);
+};
+
+void test_ok ()
+{
+  cout << "***** Test OK *****" << endl;
+  exit (0);
+};
+
+template <class T>
+void test(T exp1, T exp2, char * file, uint32_t line)
+{
+  if (exp1 != exp2)
+    {
+      cerr << "Expression is different : " << endl
+	   << " - exp1 : " << exp1 << endl
+	   << " - exp2 : " << exp2 << endl;
+
+      test_ko (file,line);
+    }
+};
+
+#define TEST(type,exp1,exp2) do { test<type> (exp1,exp2,__FILE__,__LINE__);} while(0)
+
+//-----[ main ]--------------------------------------------------
+int main ()
+{
+  cout << "<main> Begin" << endl;
+
+  //              name       , nb_line, size_line, size_word, associativity, hit_latence, miss_penality
+#define L1a_CACHE "L1a_CACHE",       4,         2,         4,             4,           1,             5
+#define L1b_CACHE "L1b_CACHE",       4,         4,         4,             2,           2,             4
+#define L1c_CACHE "L1c_CACHE",       4,         2,         4,             1,           1,             6
+#define L1d_CACHE "L1d_CACHE",       4,         2,         4,             4,           2,             3
+#define L2_CACHE  "L2_CACHE" ,       8,         4,         4,             2,           2,             8
+#define L3_CACHE  "L3_CACHE" ,      16,         8,         4,             1,           3,            15
+
+  cout << " * 3 caches" << endl;
+  cout << "   * L1 :  4 lines - 2 words - associtivity 4 ways" << endl;
+  cout << "   * L2 :  8 lines - 4 words - associtivity 2 ways" << endl;
+  cout << "   * L3 : 16 lines - 8 words - associtivity 1 ways" << endl;
+  
+  {
+    const uint32_t NB_CACHE = 2;
+    const uint32_t NB_PORT  = 3;
+
+    cout << "<main> Test de \"Cache_Multilevel\"" << endl;
+    
+    param_cache_t param_cache [NB_CACHE] = { param_cache_t (L1a_CACHE) ,
+					     param_cache_t (L2_CACHE) };
+    Cache_Multilevel my_cache (cache_multilevel::param_t("my_cache_multilevel",NB_CACHE, NB_PORT, param_cache));
+    
+    my_cache.reset();
+    
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  0] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+    
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
+      }
+    
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  1] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+    
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+    
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),15);
+      }
+    
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  2] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+    
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+    
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),14);
+      }
+    
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  3] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+    
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x200+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  4] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  5] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  6] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  7] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),9);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  8] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  9] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 10] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 11] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 12] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 13] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 14] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 15] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 16] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 17] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 18] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 19] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 20] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),1);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 21] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x200+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),1);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 22] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x300+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 23] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x400+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 24] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x500+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),(uint32_t)16);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [+40] **********" << endl;
+    cout << "**************************************" << endl;
+    for (uint32_t it = 24; it < 40; it ++)
+      {
+	cout << it << endl;
+	my_cache.transition();
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 40] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    cout << my_cache << endl;
+
+    cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
+
+    for (uint32_t i = 0; i < NB_PORT; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
+      }
+
+  }//end test Cache_Multilevel
+
+  cout << "-------------------------------------------------------------------------" << endl;
+  cout << "-------------------------------------------------------------------------" << endl;
+  cout << "-------------------------------------------------------------------------" << endl;
+
+  {
+    const uint32_t nb_entity = 2;
+    const uint32_t nb_iport  = 3;
+    const uint32_t nb_dport  = 2;
+   
+    cout << "<main> Test de \"Cache\"" << endl;
+
+    param_cache_t             param_cache_1a     [1] = { param_cache_t (L1a_CACHE) };
+    param_cache_t             param_cache_1b     [1] = { param_cache_t (L1b_CACHE) };
+    param_cache_t             param_cache_1c     [1] = { param_cache_t (L1c_CACHE) };
+    param_cache_t             param_cache_1d     [1] = { param_cache_t (L1d_CACHE) };
+    param_cache_t             param_cache_2      [2] = { param_cache_t (L2_CACHE) ,
+							 param_cache_t (L3_CACHE) };
+   
+    cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",1,nb_iport,param_cache_1a),
+								    cache_multilevel::param_t ("param_icache_dedicated[1]",1,nb_iport,param_cache_1b)};
+
+    cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",1,nb_dport,param_cache_1c),
+								    cache_multilevel::param_t ("param_dcache_dedicated[1]",1,nb_dport,param_cache_1d)};
+
+    cache_multilevel::param_t param_cache_shared   ("param_cache_shared", 2, nb_entity*(nb_iport+nb_dport), param_cache_2);
+
+    cache::param_t            param_cache          ("cache"                ,
+						    nb_entity              ,
+						    param_icache_dedicated ,
+						    param_dcache_dedicated ,
+						    param_cache_shared     );
+
+    Cache my_cache (param_cache);
+
+    ////cout << my_cache << endl;
+    my_cache.reset();
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  0] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+    
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),34);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  1] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    // cout << my_cache << endl;
+    
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x200+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),34);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  2] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+    
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x300+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),(uint32_t)34);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  3] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    cout << my_cache << endl;
+
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),31);
+      }
+
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_dport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (DATA_CACHE,1,i,address,0,CACHED,READ),30); // miss penality is 3 
+      }
+
+    //cout << my_cache << endl;
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  4] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    cout << my_cache << endl;
+
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,1,CACHED,READ),(uint32_t)34);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [+34] **********" << endl;
+    cout << "**************************************" << endl;
+    for (uint32_t it = 0; it < 30; it ++)
+      {
+	cout << it << endl;
+	my_cache.transition();
+	if (it == 0)
+	  cout << my_cache << endl;
+
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 34] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    cout << my_cache << endl;
+
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x200+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ), 2);
+      }
+
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_dport; i ++)
+      {
+	uint address = 0x200+i*4;
+	TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,0,CACHED,READ),20); // Miss L1-L2 Hit L3
+      }
+    
+    
+  }//end test Cache
+
+  cout << "-------------------------------------------------------------------------" << endl;
+  cout << "-------------------------------------------------------------------------" << endl;
+  cout << "-------------------------------------------------------------------------" << endl;
+
+
+  {
+    const uint32_t nb_entity = 1;
+    const uint32_t nb_iport  = 3;
+    const uint32_t nb_dport  = 2;
+   
+    cout << "<main> Test de \"Cache\"" << endl;
+
+    param_cache_t             param_cache_1a     [1] = { param_cache_t (L1a_CACHE) };
+    param_cache_t             param_cache_1b     [1] = { param_cache_t (L1b_CACHE) };
+   
+    cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",1,nb_iport,param_cache_1a)};
+
+    cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",1,nb_dport,param_cache_1b)};
+
+    cache_multilevel::param_t param_cache_shared   ("param_cache_shared",0, 0, NULL);
+
+    cache::param_t            param_cache          ("cache"                ,
+						    nb_entity              ,
+						    param_icache_dedicated ,
+						    param_dcache_dedicated ,
+						    param_cache_shared     );
+
+    Cache my_cache (param_cache);
+
+    cout << my_cache << endl;
+   
+    my_cache.reset();
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  0] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)6);
+      }
+
+    cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_dport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)6);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  1] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)5);
+      }
+
+
+  }
+
+  {
+    const uint32_t nb_entity = 1;
+    const uint32_t nb_iport  = 3;
+    const uint32_t nb_dport  = 2;
+   
+    cout << "<main> Test de \"Cache\"" << endl;
+
+    param_cache_t             param_cache_2      [1] = { param_cache_t (L2_CACHE)};
+
+    cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",0,nb_iport,NULL)};
+
+    cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",0,nb_dport,NULL)};
+
+    cache_multilevel::param_t param_cache_shared   ("param_cache_shared",1, nb_entity * (nb_iport + nb_dport), param_cache_2);
+
+    cache::param_t            param_cache          ("cache"                ,
+						    nb_entity              ,
+						    param_icache_dedicated ,
+						    param_dcache_dedicated ,
+						    param_cache_shared     );
+
+    Cache my_cache (param_cache);
+
+    cout << my_cache << endl;
+   
+    my_cache.reset();
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  0] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)10);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  1] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)9);
+      }
+
+    cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_dport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)9);
+      }
+
+
+  }
+
+  cout << "-------------------------------------------------------------------------" << endl;
+  cout << "-------------------------------------------------------------------------" << endl;
+  cout << "-------------------------------------------------------------------------" << endl;
+
+  {
+    const uint32_t nb_entity = 1;
+    const uint32_t nb_iport  = 3;
+    const uint32_t nb_dport  = 2;
+    
+    cout << "<main> Test des Types et direction" << endl;
+
+    param_cache_t             param_cache_1a     [1] = { param_cache_t (L1a_CACHE) };
+    param_cache_t             param_cache_1b     [1] = { param_cache_t (L1b_CACHE) };
+    param_cache_t             param_cache_2      [1] = { param_cache_t (L2_CACHE)  };
+   
+    cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",1,nb_iport,param_cache_1a)};
+    cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",1,nb_dport,param_cache_1b)};
+    cache_multilevel::param_t param_cache_shared   ("param_cache_shared",1, nb_entity*(nb_iport+nb_dport), param_cache_2);
+
+    cache::param_t            param_cache          ("cache"                ,
+						    nb_entity              ,
+						    param_icache_dedicated ,
+						    param_dcache_dedicated ,
+						    param_cache_shared     );
+
+    Cache my_cache (param_cache);
+
+    //    cout << my_cache << endl;
+    my_cache.reset();
+
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  0] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+    //cout << my_cache << endl;
+
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)16);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [+ 9] **********" << endl;
+    cout << "**************************************" << endl;
+    for (uint32_t it = 1; it < 9; it ++)
+      {
+	cout << it << endl;
+	my_cache.transition();
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  9] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+         cout << my_cache << endl;
+    
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x200+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)16);
+      }
+
+    cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_dport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)8);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  5] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+//     cout << my_cache << endl;
+    
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)6);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  6] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+//     cout << my_cache << endl;
+    
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,UNCACHED,READ),(uint32_t)16);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [  7] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+//  cout << my_cache << endl;
+    
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)4);
+      }
+    
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [+18] **********" << endl;
+    cout << "**************************************" << endl;
+    for (uint32_t it = 8; it < 18; it ++)
+      {
+	cout << it << endl;
+	my_cache.transition();
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 18] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+//  cout << my_cache << endl;
+    
+    cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_iport; i ++)
+      {
+	uint address = 0x100+i*4;
+	TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)1);
+      }
+
+    cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_dport; i ++)
+      {
+	uint address = 0x200+i*4;
+	TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)8);
+      }
+
+    cout << "**************************************" << endl;
+    cout << "********** TRANSITION [ 19] **********" << endl;
+    cout << "**************************************" << endl;
+    my_cache.transition();
+//  cout << my_cache << endl;
+    
+    cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
+    for (uint32_t i = 0; i < nb_dport; i ++)
+      {
+	uint address = 0x200+i;
+	TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)7);
+      }
+
+  }
+
+  test_ok ();
+}//end main  
Index: /trunk/IPs/systemC/hierarchy_memory/cache/tag.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/tag.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/tag.h	(revision 3)
@@ -0,0 +1,33 @@
+#ifndef TAG_H
+#define TAG_H
+
+#include <iostream>
+using namespace std;
+
+namespace hierarchy_memory          {
+namespace cache                     {
+namespace cache_multilevel          {
+namespace cache_onelevel            {
+
+class tag_t
+{
+public    : bool            valid    ;
+public    : uint32_t        address  ;
+public    : uint32_t        trdid    ;
+public    : uint32_t        index_lru;
+  
+  friend ostream& operator<< (ostream& output_stream, const tag_t &x)
+  {
+    output_stream <<                                   x.valid     << " "
+		  << hex << setw(8) << setfill('0') << x.address   << " " << dec
+		  <<                                   x.trdid     << " "
+		  <<                                   x.index_lru;
+    
+    return output_stream;
+  }
+  
+};
+
+};};};};
+
+#endif //!TAG_H
Index: /trunk/IPs/systemC/hierarchy_memory/cache/type_req_cache.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/type_req_cache.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/type_req_cache.h	(revision 3)
@@ -0,0 +1,24 @@
+#ifndef TYPE_REQ_CACHE_H
+#define TYPE_REQ_CACHE_H
+
+namespace hierarchy_memory
+{
+typedef enum
+  {
+    READ       ,
+    WRITE      ,
+    NONE
+  } direction_req_cache_t;
+
+typedef enum 
+  {
+    CACHED     , // address can be in the cache
+    UNCACHED   , // Always miss (not address in cache)
+    INVALIDATE , // The direction is not used
+    PREFETCH   , // The direction is not used
+    FLUSH        // The direction is not used
+  } type_req_cache_t;
+};
+
+#endif //!TYPE_REQ_CACHE_H
+
Index: /trunk/IPs/systemC/hierarchy_memory/cache/type_rsp_cache.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/type_rsp_cache.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/type_rsp_cache.h	(revision 3)
@@ -0,0 +1,17 @@
+#ifndef TYPE_RSP_CACHE_H
+#define TYPE_RSP_CACHE_H
+
+namespace hierarchy_memory
+{
+  typedef enum 
+    {
+      HIT_CACHE        ,
+      HIT_BYPASS       ,
+      HIT_WRITE_BUFFER ,
+      MISS
+    } type_rsp_cache_t;
+};
+
+
+#endif //!TYPE_RSP_CACHE_H
+
Index: /trunk/IPs/systemC/hierarchy_memory/cache/write_buffer.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/cache/write_buffer.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/cache/write_buffer.h	(revision 3)
@@ -0,0 +1,40 @@
+#ifndef WRITE_BUFFER_H
+#define WRITE_BUFFER_H
+
+#include "address.h"
+#include <iostream>
+using namespace std;
+
+namespace hierarchy_memory          {
+namespace cache                     {
+namespace cache_multilevel          {
+namespace cache_onelevel            {
+
+  class write_buffer_t
+    {
+    public    : address_t       address;
+    public    : uint32_t        trdid;
+
+    public    : write_buffer_t ()
+      {
+      }
+
+    public    : write_buffer_t (address_t address, uint32_t trdid)
+      {
+	this->address = address;
+	this->trdid   = trdid;
+      }
+
+      friend ostream& operator<< (ostream& output_stream, const write_buffer_t &x)
+      {
+	output_stream << x.address           << " "
+		      << x.trdid;
+
+	return output_stream;
+      }
+
+    };
+
+};};};};
+
+#endif //!WRITE_BUFFER_H
Index: /trunk/IPs/systemC/hierarchy_memory/data/Makefile
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/data/Makefile	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/data/Makefile	(revision 3)
@@ -0,0 +1,27 @@
+RM			= rm -f
+
+INCDIR			= -I../../    			\
+			  -I$(TOOLS)/soclib/include
+
+LIBDIR			= -L$(TOOLS)/soclib/lib-$(TARGET_ARCH)	\
+			  -L$(TOOLS)/or1k/lib/
+
+LIB			= -lsoclib -lbfd -liberty 
+
+CXX			= g++
+CXX_OPT			= -g3 -Wall -Werror -ansi $(INCDIR)       
+LXX_OPT			= $(LIBDIR) $(LIB)
+
+EXE			= $(patsubst %.cpp,%.x ,$(wildcard *.cpp) )
+HEADERS			= $(wildcard *.h)
+
+all			: $(EXE)
+			./$(EXE)
+
+%.x			: %.cpp $(HEADERS)
+			$(CXX) $(CXX_OPT) -o $@ $<  $(LXX_OPT) 
+#			$(CXX) $(CXX_OPT) -c -o $@.o $<
+#			$(CXX)               -o $@   $@.o $(LXX_OPT)
+
+clean			:
+			$(RM) $(EXE) *~ *.o
Index: /trunk/IPs/systemC/hierarchy_memory/data/data.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/data/data.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/data/data.h	(revision 3)
@@ -0,0 +1,173 @@
+#ifndef DATA_H
+#define DATA_H
+
+#include <stdint.h>
+#include <iostream>
+#include "segment.h"
+#include "shared/soclib_segment_table.h"
+
+using namespace std;
+
+namespace hierarchy_memory {
+namespace data             {
+
+  class entity_t
+  {
+  public : bool        present;
+  public : segment_t * segment;
+    
+  public : entity_t (bool present)
+    {
+      this->present = present;
+    }
+    
+  public : entity_t (bool        present ,
+		     segment_t * segment )
+    {
+      this->present = present;
+      this->segment = segment;
+    }
+
+    friend ostream& operator<< (ostream& output_stream, const entity_t & x)
+    {
+      output_stream << x.present;
+      if (x.present == true)
+	output_stream << " " << *x.segment;
+
+      return output_stream;
+    }
+  }; //end entity_t
+
+  class param_t
+  {
+  public : char *                 name       ;
+  public : uint32_t               max_seg    ;
+  public : unsigned int           globalIndex;
+  public : unsigned int           localIndex ;
+  public : SOCLIB_SEGMENT_TABLE * segtab     ;
+
+  public : param_t (char                 * name       ,
+		    uint32_t               max_seg    ,
+		    unsigned int           globalIndex,
+		    unsigned int           localIndex ,
+		    SOCLIB_SEGMENT_TABLE * segtab     )
+    {
+      this->name        = name       ;
+      this->max_seg     = max_seg    ;
+      this->globalIndex = globalIndex;
+      this->localIndex  = localIndex ;
+      this->segtab      = segtab     ;
+    }    
+  }; //end param_t
+  
+  class Data
+  {
+  private   : char *         name;
+  protected : const uint32_t max_seg;
+  protected : uint32_t       nb_seg;
+  protected : segment_t   ** segment;
+
+  public : Data (param_t param) :
+    max_seg (param.max_seg)
+    {
+      uint32_t size_name = strlen(param.name)+1;
+      name               = new char [size_name];
+      strncpy(name,param.name,size_name);
+
+      std::list<SEGMENT_TABLE_ENTRY>           seglist = param.segtab->getSegmentList(param.globalIndex,param.localIndex);
+      std::list<SEGMENT_TABLE_ENTRY>::iterator iter;
+      nb_seg = 0;
+
+      segment = new segment_t * [max_seg];
+
+      for (iter = seglist.begin() ; iter != seglist.end() ; ++iter , nb_seg ++)
+	{
+	  SEGMENT_TABLE_ENTRY entry = *iter;
+	  if (nb_seg >= max_seg)
+	    {
+	      cerr << "The number of seg can't be higher that " << max_seg << endl;
+	      exit (1);
+	    }
+	  segment [nb_seg] = new segment_t (entry);
+	  
+	  param.segtab->setAddrAlloc(entry.getBase(),(void *)(segment [nb_seg]->data_addr()));
+	}
+    }
+
+    //*****[ init ]*****
+  public : bool init (char * section, const char * filename, const char ** list_section)
+    {
+      for (uint32_t it = 0; it < nb_seg; it ++)
+	if (segment[it]->test(section) == true)
+	  return segment[it]->init(filename,list_section);
+
+      return false;
+    }
+    
+    //*****[ read ]*****
+    // Read a lot of byte
+  public : bool read (uint32_t address, uint32_t size, char * & data_dest)
+    {
+      uint32_t num_seg = 0;
+      bool     res     = false;
+      for (num_seg = 0; num_seg < nb_seg; num_seg ++)
+	if (segment[num_seg]->test (address,size) == true)
+	  {
+	    segment[num_seg]->read (address,size,data_dest);
+	    res = true;
+	    break;
+	  }
+
+      return res;
+    }
+
+    //*****[ entity ]*****
+  public : entity_t entity (uint32_t address, uint32_t size)
+    {
+      for (uint32_t num_seg = 0; num_seg < nb_seg; num_seg ++)
+	if (segment[num_seg]->test (address,size) == true)
+	  return entity_t (true,segment[num_seg]);
+      
+      return entity_t (false);
+    }
+
+  public : entity_t entity (char * name)
+    {
+      for (uint32_t num_seg = 0; num_seg < nb_seg; num_seg ++)
+	if (segment[num_seg]->test(name) == true)
+	  return entity_t (true,segment[num_seg]);
+      
+      return entity_t (false);
+    }
+
+    //*****[ write ]*****
+    // Write a lot of byte
+  public : bool write (uint32_t address, uint32_t size, char * & data_src)
+    {
+      uint32_t num_seg = 0;
+      bool     res     = false;
+      for (num_seg = 0; num_seg < nb_seg; num_seg ++)
+	if (segment[num_seg]->test (address,size) == true)
+	  {
+	    segment[num_seg]->write (address,size,data_src);
+	    res = true;
+	    break;
+	  }
+
+      return res;
+    }
+
+  public    : friend ostream& operator<< (ostream& output_stream, const Data & x)
+    {
+      output_stream << "<" << x.name << ">" << endl
+		    << "  * nb_seg  : " << x.nb_seg  << endl 
+		    << "  * max_seg : " << x.max_seg << endl;
+
+      for (uint32_t it = 0; it < x.nb_seg; it ++)
+	output_stream << *x.segment[it] << endl;
+      return output_stream;
+    };
+  };
+
+};}; //end namespace
+#endif //!DATA_H
Index: /trunk/IPs/systemC/hierarchy_memory/data/main.cpp
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/data/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/data/main.cpp	(revision 3)
@@ -0,0 +1,163 @@
+#include "data.h"
+#include <iostream>
+
+#define	TEXT_BASE		0x00000000
+#define	TEXT_SIZE		0x00005000
+
+#define	DATA_CACHED_BASE	0x10000000
+#define	DATA_CACHED_SIZE	0x00000100
+
+#define	DATA_UNCACHED_BASE	0x40000000
+#define	DATA_UNCACHED_SIZE	0x00000100
+
+#define	STACK_BASE		0x50000000
+#define	STACK_SIZE		0x00000200
+				
+#define TTY_BASE        	0x60000000
+#define TTY_SIZE        	0x00000100 
+
+#define SIM2OS_BASE     	0x70000000
+#define SIM2OS_SIZE     	0x00000100 
+
+#define RAMLOCK_BASE    	0x80000000
+#define RAMLOCK_SIZE    	0x00000100 
+
+using namespace hierarchy_memory::data;
+using namespace std;
+
+void test_ko (int val)
+{
+  cout << "***** Test(" << val << ") KO *****" << endl;
+  exit (val);
+}
+
+void test_ok ()
+{
+  cout << "***** Test OK *****" << endl;
+  exit (0);
+}
+
+static uint32_t num_test = 1;
+
+template <class T>
+void test(T exp1, T exp2)
+{
+  if (exp1 != exp2)
+    test_ko (num_test);
+  num_test ++;
+}
+
+int main ()
+{
+  cout << "<main> Test de \"Data\"" << endl;
+  
+  cout << "  * Create a Data" << endl;
+
+  SOCLIB_SEGMENT_TABLE segtable;
+  segtable.setMSBNumber    (8);
+  segtable.setDefaultTarget(0,0);
+  
+  //shared data segment
+
+
+  
+  // Add a segment   :name        , address of base    , size               , global index , local index, uncache
+  segtable.addSegment("text"      , TEXT_BASE          , TEXT_SIZE          , 0            ,0           , false);
+  segtable.addSegment("data"      , DATA_CACHED_BASE   , DATA_CACHED_SIZE   , 0            ,0           , false);
+  segtable.addSegment("data_unc"  , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0            ,0           , true );
+  segtable.addSegment("stack"     , STACK_BASE         , STACK_SIZE         , 0            ,0           , false);
+  segtable.addSegment("tty"       , TTY_BASE           , TTY_SIZE           , 0            ,0           , true );
+  segtable.addSegment("sim2os"    , SIM2OS_BASE        , SIM2OS_SIZE        , 0            ,0           , true );
+  segtable.addSegment("ramlock"   , RAMLOCK_BASE       , RAMLOCK_SIZE       , 0            ,0           , true );
+
+  Data my_data = Data(param_t("my_data",16,0,0,&segtable));
+
+  const char * sections_text  []  = {".text",NULL}; 
+  const char * sections_data  []  = {".data",".rodata",".sdata",".sbss",".bss", NULL}; 
+  const char * sections_stack []  = {".stack",NULL}; 
+  const char * filename           = "soft.x";
+
+  test <bool> (my_data.init("text"   , filename, sections_text) ,true);
+  test <bool> (my_data.init("stack"  , filename, sections_stack),true);
+  test <bool> (my_data.init("data"   , filename, sections_data) ,true);
+  
+  segtable.print();
+
+  cout << my_data << endl;
+
+  uint32_t size, offset;
+  char   * data = new char [100];
+
+  // *************************************************************
+  offset = 0;
+  size   = 32;
+  
+  cout << " * Read  of bytes [" << DATA_CACHED_BASE+offset << ":" << DATA_CACHED_BASE+offset+size << "[" << endl;
+
+  test <bool> (my_data.read(DATA_CACHED_BASE+offset,size,data), true);
+
+  for (uint32_t it = 0; it < size; it ++)
+    {
+      if (it % 4 == 0)
+	printf("\n");
+
+      printf("%.2x",(unsigned char)(data[it]));
+    }
+  printf("\n");
+
+  // *************************************************************
+  offset = 8;
+  size   = 16;
+  char * data_src = new char [100];
+  sprintf(data_src,"123456780abcdef0");
+
+  cout << " * Write of bytes [" << DATA_CACHED_BASE+offset << ":" << DATA_CACHED_BASE+offset+size << "[" << endl;
+
+  test <bool> (my_data.write(DATA_CACHED_BASE+offset,size,data_src), true);
+
+  for (uint32_t it = 0; it < size; it ++)
+    {
+      if (it % 4 == 0)
+	printf("\n");
+
+      printf("%.2x",(unsigned char)(data_src[it]));
+    }
+  printf("\n");
+
+  // *************************************************************
+  offset = 0;
+  size   = 32;
+  cout << " * Read  of bytes [" << DATA_CACHED_BASE+offset << ":" << DATA_CACHED_BASE+offset+size << "[" << endl;
+
+  test <bool> (my_data.read(DATA_CACHED_BASE+offset,size,data), true);
+
+  for (uint32_t it = 0; it < size; it ++)
+    {
+      if (it % 4 == 0)
+	printf("\n");
+
+      printf("%.2x",(unsigned char)(data[it]));
+    }
+  printf("\n");
+
+  // *************************************************************
+
+  cout << " * Recherche of address" << endl;
+  test<bool> (my_data.entity(0x00000034, 2).present,true );
+  test<bool> (my_data.entity(0x00005000, 1).present,false);
+  test<bool> (my_data.entity(0x00004FFD, 2).present,true );
+  test<bool> (my_data.entity(0x00004FFD, 4).present,false);
+  test<bool> (my_data.entity(0x10000000, 1).present,true );
+  test<bool> (my_data.entity(0x0FFFFFFF,10).present,false);
+
+  cout << " * Typage" << endl;
+  cout << my_data.entity(TTY_BASE,TTY_SIZE) << endl;
+  my_data.entity(TTY_BASE,TTY_SIZE).segment->define_target (TYPE_TTY,0);
+  cout << my_data.entity(TTY_BASE,TTY_SIZE) << endl;
+
+  cout << my_data.entity("ramlock") << endl;
+  my_data.entity("ramlock").segment->define_target (TYPE_RAMLOCK,0);
+  cout << my_data.entity("ramlock") << endl;
+
+  test_ok ();
+}
Index: /trunk/IPs/systemC/hierarchy_memory/data/segment.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/data/segment.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/data/segment.h	(revision 3)
@@ -0,0 +1,165 @@
+#ifndef SEGMENT_H
+#define SEGMENT_H
+
+#include <stdint.h>
+#include <iomanip>
+#include <iostream>
+#include "type_target.h"
+#include "shared/soclib_segment_table.h"
+
+using namespace std;
+
+extern "C" void loadexec(void **emem, int *esize, int *eoffset, const char *file, const char ** sections);
+
+
+namespace hierarchy_memory {
+namespace data             {
+  
+  class segment_t
+  {
+  protected : uint32_t      base;
+  protected : uint32_t      size;
+  protected : bool          uncached;
+  protected : char        * name;
+  protected : char        * data;
+  protected : type_target_t type;
+  protected : uint32_t      index;
+
+  public : segment_t ()
+    {
+      base     = 0;
+      size     = 0;
+      uncached = false;
+      name     = NULL;
+      data     = NULL;
+      type     = TYPE_MEMORY;
+      index    = 0;
+    }
+
+  public : segment_t (SEGMENT_TABLE_ENTRY segment)
+    {
+      uint32_t size_name = strlen (segment.getName())+1;
+
+      base     = segment.getBase();
+      size     = segment.getSize();
+      uncached = segment.getUncached();
+      name     = new char [size_name];
+      name     = strncpy (name, segment.getName(),size_name);
+      data     = new char [size];
+      type     = TYPE_MEMORY;
+      index    = 0;
+    };
+
+    //*****[ init ]*****
+  public : bool init (const char * filename,const  char ** sections)
+    {
+      void * ptab;
+      int    size   = this->size;
+      int    offset = 0;
+
+      loadexec(&ptab,&size,&offset,filename,sections);
+
+      cout << "    - size         : " << size         << endl;
+      cout << "    - offset       : " << offset       << endl;
+
+      if (size > (int)this->size)
+	{
+	  cerr << "<segment.init> : segment " << name << " is to small : size is " << this->size << " and requiert is " << size << endl;
+	  return false;
+	}
+      
+      memcpy(data, ptab, size);
+
+      free  (ptab);
+      
+      return true;
+    }
+
+    //*****[ define_target ]*****
+  public : void define_target (type_target_t type, uint32_t index)
+    {
+      this->type  = type;
+      this->index = index;
+    }
+
+    //*****[ getType ]*****
+  public : type_target_t getType ()
+    {
+      return type;
+    }
+
+    //*****[ getIndex ]*****
+  public : uint32_t getIndex ()
+    {
+      return index;
+    }
+
+    //*****[ getBase ]*****
+  public : uint32_t getBase ()
+    {
+      return base;
+    }
+
+    //*****[ getSize ]*****
+  public : uint32_t getSize ()
+    {
+      return size;
+    }
+
+    //*****[ getUncached ]*****
+  public : uint32_t getUncached ()
+    {
+      return uncached;
+    }
+
+    //*****[ data_addr ]*****
+    // Return the data address
+  public : char * data_addr ()
+    {
+      return data;
+    }
+
+    //*****[ test ]*****
+  public : bool test (char * name)
+    {
+      return (strcmp(this->name,name) == 0);
+    }
+
+  public : bool test (uint32_t address, uint32_t size)
+    {
+      bool res = (((address     ) >=  this->base           ) && 
+		  ((address+size) <= (this->base+this->size)));
+
+      return res;
+    }
+
+    //*****[ read ]*****
+  public : void read (uint32_t address, uint32_t size, char * & data_dest)
+    {
+      for (uint32_t it = 0; it < size ; it ++)
+	data_dest [it] = data[address-base+it];
+    }
+
+    //*****[ write ]*****
+  public : void write (uint32_t address, uint32_t size, char * & data_src)
+    {
+      for (uint32_t it = 0; it < size ; it ++)
+	data[address-base+it] = data_src [it];
+    }
+
+    friend ostream& operator<< (ostream& output_stream, const segment_t & x)
+    {
+      output_stream << "Segment \"" << x.name << "\""     << endl
+		    << hex
+		    << "  * base     : " << setw(8) << setfill('0') << x.base << endl
+		    << "  * size     : " << setw(8) << setfill('0') << x.size << endl
+		    << dec
+		    << "  * uncached : " << x.uncached    << endl
+		    << "  * type     : " << x.type        << endl;
+	
+      return output_stream;
+    };
+  };
+
+};}; //end namespace
+#endif //!SEGMENT_H
Index: /trunk/IPs/systemC/hierarchy_memory/data/type_target.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/data/type_target.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/data/type_target.h	(revision 3)
@@ -0,0 +1,16 @@
+#ifndef TYPE_TARGET_H
+#define TYPE_TARGET_H
+
+namespace hierarchy_memory {
+namespace data             {
+  
+  typedef enum 
+    {
+      TYPE_MEMORY      ,
+      TYPE_TTY         ,
+      TYPE_RAMLOCK     ,
+      TYPE_SIM2OS
+    } type_target_t;
+  
+};}; //end namespace
+#endif //!TYPE_TARGET_H
Index: /trunk/IPs/systemC/hierarchy_memory/endianness/endianness.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/endianness/endianness.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/endianness/endianness.h	(revision 3)
@@ -0,0 +1,166 @@
+#ifndef _ENDIANNESS_H
+#define _ENDIANNESS_H
+//=====[ endianness ]==========================================================
+
+/* 
+ * file              : endianness.h
+ * date (yyyy/mm/dd) : 2006/05/02
+ * authors           : Rosiere Mathieu
+ */
+
+#include <byteswap.h>
+
+#define LittleEndian false
+#define BigEndian    true
+
+union TestEndian 
+{
+  unsigned long total;
+  struct 
+  {
+    unsigned char octet1;
+    unsigned char octet2;
+    unsigned char octet3;
+    unsigned char octet4;
+  } octets;
+};
+
+//-----[ hostEndianness ]------------------------------------------------------
+/*
+ * false : LitteEndian
+ * true  : BigEndian
+ */
+inline bool hostEndianness()
+{
+  union TestEndian test_endian;
+  test_endian.total = 0xFF;
+  
+  return (test_endian.octets.octet1 == 0xFF)?LittleEndian:BigEndian;
+}
+
+//-----[ cpuEndianness ]-------------------------------------------------------
+/*
+ * false : LitteEndian
+ * true  : BigEndian
+ */
+inline bool cpuEndianness(unsigned int cpu_id)
+{
+  return(BigEndian);
+
+  /*
+   * Comment connaitre l'endianness ?
+   * static    : table generee dans le top level
+   * dynamique : table generee par un l'equivalent de hostEndianness et ecrivant dans un segment precis de la ram
+   */
+}
+
+//-----[ isSameEndianness ]----------------------------------------------------
+
+/*
+ * The host machine and the simulate processeur have the same endianness
+ */
+inline bool isSameEndianness(unsigned int cpu_id)
+{
+  return ((hostEndianness() ^ cpuEndianness(cpu_id)) == false);
+}
+
+//-----[ swapBytes ]-----------------------------------------------------------
+/*
+ * swapBytes -> change the endiannes
+ * exemple for 16 and size_access = 4, [0123456789abcdef] -> [32107654ba98fedc]
+ */
+inline char * swapBytes (char * string_src , unsigned int size_string, unsigned int size_access)
+{
+  char string_tmp [size_string];
+
+  if (size_access == 1)
+    return string_src;
+
+  if (size_string % size_access != 0)
+    {
+      cerr << "<swapBytes> : Size of string must be a multiple of size_access." << endl;
+      exit(1);
+    }
+
+  // size_access :
+  // 1 -> bytes
+  // 2 -> half
+  // 4 -> word
+  // 8 -> doubleword
+
+  memcpy (string_tmp,string_src,size_string);
+
+  // Loop to reorganize the string
+  for (unsigned int it_size_string = 0 ; it_size_string < size_string; it_size_string += size_access)
+    {
+      // Permutation
+//       for (unsigned int it_size_access = 0 ; it_size_access < size_access; it_size_access ++)
+// 	string_src [it_size_string+it_size_access] = string_tmp [it_size_string + (size_access-1) - it_size_access];
+      switch (size_access)
+	{
+	case 2  : 
+	  {
+	    string_src[it_size_string+0] = string_tmp[it_size_string+1];
+	    string_src[it_size_string+1] = string_tmp[it_size_string+0];
+	    break;
+	  }
+	case 4  :
+	  {
+	    string_src[it_size_string+0] = string_tmp[it_size_string+3];
+	    string_src[it_size_string+1] = string_tmp[it_size_string+2];
+	    string_src[it_size_string+2] = string_tmp[it_size_string+1];
+	    string_src[it_size_string+3] = string_tmp[it_size_string+0];
+	    break;
+	  }
+	case 8  :
+	  {
+	    string_src[it_size_string+0] = string_tmp[it_size_string+7];
+	    string_src[it_size_string+1] = string_tmp[it_size_string+6];
+	    string_src[it_size_string+2] = string_tmp[it_size_string+5];
+	    string_src[it_size_string+3] = string_tmp[it_size_string+4];
+	    string_src[it_size_string+4] = string_tmp[it_size_string+3];
+	    string_src[it_size_string+5] = string_tmp[it_size_string+2];
+	    string_src[it_size_string+6] = string_tmp[it_size_string+1];
+	    string_src[it_size_string+7] = string_tmp[it_size_string+0];
+	    break;
+	  }
+	default :  
+	  {
+	    cerr << "<swapBytes> : Illegal size of access (size_access = " << size_access << ")" << endl;
+	    exit(1);
+	    break;
+	  }
+	}//end switch(size_access)
+    }//end it_size_string
+  
+
+//   cout << "size_access : " << size_access << endl;
+//   cout << "size_string : " << size_string << endl;
+
+//   for (unsigned int it_size_string = 0 ; it_size_string < size_string; it_size_string ++)
+//     printf("%.2x",(unsigned int)string_src[it_size_string]);
+//   printf("\n");
+
+//   // Loop to reorganize the string
+//   for (unsigned int it_size_string = 0 ; it_size_string < size_string; it_size_string += size_access)
+//     {
+//       switch (size_access)
+// 	{
+// 	case 2  : string_src[it_size_string] = bswap_16((unsigned short)   string_src[it_size_string]); break;
+// 	case 4  : string_src[it_size_string] = bswap_32((unsigned int  )   string_src[it_size_string]); break;
+// 	case 8  : string_src[it_size_string] = bswap_64((unsigned long int)string_src[it_size_string]); break;
+// 	default :  
+// 	  {
+// 	    cerr << "<swapBytes> : Illegal size of access (size_access = " << size_access << ")" << endl;
+// 	    exit(1);
+// 	    break;
+// 	  }
+// 	}//end switch(size_access)
+
+//   for (unsigned int it_size_string = 0 ; it_size_string < size_string; it_size_string ++)
+//     printf("%.2x",(unsigned int)string_src[it_size_string]);
+//   printf("\n");
+
+  return string_src;
+}
+#endif //_ENDIANNESS_H
Index: /trunk/IPs/systemC/hierarchy_memory/file/Makefile
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/file/Makefile	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/file/Makefile	(revision 3)
@@ -0,0 +1,16 @@
+
+CXX			= g++
+CXX_OPT			= -g3 -Wall -Werror -ansi
+RM			= rm -f
+
+EXE			= $(patsubst %.cpp,%.x ,$(wildcard *.cpp) )
+HEADERS			= $(wildcard *.h)
+
+all			: $(EXE)
+			./$(EXE)
+
+%.x			: %.cpp $(HEADERS)
+			$(CXX) $(CXX_OPT) -o $@ $<
+
+clean			:
+			$(RM) $(EXE) *~
Index: /trunk/IPs/systemC/hierarchy_memory/file/entry.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/file/entry.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/file/entry.h	(revision 3)
@@ -0,0 +1,67 @@
+#ifndef ENTRY_H
+#define ENTRY_H
+
+#include <stdint.h>
+#include <iostream>
+
+using namespace std; // Utilisation de l'espace de nommage standard
+
+namespace hierarchy_memory
+{
+  namespace sort_file
+  {
+    class Entry
+    {
+    public : uint32_t   trdid  ;  // number of thread
+    public : uint32_t   pktid  ;  // number of packet
+    public : uint32_t   nb_word;
+    public : uint32_t   size_word;
+    public : char    ** data   ;
+    public : uint32_t   error  ;
+      
+      Entry () {};
+      
+      Entry (uint32_t   trdid    ,
+	     uint32_t   pktid    ,
+	     uint32_t   nb_word  ,
+	     uint32_t   size_word,
+	     char    ** data     ,
+	     uint32_t   error 
+	     )
+      {
+	this->trdid     = trdid;
+	this->pktid     = pktid;
+	this->nb_word   = nb_word;
+	this->size_word = size_word;
+	this->data      = new char * [nb_word];
+	this->error     = error;
+
+	for (uint32_t num_word = 0; num_word < nb_word; num_word++)
+	  {
+	    this->data[num_word] = new char [size_word];
+	    memcpy(this->data[num_word],data[num_word],size_word);
+	  }
+      };
+      
+      friend ostream& operator<< (ostream& output_stream, Entry x)
+      {
+	output_stream << x.trdid              << " " 
+		      << x.pktid              << " " 
+		      << x.error              << " ";
+
+	output_stream << hex;
+
+	for (uint32_t it_nb_word = 0; it_nb_word < x.nb_word; it_nb_word ++)
+	  {
+	    for (uint32_t it_size_word = x.size_word; it_size_word > 0 ; it_size_word --)
+	      output_stream << setw(2) << setfill('0') << (0xff & (static_cast<uint32_t>(x.data [it_nb_word][it_size_word-1])));
+	    output_stream << " - ";
+	  } 
+	output_stream << dec;
+
+	return output_stream;
+      }
+    };
+  }; //sort_file
+}; //hierarchy_memory
+#endif //!ENTRY_H
Index: /trunk/IPs/systemC/hierarchy_memory/file/entry_test.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/file/entry_test.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/file/entry_test.h	(revision 3)
@@ -0,0 +1,42 @@
+#ifndef ENTRY_H
+#define ENTRY_H
+
+#include <stdint.h>
+#include <iostream>
+using namespace std; // Utilisation de l'espace de nommage standard
+
+namespace hierarchy_memory
+{
+  namespace sort_file
+  {
+    class Entry
+    {
+    public : uint32_t       trdid;  // number of thread
+    public : uint32_t       pktid;  // number of packet
+    public : uint64_t       data;
+      
+      Entry () 
+      {
+	trdid = 0;
+	pktid = 0;
+	data  = 0;
+      };
+      
+      Entry (uint32_t       trdid ,
+	     uint32_t       pktid ,
+	     uint64_t       data  )
+      {
+	this->trdid = trdid;
+	this->pktid = pktid;
+	this->data  = data ;
+      };
+      
+      friend ostream& operator<< (ostream& output_stream, Entry x)
+      {
+	output_stream << x.trdid << " " << x.pktid << " " << hex << x.data << dec;
+	return output_stream;
+      }
+    };
+  }; //sort_file
+}; //hierarchy_memory
+#endif //!ENTRY_H
Index: /trunk/IPs/systemC/hierarchy_memory/file/file.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/file/file.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/file/file.h	(revision 3)
@@ -0,0 +1,83 @@
+#ifndef FILE_H
+#define FILE_H
+
+#include <stdint.h>
+#include <iostream>
+#include "slot.h"
+
+using namespace std;
+
+namespace hierarchy_memory
+{
+  namespace sort_file
+  {
+    template <class T>
+    class File
+    {
+    protected : char      * name;
+    protected : uint32_t    nb_slot;   // number of slot
+    protected : uint32_t    size;      // size of file
+    protected : slot_t<T> * slot;
+
+    public : File (char   * name,
+		   uint32_t size)
+      {
+	uint32_t size_name = strlen(name)+1;
+	this->name = new char [size_name];
+	strncpy(this->name,name,size_name);
+
+	nb_slot    = 0;
+	this->size = size;
+	slot       = new slot_t<T> [size];
+      };
+
+    public : virtual ~File ()
+      {
+      };
+
+      // *****[ empty ]*****
+      // Test if the file is empty
+    public : bool empty ()
+      {
+	return (nb_slot == 0);
+      }
+      
+      // *****[ full ]*****
+      // Test if the file is full
+    public : bool full ()
+      {
+	return (nb_slot == size);
+      }
+
+      // *****[ nb_slot_free ]*****
+      // return the number of free slot
+    public : uint32_t nb_slot_free ()
+      {
+	return (size-nb_slot);
+      }
+
+      // *****[ nb_slot_use ]*****
+      // return the number of use slot
+    public : uint32_t nb_slot_use ()
+      {
+	return (nb_slot);
+      }
+
+      // *****[ pop ]*****
+      // read the file, and update the pointer
+    public : virtual T    pop  ()             {return T();};
+
+      // *****[ pop ]*****
+      // read the file, and update the pointer
+    public : virtual T    pop  (uint32_t num) {return T();};
+
+      // *****[ push ]*****
+      // Push a new value (they must have a slot free)
+    public : virtual bool push (T val)        {return false;};
+  
+    }; // File
+    
+  }; //sort_file
+}; //hierarchy_memory
+#endif //!FILE_H
+  
Index: /trunk/IPs/systemC/hierarchy_memory/file/main.cpp
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/file/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/file/main.cpp	(revision 3)
@@ -0,0 +1,187 @@
+#include "sort_file.h"
+#include "sort_file_dynamic.h"
+#include "entry_test.h"
+#include <iostream>
+
+using namespace hierarchy_memory::sort_file;
+using namespace std;
+
+void test_ko (int val)
+{
+  cout << "***** Test(" << val << ") KO *****" << endl;
+  exit (val);
+};
+
+void test_ok ()
+{
+  cout << "***** Test OK *****" << endl;
+  exit (0);
+};
+
+static uint32_t num_test = 1;
+
+template <class T>
+void test(T exp1, T exp2)
+{
+  if (exp1 != exp2)
+    {
+      cerr << "exp1 : " << exp1 << endl;
+      cerr << "exp2 : " << exp2 << endl;
+      test_ko (num_test);
+    }
+  num_test ++;
+};
+
+int main ()
+{
+  {
+    cout << "<main> Test de \"Sort_File\"" << endl;
+
+    cout << " * creation d'une Sort_File de taille 5" << endl;
+    Sort_File <Entry> my_Sort_File = Sort_File <Entry> (param_t("my_file",5));
+    my_Sort_File.reset();
+    cout << my_Sort_File << endl;
+
+    cout << " * must be empty ..." << endl;
+    if ( (my_Sort_File.empty() == false) ||
+	 (my_Sort_File.full () == true ) )
+      test_ko (1);
+
+    cout << " * insert 6 elements" << endl;
+  
+    if (my_Sort_File.push((uint32_t)5,Entry(1,1,0x44444444)) != true ) test_ko (2); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)6,Entry(2,2,0x55555555)) != true ) test_ko (3); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)3,Entry(3,3,0x22222222)) != true ) test_ko (4); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)5,Entry(4,4,0x33333333)) != true ) test_ko (5); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)1,Entry(5,5,0x11111111)) != true ) test_ko (6); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)4,Entry(6,6,0x00000BAD)) != false) test_ko (7); cout << my_Sort_File << endl;
+
+    cout << " * must be full  ..." << endl;
+    if ( (my_Sort_File.empty() == true ) ||
+	 (my_Sort_File.full () == false) )
+      test_ko (8);
+
+    cout << " * extract 6 elements" << endl;
+    if (my_Sort_File.pop().data != 0x11111111) test_ko (9);
+    if (my_Sort_File.pop().data != 0x22222222) test_ko (10);
+    if (my_Sort_File.pop().data != 0x33333333) test_ko (11);
+    if (my_Sort_File.pop().data != 0x44444444) test_ko (12);
+    if (my_Sort_File.pop().data != 0x55555555) test_ko (13);
+
+    cout << " * ajout de 8 elements (reset apres le deuxieme)" << endl;
+
+    if (my_Sort_File.push((uint32_t)5,Entry(1,1,0x44444444)) != true ) test_ko (14); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)6,Entry(2,2,0x55555555)) != true ) test_ko (15); cout << my_Sort_File << endl;
+    my_Sort_File.reset();							        
+    if (my_Sort_File.push((uint32_t)3,Entry(3,3,0x22222222)) != true ) test_ko (16); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)5,Entry(4,4,0x33333333)) != true ) test_ko (17); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)5,Entry(1,1,0x44444444)) != true ) test_ko (18); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)7,Entry(2,2,0x55555555)) != true ) test_ko (19); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)1,Entry(5,5,0x11111111)) != true ) test_ko (20); cout << my_Sort_File << endl;
+    if (my_Sort_File.push((uint32_t)4,Entry(6,6,0x00000BAD)) != false) test_ko (21); cout << my_Sort_File << endl;
+
+    cout << " * 3 transitions" << endl;
+  
+    my_Sort_File.transition(); cout << my_Sort_File << endl;
+    my_Sort_File.transition(); cout << my_Sort_File << endl;
+    my_Sort_File.transition(); cout << my_Sort_File << endl;
+
+    cout << " * extract 1 element" << endl;
+
+    if (my_Sort_File.pop().data != 0x11111111) test_ko (22);  
+  
+    cout << my_Sort_File << endl;
+
+    for (uint32_t it = 0; it < my_Sort_File.nb_slot_use(); it ++)
+      {
+	slot_t<Entry> val = my_Sort_File.read(it);
+	cout << val.delay << " " << val.data << endl;
+      }
+
+    cout << " * Test pop(n)" << endl;
+  
+    test <uint32_t> (my_Sort_File.pop(1).data, 0x44444444);
+    test <uint32_t> (my_Sort_File.pop(2).data, 0x55555555);
+    test <uint32_t> (my_Sort_File.pop(0).data, 0x22222222);
+    test <uint32_t> (my_Sort_File.pop(0).data, 0x33333333);
+  }
+
+  {
+    cout << "<main> Test de \"Sort_File_Dynamic\"" << endl;
+
+    cout << " * creation d'une Sort_File de taille 5" << endl;
+    Sort_File_Dynamic <Entry> my_Sort_File_Dynamic = Sort_File_Dynamic <Entry> (param_t("my_file_dynamic",5));
+    my_Sort_File_Dynamic.reset();
+    cout << my_Sort_File_Dynamic << endl;
+
+    cout << " * must be empty ..." << endl;
+    if ( (my_Sort_File_Dynamic.empty() == false) ||
+	 (my_Sort_File_Dynamic.full () == true ) )
+      test_ko (1);
+
+    if (my_Sort_File_Dynamic.push(5,Entry(1,1, 4)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(6,Entry(2,2, 6)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(3,Entry(3,3, 2)) != true ) test_ko ( 4); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(5,Entry(4,4, 5)) != true ) test_ko ( 5); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(1,Entry(5,5, 1)) != true ) test_ko ( 6); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(4,Entry(6,6, 3)) != true ) test_ko ( 7); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(9,Entry(1,1,12)) != true ) test_ko ( 8); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(6,Entry(2,2, 7)) != true ) test_ko ( 9); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(7,Entry(3,3, 8)) != true ) test_ko (10); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(7,Entry(4,4, 9)) != true ) test_ko (11); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(8,Entry(5,5,11)) != true ) test_ko (12); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(7,Entry(6,6,10)) != true ) test_ko (13); cout << my_Sort_File_Dynamic << endl;
+
+    if (my_Sort_File_Dynamic.pop().data !=  1 ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  2 ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  3 ) test_ko ( 4); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  4 ) test_ko ( 5); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  5 ) test_ko ( 6); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  6 ) test_ko ( 7); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  7 ) test_ko ( 8); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  8 ) test_ko ( 9); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  9 ) test_ko (10); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data != 10 ) test_ko (11); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data != 11 ) test_ko (12); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data != 12 ) test_ko (13); cout << my_Sort_File_Dynamic << endl;
+
+
+    if (my_Sort_File_Dynamic.push(5,Entry(1,1, 4)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(6,Entry(2,2, 6)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(3,Entry(3,3, 2)) != true ) test_ko ( 4); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(5,Entry(4,4, 5)) != true ) test_ko ( 5); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(1,Entry(5,5, 1)) != true ) test_ko ( 6); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(4,Entry(6,6, 3)) != true ) test_ko ( 7); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(9,Entry(1,1,12)) != true ) test_ko ( 8); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(6,Entry(2,2, 7)) != true ) test_ko ( 9); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(7,Entry(3,3, 8)) != true ) test_ko (10); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(7,Entry(4,4, 9)) != true ) test_ko (11); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(8,Entry(5,5,11)) != true ) test_ko (12); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(7,Entry(6,6,10)) != true ) test_ko (13); cout << my_Sort_File_Dynamic << endl;
+
+    if (my_Sort_File_Dynamic.pop().data !=  1 )              test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  2 )              test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+
+    if (my_Sort_File_Dynamic.push(0,Entry(1,1, 1)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(0,Entry(2,2, 2)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  1 )              test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  2 )              test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(0,Entry(1,1, 1)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(0,Entry(2,2, 2)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  1 )              test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  2 )              test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(0,Entry(1,1, 1)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(0,Entry(2,2, 2)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  1 )              test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  2 )              test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(0,Entry(1,1, 1)) != true ) test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.push(0,Entry(2,2, 2)) != true ) test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  1 )              test_ko ( 2); cout << my_Sort_File_Dynamic << endl;
+    if (my_Sort_File_Dynamic.pop().data !=  2 )              test_ko ( 3); cout << my_Sort_File_Dynamic << endl;
+    
+
+  }
+
+  test_ok ();
+    
+}
Index: /trunk/IPs/systemC/hierarchy_memory/file/param.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/file/param.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/file/param.h	(revision 3)
@@ -0,0 +1,32 @@
+#ifndef PARAM_H
+#define PARAM_H
+
+#include <stdint.h>
+#include <iostream>
+#include "slot.h"
+#include "file.h"
+
+using namespace std;
+using namespace hierarchy_memory::sort_file;
+
+namespace hierarchy_memory
+{
+  namespace sort_file
+  {
+    class param_t
+    {
+    public : char   * name;
+    public : uint32_t size;
+
+    public : param_t (char * name,
+		      uint32_t size)
+      {
+	this->name = name;
+	this->size = size;
+      }
+    };
+
+  }; //sort_file
+}; //hierarchy_memory
+#endif //!PARAM_H
+  
Index: /trunk/IPs/systemC/hierarchy_memory/file/slot.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/file/slot.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/file/slot.h	(revision 3)
@@ -0,0 +1,39 @@
+#ifndef SLOT_H
+#define SLOT_H
+
+#include <stdint.h>
+#include <iostream>
+
+using namespace std;
+
+namespace hierarchy_memory
+{
+  namespace sort_file
+  {
+    template <class T>
+    class slot_t
+    {
+    public    : uint32_t       delay;     // delay of disponibilty of data
+    public    : T              data;
+
+    public    : slot_t ()
+      {
+      }
+
+    public    : slot_t (uint32_t delay, T data)
+      {
+	this->delay = delay;
+	this->data  = data;
+      }
+	
+    public    : friend ostream& operator<< (ostream& output_stream, const slot_t & x)
+      {
+	output_stream << x.delay << " " << x.data;	
+	return output_stream;
+      }
+    };
+   
+  }; //sort_file
+}; //hierarchy_memory
+#endif //!SLOT_H
+  
Index: /trunk/IPs/systemC/hierarchy_memory/file/sort_file.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/file/sort_file.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/file/sort_file.h	(revision 3)
@@ -0,0 +1,165 @@
+#ifndef SORT_FILE_H
+#define SORT_FILE_H
+
+#include <stdint.h>
+#include <iostream>
+#include "file.h"
+#include "slot.h"
+#include "param.h"
+
+using namespace std;
+using namespace hierarchy_memory::sort_file;
+
+namespace hierarchy_memory
+{
+  namespace sort_file
+  {
+    /*
+     * Cicurlar file, sort by delay
+     */
+
+    template <class T>
+    class Sort_File : public File<T>
+    {
+      // *****[ variables ]*****
+    protected : uint32_t       ptr_read;  // pointer of the next slot to read
+    protected : uint32_t       ptr_write; // pointer of the next slot to write
+      
+      // *****[ constructor ]*****
+    public : Sort_File (param_t param) : File <T> (param.name,param.size)
+      {
+	
+      };
+      
+      // *****[ destructor ]*****
+    public : ~Sort_File ()
+      {
+      };
+      
+      // *****[ reset ]*****
+      // Reset the file in the empty state
+    public : void reset ()
+      {
+	ptr_read  = 0;
+	ptr_write = 0;
+	File <T>::nb_slot   = 0;
+	//nb_slot   = 0;
+      };
+      
+      // *****[ transition ]*****
+      // Decrease the delay at all cycle
+    public : void transition ()
+      {
+	for (uint32_t it = 0; it < File <T>::nb_slot; it ++)
+	  {
+	    uint32_t ptr = (ptr_read + it)%File <T>::size;
+	    
+	    if (File <T>::slot[ptr].delay != 0)
+	      File <T>::slot[ptr] .delay --;
+	  }
+      }
+      
+      // *****[ read ]*****
+      // return the n-eme slot.
+      // (first = 0)
+    public : slot_t<T> read (uint32_t num)
+      {
+	if (num >= File <T>::nb_slot)
+	  {
+	    cerr << "<Sort_File.read> {ERROR} can't read because : num (" << num << ") >= nb_slot (" << File <T>::nb_slot << ")" << endl;
+	    exit(1);
+	  }
+
+	return File <T>::slot[(ptr_read + num)%File <T>::size];
+      };
+      
+      // *****[ pop ]*****
+      // read the file, and update the pointer
+    public : T pop  ()
+      {
+	return pop (0);
+      }
+
+      // *****[ pop ]*****
+      // read the file, and update the pointer
+    public : T pop  (uint32_t num)
+      {
+	if (num >= File <T>::nb_slot)
+	  {
+	    cerr << "<Sort_File.pop> {ERROR} can't read because : num (" << num << ") >= nb_slot (" << File <T>::nb_slot << ")" << endl;
+	    exit(1);
+	  }
+
+	T val = File <T>::slot [(ptr_read+num)%File <T>::size].data;
+	
+	// Reorganize the file
+
+ 	for (uint32_t it = 0; it < num; it ++)
+	  {
+	    uint32_t ptr      = (ptr_read + num - it   )%File <T>::size;
+	    uint32_t ptr_next = (ptr-1)%File <T>::size;
+
+	    File <T>::slot [ptr] = File <T>::slot [ptr_next];
+	  }
+
+	File <T>::nb_slot --;
+	ptr_read = (ptr_read+1)%File <T>::size;
+	
+	return val;
+      }
+      
+      // *****[ push ]*****
+      // Push a new value (they must have a slot free)
+      // Is sort by delay
+    public : bool push (uint32_t delay, T val)
+      {
+	// If full -> quit
+	if (File <T>::nb_slot == File <T>::size)
+	  return false;
+	
+	uint32_t ptr = ptr_write;
+	
+	// Scan the fill to find the good position (keep the sort)
+	for (uint32_t it = 0; it < File <T>::nb_slot; it ++)
+	  {
+	    uint32_t ptr_scan = (ptr-1)%File <T>::size;
+	    
+	    if (File <T>::slot[ptr_scan].delay <= delay)
+	      break; //find
+	    
+	    // reformor the file
+	    File <T>::slot [ptr] = File <T>::slot [ptr_scan];
+	    ptr                  = ptr_scan;
+	  }
+	
+	File <T>::slot [ptr] = slot_t <T> (delay,val);
+	ptr_write            = (ptr_write+1)%File <T>::size; // update the pointer
+	File <T>::nb_slot ++;
+	
+	return true;
+      }
+
+      // *****[ print ]*****
+    public    : friend ostream& operator<< (ostream& output_stream, const Sort_File & x)
+      {
+	output_stream << "<" << x.name << ">" << endl;
+	output_stream << " * ptr_read    : " << x.ptr_read  << endl;
+	output_stream << " * ptr_write   : " << x.ptr_write << endl;
+	output_stream << " * nb_slot     : " << x.nb_slot   << endl;
+	output_stream << " * size        : " << x.size      << endl;
+	
+	for (uint32_t it = 0; it < x.nb_slot; it ++)
+	  {
+	    uint32_t ptr = (x.ptr_read+it)%x.size;
+	    output_stream << x.slot [ptr] << endl;
+	  }
+	
+	return output_stream;
+      };
+
+    };
+    
+  }; //sort_file
+}; //hierarchy_memory
+#endif //!SORT_FILE_H
+  
Index: /trunk/IPs/systemC/hierarchy_memory/file/sort_file_dynamic.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/file/sort_file_dynamic.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/file/sort_file_dynamic.h	(revision 3)
@@ -0,0 +1,224 @@
+#ifndef SORT_FILE_DYNAMIC_H
+#define SORT_FILE_DYNAMIC_H
+
+#include <stdint.h>
+#include <iostream>
+#include "file.h"
+#include "slot.h"
+#include "param.h"
+
+using namespace std;
+
+namespace hierarchy_memory
+{
+  namespace sort_file
+  {
+    /*
+     * File, sort by delay with a dynamic size
+     */
+    
+    template <class T>
+    class Sort_File_Dynamic : public File<T>
+    {
+      // *****[ variables ]*****
+    protected : uint32_t       ptr_read ; // pointer of the next slot to read
+    protected : uint32_t       ptr_write; // pointer of the next slot to write
+    private   : uint32_t       factor   ;
+    private   : const uint32_t size_base;
+      // *****[ constructor ]*****
+    public : Sort_File_Dynamic (param_t param) : File <T> (param.name,param.size), size_base (param.size)
+      {
+	factor = 1;
+      };
+      
+      // *****[ destructor ]*****
+    public : ~Sort_File_Dynamic ()
+      {
+      };
+      
+      // *****[ must_decrease ]*****
+      // Test if the file must be decrease
+    private : bool must_decrease (void)
+      {
+	return ( (factor                         > 1             ) &&
+		 (((100*File <T>::nb_slot)/File <T>::size) <= 33));
+      }
+
+      // *****[ must_increase ]*****
+      // Test if the file must be increase
+    private : bool must_increase (void)
+      {
+	return (((100*File <T>::nb_slot)/File <T>::size) >= 90);
+      }
+
+      // *****[ increase ]*****
+      // increase the file
+    private : void increase (void)
+      {
+	factor ++;
+	change_size (factor*size_base);
+      }
+      
+      // *****[ decrease ]*****
+      // decrease the file
+    private : void decrease (void)
+      {
+	factor --;
+	change_size (factor*size_base);
+      }
+
+      // *****[ change_size ]*****
+      // decrease the file
+    private : void change_size (uint32_t new_size)
+      {
+	uint32_t    old_size = File <T>::size;
+	slot_t<T> * new_slot = new slot_t<T> [new_size];
+
+	// copy data
+	for (uint32_t it = 0; it < File <T>::nb_slot; it ++)
+	  {
+	    uint32_t ptr = (ptr_read+it)%old_size;
+	    
+	    new_slot [it] = File <T>::slot [ptr];
+	  }
+	// Change information
+	delete File <T>::slot;
+	File <T>::slot = new_slot;
+	File <T>::size = new_size;
+	ptr_write      = File <T>::nb_slot;
+	ptr_read       = 0;
+      }
+      
+      // *****[ reset ]*****
+      // Reset the file in the empty state
+    public : void reset (void)
+      {
+	ptr_read  = 0;
+	ptr_write = 0;
+	File <T>::nb_slot   = 0;
+	//nb_slot   = 0;
+      };
+      
+      // *****[ transition ]*****
+      // Decrease the delay at all cycle
+    public : void transition ()
+      {
+	for (uint32_t it = 0; it < File <T>::nb_slot; it ++)
+	  {
+	    uint32_t ptr = (ptr_read + it)%File <T>::size;
+	    
+	    if (File <T>::slot[ptr].delay != 0)
+	      File <T>::slot[ptr] .delay --;
+	  }
+      }
+      
+      // *****[ read ]*****
+      // return the n-eme slot.
+      // (first = 0)
+    public : slot_t<T> read (uint32_t num)
+      {
+	if (num >= File <T>::nb_slot)
+	  {
+	    cerr << "<Sort_File_Dynamic.read> {ERROR} can't read because : num (" << num << ") >= nb_slot (" << File <T>::nb_slot << ")" << endl;
+	    exit(1);
+	  }
+
+	return File <T>::slot[(ptr_read + num)%File <T>::size];
+      };
+      
+      // *****[ pop ]*****
+      // read the file, and update the pointer
+    public : T pop  ()
+      {
+	return pop (0);
+      }
+
+      // *****[ pop ]*****
+      // read the file, and update the pointer
+    public : T pop  (uint32_t num)
+      {
+	if (num >= File <T>::nb_slot)
+	  {
+	    cerr << "<Sort_File_Dynamic.pop> {ERROR} can't read because : num (" << num << ") >= nb_slot (" << File <T>::nb_slot << ")" << endl;
+	    exit(1);
+	  }
+
+	// If full -> quit
+	if (must_decrease() == true)
+	  decrease();
+
+
+	T val = File <T>::slot [(ptr_read+num)%File <T>::size].data;
+	
+	// Reorganize the file
+
+ 	for (uint32_t it = 0; it < num; it ++)
+	  {
+	    uint32_t ptr      = (ptr_read + num - it   )%File <T>::size;
+	    uint32_t ptr_next = (ptr-1)%File <T>::size;
+
+	    File <T>::slot [ptr] = File <T>::slot [ptr_next];
+	  }
+
+	File <T>::nb_slot --;
+	ptr_read = (ptr_read+1)%File <T>::size;
+	
+	return val;
+      }
+      
+      // *****[ push ]*****
+      // Push a new value (they must have a slot free)
+      // Is sort by delay
+    public : bool push (uint32_t delay, T val)
+      {
+	// If full -> quit
+	if (must_increase() == true)
+	  increase();
+
+	uint32_t ptr = ptr_write;
+	
+	// Scan the fill to find the good position (keep the sort)
+	for (uint32_t it = 0; it < File <T>::nb_slot; it ++)
+	  {
+	    uint32_t ptr_scan = (ptr != 0)?ptr:(File <T>::size);
+	    ptr_scan --;
+
+	    if (File <T>::slot[ptr_scan].delay <= delay)
+	      break; //find
+	    
+	    // reformor the file
+	    File <T>::slot [ptr] = File <T>::slot [ptr_scan];
+	    ptr                  = ptr_scan;
+	  }
+
+	File <T>::slot [ptr] = slot_t <T> (delay,val);
+	ptr_write            = (ptr_write+1)%File <T>::size; // update the pointer
+	File <T>::nb_slot ++;
+	
+	return true;
+      }
+      // *****[ print ]*****
+    public    : friend ostream& operator<< (ostream& output_stream, const Sort_File_Dynamic & x)
+      {
+	output_stream << "<" << x.name << ">" << endl;
+	output_stream << " * ptr_read    : " << x.ptr_read  << endl;
+	output_stream << " * ptr_write   : " << x.ptr_write << endl;
+	output_stream << " * nb_slot     : " << x.nb_slot   << endl;
+	output_stream << " * size        : " << x.size      << endl;
+	output_stream << " * factor      : " << x.factor    << endl;
+	
+	for (uint32_t it = 0; it < x.nb_slot; it ++)
+	  {
+	    uint32_t ptr = (x.ptr_read+it)%x.size;
+	    output_stream << x.slot [ptr] << endl;
+	  }
+	
+	return output_stream;
+      };
+      
+
+    };
+  }; //sort_file
+}; //hierarchy_memory
+#endif //!SORT_FILE_DYNAMIC_H
+  
Index: /trunk/IPs/systemC/hierarchy_memory/hierarchy_memory.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/hierarchy_memory.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/hierarchy_memory.h	(revision 3)
@@ -0,0 +1,952 @@
+#ifndef HIERARCHY_MEMORY_H
+#define HIERARCHY_MEMORY_H
+#include <iostream>
+#include <stdint.h>
+#include <stdarg.h>
+
+#include <systemc.h>
+#include "shared/soclib_segment_table.h"
+#include "shared/soclib_caches_interfaces.h"
+
+#include "hierarchy_memory/data/data.h"
+#include "hierarchy_memory/file/sort_file.h"
+#include "hierarchy_memory/file/entry.h"
+#include "hierarchy_memory/cache/cache.h"
+#include "hierarchy_memory/ramlock/ramlock.h"
+#include "hierarchy_memory/tty/tty.h"
+#include "hierarchy_memory/sim2os/sim2os.h"
+
+#include "hierarchy_memory/cache/type_req_cache.h"
+
+using namespace std;
+using namespace hierarchy_memory::data;
+using namespace hierarchy_memory::sort_file;
+using namespace hierarchy_memory::cache;
+using namespace hierarchy_memory::ramlock;
+using namespace hierarchy_memory::tty;
+using namespace hierarchy_memory::sim2os;
+
+namespace hierarchy_memory
+{
+  template <class T>
+  class param_entity_t
+  {
+  public : uint32_t address ;
+  public : uint32_t size    ;
+  public : T        param   ;
+    
+  public : param_entity_t () {};
+
+  public : param_entity_t (uint32_t address ,
+			   uint32_t size    ,
+			   T        param   )
+    {
+      this->address = address ;
+      this->size    = size    ;
+      this->param   = param   ;
+    }
+  };//end param_entity_t
+
+  class param_t
+  {
+  public : uint32_t                            nb_entity_tty;
+  public : param_entity_t <tty::param_t>     * param_tty;
+  public : uint32_t                            nb_entity_ramlock;
+  public : param_entity_t <ramlock::param_t> * param_ramlock;
+  public : param_entity_t <sim2os::param_t>    param_sim2os;
+  public : cache::param_t                      param_cache;
+
+  public : param_t () {};
+
+  public : param_t (uint32_t                            nb_entity_tty     ,
+		    param_entity_t <tty::param_t>     * param_tty         ,
+		    uint32_t                            nb_entity_ramlock ,
+		    param_entity_t <ramlock::param_t> * param_ramlock     ,
+		    param_entity_t <sim2os::param_t>    param_sim2os      ,
+		    cache::param_t                      param_cache)
+    {
+      this->nb_entity_tty     = nb_entity_tty;
+      this->param_tty         = param_tty;
+      this->nb_entity_ramlock = nb_entity_ramlock;
+      this->param_ramlock     = param_ramlock;
+      this->param_sim2os      = param_sim2os;
+      this->param_cache       = param_cache;
+    }
+  };//end param_t
+
+  template<uint32_t SIZE_TRDID    ,
+	   uint32_t SIZE_IPKTID   ,
+	   uint32_t SIZE_IADDR    ,
+	   uint32_t SIZE_IDATA    ,
+	   uint32_t NB_IWORD      ,
+	   uint32_t SIZE_DPKTID   ,
+	   uint32_t SIZE_DADDR    ,
+	   uint32_t SIZE_DDATA    
+	   >
+
+  class HIERARCHY_MEMORY : sc_module 
+  {
+    //---------------------------------------------------------------------------------------------
+    //-----[ PORT ]--------------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+
+  public : sc_in_clk                                                                        CLK;
+  public : sc_in<bool>                                                                      NRESET;
+  public : ICACHE_CACHE_PORTS<SIZE_TRDID, SIZE_IPKTID, SIZE_IADDR, SIZE_IDATA, NB_IWORD> ** ICACHE;
+  public : DCACHE_CACHE_PORTS<SIZE_TRDID, SIZE_DPKTID, SIZE_DADDR, SIZE_DDATA>           ** DCACHE;
+
+    //---------------------------------------------------------------------------------------------
+    //-----[ INTERNAL SIGNAL ]---------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+  private: bool                                                                          ** irsp_val;
+  private: bool                                                                          ** drsp_val;
+
+  private: bool                                                                          ** ireq_ack;
+  private: bool                                                                          ** dreq_ack;
+    
+    //---------------------------------------------------------------------------------------------
+    //-----[ COMPONENT ]---------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+  private: Data                                                                           * component_data;
+  private: Sort_File<Entry>                                                              ** component_buffer_irsp;
+  private: Sort_File<Entry>                                                              ** component_buffer_drsp;
+
+  private: Sim2os                                                                         * component_sim2os;
+  private: Tty                                                                           ** component_tty;
+  private: Ramlock                                                                       ** component_ramlock;
+
+  private: Cache                                                                          * component_cache;
+    //---------------------------------------------------------------------------------------------
+    //-----[ VARIABLE ] ---------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+
+  private: char                                                                           * NAME;                    // instance name
+  private: uint32_t                                                                       * nb_iport;
+  private: uint32_t                                                                       * nb_dport;
+  private: const uint32_t                                                                   nb_context;
+  private: const uint32_t                                                                   nb_entity;
+  private: const uint32_t                                                                   nb_entity_tty;
+  private: const uint32_t                                                                   nb_entity_ramlock;
+
+  private: char **                                                                          read_iram;
+  private: char *                                                                           read_dram;
+  private: char *                                                                           write_dram;
+
+  private: bool                                                                           * context_stop;    // to determine which context have send the signal stop (a same thread can send many signal)
+  private: uint32_t                                                                         nb_context_stop; // stop the simulation when all context have send the stop signal 
+    //---------------------------------------------------------------------------------------------
+    //-----[ CONSTRUCTOR ]-------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+    SC_HAS_PROCESS(HIERARCHY_MEMORY);
+    
+  public : HIERARCHY_MEMORY (// Fixe parameter
+			     sc_module_name              insname               ,
+			     uint32_t                    globalIndex           , // VCI target index
+			     uint32_t                    localIndex            ,
+			     SOCLIB_SEGMENT_TABLE      * segtab                , // segment table pointer
+			     // variable parameter			           
+			     uint32_t                    nb_entity             ,
+			     uint32_t                    nb_context            ,
+			     //*****[ buffer respons ]*****	           
+			     uint32_t                    size_buffer_irsp      ,
+			     uint32_t                    size_buffer_drsp      ,
+			     //*****[ entity_param   ]*****
+			     param_t                     param        				  
+			     ):
+    nb_context        (nb_context             ),
+    nb_entity         (nb_entity              ),
+    nb_entity_tty     (param.nb_entity_tty    ),
+    nb_entity_ramlock (param.nb_entity_ramlock)
+    {
+      uint32_t size_name = strlen(insname)+1;
+      NAME               = new char [size_name];
+      strncpy(NAME,insname,size_name);
+
+      // *****[ Signal creation ]*****
+      ICACHE = new ICACHE_CACHE_PORTS<SIZE_TRDID, SIZE_IPKTID, SIZE_IADDR, SIZE_IDATA, NB_IWORD> * [nb_entity];
+      DCACHE = new DCACHE_CACHE_PORTS<SIZE_TRDID, SIZE_DPKTID, SIZE_DADDR, SIZE_DDATA>           * [nb_entity];
+
+      nb_iport     = new uint32_t     [nb_entity];
+      nb_dport     = new uint32_t     [nb_entity];
+	           		      
+      irsp_val     = new bool *       [nb_entity];
+      drsp_val     = new bool *       [nb_entity];
+	           		      
+      ireq_ack     = new bool *       [nb_entity];
+      dreq_ack     = new bool *       [nb_entity];
+
+      for (uint32_t it = 0; it < nb_entity; it++)
+	{
+	  nb_iport     [it] = param.param_cache.param_icache_dedicated [it].nb_port;
+	  nb_dport     [it] = param.param_cache.param_dcache_dedicated [it].nb_port;
+		      
+	  irsp_val     [it] = new bool       [nb_iport[it]];
+	  drsp_val     [it] = new bool       [nb_dport[it]];
+		     
+	  ireq_ack     [it] = new bool       [nb_iport[it]];
+	  dreq_ack     [it] = new bool       [nb_dport[it]];
+
+	  ICACHE [it] = new ICACHE_CACHE_PORTS<SIZE_TRDID, SIZE_IPKTID, SIZE_IADDR, SIZE_IDATA, NB_IWORD> [nb_iport [it]];
+	  DCACHE [it] = new DCACHE_CACHE_PORTS<SIZE_TRDID, SIZE_DPKTID, SIZE_DADDR, SIZE_DDATA>           [nb_dport [it]];
+	}
+
+      read_iram = new char * [NB_IWORD];
+      for (unsigned int num_word = 0; num_word < NB_IWORD; num_word ++)
+	read_iram [num_word] = new char [SIZE_IDATA/8]; 
+
+      read_dram  = new char [SIZE_DDATA/8];
+      write_dram = new char [SIZE_DDATA/8];
+
+      // *****[ Create internal structure ]*****
+
+      component_data        = new Data     (data::param_t("component_data", 16, globalIndex, localIndex, segtab));
+      component_buffer_irsp = new Sort_File<Entry> * [nb_entity];
+      component_buffer_drsp = new Sort_File<Entry> * [nb_entity];
+
+      for (uint32_t it = 0; it < nb_entity; it++)
+	{
+	  char name [100];
+	  sprintf(name,"component_buffer_irsp[%d]",it);
+	  component_buffer_irsp [it] = new Sort_File<Entry> (sort_file::param_t(name,size_buffer_irsp));
+	  sprintf(name,"component_buffer_drsp[%d]",it);
+	  component_buffer_drsp [it] = new Sort_File<Entry> (sort_file::param_t(name,size_buffer_drsp));
+	  
+	}
+
+      component_cache       = new Cache   (param.param_cache);
+      component_tty         = new Tty     * [nb_entity_tty    ];
+      component_ramlock     = new Ramlock * [nb_entity_ramlock];
+
+      for (uint32_t it = 0; it < nb_entity_tty    ; it++)
+	{
+	  component_tty     [it] = new Tty     (param.param_tty[it]    .param);
+	  entity_t entity = component_data->entity(param.param_tty[it].address,     param.param_tty[it].size);
+	  
+	  if (entity.present == false)
+	    {
+	      cerr << "<HIERARCHY_MEMORY> the tty [" << it << "] have not a segment in the segment table" << endl;
+	      exit (1);
+	    }
+
+	  entity.segment->define_target(TYPE_TTY,it);
+	} 
+
+      for (uint32_t it = 0; it < nb_entity_ramlock; it++)
+	{
+	  component_ramlock [it] = new Ramlock (param.param_ramlock[it].param);
+	  entity_t entity = component_data->entity(param.param_ramlock[it].address, param.param_ramlock[it].size);
+
+	  if (entity.present == false)
+	    {
+	      cerr << "<HIERARCHY_MEMORY> the ramlock [" << it << "] have not a segment in the segment table" << endl;
+	      exit (1);
+	    }
+
+	  entity.segment->define_target(TYPE_RAMLOCK,it);
+	}
+
+      component_sim2os = new Sim2os   (param.param_sim2os.param);
+      entity_t entity  = component_data->entity(param.param_sim2os.address, param.param_sim2os.size);
+
+      if (entity.present == false)
+	{
+	  cerr << "<HIERARCHY_MEMORY> the sim2os have not a segment in the segment table" << endl;
+	  exit (1);
+	}
+      
+      entity.segment->define_target(TYPE_SIM2OS,0);
+
+      nb_context_stop = 0;
+      context_stop    = new bool [1<<SIZE_TRDID]; // the number of context is include in the REQ_TRDID
+      for (uint32_t num_thread = 0; num_thread < (1<<SIZE_TRDID); num_thread ++)
+	context_stop [num_thread] = false;
+      
+      // *****[ Definition of method ]*****
+      SC_METHOD (transition);
+      sensitive_pos << CLK;
+      
+      SC_METHOD (genMoore);
+      sensitive_neg << CLK;
+
+      cout << "<" << NAME << "> Successful Instanciation" << endl;
+    };
+    
+    //---------------------------------------------------------------------------------------------
+    //-----[ DESTRUCTOR ]--------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+  public : ~HIERARCHY_MEMORY ()
+    {
+      for (uint32_t it = 0; it < nb_entity_ramlock; it++)
+	delete component_ramlock [it];      
+      for (uint32_t it = 0; it < nb_entity_tty    ; it++)
+	delete component_tty     [it];
+
+      for (uint32_t it = 0; it < nb_entity        ; it++)
+	{
+	  delete component_buffer_drsp [it];
+	  delete component_buffer_irsp [it];
+	}
+
+      delete component_cache       ;
+      delete component_data        ;
+      delete component_sim2os      ;
+    }
+
+    //---------------------------------------------------------------------------------------------
+    //-----[ req_type2cache_type ]-----------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+
+    class req_type2cache_type_t
+    {
+    public : type_req_cache_t      type      ;
+    public : direction_req_cache_t direction ;
+
+    public : req_type2cache_type_t () {};
+
+    public : req_type2cache_type_t (type_req_cache_t      type      ,
+				    direction_req_cache_t direction )
+      {
+	this->type      = type     ;
+	this->direction = direction;
+      };
+    };
+
+    req_type2cache_type_t ireq_type2cache_type (uint32_t ireq_type, bool uncached)
+    {
+      type_req_cache_t      type     ;
+      direction_req_cache_t direction;
+      
+      switch (ireq_type)
+	{
+	case ITYPE_READ       : direction=READ ; type=CACHED    ; break;
+	case ITYPE_INVALIDATE : direction=NONE ; type=INVALIDATE; break;
+	case ITYPE_PREFETCH   : direction=NONE ; type=PREFETCH  ; break;
+	default : cerr << "<HIERARCHY_MEMORY.ireq_type2cache_type> Unkown type (" << type << ")" << endl; exit(1);
+	}
+
+      return req_type2cache_type_t (type,direction);
+    }
+
+    req_type2cache_type_t dreq_type2cache_type (uint32_t dreq_type, bool uncached)
+    {
+      type_req_cache_t      type     ;
+      direction_req_cache_t direction;
+      
+      switch (dreq_type)
+	{
+	case DTYPE_READ       : direction=READ ; type=((uncached==true)?UNCACHED:CACHED); break;
+	case DTYPE_INVALIDATE : direction=NONE ; type=INVALIDATE                        ; break;
+	case DTYPE_WRITE      : direction=WRITE; type=((uncached==true)?UNCACHED:CACHED); break;
+	case DTYPE_WRITE_ACK  : direction=WRITE; type=((uncached==true)?UNCACHED:CACHED); break;
+	case DTYPE_FLUSH      : direction=NONE ; type=FLUSH                             ; break;
+	case DTYPE_PREFETCH   : direction=NONE ; type=INVALIDATE                        ; break;
+	  
+	default : cerr << "<HIERARCHY_MEMORY.ireq_type2cache_type> Unkown type (" << type << ")" << endl; exit(1);
+	}
+
+      return req_type2cache_type_t (type,direction);
+    }
+    //---------------------------------------------------------------------------------------------
+    //-----[ init ]--------------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+  public : bool init (char * section, const char * filename, const char ** list_section)
+    {
+      return component_data->init(section,filename,list_section);
+    }
+    //---------------------------------------------------------------------------------------------
+    //-----[ reset ]-------------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+  public : void reset ()
+    {
+      component_cache -> reset();
+      // Reset buffer of respons
+      for (uint32_t it = 0; it < nb_entity; it++)
+	{
+	  component_buffer_irsp [it] ->reset();
+	  component_buffer_drsp [it] ->reset();
+	}
+      for (uint32_t it = 0; it < nb_entity_ramlock; it++)
+	component_ramlock [it]   ->reset();
+      for (uint32_t it = 0; it < nb_entity_tty    ; it++)
+	component_tty     [it]   ->reset();
+    }//end reset
+
+    //---------------------------------------------------------------------------------------------
+    //-----[ itoa ]--------------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+  private :char * itoa (uint32_t int_src, char * string_dest, uint32_t size)
+    {
+      for (unsigned int it_size = 0; it_size < size; it_size ++)
+	{
+	  string_dest [it_size] = (int_src & 0xFF);
+	  //string_dest [size-it_size-1] = (int_src & 0xFF);
+
+	  int_src >>= 8;
+	}
+      return string_dest;
+    }
+
+    //---------------------------------------------------------------------------------------------
+    //-----[ stop ]--------------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+  public : bool stop ()
+    {
+      return (nb_context_stop >= nb_context);
+    }
+
+    //---------------------------------------------------------------------------------------------
+    //-----[ transition ]--------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+  public : void transition()
+    {
+      if (NRESET.read() == false)
+	{
+	  reset ();
+	  return;
+	}
+      
+      //~~~~~[ respons ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+      // POP All buffer of respons
+      for (uint32_t num_entity = 0; num_entity < nb_entity; num_entity++)
+	{
+	  for (uint32_t num_port = nb_iport [num_entity]; num_port > 0 ; num_port --)
+	    if ((irsp_val[num_entity][num_port-1] && ICACHE [num_entity][num_port-1].RSP_ACK.read())==true)
+	      component_buffer_irsp [num_entity]->pop(num_port-1);
+	  
+	  for (uint32_t num_port = nb_dport [num_entity]; num_port > 0 ; num_port --)
+	    if ((drsp_val[num_entity][num_port-1] && DCACHE [num_entity][num_port-1].RSP_ACK.read())==true)
+	      component_buffer_drsp [num_entity]->pop(num_port-1);
+	}
+
+      //~~~~~[ request ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+      //       cout << "<HIERARCHY_MEMORY.transition>" << endl;
+      for (uint32_t num_entity = 0; num_entity < nb_entity; num_entity++)
+	{
+	  // ******************
+	  // ***** ICACHE *****
+	  // ******************
+	  for (uint32_t num_port = 0; num_port < nb_iport [num_entity]; num_port ++)
+	    {
+	      // Test if transaction
+	      if ( (ICACHE [num_entity][num_port].REQ_VAL.read() && ireq_ack [num_entity][num_port]) == false)
+		continue;
+
+	      entity_t entity    = component_data->entity((uint32_t)ICACHE [num_entity][num_port].REQ_ADDR.read(), SIZE_IDATA/8);
+	      bool     uncached  = false;
+	      bool     bus_error = false;
+	      
+	      sc_uint<2>           type           = ICACHE[num_entity][num_port].REQ_TYPE  .read();
+	      // A lot of flag
+	      bool                 must_read      = ((type == DTYPE_READ      ) );
+	      bool                 must_ack       = ((type == DTYPE_READ      ) );
+	      
+	      // Test the type of the address : if != MEMORY -> error
+	      if ((entity.present == true) && (entity.segment->getType() == TYPE_MEMORY))
+		{
+		if (must_read == true) // Test if must read the ram
+		  for (unsigned int num_word = 0; num_word < NB_IWORD; num_word ++)
+		    {
+		      uint32_t addr = (uint32_t) ICACHE [num_entity][num_port].REQ_ADDR.read()+num_word*(SIZE_IDATA/8);
+		      bus_error |= !component_data->read(addr               ,
+							SIZE_IDATA/8       ,
+							read_iram[num_word]);
+		      
+		      if (isSameEndianness((uint32_t)ICACHE[num_entity][num_port].REQ_TRDID.read()) == false) 
+			read_iram[num_word] = swapBytes(read_iram[num_word],SIZE_IDATA/8,4);
+		    }
+		uncached = entity.segment->getUncached();
+		}
+		else
+		  {
+		    // Have a bus error
+		    bus_error = true;
+		    uncached  = true;
+		  }
+
+	      req_type2cache_type_t cache_type = ireq_type2cache_type ((uint32_t)type,uncached);
+	      // Simplification : the size of a line is a multiple of size_iword (no test)
+	      uint32_t latence = component_cache->latence(INSTRUCTION_CACHE                                        ,
+							  num_entity                                               ,
+							  num_port                                                 ,
+							  (uint32_t)ICACHE [num_entity][num_port].REQ_ADDR .read() ,
+							  (uint32_t)ICACHE [num_entity][num_port].REQ_TRDID.read() ,
+							  cache_type.type                                          ,
+							  cache_type.direction                                     );
+	      
+	      // If is a respons -> compute the latence and push in the write_buffer
+	      if (must_ack == true)
+		{
+		  if (bus_error == true)
+		    cout << "Icache : have a bus error" << endl
+			 << "  * num_entity : " << num_entity << endl
+			 << "  * num_port   : " << num_port   << endl
+			 << hex
+			 << "  * req_addr   : " << (uint32_t)ICACHE [num_entity][num_port].REQ_ADDR .read() << endl
+			 << dec
+			 << "  * req_trdid  : " << (uint32_t)ICACHE [num_entity][num_port].REQ_TRDID.read() << endl
+			 << "  * req_pktid  : " << (uint32_t)ICACHE [num_entity][num_port].REQ_PKTID.read() << endl;
+		  
+		  component_buffer_irsp [num_entity]->push(latence,
+							   Entry((uint32_t)ICACHE [num_entity][num_port].REQ_TRDID.read() ,
+								 (uint32_t)ICACHE [num_entity][num_port].REQ_PKTID.read() ,
+								 NB_IWORD                                                 ,
+								 SIZE_IDATA/8                                             ,
+								 read_iram                                                ,
+								 (bus_error==true)?ERR_BUS:ERR_NO                         )
+							   );			
+		}
+	    }//num_port
+
+	  // ******************
+	  // ***** DCACHE *****
+	  // ******************
+
+	  for (uint32_t num_port = 0; num_port < nb_dport [num_entity]; num_port ++)
+	    {
+	      // Test if transaction
+// 	      cout << "[" << num_entity << "]"
+// 		   << "[" << num_port   << "] "
+// 		   << "dreq_val : " << DCACHE [num_entity][num_port].REQ_VAL.read() << " "
+// 		   << "dreq_ack : " << dreq_ack [num_entity][num_port] << endl;
+
+	      if ( (DCACHE [num_entity][num_port].REQ_VAL.read() && dreq_ack [num_entity][num_port]) == false)
+		continue;
+	      
+	      entity_t             entity         = component_data->entity((uint32_t)DCACHE [num_entity][num_port].REQ_ADDR.read(), SIZE_DDATA/8);
+
+	      bool                 uncached       = DCACHE [num_entity][num_port].REQ_UNC.read();
+	      bool                 bus_error      = false;
+	      
+	      uint32_t             addr           = (uint32_t) DCACHE [num_entity][num_port].REQ_ADDR.read();
+	      sc_uint<SIZE_DDATA>  wdata          = DCACHE[num_entity][num_port].REQ_WDATA .read();
+	      sc_uint<3>           type           = DCACHE[num_entity][num_port].REQ_TYPE  .read();
+	      uint32_t             nb_bytes       = access_nb_bytes(DCACHE[num_entity][num_port].REQ_ACCESS.read());
+	      // A lot of flag
+	      bool                 must_read      = ((type == DTYPE_READ      ));
+	      bool                 must_write     = ((type == DTYPE_WRITE     ) ||
+						     (type == DTYPE_WRITE_ACK ) );
+	      bool                 must_ack       = ((type == DTYPE_READ      ) ||
+						     (type == DTYPE_WRITE_ACK ) );
+
+	      // Test the type of the address
+	      if (entity.present == true)
+		{
+		switch (entity.segment->getType())
+		  {
+		    // ACCESS AT A RAM
+		  case TYPE_MEMORY  : 
+		    {
+		      if (must_read == true)
+			{
+			  // Read
+			  bus_error |= !component_data->read(addr         ,
+							    SIZE_DDATA/8 , // always read a complete word
+							    read_dram    );
+			  
+			  for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes)
+			    memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes);
+
+			  // Permutation if problem of endianness
+			  if (isSameEndianness((uint32_t)DCACHE[num_entity][num_port].REQ_TRDID.read()) == false) 
+			    read_dram  = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes);
+			}
+		      
+		      if (must_write == true)
+			{
+			  // Write
+			  for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
+			    write_dram [it_nb_bytes] = wdata.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes);
+			}
+		      break;
+		    }
+		    //ACCESS AT THE TTY
+		  case TYPE_TTY     :
+		    {
+		      if (must_write == false)
+			{
+			  bus_error = true;
+			  break;
+			}
+		      uint32_t num_tty           = (addr - entity.segment->getBase())>>4;
+		      uint32_t num_print         = ((addr>>2) & 0x3);
+		      
+		      switch (num_print)
+			{
+			case 0 : // Write TTY
+			  {
+			    uint32_t num_component_tty = entity.segment->getIndex();
+			    char     char_write        = (char)wdata.range( 7, 0);
+			    bus_error |= !component_tty [num_component_tty]->write(num_tty,char_write);
+			    break;
+			  }
+			case 1 : // STOP
+			  {
+			    printf("\n\t***** [ stop    ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x         *****\n"
+				   ,(unsigned int)sc_simulation_time()
+				   ,(unsigned int)addr
+				   ,(unsigned int)wdata.range(31,24)
+				   ,(unsigned int)wdata.range(23,16)
+				   ,(unsigned int)wdata.range(15, 8)
+				   ,(unsigned int)wdata.range( 7, 0)
+				   );
+
+			    uint32_t trdid = (uint32_t) DCACHE[num_entity][num_port].REQ_TRDID.read();
+			    
+			    if (context_stop [trdid] == false)
+			      {
+				context_stop [trdid] = true;
+				nb_context_stop ++;
+
+				if (nb_context_stop >= nb_context)
+				  sc_stop();
+			      }
+
+			    break;
+			  }
+			case 2 : // PRINT
+			  {
+			    printf("\n\t----- [ print   ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x         -----\n"
+				   ,(unsigned int)sc_simulation_time()
+				   ,(unsigned int)addr
+				   ,(unsigned int)wdata.range(31,24)
+				   ,(unsigned int)wdata.range(23,16)
+				   ,(unsigned int)wdata.range(15, 8)
+				   ,(unsigned int)wdata.range( 7, 0)
+				   );
+			    
+			    break;
+			  }
+			default :
+			  {
+			    printf("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);
+			    exit(1);
+			  }
+			}
+		      
+		      break;
+		    }
+		  case TYPE_RAMLOCK :
+		    {
+		      // Access is on a byte, else error
+		      if (nb_bytes != 1)
+			{
+			  bus_error = true;
+			  break;
+			}
+		      uint32_t num_ramlock           = (addr - entity.segment->getBase()); // Char access
+		      uint32_t num_component_ramlock = entity.segment->getIndex();
+		      bus_error |= !component_ramlock [num_component_ramlock]->test(num_ramlock);
+		      
+		      if (bus_error == true)
+			break;
+		      
+		      memset (read_dram,0,SIZE_DDATA/8);
+			
+		      if (must_read == true)
+			read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock);
+		      if (must_write == true)
+			read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock);
+
+		      /*
+		      printf("Access ramlock   ( %d )\n" ,(uint32_t)sc_simulation_time());
+		      printf(" * addr          : %.8x\n" ,(uint32_t)addr);
+		      printf(" * trdid         : %d\n"   ,(uint32_t)DCACHE[num_entity][num_port].REQ_TRDID.read());
+		      printf(" * r/w           : %d/%d\n",must_read,must_write);
+		      printf(" * val           : %d\n"   ,(uint32_t)read_dram[0]);
+		      */
+		      break;
+		    }
+		  case TYPE_SIM2OS  :
+		    {
+		      // Mapping :
+		      // [0]  number of service - Wonly - A write in this register lunch the execution of service
+		      // [1]  result            - Ronly - Content the result of the service
+		      // [2]  error             - Ronly - Content the code of errno
+		      // [3+] argument          - Wonly - it's all argument to execute the service
+
+		      uint32_t num_reg = (addr - entity.segment->getBase())>>2;
+		      
+		      switch (num_reg)
+			{
+			case 0  : // ---> number of service
+			  {
+			    if (must_write == false)
+			      {
+				cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl;
+				bus_error = true;
+			      }
+			    else
+			      {
+				printf("<sim2os> service     : %.8x\n",(uint32_t)wdata);
+				component_sim2os->execute(int2service((uint32_t)wdata));
+			      }
+			  break;
+			  }
+			case 1  : // ---> result
+			  { 
+			    if (must_read == false)
+			      {
+				cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl;
+				bus_error = true;
+			      }
+			    else
+			      {
+				// Decomposition en groupe octect
+				uint32_t result = (uint32_t) component_sim2os->result;
+				printf("<sim2os> result      : %.8x (%d)\n",result,result);
+				
+				read_dram = itoa(result,read_dram,SIZE_DDATA/8);
+			      }
+			    break;
+			  }
+			case 2  : // ---> error
+			  {
+			    if (must_read == false)
+			      {
+				cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl;
+				bus_error = true;
+			      }
+			    else
+			      {
+				// Decomposition en groupe octect
+				uint32_t error = (uint32_t) component_sim2os->error;
+				printf("<sim2os> error       : %.8x\n",error);
+				read_dram = itoa(error ,read_dram,SIZE_DDATA/8);
+			      }
+			    break;
+			  }
+			default : // ---> argument
+			  { 
+			    if (must_write == false)
+			      {
+				cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl;
+				bus_error = true;
+			      }
+			    else
+			      {
+				uint32_t data = (uint32_t)wdata;
+				printf("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);
+				component_sim2os->parameter(num_reg-2,(void *)data);
+			      }
+			    break;
+			  }
+			}//end switch num_reg
+		      
+		      break;
+		    }
+		  default           :
+		    {
+		      // Have a bus error
+		      bus_error = true;
+		      break;
+		    }
+		  }// switch
+		uncached |= entity.segment->getUncached();
+		}
+	      else
+		uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist
+
+
+	      if ((must_write == true) && (bus_error == false))
+		{
+		  // Permutation if problem of endianness
+		  if (isSameEndianness((uint32_t)DCACHE[num_entity][num_port].REQ_TRDID.read()) == false) 
+		    write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes);
+		  
+		  bus_error |= !component_data->write(addr                   ,
+						     nb_bytes, // take the good access
+						     write_dram             );
+		}
+	      
+
+	      // Acces at the cache !!!
+	      req_type2cache_type_t cache_type = dreq_type2cache_type (type, uncached);
+	      
+	      uint32_t latence = component_cache->latence(DATA_CACHE                                               ,
+							  num_entity                                               ,
+							  num_port                                                 ,
+							  (uint32_t)DCACHE [num_entity][num_port].REQ_ADDR .read() ,
+							  (uint32_t)DCACHE [num_entity][num_port].REQ_TRDID.read() ,
+							  cache_type.type                                          ,
+							  cache_type.direction                                     );
+	      
+	      // If is a respons -> compute the latence and push in the write_buffer
+	      if ( must_ack == true)
+		{
+		  if (bus_error == true)
+		    cout << "Dcache : have a bus error" << endl;
+		  component_buffer_drsp [num_entity]->push(latence,
+							   Entry((uint32_t)DCACHE [num_entity][num_port].REQ_TRDID.read() ,
+								 (uint32_t)DCACHE [num_entity][num_port].REQ_PKTID.read() ,
+								 1                                                        ,
+								 SIZE_DDATA/8                                             ,
+								 &read_dram                                               ,
+								 (bus_error==true)?ERR_BUS:ERR_NO                         )
+							   );			
+		}
+	    }// dnb_port
+	}//num_entity
+      
+      // Transition for each component
+      component_cache -> transition();
+      // Transition buffer of respons
+      for (uint32_t it = 0; it < nb_entity; it++)
+	{
+	  component_buffer_irsp [it] ->transition();
+	  component_buffer_drsp [it] ->transition();
+	}
+      component_sim2os->transition();
+
+    }//end transition
+
+    //---------------------------------------------------------------------------------------------
+    //-----[ genMoore ]----------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+  public : void genMoore()
+    {
+      //Scan all entity and for each entity scan all port
+      for (uint32_t num_entity = 0; num_entity < nb_entity; num_entity++)
+	{
+	  //##### REQUEST #####
+	  uint32_t nb_slot_free = component_buffer_irsp [num_entity]->nb_slot_free ();
+	  for (uint32_t num_port = 0; num_port < nb_iport [num_entity]; num_port ++)
+	    {
+	      ireq_ack [num_entity][num_port] = (num_port < nb_slot_free);
+	    
+	      ICACHE [num_entity][num_port].REQ_ACK.write (ireq_ack [num_entity][num_port]);
+	    }
+
+	  nb_slot_free = component_buffer_drsp [num_entity]->nb_slot_free ();
+	  for (uint32_t num_port = 0; num_port < nb_dport [num_entity]; num_port ++)
+	    {
+	      dreq_ack [num_entity][num_port] = (num_port < nb_slot_free );
+	    
+	      DCACHE [num_entity][num_port].REQ_ACK.write (dreq_ack [num_entity][num_port]);
+	    }
+
+	  //##### RESPONS #####
+      	  // ~~~~~> ICACHE <~~~~~
+      	  for (uint32_t num_port = 0; num_port < nb_iport [num_entity]; num_port ++)
+      	    {
+	      // Test the number of element in the respons's buffer
+      	      if (num_port >= component_buffer_irsp [num_entity]->nb_slot_use())
+      		{
+      		  irsp_val[num_entity][num_port] = 0; // No respons
+      		}
+      	      else
+      		{
+      		  slot_t<Entry> slot = component_buffer_irsp [num_entity]->read(num_port);
+		  
+      		  irsp_val[num_entity][num_port] = (slot.delay == 0); // respons if have a result
+      		  ICACHE  [num_entity][num_port].RSP_TRDID.write((sc_uint<SIZE_TRDID> )slot.data.trdid);
+      		  ICACHE  [num_entity][num_port].RSP_PKTID.write((sc_uint<SIZE_IPKTID>)slot.data.pktid);
+      		  ICACHE  [num_entity][num_port].RSP_ERR  .write((sc_uint<2>          )slot.data.error);
+		  
+      		  for (uint32_t num_word = 0; num_word < NB_IWORD; num_word ++)
+		    {
+		      sc_uint<SIZE_IDATA> data;
+
+		      for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_IDATA / 8; it_nb_bytes ++)
+			{
+#if defined(systemcass)
+			  RANGE_SET_VAL(SIZE_IDATA         ,
+					data               ,
+					8*(it_nb_bytes+1)-1,
+					8*it_nb_bytes      ,
+					slot.data.data [num_word][it_nb_bytes]);
+#else //#elif defined(systemc)
+			  data.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes) = slot.data.data [num_word][it_nb_bytes];
+#endif
+			}
+		      ICACHE  [num_entity][num_port].RSP_INS [num_word].write(data);
+		    }
+      		}
+
+	      ICACHE  [num_entity][num_port].RSP_VAL.write(irsp_val[num_entity][num_port]);
+      	    }//end nb_iport
+
+	  // ~~~~~> DCACHE <~~~~~
+	  for (uint32_t num_port = 0; num_port < nb_dport [num_entity]; num_port ++)
+	    {
+	      if (num_port >= component_buffer_drsp [num_entity]->nb_slot_use())
+		{
+		  drsp_val[num_entity][num_port] = 0; // No respons
+		}
+	      else
+		{
+		  slot_t<Entry> slot = component_buffer_drsp [num_entity]->read(num_port);
+		  
+		  drsp_val[num_entity][num_port] = (slot.delay == 0);
+		  DCACHE  [num_entity][num_port].RSP_TRDID   = (sc_uint<SIZE_TRDID> )slot.data.trdid;
+		  DCACHE  [num_entity][num_port].RSP_PKTID   = (sc_uint<SIZE_DPKTID>)slot.data.pktid;
+		  DCACHE  [num_entity][num_port].RSP_ERR     = (sc_uint<2>          )slot.data.error;
+
+		  sc_uint<SIZE_DDATA> data;
+
+		  for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
+		    {
+#if defined(systemcass)
+		      RANGE_SET_VAL(SIZE_DDATA         ,
+				    data               ,
+				    8*(it_nb_bytes+1)-1,
+				    8*it_nb_bytes      ,
+				    slot.data.data [0][it_nb_bytes]);
+#else //#elif defined(systemc)
+		      data.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes) = slot.data.data [0][it_nb_bytes];
+#endif
+		    }
+		  DCACHE  [num_entity][num_port].RSP_RDATA.write(data);
+		}
+	      DCACHE  [num_entity][num_port].RSP_VAL     = drsp_val[num_entity][num_port];
+	    }//nb_dport
+      	}//nb_entity
+    }//end genMoore
+
+    //---------------------------------------------------------------------------------------------
+    //-----[ operator<< ]--------------------------------------------------------------------------
+    //---------------------------------------------------------------------------------------------
+
+    friend ostream& operator<< (ostream& output_stream, const HIERARCHY_MEMORY &x)
+    {
+      output_stream << "<" << x.NAME << ">" << endl
+		    << "  * nb_entity         : " << x.nb_entity         << endl;
+
+      output_stream << "  -----[ component_data ]-----------------------------------" << endl;
+      output_stream << *x.component_data << endl;
+	    
+      output_stream << "  -----[ component_cache ]----------------------------------" << endl;
+      output_stream << *x.component_cache;
+
+      output_stream << "  -----[ component_buffer_irsp ]----------------------------" << endl;
+      for (uint32_t num_entity = 0; num_entity < x.nb_entity; num_entity++)
+	{
+	  output_stream << "  * nb_iport [" << num_entity << "]      : " << x.nb_iport [num_entity] << endl;
+	  output_stream << *x.component_buffer_irsp [num_entity];
+	}
+      
+      output_stream << "  -----[ component_buffer_drsp ]----------------------------" << endl;
+      for (uint32_t num_entity = 0; num_entity < x.nb_entity; num_entity++)
+	{
+	  output_stream << "  * nb_dport [" << num_entity << "]      : " << x.nb_dport [num_entity] << endl;
+	  output_stream << *x.component_buffer_drsp [num_entity];
+	}
+
+      //       output_stream << "  -----[ component_ramlock ]--------------------------------" << endl;
+      //       output_stream << "  * nb_entity_ramlock : " << x.nb_entity_ramlock << endl;
+      //       for (uint32_t it = 0; it < x.nb_entity_ramlock; it++)
+      // 	output_stream << *x.component_ramlock [it];      
+      
+      //       output_stream << "  -----[ component_tty ]------------------------------------" << endl;
+      //       output_stream << "  * nb_entity_tty     : " << x.nb_entity_tty     << endl;
+      //       for (uint32_t it = 0; it < x.nb_entity_tty    ; it++)
+      // 	output_stream << *x.component_tty     [it];
+
+      //       output_stream << *x.component_sim2os;
+      
+      return output_stream;
+    }
+
+  };//class
+};
+
+#endif //!HIERARCHY_MEMORY_H
Index: /trunk/IPs/systemC/hierarchy_memory/main.cpp
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/main.cpp	(revision 3)
@@ -0,0 +1,787 @@
+#include "hierarchy_memory.h"
+#include <systemc.h>
+#include <iostream>
+
+#define	TEXT_BASE		0x00000000
+#define	TEXT_SIZE		0x00005000
+
+#define	DATA_CACHED_BASE	0x10000000
+#define	DATA_CACHED_SIZE	0x00000100
+
+#define	DATA_UNCACHED_BASE	0x40000000
+#define	DATA_UNCACHED_SIZE	0x00000100
+
+#define	STACK_BASE		0x50000000
+#define	STACK_SIZE		0x00000200
+				
+#define TTY1_BASE        	0x60000000
+#define TTY1_SIZE        	0x00000100 
+
+#define TTY2_BASE        	0x60000100
+#define TTY2_SIZE        	0x00000200 
+
+#define SIM2OS_BASE     	0x70000000
+#define SIM2OS_SIZE     	0x00000100 
+
+#define RAMLOCK_BASE    	0x80000000
+#define RAMLOCK_SIZE    	0x00000100 
+
+// using namespace hierarchy_memory::data;
+using namespace std;
+using namespace hierarchy_memory;
+
+//-----[ Routine de test ]---------------------------------------
+
+void test_ko (char * file, uint32_t line)
+{
+  cerr << "***** Test KO *****" << endl
+       << " - File : " << file << endl
+       << " - Line : " << line << endl;
+  exit (line);
+};
+
+void test_ok ()
+{
+  cout << "***** Test OK *****" << endl;
+  exit (0);
+};
+
+template <class T>
+void test(T exp1, T exp2, char * file, uint32_t line)
+{
+  if (exp1 != exp2)
+    {
+      cerr << "Expression is different : " << endl
+	   << " - exp1 : " << exp1 << endl
+	   << " - exp2 : " << exp2 << endl;
+
+      test_ko (file,line);
+    }
+};
+
+#define TEST(type,exp1,exp2) do { test<type> (exp1,exp2,__FILE__,__LINE__);} while(0)
+
+int sc_main(int argc, char* argv[])
+{
+  cout << "<main> Test de \"HIERARCHY_MEMORY\"" << endl;
+
+  /*********************************************************************
+   * Declarations des constantes
+   *********************************************************************/
+  const uint32_t        nb_context  = 6;
+  const uint32_t        nb_cluster  = 2;
+  const uint32_t        nb_iport    = 1;
+  const uint32_t        nb_dport    = 3;
+  const uint32_t        size_trdid  = 5;
+  const uint32_t        size_ipktid = 4;
+  const uint32_t        size_iaddr  = 32;
+  const uint32_t        size_idata  = 32;
+  const uint32_t        nb_iword    = 2;
+  const uint32_t        size_dpktid = 2;
+  const uint32_t        size_daddr  = 32;
+  const uint32_t        size_ddata  = 32;
+
+  const uint32_t        size_buffer_irsp = 9;
+  const uint32_t        size_buffer_drsp = 7;
+  /*********************************************************************
+   * Declarations des signaux
+   *********************************************************************/
+  cout << "  * Declaration of signals" << endl;
+  sc_clock                                 CLK ("clock",1,0.5);
+  sc_signal<bool>                          NRESET;
+
+  ICACHE_SIGNALS <size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword> ** icache_signals;
+  DCACHE_SIGNALS <size_trdid, size_dpktid, size_daddr, size_ddata>           ** dcache_signals;
+
+  icache_signals = new ICACHE_SIGNALS <size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword> * [nb_cluster];
+  dcache_signals = new DCACHE_SIGNALS <size_trdid, size_dpktid, size_daddr, size_ddata>           * [nb_cluster];
+
+  for (uint32_t x = 0; x < nb_cluster; x ++)
+    {
+      icache_signals[x] = new ICACHE_SIGNALS <size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword> [nb_iport];
+      dcache_signals[x] = new DCACHE_SIGNALS <size_trdid, size_dpktid, size_daddr, size_ddata>           [nb_dport];
+    }
+
+  /*********************************************************************
+   * Segmentation table
+   *********************************************************************/
+  cout << "  * Segment_table" << endl;
+  
+  SOCLIB_SEGMENT_TABLE segtable;
+  segtable.setMSBNumber    (8);
+  segtable.setDefaultTarget(0,0);
+   
+  // Add a segment   :name        , address of base    , size               , global index , local index, uncache
+  segtable.addSegment("text"      , TEXT_BASE          , TEXT_SIZE          , 0            ,0           , false);
+  segtable.addSegment("data"      , DATA_CACHED_BASE   , DATA_CACHED_SIZE   , 0            ,0           , false);
+  segtable.addSegment("data_unc"  , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0            ,0           , true );
+  segtable.addSegment("stack"     , STACK_BASE         , STACK_SIZE         , 0            ,0           , false);
+  segtable.addSegment("tty1"      , TTY1_BASE          , TTY1_SIZE          , 0            ,0           , true );
+  segtable.addSegment("tty2"      , TTY2_BASE          , TTY2_SIZE          , 0            ,0           , true );
+  segtable.addSegment("sim2os"    , SIM2OS_BASE        , SIM2OS_SIZE        , 0            ,0           , true );
+  segtable.addSegment("ramlock"   , RAMLOCK_BASE       , RAMLOCK_SIZE       , 0            ,0           , true );
+
+  const char * sections_text  []  = {".text",NULL}; 
+  const char * sections_data  []  = {".data",".rodata",".sdata",".sbss",".bss", NULL}; 
+  const char * sections_stack []  = {".stack",NULL}; 
+  const char * filename           = "soft.x";
+
+  /*********************************************************************
+   * Declaration of component
+   *********************************************************************/
+  char * name_tty1[nb_context/2] = { "tty_0",
+				     "tty_1",
+				     "tty_2"};
+
+  char * name_tty2[nb_context/2] = { "tty_3",
+				     "tty_4",
+				     "tty_5"};
+
+  //                          nb_line, size_line, size_word, associativity, hit_latence, miss_penality
+#define L1_ICACHE "L1_ICACHE",      4,         2,         4,             4,           1,             4
+#define L1_DCACHE "L1_DCACHE",      4,         2,         4,             4,           1,             4
+#define L2_CACHE  "L2_CACHE",       8,         4,         4,             2,           2,             7
+#define L3_CACHE  "L3_CACHE",      16,         8,         4,             1,           3,            12
+
+  param_cache_t             param_icache_1     [1] = { param_cache_t (L1_ICACHE) };
+  param_cache_t             param_dcache_1     [1] = { param_cache_t (L1_DCACHE) };
+  param_cache_t             param_cache_2      [2] = { param_cache_t (L2_CACHE) ,
+						       param_cache_t (L3_CACHE) };
+  
+  cache::cache_multilevel::param_t param_icache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_icache_dedicated[0]",1, nb_iport, param_icache_1),
+									  cache::cache_multilevel::param_t ("param_icache_dedicated[1]",1, nb_iport, param_icache_1),
+  };
+			    
+  cache::cache_multilevel::param_t param_dcache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_dcache_dedicated[0]",1, nb_dport, param_dcache_1),
+									  cache::cache_multilevel::param_t ("param_dcache_dedicated[1]",1, nb_dport, param_dcache_1),
+  };
+  			    
+  cache::cache_multilevel::param_t param_cache_shared   ("param_cache_shared",2, nb_cluster*(nb_iport+nb_dport), param_cache_2);
+
+  cache::param_t                   param_cache ("cache"               ,
+						nb_cluster            ,
+						param_icache_dedicated,
+						param_dcache_dedicated,
+						param_cache_shared    );
+  param_entity_t<tty::param_t>     param_tty     [2] = {param_entity_t<tty::param_t>    (TTY1_BASE    , TTY1_SIZE    , tty::param_t ("tty1"   , nb_context/2, name_tty1,true)),
+							param_entity_t<tty::param_t>    (TTY2_BASE    , TTY2_SIZE    , tty::param_t ("tty2"   , nb_context/2, name_tty2,true))};
+  param_entity_t<ramlock::param_t> param_ramlock [1] = {param_entity_t<ramlock::param_t>(RAMLOCK_BASE, RAMLOCK_SIZE, ramlock::param_t("ramlock", RAMLOCK_SIZE))};
+  
+
+  param_entity_t<sim2os::param_t>  param_sim2os      =  param_entity_t<sim2os::param_t>(SIM2OS_BASE, SIM2OS_SIZE, sim2os::param_t("sim2os",&segtable));
+
+#define PARAM_MEMORY  2,param_tty,1,param_ramlock,param_sim2os,param_cache
+#define PARAM        "memory", 0,0, &segtable,nb_cluster, nb_context,size_buffer_irsp, size_buffer_drsp, hierarchy_memory::param_t(PARAM_MEMORY)
+#define TEMPLATE      size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword, size_dpktid, size_daddr, size_ddata
+
+  HIERARCHY_MEMORY <TEMPLATE> * memory = new HIERARCHY_MEMORY <TEMPLATE> (PARAM);
+
+  /*********************************************************************
+   * Instanciation
+   *********************************************************************/
+  memory->CLK          (CLK);
+  memory->NRESET       (NRESET);
+
+  for (uint32_t x = 0; x < nb_cluster; x ++)
+    {
+      for (uint32_t y = 0; y < nb_iport; y ++)
+	memory->ICACHE[x][y] (icache_signals [x][y]);
+      for (uint32_t y = 0; y < nb_dport; y ++)
+	memory->DCACHE[x][y] (dcache_signals [x][y]);
+    }
+
+  cout << "  * Create a HIERARCHY_MEMORY" << endl;
+
+  TEST(bool,memory->init("text"   , filename, sections_text) ,true);
+  TEST(bool,memory->init("stack"  , filename, sections_stack),true);
+  TEST(bool,memory->init("data"   , filename, sections_data) ,true);
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "  * simulation" << endl;
+  // Initialisation
+  sc_start(0);
+
+  // Init control signal
+  for (uint32_t x = 0; x < nb_cluster; x ++)
+    {
+      for (uint32_t y = 0; y < nb_iport; y ++)
+	{
+	  icache_signals [x][y].REQ_VAL.write (false);
+	  icache_signals [x][y].RSP_ACK.write (false);
+	}
+      for (uint32_t y = 0; y < nb_dport; y ++)
+	{
+	  dcache_signals [x][y].REQ_VAL.write (false);
+	  dcache_signals [x][y].RSP_ACK.write (false);
+	}
+    }
+
+  // Reset
+  uint32_t iaddr = 0x2000;
+
+#define CYCLE(n) do {sc_start(n); cout << "*****{ " << setw(5) << (uint32_t) sc_simulation_time() << " }*****" << endl;} while(0)
+#define NEXT_CYCLE() do {CYCLE(1); getchar();} while(0)
+
+  NRESET.write(false);
+  CYCLE(5);
+  NRESET.write(true);
+
+  {
+    cout << " -> Test of Icache" << endl;
+    iaddr = 0x100;
+    icache_signals [0][0].REQ_VAL  .write(true);
+    icache_signals [0][0].REQ_TRDID.write(1);
+    icache_signals [0][0].REQ_PKTID.write(0);
+    icache_signals [0][0].REQ_ADDR .write(iaddr);
+    icache_signals [0][0].REQ_TYPE .write(ITYPE_READ);
+
+    icache_signals [0][0].RSP_ACK  .write(false);
+
+    CYCLE(1);
+    iaddr = 0x2000;
+    icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
+
+    CYCLE(1);
+    icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
+
+    CYCLE(1);
+    icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
+
+    CYCLE(1);
+    icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
+
+    CYCLE(1);
+    icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
+
+    CYCLE(1);
+  
+    icache_signals [0][0].REQ_VAL  .write(false);
+
+    CYCLE(22);
+
+    icache_signals [0][0].RSP_ACK  .write(true );
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),false);
+
+    CYCLE(1);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x18400000);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xa8422000);
+
+    CYCLE(1);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x182051ff);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xa821fffc);
+
+    CYCLE(1);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x9c40fffd);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x04000624);
+
+    CYCLE(1);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0211003);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x18800050);
+
+    CYCLE(1);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xa8840000);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe08b2306);
+
+    CYCLE(1);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0212002);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe0410004);
+
+    CYCLE(1);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),false);
+
+    iaddr = 0x2008;
+    icache_signals [0][0].REQ_VAL  .write(true);
+    icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
+
+    CYCLE(1);
+    icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
+
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x9c40fffd);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x04000624);
+
+    CYCLE(1);
+    icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0211003);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x18800050);
+
+    CYCLE(1);
+    icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xa8840000);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe08b2306);
+
+    CYCLE(1);
+    icache_signals [0][0].REQ_VAL  .write(false);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),true);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0212002);
+    TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe0410004);
+
+    CYCLE(1);
+    TEST(bool               ,icache_signals [0][0].RSP_VAL   .read(),false);
+
+  }
+  {
+    {
+      CYCLE(50);
+
+      cout << " -> Test of Dcache - Read" << endl;
+
+      uint32_t daddr = 0x10000000;
+
+      dcache_signals [0][0].REQ_VAL   .write(true);
+      dcache_signals [0][0].REQ_TRDID .write(1);
+      dcache_signals [0][0].REQ_PKTID .write(0);
+      dcache_signals [0][0].REQ_ADDR  .write(daddr); daddr += (size_ddata/8);
+      dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ);
+      dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
+      dcache_signals [0][0].REQ_WDATA .write(0xdeadbeaf);
+
+      dcache_signals [0][0].RSP_ACK   .write(false);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
+      dcache_signals [0][0].REQ_ACCESS.write(ACCESS_16);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
+      dcache_signals [0][0].REQ_ACCESS.write(ACCESS_8);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
+      dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),false);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),false);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),false);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),false);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_VAL  .write(false);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),false);
+
+      CYCLE(19);
+
+      dcache_signals [0][0].RSP_ACK  .write(true );
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),false);
+
+      CYCLE(1);
+
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x3c746573);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),false);
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x745f696e);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true );
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),false);
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),false);
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      printf("%.8x\n",(uint32_t)dcache_signals [0][0].RSP_RDATA .read());
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x74657465);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true );
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true );
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),false);
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x69696969);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true );
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true );
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true );
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x20546573);
+      TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true );
+      TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true );
+      TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true );
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x74206973);
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x204b6f00);
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+    }
+    {
+      CYCLE(50);
+
+      cout << " -> Test of Dcache - Write" << endl;
+
+      dcache_signals [0][0].REQ_VAL   .write(true);
+      dcache_signals [0][0].REQ_TRDID .write(1);
+      dcache_signals [0][0].REQ_PKTID .write(0);
+      dcache_signals [0][0].REQ_ADDR  .write(0x10000000);
+      dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ);
+      dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
+      dcache_signals [0][0].REQ_WDATA .write(0xdeadbeaf);
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x3c746573);
+      dcache_signals [0][0].REQ_TYPE  .write(DTYPE_WRITE);
+  
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+      dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ );
+  
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0xdeadbeaf);
+      dcache_signals [0][0].REQ_ADDR  .write(0x10000000);
+      dcache_signals [0][0].REQ_TYPE  .write(DTYPE_WRITE);
+      dcache_signals [0][0].REQ_ACCESS.write(ACCESS_16);
+      dcache_signals [0][0].REQ_WDATA .write(0x0bad0bad);
+  
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+      dcache_signals [0][0].REQ_ADDR  .write(0x10000000);
+      dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ);
+      dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x0badbeaf);
+      dcache_signals [0][0].REQ_ADDR  .write(0x10000002);
+      dcache_signals [0][0].REQ_TYPE  .write(DTYPE_WRITE_ACK);
+      dcache_signals [0][0].REQ_ACCESS.write(ACCESS_16);
+      dcache_signals [0][0].REQ_WDATA .write(0xbebebebe);
+  
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      dcache_signals [0][0].REQ_ADDR  .write(0x10000000);
+      dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ);
+      dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
+
+      CYCLE(1);
+      dcache_signals [0][0].REQ_VAL   .write(false);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true);
+      TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x0badbebe);
+
+      CYCLE(1);
+      TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+
+      CYCLE(1);
+      dcache_signals [0][0].RSP_ACK  .write(false);
+    }
+  }
+  {
+    CYCLE(50);
+    cout << " -> Test of TTY" << endl;
+    dcache_signals [0][0].REQ_VAL   .write(true);
+    dcache_signals [0][0].REQ_TRDID .write(1);
+    dcache_signals [0][0].REQ_PKTID .write(0);
+    dcache_signals [0][0].REQ_ADDR  .write(0x60000000);
+    dcache_signals [0][0].REQ_TYPE  .write(DTYPE_WRITE);
+    dcache_signals [0][0].REQ_ACCESS.write(ACCESS_8);
+    dcache_signals [0][0].REQ_WDATA .write(0x30303030);
+    TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+  
+    CYCLE(1);
+    dcache_signals [0][0].REQ_ADDR  .write(0x60000004);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_ADDR  .write(0x60000010);
+    dcache_signals [0][0].REQ_WDATA .write(0x31313131);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_ADDR  .write(0x60000110);
+    dcache_signals [0][0].REQ_WDATA .write(0x32323232);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_ADDR  .write(0x60000128);
+    dcache_signals [0][0].REQ_WDATA .write(0xdeadbeaf);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(false);
+  }
+  {
+    CYCLE(50);
+    cout << " -> Test of RAMLOCK" << endl;
+    dcache_signals [0][0].RSP_ACK  .write(true );
+    dcache_signals [0][1].RSP_ACK  .write(true );
+    dcache_signals [0][2].RSP_ACK  .write(true );
+
+    dcache_signals [0][0].REQ_VAL   .write(true);
+    dcache_signals [0][0].REQ_TRDID .write(1);
+    dcache_signals [0][0].REQ_PKTID .write(0);
+    dcache_signals [0][0].REQ_ADDR  .write(0x8000000C);
+    dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ);
+    dcache_signals [0][0].REQ_ACCESS.write(ACCESS_8);
+    dcache_signals [0][0].REQ_WDATA .write(0);
+    TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(false);
+
+    CYCLE(28);
+
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+    TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(true);
+    dcache_signals [0][0].REQ_ADDR  .write(0x8000000C);
+    dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ);
+    TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(false);
+  
+    CYCLE(28);
+
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+    TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),LOCK);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(true);
+    dcache_signals [0][0].REQ_ADDR  .write(0x8000000C);
+    dcache_signals [0][0].REQ_TYPE  .write(DTYPE_WRITE_ACK);
+    TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(false);
+  
+    CYCLE(28);
+
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+    TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),LOCK);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(true);
+    dcache_signals [0][0].REQ_ADDR  .write(0x8000000C);
+    dcache_signals [0][0].REQ_TYPE  .write(DTYPE_WRITE_ACK);
+    TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(false);
+  
+    CYCLE(28);
+
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+    TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(true);
+    dcache_signals [0][0].REQ_ADDR  .write(0x8000000C);
+    dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ);
+    TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(false);
+  
+    CYCLE(28);
+
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+    TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(true);
+    dcache_signals [0][1].REQ_VAL   .write(true);
+    dcache_signals [0][2].REQ_VAL   .write(true);
+    dcache_signals [0][0].REQ_ADDR  .write(0x8000000E);
+    dcache_signals [0][1].REQ_ADDR  .write(0x8000000E);
+    dcache_signals [0][2].REQ_ADDR  .write(0x8000000E);
+    dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ );
+    dcache_signals [0][1].REQ_TYPE  .write(DTYPE_READ );
+    dcache_signals [0][2].REQ_TYPE  .write(DTYPE_READ );
+    TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(false);
+    dcache_signals [0][1].REQ_VAL   .write(false);
+    dcache_signals [0][2].REQ_VAL   .write(false);
+  
+    CYCLE(28);
+
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),true );
+    TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK);
+    TEST(sc_uint<size_ddata>,dcache_signals [0][1].RSP_RDATA .read(),LOCK);
+    TEST(sc_uint<size_ddata>,dcache_signals [0][2].RSP_RDATA .read(),LOCK);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(true);
+    dcache_signals [0][1].REQ_VAL   .write(true);
+    dcache_signals [0][2].REQ_VAL   .write(true);
+    dcache_signals [0][0].REQ_ADDR  .write(0x8000000E);
+    dcache_signals [0][1].REQ_ADDR  .write(0x8000000E);
+    dcache_signals [0][2].REQ_ADDR  .write(0x8000000E);
+    dcache_signals [0][0].REQ_TYPE  .write(DTYPE_READ );
+    dcache_signals [0][1].REQ_TYPE  .write(DTYPE_WRITE_ACK);
+    dcache_signals [0][2].REQ_TYPE  .write(DTYPE_READ );
+    TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(false);
+    dcache_signals [0][1].REQ_VAL   .write(false);
+    dcache_signals [0][2].REQ_VAL   .write(false);
+  
+    CYCLE(28);
+
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),true );
+    TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),LOCK);
+    TEST(sc_uint<size_ddata>,dcache_signals [0][1].RSP_RDATA .read(),LOCK);
+    TEST(sc_uint<size_ddata>,dcache_signals [0][2].RSP_RDATA .read(),UNLOCK);
+  }
+
+  {
+    CYCLE(50);
+    cout << " -> Test of SIM2OS" << endl;
+
+    dcache_signals [0][0].RSP_ACK  .write(true );
+    dcache_signals [0][1].RSP_ACK  .write(true );
+    dcache_signals [0][2].RSP_ACK  .write(true );
+
+    dcache_signals [0][0].REQ_VAL   .write(true);
+    dcache_signals [0][0].REQ_TRDID .write(1);
+    dcache_signals [0][0].REQ_PKTID .write(0);
+    dcache_signals [0][0].REQ_ADDR  .write(0x7000000C);
+    dcache_signals [0][0].REQ_TYPE  .write(DTYPE_WRITE);
+    dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
+    dcache_signals [0][0].REQ_WDATA .write(0x10000004);
+    TEST(bool               ,dcache_signals [0][0].REQ_ACK   .read(),true);
+
+    dcache_signals [0][1].REQ_VAL   .write(true);
+    dcache_signals [0][1].REQ_TRDID .write(1);
+    dcache_signals [0][1].REQ_PKTID .write(0);
+    dcache_signals [0][1].REQ_ADDR  .write(0x70000000);
+    dcache_signals [0][1].REQ_TYPE  .write(DTYPE_WRITE);
+    dcache_signals [0][1].REQ_ACCESS.write(ACCESS_32);
+    dcache_signals [0][1].REQ_WDATA .write(SERVICE_TIME);
+
+    TEST(bool               ,dcache_signals [0][1].REQ_ACK   .read(),true);
+
+    dcache_signals [0][2].REQ_VAL   .write(true);
+    dcache_signals [0][2].REQ_TRDID .write(1);
+    dcache_signals [0][2].REQ_PKTID .write(0);
+    dcache_signals [0][2].REQ_ADDR  .write(0x70000004);
+    dcache_signals [0][2].REQ_TYPE  .write(DTYPE_READ);
+    dcache_signals [0][2].REQ_ACCESS.write(ACCESS_32);
+    dcache_signals [0][2].REQ_WDATA .write(SERVICE_TIME);
+
+    TEST(bool               ,dcache_signals [0][2].REQ_ACK   .read(),true);
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+
+    CYCLE(1);
+    dcache_signals [0][0].REQ_VAL   .write(false);
+    dcache_signals [0][1].REQ_VAL   .write(false);
+    dcache_signals [0][2].REQ_VAL   .write(false);
+    CYCLE(28);
+
+    TEST(bool               ,dcache_signals [0][0].RSP_VAL   .read(),true );
+    TEST(bool               ,dcache_signals [0][1].RSP_VAL   .read(),false);
+    TEST(bool               ,dcache_signals [0][2].RSP_VAL   .read(),false);
+  }
+  //cout << *memory << endl; test_ok();
+  //  CYCLE(1);
+  
+  cout << "Press a key to quit the test" << endl;
+  getchar();
+  delete memory;
+  test_ok ();
+
+  return 1;
+};
Index: /trunk/IPs/systemC/hierarchy_memory/ramlock/Makefile
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/ramlock/Makefile	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/ramlock/Makefile	(revision 3)
@@ -0,0 +1,18 @@
+INCLUDE			= ../file
+# DEBUG			= -DDEBUG
+DEBUG			=
+CXX			= g++
+CXX_OPT			= -g3 -Wall -Werror -ansi -I$(INCLUDE) $(DEBUG)
+RM			= rm -f
+
+EXE			= $(patsubst %.cpp,%.x ,$(wildcard *.cpp) )
+HEADERS			= $(wildcard *.h)
+
+all			: $(EXE)
+			./$(EXE)
+
+%.x			: %.cpp $(HEADERS)
+			$(CXX) $(CXX_OPT) -o $@ $<
+
+clean			:
+			$(RM) $(EXE) *~
Index: /trunk/IPs/systemC/hierarchy_memory/ramlock/main.cpp
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/ramlock/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/ramlock/main.cpp	(revision 3)
@@ -0,0 +1,36 @@
+#include "ramlock.h"
+#include <iostream>
+
+using namespace hierarchy_memory::ramlock;
+using namespace std;
+
+void test_ko (int val)
+{
+  cout << "***** Test(" << val << ") KO *****" << endl;
+  exit (val);
+}
+
+void test_ok ()
+{
+  cout << "***** Test OK *****" << endl;
+  exit (0);
+}
+
+int main ()
+{
+  cout << "<main> Test de \"Ramlock\"" << endl;
+  
+  cout << "  * Create a Ramlock with a size of 70" << endl;
+
+  Ramlock my_ramlock = Ramlock(param_t("my_ramlock",70));
+  my_ramlock.reset();
+
+  cout << my_ramlock << endl;
+
+  if (my_ramlock.read (10) != UNLOCK) test_ko(1);  cout << my_ramlock << endl;
+  if (my_ramlock.read (10) !=   LOCK) test_ko(2);  cout << my_ramlock << endl;
+  if (my_ramlock.write(10) !=   LOCK) test_ko(3);  cout << my_ramlock << endl;
+  if (my_ramlock.write(10) != UNLOCK) test_ko(4);  cout << my_ramlock << endl;
+
+  test_ok ();
+}
Index: /trunk/IPs/systemC/hierarchy_memory/ramlock/ramlock.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/ramlock/ramlock.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/ramlock/ramlock.h	(revision 3)
@@ -0,0 +1,99 @@
+#ifndef RAMLOCK_H
+#define RAMLOCK_H
+
+#include <stdint.h>
+#include <iostream>
+
+using namespace std;
+
+namespace hierarchy_memory {
+namespace ramlock          {
+
+  const static bool UNLOCK = false;
+  const static bool LOCK   = true;
+
+  class param_t
+  {
+  public : char   * name;
+  public : uint32_t size;
+
+  public : param_t () {};
+
+  public : param_t (char   * name,
+		    uint32_t size)
+    {
+      this->name = name;
+      this->size = size;
+    }
+  };
+
+  class Ramlock
+  {
+  private   : char           * name;
+  protected : bool           * lock;
+  protected : const uint32_t   size;
+
+  public : Ramlock (param_t param):
+    size    (param.size)
+    {
+      uint32_t size_name = strlen(param.name)+1;
+      name = new char [size_name];
+      strncpy(name,param.name,size_name);
+      lock   = new bool          [size];
+    }
+    
+    // *****[ reset ]*****
+  public : void reset ()
+    {
+      for (uint32_t it = 0; it < size; it ++)
+	lock [it] = UNLOCK;
+    }
+
+    // *****[ test ]*****
+  public : bool test (uint32_t num_lock)
+    {
+      return num_lock < size;
+    }
+
+    // *****[ read ]*****
+    // return the value of the lock and take this
+    // NOTE : the caller must test if the num_lock is < size
+  public : bool read (uint32_t num_lock)
+    {
+      bool val = lock [num_lock];
+      lock [num_lock] = LOCK;
+      
+      return val;
+    }
+
+    // *****[ write ]*****
+    // return the value of the lock and untake this
+    // NOTE : the caller must test if the num_lock is < size
+  public : bool write (uint32_t num_lock)
+    {
+      bool val = lock [num_lock];
+      lock [num_lock] = UNLOCK;
+      
+      return val;
+    }
+
+  public    : friend ostream& operator<< (ostream& output_stream, const Ramlock & x)
+      {
+	output_stream << "<" << x.name << ">" << endl;
+	output_stream << " * size        : " << x.size      << endl;
+	
+	for (uint32_t it = 0; it < x.size; it ++)
+	  {
+	    if (it % 32 == 0)
+	      output_stream << endl;
+
+	    output_stream << x.lock [it] << " ";
+	  }
+	output_stream << endl;
+
+	return output_stream;
+      };
+  };
+
+};}; //end namespace
+#endif //!RAMLOCK_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/service.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/service.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/service.h	(revision 3)
@@ -0,0 +1,23 @@
+#ifndef SERVICE_H
+#define SERVICE_H
+
+// namespace hierarchy_memory
+// {
+//   namespace sim2os
+//   {
+
+    typedef enum 
+      {
+	SERVICE_OPEN          ,
+	SERVICE_CLOSE         ,
+	SERVICE_READ          ,
+	SERVICE_WRITE         ,
+	SERVICE_TIME          ,
+	SERVICE_CLOCK         ,
+	SERVICE_LSEEK         ,
+	SERVICE_UNDEFINED     ,
+	SERVICE_UNIMPLEMENTED
+      } service_t;
+
+//   };};
+#endif //SERVICE_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_clock.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_clock.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_clock.h	(revision 3)
@@ -0,0 +1,30 @@
+#ifndef SERVICE_CLOCK_H
+#define SERVICE_CLOCK_H
+
+#include "../sim2os.h"
+
+namespace hierarchy_memory {
+  namespace sim2os {
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ service_clock ]~~~~~
+    void *
+    Sim2os ::
+    service_clock ()
+    {
+      if (have_all_arguments(0) == false)
+	{
+	  cerr << "<" << NAME << "> Usage : clock_t clock();" << endl;
+	  return NULL;
+	}
+
+      void *      result   = (void *) nb_cycle;
+      error                = 0;
+  
+      cout << "\n\t***** service : clock         *****" << endl;
+      cout << "\tresult    : " << (unsigned int) result << endl;
+      cout << "\terrno     : " << (unsigned int) error  << endl;
+  
+      return      result;
+    }
+  };};
+#endif //SERVICE_CLOCK_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_close.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_close.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_close.h	(revision 3)
@@ -0,0 +1,33 @@
+#ifndef SERVICE_CLOSE_H
+#define SERVICE_CLOSE_H
+
+#include "../sim2os.h"
+
+namespace hierarchy_memory {
+  namespace sim2os {
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ service_close ]~~~~~
+    void *
+    Sim2os ::
+    service_close ()
+    {
+      if (have_all_arguments(1) == false)
+	{
+	  cerr << "<" << NAME << "> Usage : int close(int fd);" << endl;
+	  return NULL;
+	}
+  
+      int         fd       = (int)          arguments[1];
+      void *      result   = (void *)       close(fd);
+      error                = errno;
+
+      cout << "\n\t***** service : close         *****" << endl;
+      cout << "\tfd        : " << (unsigned int) fd     << endl;
+      cout << "\tresult    : " << (unsigned int) result << endl;
+      cout << "\terrno     : " << (unsigned int) error  << endl;
+
+      return      result;
+    }
+
+  };};
+#endif //!SERVICE_CLOSE_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_lseek.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_lseek.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_lseek.h	(revision 3)
@@ -0,0 +1,39 @@
+#ifndef SERVICE_LSEEK_H
+#define SERVICE_LSEEK_H
+
+#include "../sim2os.h"
+
+namespace hierarchy_memory {
+  namespace sim2os {
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ service_lseek ]~~~~~
+    void *
+    Sim2os ::
+    service_lseek ()
+    {
+      if (have_all_arguments(3) == false)
+	{
+	  cerr << "<" << NAME << "> Usage : off_t lseek(int fildes, off_t offset, int whence);" << endl;
+	  return NULL;
+	}
+  
+      int         flides   = (int)    arguments[1];
+      off_t       offset   = (off_t)  arguments[2];
+      int         whence   = (int)    arguments[3];
+      void *      result   = (void *) lseek(flides,offset,whence);
+      error                = errno;
+  
+      // No swap -> because no access memory
+
+      cout << "\n\t***** service : lseek         *****"        << endl;
+      cout << "\tflides    : " << (unsigned int) flides << endl;
+      cout << "\toffset    : " << (unsigned int) offset << endl;
+      cout << "\twhence    : " << (unsigned int) whence << endl;
+      cout << "\tresult    : " << (unsigned int) result << endl;
+      cout << "\terrno     : " << (unsigned int) error  << endl;
+
+      return      result;
+    }
+
+  };};
+#endif //SERVICE_LSEEK_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_open.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_open.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_open.h	(revision 3)
@@ -0,0 +1,41 @@
+#ifndef SERVICE_OPEN_H
+#define SERVICE_OPEN_H
+
+#include "../sim2os.h"
+
+namespace hierarchy_memory {
+  namespace sim2os {
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ service_open ]~~~~~
+    void *
+    Sim2os::
+    service_open ()
+    {
+      if (have_all_arguments(3) == false)
+	{
+	  cerr << "<" << NAME << "> Usage : int open(const char *pathname, int flags, mode_t mode);" << endl;
+	  return NULL;
+	}
+  
+      const char *pathname = (const char *) convert_address(arguments[1]);
+      int         flags    = (int)          arguments[2];
+      mode_t      mode     = (mode_t)       arguments[3];
+      void *      result   = (void *)       open(pathname,flags,mode);
+      error                = errno;
+
+      cout << "\n\t***** service : open          *****"          << endl;
+      cout << "\tpathname  : " <<                       pathname << endl;
+      cout << "\tflags /8  : " << oct << (unsigned int) flags    << endl;
+      cout << "\tflags /10 : " << dec << (unsigned int) flags    << endl;
+      cout << "\tflags /16 : " << hex << (unsigned int) flags    << endl;
+      cout << "\tmode  /8  : " << oct << (unsigned int) mode     << endl;
+      cout << "\tmode  /10 : " << dec << (unsigned int) mode     << endl;
+      cout << "\tmode  /16 : " << hex << (unsigned int) mode     << endl;
+      cout << "\tresult    : " << dec << (unsigned int) result   << endl;
+      cout << "\terrno     : " <<        (unsigned int) error    << endl;
+
+      return      result;
+    }
+
+  };};
+#endif //SERVICE_OPEN_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_read.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_read.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_read.h	(revision 3)
@@ -0,0 +1,38 @@
+#ifndef SERVICE_READ_H
+#define SERVICE_READ_H
+
+#include "../sim2os.h"
+
+namespace hierarchy_memory {
+  namespace sim2os {
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ service_read ]~~~~~
+    void *
+    Sim2os ::
+    service_read ()
+    {
+      if (have_all_arguments(3) == false)
+	{
+	  cerr << "<" << NAME << "> Usage : ssize_t read(int fd, void *buf, size_t count);" << endl;
+	  return NULL;
+	}
+  
+      int         fd       = (int)          arguments[1];
+      void *      buf      = (void *)       convert_address(arguments[2]);
+      ssize_t     count    = (ssize_t)      arguments[3];
+      void *      result   = (void *)       read(fd,buf,count);
+
+      cout << "\n\t***** service : read          *****"        << endl;
+      cout << "\tfd        : " <<        (unsigned int) fd     << endl;
+      cout << "\tbuf       : " << hex << (unsigned int) buf    << endl;
+      //cout << "\tbuf       : " << dec << (char *)       buf    << endl;
+      cout << "\tcount     : " << dec << (unsigned int) count  << endl;
+      cout << "\tresult    : " <<        (unsigned int) result << endl;
+      cout << "\terrno     : " <<        (unsigned int) error  << endl;
+
+      error                = errno;
+      return      result;
+    }
+
+  };};
+#endif //SERVICE_READ_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_time.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_time.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_time.h	(revision 3)
@@ -0,0 +1,36 @@
+#ifndef SERVICE_TIME_H
+#define SERVICE_TIME_H
+
+#include "../sim2os.h"
+
+namespace hierarchy_memory {
+  namespace sim2os {
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ service_time ]~~~~~
+    void *
+    Sim2os ::
+    service_time ()
+    {
+      if (have_all_arguments(1) == false)
+	{
+	  cerr << "<" << NAME << "> Usage : time_t time(time_t * t);" << endl;
+	  return NULL;
+	}
+  
+      time_t     *t        = (time_t *)     convert_address(arguments[1]);
+      void *      result   = (void *)       time(t);
+      error                = errno;
+  
+      cout << "\n\t***** service : time          *****" << endl;
+      cout << "\tt         : " << hex << (unsigned int) t                                      << endl;
+      cout << "\tresult    : " << dec << (unsigned int) result << " - " << ctime((time_t *) t) << endl;
+      cout << "\terrno     : " <<        (unsigned int) error                                  << endl;
+
+      // Must swap, because it's a pointer
+      t = (time_t *)swapBytes((char *)t,sizeof(time_t),sizeof(time_t));
+  
+      return      result;
+    }
+
+  };};
+#endif //SERVICE_TIME_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_write.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_write.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/service/service_write.h	(revision 3)
@@ -0,0 +1,40 @@
+#ifndef SERVICE_WRITE_H
+#define SERVICE_WRITE_H
+
+#include "../sim2os.h"
+
+namespace hierarchy_memory {
+  namespace sim2os {
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ service_write ]~~~~~
+    void *
+    Sim2os ::
+    service_write ()
+    {
+      if (have_all_arguments(3) == false)
+	{
+	  cerr << "<" << NAME << "> Usage : ssize_t write(int fd, void *buf, size_t count);" << endl;
+	  return NULL;
+	}
+  
+      int         fd       = (int)          arguments[1];
+      const void *buf      = (const void *) convert_address(arguments[2]);
+      ssize_t     count    = (ssize_t)      arguments[3];
+      void *      result   = (void *)       write(fd,buf,count);
+      error                = errno;
+  
+      // No swap -> because it's a char
+
+      cout << "\n\t***** service : write         *****"        << endl;
+      cout << "\tfd        : " <<        (unsigned int) fd     << endl;
+      cout << "\tbuf       : " << hex << (unsigned int) buf    << endl;
+      //cout << "\tbuf       : " << dec << (char *)       buf    << endl;
+      cout << "\tcount     : " << dec << (unsigned int) count  << endl;
+      cout << "\tresult    : " <<        (unsigned int) result << endl;
+      cout << "\terrno     : " <<        (unsigned int) error  << endl;
+
+      return      result;
+    }
+
+  };};
+#endif //SERVICE_WRITE_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/service_conversion.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/service_conversion.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/service_conversion.h	(revision 3)
@@ -0,0 +1,35 @@
+#ifndef SERVICE_CONVERSION_H
+#define SERVICE_CONVERSION_H
+
+#include "service.h"
+
+namespace hierarchy_memory
+{
+  namespace sim2os
+  {
+    namespace service
+    {
+    
+      int service2int(service_t num_service)
+      {
+	return (int)num_service;
+      }
+
+      service_t int2service (int val)
+      {
+	switch (val)
+	  {
+	  case SERVICE_OPEN          : return SERVICE_OPEN ;
+	  case SERVICE_CLOSE         : return SERVICE_CLOSE;
+	  case SERVICE_READ          : return SERVICE_READ ;
+	  case SERVICE_WRITE         : return SERVICE_WRITE;
+	  case SERVICE_TIME          : return SERVICE_TIME ;
+	  case SERVICE_CLOCK         : return SERVICE_CLOCK;
+	  case SERVICE_LSEEK         : return SERVICE_LSEEK;
+	  case SERVICE_UNIMPLEMENTED : return SERVICE_UNIMPLEMENTED;
+	  default                    : return SERVICE_UNDEFINED;
+	  }//end switch
+      }
+
+    };};};
+#endif //SERVICE_CONVERSION_H
Index: /trunk/IPs/systemC/hierarchy_memory/sim2os/sim2os.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/sim2os/sim2os.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/sim2os/sim2os.h	(revision 3)
@@ -0,0 +1,307 @@
+// ### -------------------------------------------------------------- ###
+// #                                                                    #
+// # File       : sim2os.h                                              #
+// # Authors    : Rosière Mathieu                                       #
+// # Date       : 12/06/2006                                            #
+// # Modif.     : dd/mm/yyyy                                            #
+// # Version    : 1.0                                                   #
+// #                                                                    #
+// # Origin     : this description has been developed by CAO-VLSI team  #
+// #              at ASIM laboratory, University Pierre et Marie Curie  #
+// #              4 Place Jussieu 75252 Paris Cedex 05 - France         #
+// #                                                                    #
+// ### -------------------------------------------------------------- ###
+
+/*
+ * WARNING :
+ * This bridge can be use, if :
+ *  - sizeof between the host's cpu and the simulation's cpu is the same
+ *  -
+ */
+
+#ifndef SIM2OS_H
+#define SIM2OS_H
+
+#include "service.h"
+#include "service_conversion.h"
+#include <iostream>
+#include <map>
+using namespace std;
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <stdarg.h>
+#include "shared/soclib_segment_table.h"
+#include "../endianness/endianness.h"
+using namespace std;
+using namespace hierarchy_memory::sim2os::service;
+
+namespace hierarchy_memory {
+  namespace sim2os {
+
+
+
+    //******************************************************************************************
+    // Interface
+    //******************************************************************************************
+
+
+
+  class param_t
+  {
+  public : char *                 name          ;
+  public : SOCLIB_SEGMENT_TABLE * segment_table ;
+
+  public : param_t () {};
+    
+  public : param_t (char *                 name       , 
+		    SOCLIB_SEGMENT_TABLE * segment_table     )
+    {
+      this->name          = name       ;
+      this->segment_table = segment_table     ;
+    }    
+  }; //end param_t
+
+    class Sim2os
+    {
+      //=====[ Private ]==========================================================================
+      //-----[ Champ ]----------------------------------------------------------------------------
+    private : const char *             NAME;
+    private : service_t                num_service;    // number of service
+    private : map<unsigned int,void *> arguments;
+    private : SOCLIB_SEGMENT_TABLE   * segment_table;
+    private : unsigned long long       nb_cycle;
+
+      //-----[ Methods ]--------------------------------------------------------------------------
+    private : bool                     have_all_arguments (unsigned int);
+    private : void *                   convert_address    (void *);
+
+    private : void *                   service_open       ();
+    private : void *                   service_close      ();
+    private : void *                   service_read       ();
+    private : void *                   service_write      ();
+    private : void *                   service_time       ();
+    private : void *                   service_clock      ();
+    private : void *                   service_lseek      ();
+
+      //=====[ Public ]===========================================================================
+    public  : void *                   result;
+    public  : int                      error; // It's errno
+
+      //-----[ Methods ]--------------------------------------------------------------------------
+    public  :                          Sim2os             (param_t);
+    public  :                          ~Sim2os            ();
+    public  : void *                   execute            ();
+    public  : void *                   execute            (service_t);
+    public  : void *                   execute            (service_t, void *, ...);
+    public  : void                     parameter          (unsigned int, void *);
+    public  : void                     transition         ();
+
+      //=====[ Friend ]===========================================================================
+      //-----[ Methods ]--------------------------------------------------------------------------
+      friend    ostream&                 operator<<         (ostream&, Sim2os);
+    };
+
+
+
+    //******************************************************************************************
+    // Implementation
+    //******************************************************************************************
+
+
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ Sim2os ]~~~~~
+    Sim2os ::
+    Sim2os (param_t param) :
+      NAME (param.name)
+    {
+      segment_table = param.segment_table;
+      result        = (void *)-1;
+      error         =          1;
+      nb_cycle      =          0;
+      cout << "<" << NAME << "> Successful Instanciation" << endl;
+    };
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ ~Sim2os ]~~~~~
+    Sim2os ::
+    ~Sim2os ()
+    {
+      cout << "<" << NAME << "> Destructor" << endl;
+    };
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ have_all_arguments ]~~~~~
+    /*
+     * Test if all arguments is here
+     * (don't test the coherencies of this)
+     */
+    bool
+    Sim2os ::
+    have_all_arguments (unsigned int nb_val)
+    {
+      //   while ((nb_val > 0) &&
+      // 	 (arguments.find(nb_val) != arguments.end()))
+      //     nb_val --;
+
+      unsigned int val = nb_val;
+      while (nb_val > 0)
+	if (arguments.find(nb_val) != arguments.end())
+	  nb_val --;
+	else
+	  {
+	    cerr << "argument[" << nb_val << "] on " << val << ", is not find." << endl;
+	    break;
+	  }
+
+      return (nb_val == 0);
+    };
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ convert_address ]~~~~~
+    /*
+     * convert a address in the simulator on a address in OS
+     */
+    void *
+    Sim2os ::
+    convert_address (void * address)
+    {
+      void * result = segment_table->getAddrAlloc((unsigned int)address);
+  
+      if (result == NULL)
+	{
+	  cerr << "<" << NAME << "> address don't match : " << hex << (unsigned int)address << dec << endl;
+	  exit(0);
+	}
+  
+      return result;
+    }
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ transition ]~~~~~
+    /*
+     * have a new cycle : update register cycle's depend
+     */
+    void 
+    Sim2os ::
+    transition ()
+    {
+      nb_cycle ++;
+    }
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ execute ]~~~~~
+    /*
+     * execute the service with num_service in argument
+     */
+    void *
+    Sim2os ::
+    execute (service_t num)
+    {
+      num_service = num;
+
+      return execute();
+    }
+
+    /*
+     * execute the service with all
+     * the list of arg must be finish by "NULL"
+     * also the list can't have a NULL as param
+     */
+    void *
+    Sim2os ::
+    execute (service_t num, void * arg, ...)
+    {
+  
+      num_service = num;
+
+      va_list ap;
+      va_start (ap,arg);
+      unsigned int it = 1;
+      while (arg != NULL)
+	{
+	  arguments[it] = arg;  
+	  it ++;
+	  arg = va_arg(ap,void *);
+	}
+  
+      va_end(ap);
+      return execute();
+    }
+
+    /*
+     * execute the service without argument
+     */
+    void *
+    Sim2os ::
+    execute ()
+    {
+      result = NULL;
+
+      switch (num_service)
+	{
+	case SERVICE_OPEN          : {result = service_open     (); break;}
+	case SERVICE_CLOSE         : {result = service_close    (); break;}
+	case SERVICE_READ          : {result = service_read     (); break;}
+	case SERVICE_WRITE         : {result = service_write    (); break;}
+	case SERVICE_TIME          : {result = service_time     (); break;}
+	case SERVICE_CLOCK         : {result = service_clock    (); break;}
+	case SERVICE_LSEEK         : {result = service_lseek    (); break;}
+	case SERVICE_UNIMPLEMENTED :
+	  {
+	    cerr << "<" << NAME << "> service Unimplemented : " << num_service << endl;
+	    break;
+	  }
+
+	case SERVICE_UNDEFINED     :
+	default                    :
+	  {
+	    cerr << "<" << NAME << "> service Undefine      : " << num_service << endl;
+	    break;
+	  }
+	}//end switch
+
+      // Erase all elt;
+      arguments.erase(arguments.begin(),arguments.end());
+      return result;
+    };
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ parameter ]~~~~~
+    /*
+     * Add a new parameter
+     * if num_reg == 0, it's the number of service
+     * else             it's a arguments
+     */
+    void
+    Sim2os ::
+    parameter (unsigned int num_reg,
+	       void       * val)
+    {
+      if (num_reg == 0)
+	num_service = int2service((int) val);
+      else
+	arguments[num_reg] = val;
+    };
+
+    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~[ operator<< ]~~~~~
+    ostream& operator<< (ostream& output, Sim2os input)
+    {
+      //   output << "<" << input.NAME << ">" << endl;
+      //   output << "num_service : " << input.num_service << endl;
+
+      //   for (map<unsigned int,void *>::iterator it = input.arguments.begin(); 
+      //        it != input.arguments.end();
+      //        it ++)
+      //     output << "[" << it.first << "] : " << it.second << endl;
+      return output;
+    };
+
+  };};
+
+    // Include all service !!!
+#include "service/service_open.h"
+#include "service/service_close.h"
+#include "service/service_read.h"
+#include "service/service_write.h"
+#include "service/service_time.h"
+#include "service/service_clock.h"
+#include "service/service_lseek.h"
+
+
+#endif //!SIM2OS_H
Index: /trunk/IPs/systemC/hierarchy_memory/tty/Makefile
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/tty/Makefile	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/tty/Makefile	(revision 3)
@@ -0,0 +1,18 @@
+INCLUDE			= ../file
+# DEBUG			= -DDEBUG
+DEBUG			=
+CXX			= g++
+CXX_OPT			= -g3 -Wall -Werror -ansi -I$(INCLUDE) $(DEBUG)
+RM			= rm -f
+
+EXE			= $(patsubst %.cpp,%.x ,$(wildcard *.cpp) )
+HEADERS			= $(wildcard *.h)
+
+all			: $(EXE)
+			./$(EXE)
+
+%.x			: %.cpp $(HEADERS)
+			$(CXX) $(CXX_OPT) -o $@ $<
+
+clean			:
+			$(RM) $(EXE) *~ tty_*
Index: /trunk/IPs/systemC/hierarchy_memory/tty/main.cpp
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/tty/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/tty/main.cpp	(revision 3)
@@ -0,0 +1,48 @@
+#include "tty.h"
+#include <iostream>
+
+using namespace hierarchy_memory::tty;
+using namespace std;
+
+void test_ko (int val)
+{
+  cout << "***** Test(" << val << ") KO *****" << endl;
+  exit (val);
+}
+
+void test_ok ()
+{
+  cout << "***** Test OK *****" << endl;
+//   exit (0);
+}
+
+int main ()
+{
+  cout << "<main> Test de \"Tty\"" << endl;
+  
+  cout << "  * Create a Tty with a size of 4" << endl;
+  
+  const uint32_t nb_tty = 4;
+  char * name_tty [nb_tty] = {"tty_0","tty_1","tty_2","tty_3"};
+  Tty    my_tty = Tty(param_t("my_tty",nb_tty,name_tty,false));
+  my_tty.reset();
+
+  cout << my_tty << endl;
+
+  char * message [nb_tty] = {
+    "Ici Londre : Adeline aime la saucisse de Frankort, je repete : Adeline aime la saucisse de Frankort"  ,
+    "Ici Londre : Maurice a garer le camion de bernard dans la cour, je repete Maurice a garer le camion de bernard dans la cour",
+    "Ici Londre : Londre est la ville qui diffuse des messages a la con, je repete : Londre est la ville qui diffuse des messages a la con",
+    "Ici Londre : Non, le debarquement n'aura pas lieu le 6 juin 1944 en Normandie, et je ne me repete pas"};
+
+  for (uint32_t j = 0; j < nb_tty ; j ++)
+    for (uint32_t i = 0; i < strlen(message[j]); i++)
+      my_tty.write(j,message[j][i]);
+
+  
+  cout << "<main> Press <Enter> to stop the test" << endl;
+  
+  getchar();
+
+  test_ok ();
+}
Index: /trunk/IPs/systemC/hierarchy_memory/tty/tty.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/tty/tty.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/tty/tty.h	(revision 3)
@@ -0,0 +1,139 @@
+#ifndef TTY_H
+#define TTY_H
+#include <fcntl.h>
+#include <stdarg.h>
+#include <stdio.h>
+
+#include <unistd.h>
+#include <signal.h>
+#include <stdint.h>
+#include <iostream>
+#include "xtty.h"
+
+using namespace std;
+
+namespace hierarchy_memory {
+namespace tty          {
+
+  class param_t
+  {
+  public : char   * name;
+  public : uint32_t nb_tty;
+  public : char  ** name_tty;
+  public : bool     with_xtty;
+
+  public : param_t () {};
+
+  public : param_t (char   * name    ,
+		    uint32_t nb_tty  ,
+		    char  ** name_tty,
+		    bool     with_xtty)
+    {
+      this->name     = name;
+      this->nb_tty   = nb_tty;
+      this->name_tty = name_tty;
+      this->with_xtty = with_xtty;
+    }
+  };
+
+  class Tty
+  {
+  private   : char           * name;
+  protected : const uint32_t   nb_tty;
+  private   : const bool       with_xtty;
+  private   : xtty_t         * xtty;
+
+  public : Tty (param_t param):
+    nb_tty    (param.nb_tty),
+    with_xtty  (param.with_xtty)
+    {
+      uint32_t size_name = strlen(param.name)+1;
+      name = new char [size_name];
+      strncpy(name,param.name,size_name);
+
+      xtty = new xtty_t [nb_tty];
+
+      for (uint32_t i = 0; i < nb_tty; i++)
+	{
+	  // ***** Create a log_file *****
+	  xtty [i].log_file = fopen(param.name_tty[i],"w");
+
+	  if (xtty [i].log_file == NULL)
+	    {
+	      // Error
+	      cerr << "<Tty> Can't open the file : \"" << param.name_tty[i] << "\"" << endl;
+	      exit(1);
+	    }
+
+	  if (with_xtty == true)
+	    {
+	      // ***** TTY and pipe init *****
+	      canal canal_output;
+	      
+	      if (pipe (canal_output.CanalPipe) != 0)
+		{
+		  cerr << "<Tty> Error in pipe creation" << endl;
+		  exit(1);
+		}
+	      
+	      if ((xtty[i].pid = fork()) == 0)
+		{
+		  // Childen -> transform in a xtty
+		  close(0);
+		  dup (canal_output.CanalPipe [0]);
+		  close(1);
+		  execlp("xtty","xtty", param.name_tty [i] ,NULL); // devient un tty
+		  
+		  cerr << "<Tty> Error in the creation of tty" << endl;
+		  exit (1);
+		}
+	      else
+		{
+		  // father
+		  xtty[i].pipe_output = canal_output.CanalPipe [1];
+		}
+	    }
+	}//end for
+    }
+
+  public : ~Tty ()
+    {
+      // Kill all tty
+      for (unsigned int i=0; i<nb_tty; i++)
+      {
+	if (with_xtty == true)
+	  if (xtty[i].pid)
+	    kill(xtty[i].pid,SIGTERM);
+	fclose(xtty[i].log_file);
+      }
+
+    }
+  public : void reset ()
+    {
+    }
+
+    //*****[ write ]*****
+  public : bool write (uint32_t num_tty, char data)
+    {
+      if (num_tty >= nb_tty)
+	return false;
+      char write_data = data;
+
+      if (with_xtty == true)
+	::write (xtty[num_tty].pipe_output, &write_data, 1);
+      fputc (data, xtty[num_tty].log_file);
+
+      return true;
+    }
+
+    public    : friend ostream& operator<< (ostream& output_stream, const Tty & x)
+      {
+	output_stream << "<" << x.name << ">" << endl;
+	output_stream << " * nb_tty        : " << x.nb_tty      << endl;
+
+	return output_stream;
+      };
+  };
+
+};}; //end namespace
+#endif //!TTY_H
Index: /trunk/IPs/systemC/hierarchy_memory/tty/xtty.h
===================================================================
--- /trunk/IPs/systemC/hierarchy_memory/tty/xtty.h	(revision 3)
+++ /trunk/IPs/systemC/hierarchy_memory/tty/xtty.h	(revision 3)
@@ -0,0 +1,20 @@
+#ifndef XTTY_H
+#define XTTY_H
+
+#include <sys/types.h>
+using namespace std;
+
+namespace hierarchy_memory {
+namespace tty              {
+
+  typedef struct canal {int CanalPipe[2];} canal ;
+
+  class xtty_t
+  {
+  public : FILE * log_file;
+  public : pid_t  pid;
+  public : int    pipe_output;
+  };
+
+};}; //end namespace
+#endif //!XTTY_H
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Constant/Constant_OpenRISC.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Constant/Constant_OpenRISC.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Constant/Constant_OpenRISC.h	(revision 3)
@@ -0,0 +1,41 @@
+#ifndef morpheo_behavioural_constant_Constant_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace constant {
+
+  //------------------------------------------------------[ Control ]-----
+  typedef bool    Tcontrol_t;
+
+  //----------------------------------------------------[ Condition ]-----
+  typedef uint8_t Tcondition_t;
+    
+  const Tcondition_t    cst_CONDITION_NONE            = 0x0;           // None condition (jump)
+  const Tcondition_t    cst_CONDITION_F               = 0x2;           // Branch if Flag is set
+  const Tcondition_t    cst_CONDITION_NF              = 0x3;           // Branch if Flag is clear
+  const Tcondition_t    cst_CONDITION_REG             = 0x4;           // Branch if a register is read
+  const Tcondition_t    cst_CONDITION_STACK           = 0x8;           // Branch with pop  in stack pointer
+
+  //-------------------------------------------------[ branch_state ]-----
+  typedef uint8_t Tbranch_state_t;
+
+  const Tbranch_state_t cst_BRANCH_STATE_NONE         = 0x0;           // 0 0
+  const Tbranch_state_t cst_BRANCH_STATE_NSPEC_TAKE   = 0x1;           // 0 1  -> incondionnal
+  const Tbranch_state_t cst_BRANCH_STATE_SPEC_NTAKE   = 0x2;           // 1 0
+  const Tbranch_state_t cst_BRANCH_STATE_SPEC_TAKE    = 0x3;           // 1 1
+
+
+}; // end namespace constant
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/Makefile	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../..
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libCounter.a
+
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/Makefile.deps	(revision 3)
@@ -0,0 +1,31 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+
+Counter			= yes
+
+#-----[ Library ]------------------------------------------
+Counter_LIBRARY		= 	-lCounter	\
+					$(Behavioural_LIBRARY)	
+
+Counter_DIR_LIBRARY		=	-L$(DIR_MORPHEO)/Behavioural/Generic/Counter/lib	\
+					$(Behavioural_DIR_LIBRARY)
+
+#-----[ Rules ]--------------------------------------------
+
+Counter_library		: 
+				@$(MAKE) Behavioural_library
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Counter --makefile=Makefile 
+	
+Counter_library_clean	: 
+				@$(MAKE) Behavioural_library_clean
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Counter --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,29 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../..
+
+LIBRARY				= $(Counter_LIBRARY)
+
+DIR_LIBRARY			= $(Counter_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				:
+				@$(MAKE) all_selftest
+
+library				: Counter_library
+
+library_clean			: Counter_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/configuration.cfg	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/configuration.cfg	(revision 3)
@@ -0,0 +1,3 @@
+Counter
+2	31	*2	# size_data
+1	6	+1	# nb_port
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/include/test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/include/test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/include/test.h	(revision 3)
@@ -0,0 +1,26 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::generic;
+
+using namespace morpheo::behavioural::generic::counter;
+
+void test   (string name,
+	     morpheo::behavioural::generic::counter::Parameters param);
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/mkf.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/mkf.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/mkf.info	(revision 3)
@@ -0,0 +1,81 @@
+
+# Counter_0
+target_dep	all	Counter_0.ngc
+target_dep	Counter_0.ngc	Counter_0.prj
+target_dep	Counter_0.prj	Counter_0_Pack.vhdl Counter_0.vhdl
+
+# Counter_10
+target_dep	all	Counter_10.ngc
+target_dep	Counter_10.ngc	Counter_10.prj
+target_dep	Counter_10.prj	Counter_10_Pack.vhdl Counter_10.vhdl
+
+# Counter_11
+target_dep	all	Counter_11.ngc
+target_dep	Counter_11.ngc	Counter_11.prj
+target_dep	Counter_11.prj	Counter_11_Pack.vhdl Counter_11.vhdl
+
+# Counter_12
+target_dep	all	Counter_12.ngc
+target_dep	Counter_12.ngc	Counter_12.prj
+target_dep	Counter_12.prj	Counter_12_Pack.vhdl Counter_12.vhdl
+
+# Counter_13
+target_dep	all	Counter_13.ngc
+target_dep	Counter_13.ngc	Counter_13.prj
+target_dep	Counter_13.prj	Counter_13_Pack.vhdl Counter_13.vhdl
+
+# Counter_14
+target_dep	all	Counter_14.ngc
+target_dep	Counter_14.ngc	Counter_14.prj
+target_dep	Counter_14.prj	Counter_14_Pack.vhdl Counter_14.vhdl
+
+# Counter_15
+target_dep	all	Counter_15.ngc
+target_dep	Counter_15.ngc	Counter_15.prj
+target_dep	Counter_15.prj	Counter_15_Pack.vhdl Counter_15.vhdl
+
+# Counter_1
+target_dep	all	Counter_1.ngc
+target_dep	Counter_1.ngc	Counter_1.prj
+target_dep	Counter_1.prj	Counter_10_Pack.vhdl Counter_10.vhdl Counter_11_Pack.vhdl Counter_11.vhdl Counter_12_Pack.vhdl Counter_12.vhdl Counter_13_Pack.vhdl Counter_13.vhdl Counter_14_Pack.vhdl Counter_14.vhdl Counter_15_Pack.vhdl Counter_15.vhdl Counter_1_Pack.vhdl Counter_1.vhdl
+
+# Counter_2
+target_dep	all	Counter_2.ngc
+target_dep	Counter_2.ngc	Counter_2.prj
+target_dep	Counter_2.prj	Counter_2_Pack.vhdl Counter_2.vhdl
+
+# Counter_3
+target_dep	all	Counter_3.ngc
+target_dep	Counter_3.ngc	Counter_3.prj
+target_dep	Counter_3.prj	Counter_3_Pack.vhdl Counter_3.vhdl
+
+# Counter_4
+target_dep	all	Counter_4.ngc
+target_dep	Counter_4.ngc	Counter_4.prj
+target_dep	Counter_4.prj	Counter_4_Pack.vhdl Counter_4.vhdl
+
+# Counter_5
+target_dep	all	Counter_5.ngc
+target_dep	Counter_5.ngc	Counter_5.prj
+target_dep	Counter_5.prj	Counter_5_Pack.vhdl Counter_5.vhdl
+
+# Counter_6
+target_dep	all	Counter_6.ngc
+target_dep	Counter_6.ngc	Counter_6.prj
+target_dep	Counter_6.prj	Counter_6_Pack.vhdl Counter_6.vhdl
+
+# Counter_7
+target_dep	all	Counter_7.ngc
+target_dep	Counter_7.ngc	Counter_7.prj
+target_dep	Counter_7.prj	Counter_7_Pack.vhdl Counter_7.vhdl
+
+# Counter_8
+target_dep	all	Counter_8.ngc
+target_dep	Counter_8.ngc	Counter_8.prj
+target_dep	Counter_8.prj	Counter_8_Pack.vhdl Counter_8.vhdl
+
+# Counter_9
+target_dep	all	Counter_9.ngc
+target_dep	Counter_9.ngc	Counter_9.prj
+target_dep	Counter_9.prj	Counter_9_Pack.vhdl Counter_9.vhdl
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,44 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/SelfTest/include/test.h"
+
+#define NB_PARAMS 2
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - size_data     (unsigned int)" << endl
+       << " - nb_port       (unsigned int)" << endl;
+
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc != 2+NB_PARAMS)
+    usage (argv[0]);
+
+  cout << "<test0> : Classic usage" << endl;
+  cout << "<test0> : Typical parameters" << endl;
+  const string   name      = argv[1];
+  const uint32_t size_data = atoi(argv[2]);
+  const uint32_t nb_port   = atoi(argv[3]);
+
+  morpheo::behavioural::generic::counter::Parameters param (size_data,
+							    nb_port  );
+
+  test (name,param);
+
+  return (EXIT_SUCCESS);
+}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp	(revision 3)
@@ -0,0 +1,138 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#define NB_ITERATION 1024
+
+#include "Behavioural/Generic/Counter/SelfTest/include/test.h"
+#include "Include/Test.h"
+
+void test (string name,
+	   morpheo::behavioural::generic::counter::Parameters param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  try 
+    {
+      cout << param.print(1);
+      param.test();
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      return;
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+  Counter * _Counter = new Counter (name.c_str(),
+#ifdef STATISTICS
+				    morpheo::behavioural::Parameters_Statistics(5,50),
+#endif
+				    param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                                 CLOCK ("clock", 1.0, 0.5);
+  sc_signal<Tdata_t>                       DATA_IN  [param._nb_port];
+  sc_signal<Tcontrol_t>                    ADDSUB   [param._nb_port];
+  sc_signal<Tdata_t>                       DATA_OUT [param._nb_port];
+
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Counter" << endl;
+ 
+ #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+  (*(_Counter->in_CLOCK))        (CLOCK);
+#endif
+
+  for (uint32_t i=0; i<param._nb_port; i++)
+    {
+      (*(_Counter-> in_COUNTER_DATA  [i]))        (DATA_IN  [i]);
+      (*(_Counter-> in_COUNTER_ADDSUB[i]))        (ADDSUB   [i]);
+      (*(_Counter->out_COUNTER_DATA  [i]))        (DATA_OUT [i]);
+    }
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  // Initialisation
+
+  srand(0);
+  //srand(TIME(NULL));
+
+  Tdata_t    data_in  [param._nb_port];
+  Tdata_t    data_out [param._nb_port];
+  Tcontrol_t addsub   [param._nb_port];
+
+  sc_start(0);
+  _Counter->vhdl_testbench_label("Initialisation");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl;
+
+  _Counter->vhdl_testbench_label("Loop of Test");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl;
+
+  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+    {
+      _Counter->vhdl_testbench_label("Iteration "+toString(iteration));
+      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} Itération " << iteration << endl;
+      for (uint32_t i=0; i<param._nb_port; i++)
+	{
+	  Tdata_t data = rand()%param._data_max;
+	  data_in  [i] = data;
+	  addsub   [i] = (rand()%2)==1; 
+	  
+	  DATA_IN  [i].write(data      );
+	  ADDSUB   [i].write(addsub [i]);
+
+	  data_out [i] = (addsub[i]==1)?((data<param._data_max)?data+1:data):((data>0)?data-1:data);
+	}
+
+      sc_start(0);
+      
+      for (uint32_t i=0; i<param._nb_port; i++)
+	{
+	  cout << hex 
+	       << "    [" << i << "] "
+	       << data_in [i];
+
+	  if (addsub[i] == 1)
+	    cout << " ++";
+	  else
+	    cout << " --";
+
+	  cout << " = " 
+	       << DATA_OUT [i].read();
+
+	  TEST(Tdata_t,DATA_OUT [i].read(),data_out [i]);
+	   
+	  cout << dec << endl;
+	}
+      
+      sc_start(1);
+    }
+
+  sc_start(1);
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete _Counter;
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/TODO
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/TODO	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/TODO	(revision 3)
@@ -0,0 +1,3 @@
+- Rendre plus généraliste le compteur :
+	* nombre de bits
+	
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/VERSION
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/VERSION	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/VERSION	(revision 3)
@@ -0,0 +1,1 @@
+v0.2
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Counter.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Counter.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Counter.h	(revision 3)
@@ -0,0 +1,126 @@
+#ifndef morpheo_behavioural_generic_counter_Counter_h
+#define morpheo_behavioural_generic_counter_Counter_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <iostream>
+#include "Include/ToString.h"
+#include "Include/Debug.h"
+
+#include "Behavioural/Generic/Counter/include/Parameters.h"
+#include "Behavioural/Generic/Counter/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/Generic/Counter/include/Statistics.h"
+#endif
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#ifdef VHDL_TESTBENCH
+#include "Behavioural/include/Vhdl_Testbench.h"
+#endif
+
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  class Counter 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string     _name;
+
+  protected : const Parameters _param;
+//#ifdef STATISTICS
+//  protected : const morpheo::behavioural::Parameters_Statistics _param_statistics;
+//#endif
+
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+#endif
+
+#ifdef VHDL_TESTBENCH
+  private   : Vhdl_Testbench                 * _vhdl_testbench;
+#endif
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK        ;
+
+  public    : SC_IN (Tdata_t)              **  in_COUNTER_DATA         ;
+  public    : SC_IN (Tcontrol_t)           **  in_COUNTER_ADDSUB       ;
+  public    : SC_OUT(Tdata_t)              ** out_COUNTER_DATA         ;
+    
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#endif
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (Counter);
+
+  public  :          Counter              (sc_module_name                              name,
+#else					       
+  public  :          Counter              (string                                      name,
+#endif					       
+#ifdef STATISTICS
+					   morpheo::behavioural::Parameters_Statistics param_statistics,
+#endif
+					   Parameters                                  param );
+					       
+  public  :          Counter              (Parameters param );
+  public  :          ~Counter             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+  public  : void     transition                (void);
+#endif
+  public  : void     genMealy                  (void);
+#endif					       
+#ifdef STATISTICS
+  public  : string   statistics                (uint32_t depth);
+#endif
+					       
+#if VHDL				       
+  public  : void     vhdl                      (void);
+  private : void     vhdl_port                 (Vhdl & vhdl);
+  private : void     vhdl_declaration          (Vhdl & vhdl);
+  private : void     vhdl_body                 (Vhdl & vhdl);
+#endif					       
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench_port       (void);
+  private : void     vhdl_testbench_transition (void);
+#endif
+  public  : void     vhdl_testbench_label      (string label);
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Parameters.h	(revision 3)
@@ -0,0 +1,47 @@
+#ifndef morpheo_behavioural_generic_counter_Parameters_h
+#define morpheo_behavioural_generic_counter_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+    //-----[ fields ]------------------------------------------------------------
+  public : const uint32_t _size_data;
+  public : const uint32_t _nb_port  ;
+  public : const uint32_t _data_max ;
+
+    //-----[ methods ]-----------------------------------------------------------
+  public : Parameters  (uint32_t size_data,
+			uint32_t nb_port  );
+  public : Parameters  (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::generic::counter::Parameters & x);
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Statistics.h	(revision 3)
@@ -0,0 +1,55 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_generic_counter_Statistics_h
+#define morpheo_behavioural_generic_counter_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+//#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/Generic/Counter/include/Parameters.h"
+
+//using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                   _parameters;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics  (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  );
+//public   : Statistics  (Statistics & stat);
+  public   : ~Statistics () ;
+    
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : void     add        ();
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Types.h	(revision 3)
@@ -0,0 +1,28 @@
+#ifdef SYSTEMC
+#ifndef morpheo_behavioural_generic_counter_Type_h
+#define morpheo_behavioural_generic_counter_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Types.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+  typedef uint32_t Tdata_t;
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter.cpp	(revision 3)
@@ -0,0 +1,105 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+#ifdef SYSTEMC
+  Counter::Counter (sc_module_name name,
+#else
+  Counter::Counter (string name,
+#endif
+#ifdef STATISTICS
+			      morpheo::behavioural::Parameters_Statistics             param_statistics,
+#endif
+			      morpheo::behavioural::generic::counter::Parameters param ):
+			      _name              (name)
+			      ,_param            (param)
+// #ifdef STATISTICS
+// 			      ,_param_statistics (param_statistics)
+// #endif
+  {
+    log_printf(FUNC,Counter,"Counter","Begin");
+
+#ifdef STATISTICS
+    // Allocation of statistics
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // Creation of a testbench
+    //  -> port
+    //  -> clock's signals
+    _vhdl_testbench = new Vhdl_Testbench (_name);
+    vhdl_testbench_port           ();
+    _vhdl_testbench->set_clock    ("in_CLOCK",false);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    allocation ();
+
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+
+    SC_METHOD (genMealy);
+    dont_initialize ();
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      sensitive << *(in_COUNTER_DATA   [i])
+		<< *(in_COUNTER_ADDSUB [i]);
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	(*(out_COUNTER_DATA [i])) (*(in_COUNTER_DATA   [i]));
+	(*(out_COUNTER_DATA [i])) (*(in_COUNTER_ADDSUB [i]));
+      }
+#endif    
+
+#endif
+    log_printf(FUNC,Counter,"Counter","End");
+  };
+  
+  Counter::~Counter (void)
+  {
+    log_printf(FUNC,Counter,"~Counter","Begin");
+#ifdef SYSTEMC
+    deallocation ();
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // generate the test bench
+    _vhdl_testbench->generate_file();
+    delete _vhdl_testbench;
+#endif
+
+#ifdef STATISTICS
+    _stat->generate_file(statistics(0));
+    
+    delete _stat;
+#endif
+    log_printf(FUNC,Counter,"~Counter","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp	(revision 3)
@@ -0,0 +1,52 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::allocation (void)
+  {
+    string rename;
+
+    log_printf(FUNC,Counter,"allocation","Begin");
+
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+    in_CLOCK  = new SC_CLOCK           ("in_CLOCK");
+#endif
+
+     in_COUNTER_DATA  = new SC_IN (Tdata_t)    * [_param._nb_port];
+     in_COUNTER_ADDSUB= new SC_IN (Tcontrol_t) * [_param._nb_port];
+    out_COUNTER_DATA  = new SC_OUT(Tdata_t)    * [_param._nb_port];
+    
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	rename = " in_COUNTER_DATA_" +toString(i);
+	 in_COUNTER_DATA  [i] = new SC_IN (Tdata_t)    (rename.c_str());
+
+	rename = " in_COUNTER_ADDSUB_"+toString(i);
+	 in_COUNTER_ADDSUB[i] = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	rename = "out_COUNTER_DATA_" +toString(i);
+	out_COUNTER_DATA  [i] = new SC_OUT(Tdata_t)    (rename.c_str());
+      }
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    log_printf(FUNC,Counter,"allocation","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::deallocation (void)
+  {
+    log_printf(FUNC,Counter,"deallocation","Begin");
+
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+    delete in_CLOCK;
+#endif
+    
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	delete  in_COUNTER_DATA  [i];
+	delete  in_COUNTER_ADDSUB[i];
+	delete out_COUNTER_DATA  [i];
+      }
+    delete  in_COUNTER_DATA  ;
+    delete  in_COUNTER_ADDSUB;
+    delete out_COUNTER_DATA  ;
+    
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    log_printf(FUNC,Counter,"deallocation","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_genMealy.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_genMealy.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_genMealy.cpp	(revision 3)
@@ -0,0 +1,53 @@
+#ifdef SYSTEMC
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+  void Counter::genMealy (void)
+  {
+    log_printf(FUNC,Counter,"genMealy","Begin");
+
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	Tcontrol_t addsub  = PORT_READ(in_COUNTER_ADDSUB [i]);
+	Tdata_t    data_in = PORT_READ(in_COUNTER_DATA   [i]);
+	Tdata_t    data_out= data_in;
+	log_printf(TRACE,Counter,"genMealy","before : %d %s = %d",data_in,((addsub==1)?"++":"--"),data_out);
+
+	// Staturate counter
+	if (addsub == 1)
+	  {
+	    if (data_out < _param._data_max)
+	      data_out++;
+	  }
+	else
+	  {
+	    if (data_out > 0)
+	      data_out--;
+	  }
+
+	log_printf(TRACE,Counter,"genMealy","after   : %d %s = %d",data_in,((addsub==1)?"++":"--"),data_out);
+    
+	PORT_WRITE(out_COUNTER_DATA[i], data_out);
+      }
+
+    log_printf(FUNC,Counter,"genMealy","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_statistics.cpp	(revision 3)
@@ -0,0 +1,32 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+  string Counter::statistics (uint32_t depth)
+  {
+    log_printf(FUNC,Counter,"statistics","Begin");
+
+    string txt = _stat->print(depth);
+
+    log_printf(FUNC,Counter,"statistics","End");
+
+    return txt;
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_transition.cpp	(revision 3)
@@ -0,0 +1,39 @@
+#ifdef SYSTEMC
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::transition (void)
+  {
+    log_printf(FUNC,Counter,"transition","Begin");
+
+#ifdef STATISTICS
+    _stat->add();
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition ();
+#endif
+
+    log_printf(FUNC,Counter,"transition","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl.cpp	(revision 3)
@@ -0,0 +1,39 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::vhdl (void)
+  {
+    log_printf(FUNC,Counter,"vhdl","Begin");
+    Vhdl vhdl (_name);
+
+    vhdl.set_library_work (_name + "_Pack");
+
+    vhdl_port        (vhdl);
+    vhdl_declaration (vhdl);
+    vhdl_body        (vhdl);
+
+    vhdl.generate_file();
+    log_printf(FUNC,Counter,"vhdl","End");
+
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_body.cpp	(revision 3)
@@ -0,0 +1,58 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::vhdl_body (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Counter,"vhdl_body","Begin");
+    vhdl.set_body ("");
+    
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	string counter_inc, counter_dec;
+
+	if (_param._size_data > 1)
+	  {
+	    counter_inc = "in_COUNTER_DATA_"+toString(i)+"+1";
+	    counter_dec = "in_COUNTER_DATA_"+toString(i)+"-1";
+	  }
+	else
+	  {
+	    counter_inc = "in_COUNTER_DATA_"+toString(i)+"+1";
+	    counter_dec = "in_COUNTER_DATA_"+toString(i)+"-1";
+	  }
+
+	vhdl.set_body ("out_COUNTER_DATA_"+toString(i)+" <=");
+	if (_param._size_data > 1)
+	  {
+	    vhdl.set_body ("\tin_COUNTER_DATA_"+toString(i)+"+1 when in_COUNTER_ADDSUB_"+toString(i)+" = '1' and in_COUNTER_DATA_"+toString(i)+" < cst_max else");
+	    vhdl.set_body ("\tin_COUNTER_DATA_"+toString(i)+"-1 when in_COUNTER_ADDSUB_"+toString(i)+" = '0' and in_COUNTER_DATA_"+toString(i)+" > cst_min else");
+	    vhdl.set_body ("\tin_COUNTER_DATA_"+toString(i)+";");
+	  }
+	else
+	  {
+	    vhdl.set_body ("\tin_COUNTER_ADDSUB_"+toString(i)+";");
+	  }
+      }
+
+    log_printf(FUNC,Counter,"vhdl_body","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_declaration.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_declaration.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_declaration.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::vhdl_declaration (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Counter,"vhdl_declaration","Begin");
+    
+    if (_param._size_data > 1)
+      {
+	vhdl.set_constant ("cst_min",_param._size_data,std_logic_others(_param._size_data,0));
+	vhdl.set_constant ("cst_max",_param._size_data,std_logic_others(_param._size_data,1));
+      }
+
+    log_printf(FUNC,Counter,"vhdl_declaration","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_port.cpp	(revision 3)
@@ -0,0 +1,36 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::vhdl_port (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Counter,"vhdl_port","Begin");
+
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	vhdl.set_port (" in_COUNTER_DATA_"  +toString(i), IN, _param._size_data);
+	vhdl.set_port (" in_COUNTER_ADDSUB_"+toString(i), IN, 1                );
+	vhdl.set_port ("out_COUNTER_DATA_"  +toString(i),OUT, _param._size_data);
+      }
+    
+    log_printf(FUNC,Counter,"vhdl_port","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_label.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_label.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_label.cpp	(revision 3)
@@ -0,0 +1,27 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::vhdl_testbench_label (string label)
+  {
+#ifdef VHDL_TESTBENCH
+    _vhdl_testbench->add_label(label);
+#endif
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_port.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::vhdl_testbench_port ()
+  {
+    log_printf(FUNC,Counter,"vhdl_testbench_port","Begin");
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	_vhdl_testbench->set_port (" in_COUNTER_DATA_"  +toString(i), IN, _param._size_data);
+	_vhdl_testbench->set_port (" in_COUNTER_ADDSUB_"+toString(i), IN, 1);
+	_vhdl_testbench->set_port ("out_COUNTER_DATA_"  +toString(i),OUT, _param._size_data);
+      }
+
+    log_printf(FUNC,Counter,"vhdl_testbench_port","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_transition.cpp	(revision 3)
@@ -0,0 +1,49 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Counter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Counter::vhdl_testbench_transition ()
+  {
+    log_printf(FUNC,Counter,"vhdl_testbench_transition","Begin");
+
+    sc_start(0);
+
+    // In order with file Counter_vhdl_testbench_port.cpp
+    // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
+    // (because we have no control on the ordonnancer's policy)
+
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	_vhdl_testbench->add_input (PORT_READ( in_COUNTER_DATA  [i]));
+	_vhdl_testbench->add_input (PORT_READ( in_COUNTER_ADDSUB[i]));
+	_vhdl_testbench->add_output(PORT_READ(out_COUNTER_DATA  [i]));
+      }
+    
+    // add_test :
+    //  - True  : the cycle must be compare with the output of systemC
+    //  - False : no test
+    _vhdl_testbench->add_test(true);
+
+    _vhdl_testbench->new_cycle (); // always at the end
+
+    log_printf(FUNC,Counter,"vhdl_testbench_transition","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,47 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Parameters.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  Parameters::Parameters (uint32_t size_data,
+			  uint32_t nb_port  ):
+    _size_data(size_data),
+    _nb_port  (nb_port  ),
+    _data_max ((1<<size_data)-1)
+  {
+    log_printf(FUNC,Counter,"Parameters","Begin");
+    test();
+    log_printf(FUNC,Counter,"Parameters","End");
+  };
+  
+  Parameters::Parameters (Parameters & param):
+    _size_data(param._size_data),
+    _nb_port  (param._nb_port  ),
+    _data_max (param._data_max )
+  {
+    log_printf(FUNC,Counter,"Parameters","Begin");
+    test();
+    log_printf(FUNC,Counter,"Parameters","End");
+  };
+
+  Parameters::~Parameters () 
+  {
+    log_printf(FUNC,Counter,"~Parameters","Begin");
+    log_printf(FUNC,Counter,"~Parameters","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters_msg_error.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters_msg_error.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters_msg_error.cpp	(revision 3)
@@ -0,0 +1,46 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Parameters.h"
+#include "Behavioural/Generic/Counter/include/Types.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  string Parameters::msg_error(void)
+  {
+    log_printf(FUNC,Counter,"msg_error","Begin");
+
+    string msg = "";
+
+    if (_size_data < 1)
+      {
+        msg += "  - size_data must be > 0\n";
+        msg += "    * size_data                       : " + toString(_size_data) + "\n";
+      }
+
+    if (_nb_port < 1)
+      {
+        msg += "  - nb_port must be > 0\n";
+        msg += "    * nb_port                         : " + toString(_nb_port) + "\n";
+      }
+
+    return msg;
+
+    log_printf(FUNC,Counter,"msg_error","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters_print.cpp	(revision 3)
@@ -0,0 +1,50 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Parameters.h"
+#include "Behavioural/include/XML.h"
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  string Parameters::print (uint32_t depth)
+  {
+    log_printf(FUNC,Counter,"print","Begin");
+
+    XML xml ("counter");
+
+    xml.balise_open("counter");
+    xml.  singleton_begin("size_data");
+    xml.    attribut("value",toString(_size_data));
+    xml.  singleton_end();
+    xml.  singleton_begin("nb_port  ");
+    xml.    attribut("value",toString(_nb_port));
+    xml.  singleton_end();
+    xml.balise_close();
+
+    log_printf(FUNC,Counter,"print","End");
+    
+    return xml.get_body(depth);
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::generic::counter::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,40 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+    log_printf(FUNC,Counter,"Statistics","Begin");
+    log_printf(FUNC,Counter,"Statistics","End");
+  };
+  
+  Statistics::~Statistics () 
+  { 
+    log_printf(FUNC,Counter,"~Statistics","Begin");
+    log_printf(FUNC,Counter,"~Statistics","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,31 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  void Statistics::add ()
+  {
+    log_printf(FUNC,Counter,"add","Begin");
+    log_printf(FUNC,Counter,"add","End");
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,49 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  string Statistics::print (uint32_t depth)
+  {
+    log_printf(FUNC,Counter,"print","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<counter name=\"" << _name << "\" >" << endl
+        << print_body(depth+1)
+	<< tab << "</counter>" << endl;
+    
+    log_printf(FUNC,Counter,"print","End");
+
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::generic::counter::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,39 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Counter/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace counter {
+
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    log_printf(FUNC,Counter,"print_body","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "";
+    
+    log_printf(FUNC,Counter,"print_body","End");
+
+    return msg.str();
+  };
+
+}; // end namespace counter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/Makefile	(revision 3)
@@ -0,0 +1,22 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../..
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libGroup.a
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/Makefile.deps	(revision 3)
@@ -0,0 +1,31 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+
+Group			= yes
+
+#-----[ Library ]------------------------------------------
+Group_LIBRARY		= 	-lGroup	\
+				-lBehavioural
+
+Group_DIR_LIBRARY	=	-L$(DIR_MORPHEO)/Behavioural/Generic/Group/lib	\
+				-L$(DIR_MORPHEO)/Behavioural/lib
+
+#-----[ Rules ]--------------------------------------------
+
+Group_library		:
+				@$(MAKE)  Behavioural_library
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Group --makefile=Makefile 
+	
+Group_library_clean	:
+				@$(MAKE)  Behavioural_library_clean
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Group --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/include/Counters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/include/Counters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/include/Counters.h	(revision 3)
@@ -0,0 +1,38 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_generic_group_Counters_h
+#define morpheo_behavioural_generic_group_Counters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Group/include/Parameters.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace group                      {
+
+  class Counters
+  {
+  public : uint32_t _nb_cycle_none_use  ;
+  public : uint32_t _nb_cycle_full_use  ;
+  public : uint32_t _nb_cycle_normal_use;
+  public : uint32_t _nb_use             ;
+
+  public : Counters  (Parameters parameters);
+  public : Counters  (Counters & counters);
+  public : ~Counters ();
+
+  };// end class counters
+  
+}; // end namespace group 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/include/Parameters.h	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_generic_group_Parameters_h
+#define morpheo_behavioural_generic_group_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace group                      {
+  class Parameters
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Constant
+  public   : const uint32_t   _nb_elt;
+    
+    // -----[ methods ]---------------------------------------------------
+  public   :                  Parameters (uint32_t   nb_elt);
+  public   :                  ~Parameters ();
+  };
+
+}; // end namespace group 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/include/Statistics.h	(revision 3)
@@ -0,0 +1,53 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_generic_group_Statistics_h
+#define morpheo_behavioural_generic_group_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/Generic/Group/include/Parameters.h"
+#include "Behavioural/Generic/Group/include/Counters.h"
+
+using namespace morpheo::behavioural;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace group                      {
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters            _parameters;
+  private  : Counters                 ** _counters;
+
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics (string                                      name                       ,
+			 morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			 Parameters                                  parameters
+			 );
+//public   : Statistics (Statistics & stat);
+  public   : ~Statistics ();
+    
+  public   :        string   print_body (uint32_t depth);
+  public   :        string   print      (uint32_t depth);
+  public   :        void     add        (uint32_t nb_use);
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace group 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Counters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Counters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Counters.cpp	(revision 3)
@@ -0,0 +1,40 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Group/include/Counters.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace group                      {
+
+  Counters::Counters (Parameters parameters)
+    {
+      _nb_cycle_none_use   = 0;
+      _nb_cycle_full_use   = 0;
+      _nb_cycle_normal_use = 0;
+      _nb_use              = 0;
+    };
+
+  Counters::Counters (Counters & counters)
+    {
+      _nb_cycle_none_use   = counters._nb_cycle_none_use  ;
+      _nb_cycle_full_use   = counters._nb_cycle_full_use  ;
+      _nb_cycle_normal_use = counters._nb_cycle_normal_use;
+      _nb_use              = counters._nb_use             ;
+    };
+
+  Counters::~Counters ()
+  {
+  };
+
+}; // end namespace group 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Group/include/Parameters.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace group                      {
+
+  Parameters::Parameters (uint32_t   nb_elt):
+    _nb_elt (nb_elt               )
+  {};
+    
+  Parameters::~Parameters () {};
+  
+}; // end namespace group 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,42 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Group/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace group                      {
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters (parameters)
+  {};
+    
+//   Statistics::Statistics (Statistics & stat) :
+// 		       _nb_port_read      (param._nb_port_read ),
+// 		       _nb_port_write     (param._nb_port_write),
+// 		       _nb_word           (param._nb_word      ),
+// 		       _size_word         (param._size_word    )
+//     { };
+
+  Statistics::~Statistics () 
+  {
+    for (uint32_t i=0; i<_nb_statistics; i++)
+      delete _counters[i];
+  };
+
+}; // end namespace group 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,55 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/src/Statistics_test_if_save.cpp"
+#include "Behavioural/src/Statistics_save.cpp"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace group                      {
+
+  // Explicite instanciation
+  template void behavioural::Statistics::test_if_save<behavioural::generic::group::Counters,
+						      behavioural::generic::group::Parameters>
+  (behavioural::generic::group::Counters ** &,
+   behavioural::generic::group::Parameters);
+
+  template void behavioural::Statistics::save        <behavioural::generic::group::Counters,
+						      behavioural::generic::group::Parameters>
+  (behavioural::generic::group::Counters ** &,
+   behavioural::generic::group::Parameters);
+        
+
+  void Statistics::add (uint32_t nb_use)
+  {
+    test_if_save<Counters,Parameters>(_counters,_parameters);
+
+    if (_nb_statistics>0)
+      {
+	int i = _nb_statistics-1;
+	_counters[i]->_nb_use += nb_use;
+
+	if (nb_use == 0)
+	  _counters[i]->_nb_cycle_none_use   ++;
+	else 
+	  if (nb_use == _parameters._nb_elt)
+	    _counters[i]->_nb_cycle_full_use   ++;
+	  else
+	    _counters[i]->_nb_cycle_normal_use ++;
+      }
+  };
+
+}; // end namespace group 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,43 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Group/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace group                      {
+
+  string Statistics::print (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+    
+    msg << tab << "<goup name=\"" << _name << "\" >" << endl
+	<< print_body(depth+1)
+	<< tab << "</group>" << endl;
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::generic::group::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace group 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Group/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,56 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Group/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace group                      {
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+    
+    for (uint32_t i=0; i<_nb_statistics; i++)
+      {
+	uint32_t nb_cycle    = (_counters[i]->_nb_cycle_none_use + 
+				_counters[i]->_nb_cycle_full_use + 
+				_counters[i]->_nb_cycle_normal_use);
+	
+	uint32_t cycle_begin = compute_cycle_begin(i);
+	uint32_t cycle_end   = compute_cycle_end  (i,nb_cycle);
+
+	msg << tab << "\t<cycle begin=\"" << cycle_begin << "\" end=\"" << cycle_end << "\">" << endl
+	           << tab << "\t\t<nb_cycle_none_use   value=\"" 
+	                  << _counters[i]->_nb_cycle_none_use                     << "\" /> <!-- " 
+	                  << percent(_counters[i]->_nb_cycle_none_use  ,nb_cycle) << "% -->" << endl
+	           << tab << "\t\t<nb_cycle_full_use   value=\"" 
+	                  << _counters[i]->_nb_cycle_full_use                     << "\" /> <!-- " 
+	                  << percent(_counters[i]->_nb_cycle_full_use  ,nb_cycle) << "% -->" << endl
+	           << tab << "\t\t<nb_cycle_normal_use value=\"" 
+	                  << _counters[i]->_nb_cycle_normal_use                   << "\" /> <!-- " 
+	                  << percent(_counters[i]->_nb_cycle_normal_use,nb_cycle) << "% -->" << endl
+	           << tab << "\t\t<nb_use              value=\"" 
+	                  << _counters[i]->_nb_use                                << "\" /> <!-- average : " 
+	                  << average(_counters[i]->_nb_use,                    nb_cycle)      << " - " 
+	                  << percent(_counters[i]->_nb_use,_parameters._nb_elt*nb_cycle)      << "% -->" << endl
+	    << tab << "\t</cycle>" << endl;
+      }
+    
+    return msg.str();
+  };
+}; // end namespace group 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/Makefile	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../..
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libRegisterFile.a
+
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/Makefile.deps	(revision 3)
@@ -0,0 +1,37 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+ifndef Group
+include 			$(DIR_MORPHEO)/Behavioural/Generic/Group/Makefile.deps
+endif
+
+RegisterFile			= yes
+#-----[ Library ]------------------------------------------
+RegisterFile_LIBRARY		= 	-lRegisterFile		\
+					$(Group_LIBRARY)	\
+					$(Behavioural_LIBRARY)	
+
+RegisterFile_DIR_LIBRARY	=	-L$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/lib	\
+					$(Group_DIR_LIBRARY)					\
+					$(Behavioural_DIR_LIBRARY)	
+
+#-----[ Rules ]--------------------------------------------
+
+RegisterFile_library		:
+				@$(MAKE)  Behavioural_library
+				@$(MAKE)  Group_library
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile --makefile=Makefile 
+	
+RegisterFile_library_clean	:
+				@$(MAKE)  Behavioural_library_clean
+				@$(MAKE)  Group_library_clean
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,29 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../..
+
+LIBRARY				= $(RegisterFile_LIBRARY)
+
+DIR_LIBRARY			= $(RegisterFile_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				: library
+				@$(MAKE) all_selftest
+
+library				: RegisterFile_library
+
+library_clean			: RegisterFile_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration.cfg	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/configuration.cfg	(revision 3)
@@ -0,0 +1,5 @@
+RegisterFile
+1	2	+1	# nb_port_read
+1	2	+1	# nb_port_write
+2	1024	*8	# nb_word
+8	16	*2	# size_word
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/include/test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/include/test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/include/test.h	(revision 3)
@@ -0,0 +1,25 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::generic;
+using namespace morpheo::behavioural::generic::registerfile;
+
+void test   (string name,
+	     morpheo::behavioural::generic::registerfile::Parameters param);
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/mkf.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/mkf.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/mkf.info	(revision 3)
@@ -0,0 +1,801 @@
+
+# RegisterFile_0
+target_dep	all	RegisterFile_0.ngc
+target_dep	RegisterFile_0.ngc	RegisterFile_0.prj
+target_dep	RegisterFile_0.prj	RegisterFile_0_Pack.vhdl RegisterFile_0.vhdl
+
+# RegisterFile_100
+target_dep	all	RegisterFile_100.ngc
+target_dep	RegisterFile_100.ngc	RegisterFile_100.prj
+target_dep	RegisterFile_100.prj	RegisterFile_100_Pack.vhdl RegisterFile_100.vhdl
+
+# RegisterFile_101
+target_dep	all	RegisterFile_101.ngc
+target_dep	RegisterFile_101.ngc	RegisterFile_101.prj
+target_dep	RegisterFile_101.prj	RegisterFile_101_Pack.vhdl RegisterFile_101.vhdl
+
+# RegisterFile_102
+target_dep	all	RegisterFile_102.ngc
+target_dep	RegisterFile_102.ngc	RegisterFile_102.prj
+target_dep	RegisterFile_102.prj	RegisterFile_102_Pack.vhdl RegisterFile_102.vhdl
+
+# RegisterFile_103
+target_dep	all	RegisterFile_103.ngc
+target_dep	RegisterFile_103.ngc	RegisterFile_103.prj
+target_dep	RegisterFile_103.prj	RegisterFile_103_Pack.vhdl RegisterFile_103.vhdl
+
+# RegisterFile_104
+target_dep	all	RegisterFile_104.ngc
+target_dep	RegisterFile_104.ngc	RegisterFile_104.prj
+target_dep	RegisterFile_104.prj	RegisterFile_104_Pack.vhdl RegisterFile_104.vhdl
+
+# RegisterFile_105
+target_dep	all	RegisterFile_105.ngc
+target_dep	RegisterFile_105.ngc	RegisterFile_105.prj
+target_dep	RegisterFile_105.prj	RegisterFile_105_Pack.vhdl RegisterFile_105.vhdl
+
+# RegisterFile_106
+target_dep	all	RegisterFile_106.ngc
+target_dep	RegisterFile_106.ngc	RegisterFile_106.prj
+target_dep	RegisterFile_106.prj	RegisterFile_106_Pack.vhdl RegisterFile_106.vhdl
+
+# RegisterFile_107
+target_dep	all	RegisterFile_107.ngc
+target_dep	RegisterFile_107.ngc	RegisterFile_107.prj
+target_dep	RegisterFile_107.prj	RegisterFile_107_Pack.vhdl RegisterFile_107.vhdl
+
+# RegisterFile_108
+target_dep	all	RegisterFile_108.ngc
+target_dep	RegisterFile_108.ngc	RegisterFile_108.prj
+target_dep	RegisterFile_108.prj	RegisterFile_108_Pack.vhdl RegisterFile_108.vhdl
+
+# RegisterFile_109
+target_dep	all	RegisterFile_109.ngc
+target_dep	RegisterFile_109.ngc	RegisterFile_109.prj
+target_dep	RegisterFile_109.prj	RegisterFile_109_Pack.vhdl RegisterFile_109.vhdl
+
+# RegisterFile_10
+target_dep	all	RegisterFile_10.ngc
+target_dep	RegisterFile_10.ngc	RegisterFile_10.prj
+target_dep	RegisterFile_10.prj	RegisterFile_100_Pack.vhdl RegisterFile_100.vhdl RegisterFile_101_Pack.vhdl RegisterFile_101.vhdl RegisterFile_102_Pack.vhdl RegisterFile_102.vhdl RegisterFile_103_Pack.vhdl RegisterFile_103.vhdl RegisterFile_104_Pack.vhdl RegisterFile_104.vhdl RegisterFile_105_Pack.vhdl RegisterFile_105.vhdl RegisterFile_106_Pack.vhdl RegisterFile_106.vhdl RegisterFile_107_Pack.vhdl RegisterFile_107.vhdl RegisterFile_108_Pack.vhdl RegisterFile_108.vhdl RegisterFile_109_Pack.vhdl RegisterFile_109.vhdl RegisterFile_10_Pack.vhdl RegisterFile_10.vhdl
+
+# RegisterFile_110
+target_dep	all	RegisterFile_110.ngc
+target_dep	RegisterFile_110.ngc	RegisterFile_110.prj
+target_dep	RegisterFile_110.prj	RegisterFile_110_Pack.vhdl RegisterFile_110.vhdl
+
+# RegisterFile_111
+target_dep	all	RegisterFile_111.ngc
+target_dep	RegisterFile_111.ngc	RegisterFile_111.prj
+target_dep	RegisterFile_111.prj	RegisterFile_111_Pack.vhdl RegisterFile_111.vhdl
+
+# RegisterFile_112
+target_dep	all	RegisterFile_112.ngc
+target_dep	RegisterFile_112.ngc	RegisterFile_112.prj
+target_dep	RegisterFile_112.prj	RegisterFile_112_Pack.vhdl RegisterFile_112.vhdl
+
+# RegisterFile_113
+target_dep	all	RegisterFile_113.ngc
+target_dep	RegisterFile_113.ngc	RegisterFile_113.prj
+target_dep	RegisterFile_113.prj	RegisterFile_113_Pack.vhdl RegisterFile_113.vhdl
+
+# RegisterFile_114
+target_dep	all	RegisterFile_114.ngc
+target_dep	RegisterFile_114.ngc	RegisterFile_114.prj
+target_dep	RegisterFile_114.prj	RegisterFile_114_Pack.vhdl RegisterFile_114.vhdl
+
+# RegisterFile_115
+target_dep	all	RegisterFile_115.ngc
+target_dep	RegisterFile_115.ngc	RegisterFile_115.prj
+target_dep	RegisterFile_115.prj	RegisterFile_115_Pack.vhdl RegisterFile_115.vhdl
+
+# RegisterFile_116
+target_dep	all	RegisterFile_116.ngc
+target_dep	RegisterFile_116.ngc	RegisterFile_116.prj
+target_dep	RegisterFile_116.prj	RegisterFile_116_Pack.vhdl RegisterFile_116.vhdl
+
+# RegisterFile_117
+target_dep	all	RegisterFile_117.ngc
+target_dep	RegisterFile_117.ngc	RegisterFile_117.prj
+target_dep	RegisterFile_117.prj	RegisterFile_117_Pack.vhdl RegisterFile_117.vhdl
+
+# RegisterFile_118
+target_dep	all	RegisterFile_118.ngc
+target_dep	RegisterFile_118.ngc	RegisterFile_118.prj
+target_dep	RegisterFile_118.prj	RegisterFile_118_Pack.vhdl RegisterFile_118.vhdl
+
+# RegisterFile_119
+target_dep	all	RegisterFile_119.ngc
+target_dep	RegisterFile_119.ngc	RegisterFile_119.prj
+target_dep	RegisterFile_119.prj	RegisterFile_119_Pack.vhdl RegisterFile_119.vhdl
+
+# RegisterFile_11
+target_dep	all	RegisterFile_11.ngc
+target_dep	RegisterFile_11.ngc	RegisterFile_11.prj
+target_dep	RegisterFile_11.prj	RegisterFile_110_Pack.vhdl RegisterFile_110.vhdl RegisterFile_111_Pack.vhdl RegisterFile_111.vhdl RegisterFile_112_Pack.vhdl RegisterFile_112.vhdl RegisterFile_113_Pack.vhdl RegisterFile_113.vhdl RegisterFile_114_Pack.vhdl RegisterFile_114.vhdl RegisterFile_115_Pack.vhdl RegisterFile_115.vhdl RegisterFile_116_Pack.vhdl RegisterFile_116.vhdl RegisterFile_117_Pack.vhdl RegisterFile_117.vhdl RegisterFile_118_Pack.vhdl RegisterFile_118.vhdl RegisterFile_119_Pack.vhdl RegisterFile_119.vhdl RegisterFile_11_Pack.vhdl RegisterFile_11.vhdl
+
+# RegisterFile_120
+target_dep	all	RegisterFile_120.ngc
+target_dep	RegisterFile_120.ngc	RegisterFile_120.prj
+target_dep	RegisterFile_120.prj	RegisterFile_120_Pack.vhdl RegisterFile_120.vhdl
+
+# RegisterFile_121
+target_dep	all	RegisterFile_121.ngc
+target_dep	RegisterFile_121.ngc	RegisterFile_121.prj
+target_dep	RegisterFile_121.prj	RegisterFile_121_Pack.vhdl RegisterFile_121.vhdl
+
+# RegisterFile_122
+target_dep	all	RegisterFile_122.ngc
+target_dep	RegisterFile_122.ngc	RegisterFile_122.prj
+target_dep	RegisterFile_122.prj	RegisterFile_122_Pack.vhdl RegisterFile_122.vhdl
+
+# RegisterFile_123
+target_dep	all	RegisterFile_123.ngc
+target_dep	RegisterFile_123.ngc	RegisterFile_123.prj
+target_dep	RegisterFile_123.prj	RegisterFile_123_Pack.vhdl RegisterFile_123.vhdl
+
+# RegisterFile_124
+target_dep	all	RegisterFile_124.ngc
+target_dep	RegisterFile_124.ngc	RegisterFile_124.prj
+target_dep	RegisterFile_124.prj	RegisterFile_124_Pack.vhdl RegisterFile_124.vhdl
+
+# RegisterFile_125
+target_dep	all	RegisterFile_125.ngc
+target_dep	RegisterFile_125.ngc	RegisterFile_125.prj
+target_dep	RegisterFile_125.prj	RegisterFile_125_Pack.vhdl RegisterFile_125.vhdl
+
+# RegisterFile_126
+target_dep	all	RegisterFile_126.ngc
+target_dep	RegisterFile_126.ngc	RegisterFile_126.prj
+target_dep	RegisterFile_126.prj	RegisterFile_126_Pack.vhdl RegisterFile_126.vhdl
+
+# RegisterFile_127
+target_dep	all	RegisterFile_127.ngc
+target_dep	RegisterFile_127.ngc	RegisterFile_127.prj
+target_dep	RegisterFile_127.prj	RegisterFile_127_Pack.vhdl RegisterFile_127.vhdl
+
+# RegisterFile_128
+target_dep	all	RegisterFile_128.ngc
+target_dep	RegisterFile_128.ngc	RegisterFile_128.prj
+target_dep	RegisterFile_128.prj	RegisterFile_128_Pack.vhdl RegisterFile_128.vhdl
+
+# RegisterFile_129
+target_dep	all	RegisterFile_129.ngc
+target_dep	RegisterFile_129.ngc	RegisterFile_129.prj
+target_dep	RegisterFile_129.prj	RegisterFile_129_Pack.vhdl RegisterFile_129.vhdl
+
+# RegisterFile_12
+target_dep	all	RegisterFile_12.ngc
+target_dep	RegisterFile_12.ngc	RegisterFile_12.prj
+target_dep	RegisterFile_12.prj	RegisterFile_120_Pack.vhdl RegisterFile_120.vhdl RegisterFile_121_Pack.vhdl RegisterFile_121.vhdl RegisterFile_122_Pack.vhdl RegisterFile_122.vhdl RegisterFile_123_Pack.vhdl RegisterFile_123.vhdl RegisterFile_124_Pack.vhdl RegisterFile_124.vhdl RegisterFile_125_Pack.vhdl RegisterFile_125.vhdl RegisterFile_126_Pack.vhdl RegisterFile_126.vhdl RegisterFile_127_Pack.vhdl RegisterFile_127.vhdl RegisterFile_128_Pack.vhdl RegisterFile_128.vhdl RegisterFile_129_Pack.vhdl RegisterFile_129.vhdl RegisterFile_12_Pack.vhdl RegisterFile_12.vhdl
+
+# RegisterFile_130
+target_dep	all	RegisterFile_130.ngc
+target_dep	RegisterFile_130.ngc	RegisterFile_130.prj
+target_dep	RegisterFile_130.prj	RegisterFile_130_Pack.vhdl RegisterFile_130.vhdl
+
+# RegisterFile_131
+target_dep	all	RegisterFile_131.ngc
+target_dep	RegisterFile_131.ngc	RegisterFile_131.prj
+target_dep	RegisterFile_131.prj	RegisterFile_131_Pack.vhdl RegisterFile_131.vhdl
+
+# RegisterFile_132
+target_dep	all	RegisterFile_132.ngc
+target_dep	RegisterFile_132.ngc	RegisterFile_132.prj
+target_dep	RegisterFile_132.prj	RegisterFile_132_Pack.vhdl RegisterFile_132.vhdl
+
+# RegisterFile_133
+target_dep	all	RegisterFile_133.ngc
+target_dep	RegisterFile_133.ngc	RegisterFile_133.prj
+target_dep	RegisterFile_133.prj	RegisterFile_133_Pack.vhdl RegisterFile_133.vhdl
+
+# RegisterFile_134
+target_dep	all	RegisterFile_134.ngc
+target_dep	RegisterFile_134.ngc	RegisterFile_134.prj
+target_dep	RegisterFile_134.prj	RegisterFile_134_Pack.vhdl RegisterFile_134.vhdl
+
+# RegisterFile_135
+target_dep	all	RegisterFile_135.ngc
+target_dep	RegisterFile_135.ngc	RegisterFile_135.prj
+target_dep	RegisterFile_135.prj	RegisterFile_135_Pack.vhdl RegisterFile_135.vhdl
+
+# RegisterFile_136
+target_dep	all	RegisterFile_136.ngc
+target_dep	RegisterFile_136.ngc	RegisterFile_136.prj
+target_dep	RegisterFile_136.prj	RegisterFile_136_Pack.vhdl RegisterFile_136.vhdl
+
+# RegisterFile_137
+target_dep	all	RegisterFile_137.ngc
+target_dep	RegisterFile_137.ngc	RegisterFile_137.prj
+target_dep	RegisterFile_137.prj	RegisterFile_137_Pack.vhdl RegisterFile_137.vhdl
+
+# RegisterFile_138
+target_dep	all	RegisterFile_138.ngc
+target_dep	RegisterFile_138.ngc	RegisterFile_138.prj
+target_dep	RegisterFile_138.prj	RegisterFile_138_Pack.vhdl RegisterFile_138.vhdl
+
+# RegisterFile_139
+target_dep	all	RegisterFile_139.ngc
+target_dep	RegisterFile_139.ngc	RegisterFile_139.prj
+target_dep	RegisterFile_139.prj	RegisterFile_139_Pack.vhdl RegisterFile_139.vhdl
+
+# RegisterFile_13
+target_dep	all	RegisterFile_13.ngc
+target_dep	RegisterFile_13.ngc	RegisterFile_13.prj
+target_dep	RegisterFile_13.prj	RegisterFile_130_Pack.vhdl RegisterFile_130.vhdl RegisterFile_131_Pack.vhdl RegisterFile_131.vhdl RegisterFile_132_Pack.vhdl RegisterFile_132.vhdl RegisterFile_133_Pack.vhdl RegisterFile_133.vhdl RegisterFile_134_Pack.vhdl RegisterFile_134.vhdl RegisterFile_135_Pack.vhdl RegisterFile_135.vhdl RegisterFile_136_Pack.vhdl RegisterFile_136.vhdl RegisterFile_137_Pack.vhdl RegisterFile_137.vhdl RegisterFile_138_Pack.vhdl RegisterFile_138.vhdl RegisterFile_139_Pack.vhdl RegisterFile_139.vhdl RegisterFile_13_Pack.vhdl RegisterFile_13.vhdl
+
+# RegisterFile_140
+target_dep	all	RegisterFile_140.ngc
+target_dep	RegisterFile_140.ngc	RegisterFile_140.prj
+target_dep	RegisterFile_140.prj	RegisterFile_140_Pack.vhdl RegisterFile_140.vhdl
+
+# RegisterFile_141
+target_dep	all	RegisterFile_141.ngc
+target_dep	RegisterFile_141.ngc	RegisterFile_141.prj
+target_dep	RegisterFile_141.prj	RegisterFile_141_Pack.vhdl RegisterFile_141.vhdl
+
+# RegisterFile_142
+target_dep	all	RegisterFile_142.ngc
+target_dep	RegisterFile_142.ngc	RegisterFile_142.prj
+target_dep	RegisterFile_142.prj	RegisterFile_142_Pack.vhdl RegisterFile_142.vhdl
+
+# RegisterFile_143
+target_dep	all	RegisterFile_143.ngc
+target_dep	RegisterFile_143.ngc	RegisterFile_143.prj
+target_dep	RegisterFile_143.prj	RegisterFile_143_Pack.vhdl RegisterFile_143.vhdl
+
+# RegisterFile_144
+target_dep	all	RegisterFile_144.ngc
+target_dep	RegisterFile_144.ngc	RegisterFile_144.prj
+target_dep	RegisterFile_144.prj	RegisterFile_144_Pack.vhdl RegisterFile_144.vhdl
+
+# RegisterFile_145
+target_dep	all	RegisterFile_145.ngc
+target_dep	RegisterFile_145.ngc	RegisterFile_145.prj
+target_dep	RegisterFile_145.prj	RegisterFile_145_Pack.vhdl RegisterFile_145.vhdl
+
+# RegisterFile_146
+target_dep	all	RegisterFile_146.ngc
+target_dep	RegisterFile_146.ngc	RegisterFile_146.prj
+target_dep	RegisterFile_146.prj	RegisterFile_146_Pack.vhdl RegisterFile_146.vhdl
+
+# RegisterFile_147
+target_dep	all	RegisterFile_147.ngc
+target_dep	RegisterFile_147.ngc	RegisterFile_147.prj
+target_dep	RegisterFile_147.prj	RegisterFile_147_Pack.vhdl RegisterFile_147.vhdl
+
+# RegisterFile_148
+target_dep	all	RegisterFile_148.ngc
+target_dep	RegisterFile_148.ngc	RegisterFile_148.prj
+target_dep	RegisterFile_148.prj	RegisterFile_148_Pack.vhdl RegisterFile_148.vhdl
+
+# RegisterFile_149
+target_dep	all	RegisterFile_149.ngc
+target_dep	RegisterFile_149.ngc	RegisterFile_149.prj
+target_dep	RegisterFile_149.prj	RegisterFile_149_Pack.vhdl RegisterFile_149.vhdl
+
+# RegisterFile_14
+target_dep	all	RegisterFile_14.ngc
+target_dep	RegisterFile_14.ngc	RegisterFile_14.prj
+target_dep	RegisterFile_14.prj	RegisterFile_140_Pack.vhdl RegisterFile_140.vhdl RegisterFile_141_Pack.vhdl RegisterFile_141.vhdl RegisterFile_142_Pack.vhdl RegisterFile_142.vhdl RegisterFile_143_Pack.vhdl RegisterFile_143.vhdl RegisterFile_144_Pack.vhdl RegisterFile_144.vhdl RegisterFile_145_Pack.vhdl RegisterFile_145.vhdl RegisterFile_146_Pack.vhdl RegisterFile_146.vhdl RegisterFile_147_Pack.vhdl RegisterFile_147.vhdl RegisterFile_148_Pack.vhdl RegisterFile_148.vhdl RegisterFile_149_Pack.vhdl RegisterFile_149.vhdl RegisterFile_14_Pack.vhdl RegisterFile_14.vhdl
+
+# RegisterFile_150
+target_dep	all	RegisterFile_150.ngc
+target_dep	RegisterFile_150.ngc	RegisterFile_150.prj
+target_dep	RegisterFile_150.prj	RegisterFile_150_Pack.vhdl RegisterFile_150.vhdl
+
+# RegisterFile_151
+target_dep	all	RegisterFile_151.ngc
+target_dep	RegisterFile_151.ngc	RegisterFile_151.prj
+target_dep	RegisterFile_151.prj	RegisterFile_151_Pack.vhdl RegisterFile_151.vhdl
+
+# RegisterFile_152
+target_dep	all	RegisterFile_152.ngc
+target_dep	RegisterFile_152.ngc	RegisterFile_152.prj
+target_dep	RegisterFile_152.prj	RegisterFile_152_Pack.vhdl RegisterFile_152.vhdl
+
+# RegisterFile_153
+target_dep	all	RegisterFile_153.ngc
+target_dep	RegisterFile_153.ngc	RegisterFile_153.prj
+target_dep	RegisterFile_153.prj	RegisterFile_153_Pack.vhdl RegisterFile_153.vhdl
+
+# RegisterFile_154
+target_dep	all	RegisterFile_154.ngc
+target_dep	RegisterFile_154.ngc	RegisterFile_154.prj
+target_dep	RegisterFile_154.prj	RegisterFile_154_Pack.vhdl RegisterFile_154.vhdl
+
+# RegisterFile_155
+target_dep	all	RegisterFile_155.ngc
+target_dep	RegisterFile_155.ngc	RegisterFile_155.prj
+target_dep	RegisterFile_155.prj	RegisterFile_155_Pack.vhdl RegisterFile_155.vhdl
+
+# RegisterFile_156
+target_dep	all	RegisterFile_156.ngc
+target_dep	RegisterFile_156.ngc	RegisterFile_156.prj
+target_dep	RegisterFile_156.prj	RegisterFile_156_Pack.vhdl RegisterFile_156.vhdl
+
+# RegisterFile_157
+target_dep	all	RegisterFile_157.ngc
+target_dep	RegisterFile_157.ngc	RegisterFile_157.prj
+target_dep	RegisterFile_157.prj	RegisterFile_157_Pack.vhdl RegisterFile_157.vhdl
+
+# RegisterFile_158
+target_dep	all	RegisterFile_158.ngc
+target_dep	RegisterFile_158.ngc	RegisterFile_158.prj
+target_dep	RegisterFile_158.prj	RegisterFile_158_Pack.vhdl RegisterFile_158.vhdl
+
+# RegisterFile_159
+target_dep	all	RegisterFile_159.ngc
+target_dep	RegisterFile_159.ngc	RegisterFile_159.prj
+target_dep	RegisterFile_159.prj	RegisterFile_159_Pack.vhdl RegisterFile_159.vhdl
+
+# RegisterFile_15
+target_dep	all	RegisterFile_15.ngc
+target_dep	RegisterFile_15.ngc	RegisterFile_15.prj
+target_dep	RegisterFile_15.prj	RegisterFile_150_Pack.vhdl RegisterFile_150.vhdl RegisterFile_151_Pack.vhdl RegisterFile_151.vhdl RegisterFile_152_Pack.vhdl RegisterFile_152.vhdl RegisterFile_153_Pack.vhdl RegisterFile_153.vhdl RegisterFile_154_Pack.vhdl RegisterFile_154.vhdl RegisterFile_155_Pack.vhdl RegisterFile_155.vhdl RegisterFile_156_Pack.vhdl RegisterFile_156.vhdl RegisterFile_157_Pack.vhdl RegisterFile_157.vhdl RegisterFile_158_Pack.vhdl RegisterFile_158.vhdl RegisterFile_159_Pack.vhdl RegisterFile_159.vhdl RegisterFile_15_Pack.vhdl RegisterFile_15.vhdl
+
+# RegisterFile_16
+target_dep	all	RegisterFile_16.ngc
+target_dep	RegisterFile_16.ngc	RegisterFile_16.prj
+target_dep	RegisterFile_16.prj	RegisterFile_16_Pack.vhdl RegisterFile_16.vhdl
+
+# RegisterFile_17
+target_dep	all	RegisterFile_17.ngc
+target_dep	RegisterFile_17.ngc	RegisterFile_17.prj
+target_dep	RegisterFile_17.prj	RegisterFile_17_Pack.vhdl RegisterFile_17.vhdl
+
+# RegisterFile_18
+target_dep	all	RegisterFile_18.ngc
+target_dep	RegisterFile_18.ngc	RegisterFile_18.prj
+target_dep	RegisterFile_18.prj	RegisterFile_18_Pack.vhdl RegisterFile_18.vhdl
+
+# RegisterFile_19
+target_dep	all	RegisterFile_19.ngc
+target_dep	RegisterFile_19.ngc	RegisterFile_19.prj
+target_dep	RegisterFile_19.prj	RegisterFile_19_Pack.vhdl RegisterFile_19.vhdl
+
+# RegisterFile_1
+target_dep	all	RegisterFile_1.ngc
+target_dep	RegisterFile_1.ngc	RegisterFile_1.prj
+target_dep	RegisterFile_1.prj	RegisterFile_100_Pack.vhdl RegisterFile_100.vhdl RegisterFile_101_Pack.vhdl RegisterFile_101.vhdl RegisterFile_102_Pack.vhdl RegisterFile_102.vhdl RegisterFile_103_Pack.vhdl RegisterFile_103.vhdl RegisterFile_104_Pack.vhdl RegisterFile_104.vhdl RegisterFile_105_Pack.vhdl RegisterFile_105.vhdl RegisterFile_106_Pack.vhdl RegisterFile_106.vhdl RegisterFile_107_Pack.vhdl RegisterFile_107.vhdl RegisterFile_108_Pack.vhdl RegisterFile_108.vhdl RegisterFile_109_Pack.vhdl RegisterFile_109.vhdl RegisterFile_10_Pack.vhdl RegisterFile_10.vhdl RegisterFile_110_Pack.vhdl RegisterFile_110.vhdl RegisterFile_111_Pack.vhdl RegisterFile_111.vhdl RegisterFile_112_Pack.vhdl RegisterFile_112.vhdl RegisterFile_113_Pack.vhdl RegisterFile_113.vhdl RegisterFile_114_Pack.vhdl RegisterFile_114.vhdl RegisterFile_115_Pack.vhdl RegisterFile_115.vhdl RegisterFile_116_Pack.vhdl RegisterFile_116.vhdl RegisterFile_117_Pack.vhdl RegisterFile_117.vhdl RegisterFile_118_Pack.vhdl RegisterFile_118.vhdl RegisterFile_119_Pack.vhdl RegisterFile_119.vhdl RegisterFile_11_Pack.vhdl RegisterFile_11.vhdl RegisterFile_120_Pack.vhdl RegisterFile_120.vhdl RegisterFile_121_Pack.vhdl RegisterFile_121.vhdl RegisterFile_122_Pack.vhdl RegisterFile_122.vhdl RegisterFile_123_Pack.vhdl RegisterFile_123.vhdl RegisterFile_124_Pack.vhdl RegisterFile_124.vhdl RegisterFile_125_Pack.vhdl RegisterFile_125.vhdl RegisterFile_126_Pack.vhdl RegisterFile_126.vhdl RegisterFile_127_Pack.vhdl RegisterFile_127.vhdl RegisterFile_128_Pack.vhdl RegisterFile_128.vhdl RegisterFile_129_Pack.vhdl RegisterFile_129.vhdl RegisterFile_12_Pack.vhdl RegisterFile_12.vhdl RegisterFile_130_Pack.vhdl RegisterFile_130.vhdl RegisterFile_131_Pack.vhdl RegisterFile_131.vhdl RegisterFile_132_Pack.vhdl RegisterFile_132.vhdl RegisterFile_133_Pack.vhdl RegisterFile_133.vhdl RegisterFile_134_Pack.vhdl RegisterFile_134.vhdl RegisterFile_135_Pack.vhdl RegisterFile_135.vhdl RegisterFile_136_Pack.vhdl RegisterFile_136.vhdl RegisterFile_137_Pack.vhdl RegisterFile_137.vhdl RegisterFile_138_Pack.vhdl RegisterFile_138.vhdl RegisterFile_139_Pack.vhdl RegisterFile_139.vhdl RegisterFile_13_Pack.vhdl RegisterFile_13.vhdl RegisterFile_140_Pack.vhdl RegisterFile_140.vhdl RegisterFile_141_Pack.vhdl RegisterFile_141.vhdl RegisterFile_142_Pack.vhdl RegisterFile_142.vhdl RegisterFile_143_Pack.vhdl RegisterFile_143.vhdl RegisterFile_144_Pack.vhdl RegisterFile_144.vhdl RegisterFile_145_Pack.vhdl RegisterFile_145.vhdl RegisterFile_146_Pack.vhdl RegisterFile_146.vhdl RegisterFile_147_Pack.vhdl RegisterFile_147.vhdl RegisterFile_148_Pack.vhdl RegisterFile_148.vhdl RegisterFile_149_Pack.vhdl RegisterFile_149.vhdl RegisterFile_14_Pack.vhdl RegisterFile_14.vhdl RegisterFile_150_Pack.vhdl RegisterFile_150.vhdl RegisterFile_151_Pack.vhdl RegisterFile_151.vhdl RegisterFile_152_Pack.vhdl RegisterFile_152.vhdl RegisterFile_153_Pack.vhdl RegisterFile_153.vhdl RegisterFile_154_Pack.vhdl RegisterFile_154.vhdl RegisterFile_155_Pack.vhdl RegisterFile_155.vhdl RegisterFile_156_Pack.vhdl RegisterFile_156.vhdl RegisterFile_157_Pack.vhdl RegisterFile_157.vhdl RegisterFile_158_Pack.vhdl RegisterFile_158.vhdl RegisterFile_159_Pack.vhdl RegisterFile_159.vhdl RegisterFile_15_Pack.vhdl RegisterFile_15.vhdl RegisterFile_16_Pack.vhdl RegisterFile_16.vhdl RegisterFile_17_Pack.vhdl RegisterFile_17.vhdl RegisterFile_18_Pack.vhdl RegisterFile_18.vhdl RegisterFile_19_Pack.vhdl RegisterFile_19.vhdl RegisterFile_1_Pack.vhdl RegisterFile_1.vhdl
+
+# RegisterFile_20
+target_dep	all	RegisterFile_20.ngc
+target_dep	RegisterFile_20.ngc	RegisterFile_20.prj
+target_dep	RegisterFile_20.prj	RegisterFile_20_Pack.vhdl RegisterFile_20.vhdl
+
+# RegisterFile_21
+target_dep	all	RegisterFile_21.ngc
+target_dep	RegisterFile_21.ngc	RegisterFile_21.prj
+target_dep	RegisterFile_21.prj	RegisterFile_21_Pack.vhdl RegisterFile_21.vhdl
+
+# RegisterFile_22
+target_dep	all	RegisterFile_22.ngc
+target_dep	RegisterFile_22.ngc	RegisterFile_22.prj
+target_dep	RegisterFile_22.prj	RegisterFile_22_Pack.vhdl RegisterFile_22.vhdl
+
+# RegisterFile_23
+target_dep	all	RegisterFile_23.ngc
+target_dep	RegisterFile_23.ngc	RegisterFile_23.prj
+target_dep	RegisterFile_23.prj	RegisterFile_23_Pack.vhdl RegisterFile_23.vhdl
+
+# RegisterFile_24
+target_dep	all	RegisterFile_24.ngc
+target_dep	RegisterFile_24.ngc	RegisterFile_24.prj
+target_dep	RegisterFile_24.prj	RegisterFile_24_Pack.vhdl RegisterFile_24.vhdl
+
+# RegisterFile_25
+target_dep	all	RegisterFile_25.ngc
+target_dep	RegisterFile_25.ngc	RegisterFile_25.prj
+target_dep	RegisterFile_25.prj	RegisterFile_25_Pack.vhdl RegisterFile_25.vhdl
+
+# RegisterFile_26
+target_dep	all	RegisterFile_26.ngc
+target_dep	RegisterFile_26.ngc	RegisterFile_26.prj
+target_dep	RegisterFile_26.prj	RegisterFile_26_Pack.vhdl RegisterFile_26.vhdl
+
+# RegisterFile_27
+target_dep	all	RegisterFile_27.ngc
+target_dep	RegisterFile_27.ngc	RegisterFile_27.prj
+target_dep	RegisterFile_27.prj	RegisterFile_27_Pack.vhdl RegisterFile_27.vhdl
+
+# RegisterFile_28
+target_dep	all	RegisterFile_28.ngc
+target_dep	RegisterFile_28.ngc	RegisterFile_28.prj
+target_dep	RegisterFile_28.prj	RegisterFile_28_Pack.vhdl RegisterFile_28.vhdl
+
+# RegisterFile_29
+target_dep	all	RegisterFile_29.ngc
+target_dep	RegisterFile_29.ngc	RegisterFile_29.prj
+target_dep	RegisterFile_29.prj	RegisterFile_29_Pack.vhdl RegisterFile_29.vhdl
+
+# RegisterFile_2
+target_dep	all	RegisterFile_2.ngc
+target_dep	RegisterFile_2.ngc	RegisterFile_2.prj
+target_dep	RegisterFile_2.prj	RegisterFile_20_Pack.vhdl RegisterFile_20.vhdl RegisterFile_21_Pack.vhdl RegisterFile_21.vhdl RegisterFile_22_Pack.vhdl RegisterFile_22.vhdl RegisterFile_23_Pack.vhdl RegisterFile_23.vhdl RegisterFile_24_Pack.vhdl RegisterFile_24.vhdl RegisterFile_25_Pack.vhdl RegisterFile_25.vhdl RegisterFile_26_Pack.vhdl RegisterFile_26.vhdl RegisterFile_27_Pack.vhdl RegisterFile_27.vhdl RegisterFile_28_Pack.vhdl RegisterFile_28.vhdl RegisterFile_29_Pack.vhdl RegisterFile_29.vhdl RegisterFile_2_Pack.vhdl RegisterFile_2.vhdl
+
+# RegisterFile_30
+target_dep	all	RegisterFile_30.ngc
+target_dep	RegisterFile_30.ngc	RegisterFile_30.prj
+target_dep	RegisterFile_30.prj	RegisterFile_30_Pack.vhdl RegisterFile_30.vhdl
+
+# RegisterFile_31
+target_dep	all	RegisterFile_31.ngc
+target_dep	RegisterFile_31.ngc	RegisterFile_31.prj
+target_dep	RegisterFile_31.prj	RegisterFile_31_Pack.vhdl RegisterFile_31.vhdl
+
+# RegisterFile_32
+target_dep	all	RegisterFile_32.ngc
+target_dep	RegisterFile_32.ngc	RegisterFile_32.prj
+target_dep	RegisterFile_32.prj	RegisterFile_32_Pack.vhdl RegisterFile_32.vhdl
+
+# RegisterFile_33
+target_dep	all	RegisterFile_33.ngc
+target_dep	RegisterFile_33.ngc	RegisterFile_33.prj
+target_dep	RegisterFile_33.prj	RegisterFile_33_Pack.vhdl RegisterFile_33.vhdl
+
+# RegisterFile_34
+target_dep	all	RegisterFile_34.ngc
+target_dep	RegisterFile_34.ngc	RegisterFile_34.prj
+target_dep	RegisterFile_34.prj	RegisterFile_34_Pack.vhdl RegisterFile_34.vhdl
+
+# RegisterFile_35
+target_dep	all	RegisterFile_35.ngc
+target_dep	RegisterFile_35.ngc	RegisterFile_35.prj
+target_dep	RegisterFile_35.prj	RegisterFile_35_Pack.vhdl RegisterFile_35.vhdl
+
+# RegisterFile_36
+target_dep	all	RegisterFile_36.ngc
+target_dep	RegisterFile_36.ngc	RegisterFile_36.prj
+target_dep	RegisterFile_36.prj	RegisterFile_36_Pack.vhdl RegisterFile_36.vhdl
+
+# RegisterFile_37
+target_dep	all	RegisterFile_37.ngc
+target_dep	RegisterFile_37.ngc	RegisterFile_37.prj
+target_dep	RegisterFile_37.prj	RegisterFile_37_Pack.vhdl RegisterFile_37.vhdl
+
+# RegisterFile_38
+target_dep	all	RegisterFile_38.ngc
+target_dep	RegisterFile_38.ngc	RegisterFile_38.prj
+target_dep	RegisterFile_38.prj	RegisterFile_38_Pack.vhdl RegisterFile_38.vhdl
+
+# RegisterFile_39
+target_dep	all	RegisterFile_39.ngc
+target_dep	RegisterFile_39.ngc	RegisterFile_39.prj
+target_dep	RegisterFile_39.prj	RegisterFile_39_Pack.vhdl RegisterFile_39.vhdl
+
+# RegisterFile_3
+target_dep	all	RegisterFile_3.ngc
+target_dep	RegisterFile_3.ngc	RegisterFile_3.prj
+target_dep	RegisterFile_3.prj	RegisterFile_30_Pack.vhdl RegisterFile_30.vhdl RegisterFile_31_Pack.vhdl RegisterFile_31.vhdl RegisterFile_32_Pack.vhdl RegisterFile_32.vhdl RegisterFile_33_Pack.vhdl RegisterFile_33.vhdl RegisterFile_34_Pack.vhdl RegisterFile_34.vhdl RegisterFile_35_Pack.vhdl RegisterFile_35.vhdl RegisterFile_36_Pack.vhdl RegisterFile_36.vhdl RegisterFile_37_Pack.vhdl RegisterFile_37.vhdl RegisterFile_38_Pack.vhdl RegisterFile_38.vhdl RegisterFile_39_Pack.vhdl RegisterFile_39.vhdl RegisterFile_3_Pack.vhdl RegisterFile_3.vhdl
+
+# RegisterFile_40
+target_dep	all	RegisterFile_40.ngc
+target_dep	RegisterFile_40.ngc	RegisterFile_40.prj
+target_dep	RegisterFile_40.prj	RegisterFile_40_Pack.vhdl RegisterFile_40.vhdl
+
+# RegisterFile_41
+target_dep	all	RegisterFile_41.ngc
+target_dep	RegisterFile_41.ngc	RegisterFile_41.prj
+target_dep	RegisterFile_41.prj	RegisterFile_41_Pack.vhdl RegisterFile_41.vhdl
+
+# RegisterFile_42
+target_dep	all	RegisterFile_42.ngc
+target_dep	RegisterFile_42.ngc	RegisterFile_42.prj
+target_dep	RegisterFile_42.prj	RegisterFile_42_Pack.vhdl RegisterFile_42.vhdl
+
+# RegisterFile_43
+target_dep	all	RegisterFile_43.ngc
+target_dep	RegisterFile_43.ngc	RegisterFile_43.prj
+target_dep	RegisterFile_43.prj	RegisterFile_43_Pack.vhdl RegisterFile_43.vhdl
+
+# RegisterFile_44
+target_dep	all	RegisterFile_44.ngc
+target_dep	RegisterFile_44.ngc	RegisterFile_44.prj
+target_dep	RegisterFile_44.prj	RegisterFile_44_Pack.vhdl RegisterFile_44.vhdl
+
+# RegisterFile_45
+target_dep	all	RegisterFile_45.ngc
+target_dep	RegisterFile_45.ngc	RegisterFile_45.prj
+target_dep	RegisterFile_45.prj	RegisterFile_45_Pack.vhdl RegisterFile_45.vhdl
+
+# RegisterFile_46
+target_dep	all	RegisterFile_46.ngc
+target_dep	RegisterFile_46.ngc	RegisterFile_46.prj
+target_dep	RegisterFile_46.prj	RegisterFile_46_Pack.vhdl RegisterFile_46.vhdl
+
+# RegisterFile_47
+target_dep	all	RegisterFile_47.ngc
+target_dep	RegisterFile_47.ngc	RegisterFile_47.prj
+target_dep	RegisterFile_47.prj	RegisterFile_47_Pack.vhdl RegisterFile_47.vhdl
+
+# RegisterFile_48
+target_dep	all	RegisterFile_48.ngc
+target_dep	RegisterFile_48.ngc	RegisterFile_48.prj
+target_dep	RegisterFile_48.prj	RegisterFile_48_Pack.vhdl RegisterFile_48.vhdl
+
+# RegisterFile_49
+target_dep	all	RegisterFile_49.ngc
+target_dep	RegisterFile_49.ngc	RegisterFile_49.prj
+target_dep	RegisterFile_49.prj	RegisterFile_49_Pack.vhdl RegisterFile_49.vhdl
+
+# RegisterFile_4
+target_dep	all	RegisterFile_4.ngc
+target_dep	RegisterFile_4.ngc	RegisterFile_4.prj
+target_dep	RegisterFile_4.prj	RegisterFile_40_Pack.vhdl RegisterFile_40.vhdl RegisterFile_41_Pack.vhdl RegisterFile_41.vhdl RegisterFile_42_Pack.vhdl RegisterFile_42.vhdl RegisterFile_43_Pack.vhdl RegisterFile_43.vhdl RegisterFile_44_Pack.vhdl RegisterFile_44.vhdl RegisterFile_45_Pack.vhdl RegisterFile_45.vhdl RegisterFile_46_Pack.vhdl RegisterFile_46.vhdl RegisterFile_47_Pack.vhdl RegisterFile_47.vhdl RegisterFile_48_Pack.vhdl RegisterFile_48.vhdl RegisterFile_49_Pack.vhdl RegisterFile_49.vhdl RegisterFile_4_Pack.vhdl RegisterFile_4.vhdl
+
+# RegisterFile_50
+target_dep	all	RegisterFile_50.ngc
+target_dep	RegisterFile_50.ngc	RegisterFile_50.prj
+target_dep	RegisterFile_50.prj	RegisterFile_50_Pack.vhdl RegisterFile_50.vhdl
+
+# RegisterFile_51
+target_dep	all	RegisterFile_51.ngc
+target_dep	RegisterFile_51.ngc	RegisterFile_51.prj
+target_dep	RegisterFile_51.prj	RegisterFile_51_Pack.vhdl RegisterFile_51.vhdl
+
+# RegisterFile_52
+target_dep	all	RegisterFile_52.ngc
+target_dep	RegisterFile_52.ngc	RegisterFile_52.prj
+target_dep	RegisterFile_52.prj	RegisterFile_52_Pack.vhdl RegisterFile_52.vhdl
+
+# RegisterFile_53
+target_dep	all	RegisterFile_53.ngc
+target_dep	RegisterFile_53.ngc	RegisterFile_53.prj
+target_dep	RegisterFile_53.prj	RegisterFile_53_Pack.vhdl RegisterFile_53.vhdl
+
+# RegisterFile_54
+target_dep	all	RegisterFile_54.ngc
+target_dep	RegisterFile_54.ngc	RegisterFile_54.prj
+target_dep	RegisterFile_54.prj	RegisterFile_54_Pack.vhdl RegisterFile_54.vhdl
+
+# RegisterFile_55
+target_dep	all	RegisterFile_55.ngc
+target_dep	RegisterFile_55.ngc	RegisterFile_55.prj
+target_dep	RegisterFile_55.prj	RegisterFile_55_Pack.vhdl RegisterFile_55.vhdl
+
+# RegisterFile_56
+target_dep	all	RegisterFile_56.ngc
+target_dep	RegisterFile_56.ngc	RegisterFile_56.prj
+target_dep	RegisterFile_56.prj	RegisterFile_56_Pack.vhdl RegisterFile_56.vhdl
+
+# RegisterFile_57
+target_dep	all	RegisterFile_57.ngc
+target_dep	RegisterFile_57.ngc	RegisterFile_57.prj
+target_dep	RegisterFile_57.prj	RegisterFile_57_Pack.vhdl RegisterFile_57.vhdl
+
+# RegisterFile_58
+target_dep	all	RegisterFile_58.ngc
+target_dep	RegisterFile_58.ngc	RegisterFile_58.prj
+target_dep	RegisterFile_58.prj	RegisterFile_58_Pack.vhdl RegisterFile_58.vhdl
+
+# RegisterFile_59
+target_dep	all	RegisterFile_59.ngc
+target_dep	RegisterFile_59.ngc	RegisterFile_59.prj
+target_dep	RegisterFile_59.prj	RegisterFile_59_Pack.vhdl RegisterFile_59.vhdl
+
+# RegisterFile_5
+target_dep	all	RegisterFile_5.ngc
+target_dep	RegisterFile_5.ngc	RegisterFile_5.prj
+target_dep	RegisterFile_5.prj	RegisterFile_50_Pack.vhdl RegisterFile_50.vhdl RegisterFile_51_Pack.vhdl RegisterFile_51.vhdl RegisterFile_52_Pack.vhdl RegisterFile_52.vhdl RegisterFile_53_Pack.vhdl RegisterFile_53.vhdl RegisterFile_54_Pack.vhdl RegisterFile_54.vhdl RegisterFile_55_Pack.vhdl RegisterFile_55.vhdl RegisterFile_56_Pack.vhdl RegisterFile_56.vhdl RegisterFile_57_Pack.vhdl RegisterFile_57.vhdl RegisterFile_58_Pack.vhdl RegisterFile_58.vhdl RegisterFile_59_Pack.vhdl RegisterFile_59.vhdl RegisterFile_5_Pack.vhdl RegisterFile_5.vhdl
+
+# RegisterFile_60
+target_dep	all	RegisterFile_60.ngc
+target_dep	RegisterFile_60.ngc	RegisterFile_60.prj
+target_dep	RegisterFile_60.prj	RegisterFile_60_Pack.vhdl RegisterFile_60.vhdl
+
+# RegisterFile_61
+target_dep	all	RegisterFile_61.ngc
+target_dep	RegisterFile_61.ngc	RegisterFile_61.prj
+target_dep	RegisterFile_61.prj	RegisterFile_61_Pack.vhdl RegisterFile_61.vhdl
+
+# RegisterFile_62
+target_dep	all	RegisterFile_62.ngc
+target_dep	RegisterFile_62.ngc	RegisterFile_62.prj
+target_dep	RegisterFile_62.prj	RegisterFile_62_Pack.vhdl RegisterFile_62.vhdl
+
+# RegisterFile_63
+target_dep	all	RegisterFile_63.ngc
+target_dep	RegisterFile_63.ngc	RegisterFile_63.prj
+target_dep	RegisterFile_63.prj	RegisterFile_63_Pack.vhdl RegisterFile_63.vhdl
+
+# RegisterFile_64
+target_dep	all	RegisterFile_64.ngc
+target_dep	RegisterFile_64.ngc	RegisterFile_64.prj
+target_dep	RegisterFile_64.prj	RegisterFile_64_Pack.vhdl RegisterFile_64.vhdl
+
+# RegisterFile_65
+target_dep	all	RegisterFile_65.ngc
+target_dep	RegisterFile_65.ngc	RegisterFile_65.prj
+target_dep	RegisterFile_65.prj	RegisterFile_65_Pack.vhdl RegisterFile_65.vhdl
+
+# RegisterFile_66
+target_dep	all	RegisterFile_66.ngc
+target_dep	RegisterFile_66.ngc	RegisterFile_66.prj
+target_dep	RegisterFile_66.prj	RegisterFile_66_Pack.vhdl RegisterFile_66.vhdl
+
+# RegisterFile_67
+target_dep	all	RegisterFile_67.ngc
+target_dep	RegisterFile_67.ngc	RegisterFile_67.prj
+target_dep	RegisterFile_67.prj	RegisterFile_67_Pack.vhdl RegisterFile_67.vhdl
+
+# RegisterFile_68
+target_dep	all	RegisterFile_68.ngc
+target_dep	RegisterFile_68.ngc	RegisterFile_68.prj
+target_dep	RegisterFile_68.prj	RegisterFile_68_Pack.vhdl RegisterFile_68.vhdl
+
+# RegisterFile_69
+target_dep	all	RegisterFile_69.ngc
+target_dep	RegisterFile_69.ngc	RegisterFile_69.prj
+target_dep	RegisterFile_69.prj	RegisterFile_69_Pack.vhdl RegisterFile_69.vhdl
+
+# RegisterFile_6
+target_dep	all	RegisterFile_6.ngc
+target_dep	RegisterFile_6.ngc	RegisterFile_6.prj
+target_dep	RegisterFile_6.prj	RegisterFile_60_Pack.vhdl RegisterFile_60.vhdl RegisterFile_61_Pack.vhdl RegisterFile_61.vhdl RegisterFile_62_Pack.vhdl RegisterFile_62.vhdl RegisterFile_63_Pack.vhdl RegisterFile_63.vhdl RegisterFile_64_Pack.vhdl RegisterFile_64.vhdl RegisterFile_65_Pack.vhdl RegisterFile_65.vhdl RegisterFile_66_Pack.vhdl RegisterFile_66.vhdl RegisterFile_67_Pack.vhdl RegisterFile_67.vhdl RegisterFile_68_Pack.vhdl RegisterFile_68.vhdl RegisterFile_69_Pack.vhdl RegisterFile_69.vhdl RegisterFile_6_Pack.vhdl RegisterFile_6.vhdl
+
+# RegisterFile_70
+target_dep	all	RegisterFile_70.ngc
+target_dep	RegisterFile_70.ngc	RegisterFile_70.prj
+target_dep	RegisterFile_70.prj	RegisterFile_70_Pack.vhdl RegisterFile_70.vhdl
+
+# RegisterFile_71
+target_dep	all	RegisterFile_71.ngc
+target_dep	RegisterFile_71.ngc	RegisterFile_71.prj
+target_dep	RegisterFile_71.prj	RegisterFile_71_Pack.vhdl RegisterFile_71.vhdl
+
+# RegisterFile_72
+target_dep	all	RegisterFile_72.ngc
+target_dep	RegisterFile_72.ngc	RegisterFile_72.prj
+target_dep	RegisterFile_72.prj	RegisterFile_72_Pack.vhdl RegisterFile_72.vhdl
+
+# RegisterFile_73
+target_dep	all	RegisterFile_73.ngc
+target_dep	RegisterFile_73.ngc	RegisterFile_73.prj
+target_dep	RegisterFile_73.prj	RegisterFile_73_Pack.vhdl RegisterFile_73.vhdl
+
+# RegisterFile_74
+target_dep	all	RegisterFile_74.ngc
+target_dep	RegisterFile_74.ngc	RegisterFile_74.prj
+target_dep	RegisterFile_74.prj	RegisterFile_74_Pack.vhdl RegisterFile_74.vhdl
+
+# RegisterFile_75
+target_dep	all	RegisterFile_75.ngc
+target_dep	RegisterFile_75.ngc	RegisterFile_75.prj
+target_dep	RegisterFile_75.prj	RegisterFile_75_Pack.vhdl RegisterFile_75.vhdl
+
+# RegisterFile_76
+target_dep	all	RegisterFile_76.ngc
+target_dep	RegisterFile_76.ngc	RegisterFile_76.prj
+target_dep	RegisterFile_76.prj	RegisterFile_76_Pack.vhdl RegisterFile_76.vhdl
+
+# RegisterFile_77
+target_dep	all	RegisterFile_77.ngc
+target_dep	RegisterFile_77.ngc	RegisterFile_77.prj
+target_dep	RegisterFile_77.prj	RegisterFile_77_Pack.vhdl RegisterFile_77.vhdl
+
+# RegisterFile_78
+target_dep	all	RegisterFile_78.ngc
+target_dep	RegisterFile_78.ngc	RegisterFile_78.prj
+target_dep	RegisterFile_78.prj	RegisterFile_78_Pack.vhdl RegisterFile_78.vhdl
+
+# RegisterFile_79
+target_dep	all	RegisterFile_79.ngc
+target_dep	RegisterFile_79.ngc	RegisterFile_79.prj
+target_dep	RegisterFile_79.prj	RegisterFile_79_Pack.vhdl RegisterFile_79.vhdl
+
+# RegisterFile_7
+target_dep	all	RegisterFile_7.ngc
+target_dep	RegisterFile_7.ngc	RegisterFile_7.prj
+target_dep	RegisterFile_7.prj	RegisterFile_70_Pack.vhdl RegisterFile_70.vhdl RegisterFile_71_Pack.vhdl RegisterFile_71.vhdl RegisterFile_72_Pack.vhdl RegisterFile_72.vhdl RegisterFile_73_Pack.vhdl RegisterFile_73.vhdl RegisterFile_74_Pack.vhdl RegisterFile_74.vhdl RegisterFile_75_Pack.vhdl RegisterFile_75.vhdl RegisterFile_76_Pack.vhdl RegisterFile_76.vhdl RegisterFile_77_Pack.vhdl RegisterFile_77.vhdl RegisterFile_78_Pack.vhdl RegisterFile_78.vhdl RegisterFile_79_Pack.vhdl RegisterFile_79.vhdl RegisterFile_7_Pack.vhdl RegisterFile_7.vhdl
+
+# RegisterFile_80
+target_dep	all	RegisterFile_80.ngc
+target_dep	RegisterFile_80.ngc	RegisterFile_80.prj
+target_dep	RegisterFile_80.prj	RegisterFile_80_Pack.vhdl RegisterFile_80.vhdl
+
+# RegisterFile_81
+target_dep	all	RegisterFile_81.ngc
+target_dep	RegisterFile_81.ngc	RegisterFile_81.prj
+target_dep	RegisterFile_81.prj	RegisterFile_81_Pack.vhdl RegisterFile_81.vhdl
+
+# RegisterFile_82
+target_dep	all	RegisterFile_82.ngc
+target_dep	RegisterFile_82.ngc	RegisterFile_82.prj
+target_dep	RegisterFile_82.prj	RegisterFile_82_Pack.vhdl RegisterFile_82.vhdl
+
+# RegisterFile_83
+target_dep	all	RegisterFile_83.ngc
+target_dep	RegisterFile_83.ngc	RegisterFile_83.prj
+target_dep	RegisterFile_83.prj	RegisterFile_83_Pack.vhdl RegisterFile_83.vhdl
+
+# RegisterFile_84
+target_dep	all	RegisterFile_84.ngc
+target_dep	RegisterFile_84.ngc	RegisterFile_84.prj
+target_dep	RegisterFile_84.prj	RegisterFile_84_Pack.vhdl RegisterFile_84.vhdl
+
+# RegisterFile_85
+target_dep	all	RegisterFile_85.ngc
+target_dep	RegisterFile_85.ngc	RegisterFile_85.prj
+target_dep	RegisterFile_85.prj	RegisterFile_85_Pack.vhdl RegisterFile_85.vhdl
+
+# RegisterFile_86
+target_dep	all	RegisterFile_86.ngc
+target_dep	RegisterFile_86.ngc	RegisterFile_86.prj
+target_dep	RegisterFile_86.prj	RegisterFile_86_Pack.vhdl RegisterFile_86.vhdl
+
+# RegisterFile_87
+target_dep	all	RegisterFile_87.ngc
+target_dep	RegisterFile_87.ngc	RegisterFile_87.prj
+target_dep	RegisterFile_87.prj	RegisterFile_87_Pack.vhdl RegisterFile_87.vhdl
+
+# RegisterFile_88
+target_dep	all	RegisterFile_88.ngc
+target_dep	RegisterFile_88.ngc	RegisterFile_88.prj
+target_dep	RegisterFile_88.prj	RegisterFile_88_Pack.vhdl RegisterFile_88.vhdl
+
+# RegisterFile_89
+target_dep	all	RegisterFile_89.ngc
+target_dep	RegisterFile_89.ngc	RegisterFile_89.prj
+target_dep	RegisterFile_89.prj	RegisterFile_89_Pack.vhdl RegisterFile_89.vhdl
+
+# RegisterFile_8
+target_dep	all	RegisterFile_8.ngc
+target_dep	RegisterFile_8.ngc	RegisterFile_8.prj
+target_dep	RegisterFile_8.prj	RegisterFile_80_Pack.vhdl RegisterFile_80.vhdl RegisterFile_81_Pack.vhdl RegisterFile_81.vhdl RegisterFile_82_Pack.vhdl RegisterFile_82.vhdl RegisterFile_83_Pack.vhdl RegisterFile_83.vhdl RegisterFile_84_Pack.vhdl RegisterFile_84.vhdl RegisterFile_85_Pack.vhdl RegisterFile_85.vhdl RegisterFile_86_Pack.vhdl RegisterFile_86.vhdl RegisterFile_87_Pack.vhdl RegisterFile_87.vhdl RegisterFile_88_Pack.vhdl RegisterFile_88.vhdl RegisterFile_89_Pack.vhdl RegisterFile_89.vhdl RegisterFile_8_Pack.vhdl RegisterFile_8.vhdl
+
+# RegisterFile_90
+target_dep	all	RegisterFile_90.ngc
+target_dep	RegisterFile_90.ngc	RegisterFile_90.prj
+target_dep	RegisterFile_90.prj	RegisterFile_90_Pack.vhdl RegisterFile_90.vhdl
+
+# RegisterFile_91
+target_dep	all	RegisterFile_91.ngc
+target_dep	RegisterFile_91.ngc	RegisterFile_91.prj
+target_dep	RegisterFile_91.prj	RegisterFile_91_Pack.vhdl RegisterFile_91.vhdl
+
+# RegisterFile_92
+target_dep	all	RegisterFile_92.ngc
+target_dep	RegisterFile_92.ngc	RegisterFile_92.prj
+target_dep	RegisterFile_92.prj	RegisterFile_92_Pack.vhdl RegisterFile_92.vhdl
+
+# RegisterFile_93
+target_dep	all	RegisterFile_93.ngc
+target_dep	RegisterFile_93.ngc	RegisterFile_93.prj
+target_dep	RegisterFile_93.prj	RegisterFile_93_Pack.vhdl RegisterFile_93.vhdl
+
+# RegisterFile_94
+target_dep	all	RegisterFile_94.ngc
+target_dep	RegisterFile_94.ngc	RegisterFile_94.prj
+target_dep	RegisterFile_94.prj	RegisterFile_94_Pack.vhdl RegisterFile_94.vhdl
+
+# RegisterFile_95
+target_dep	all	RegisterFile_95.ngc
+target_dep	RegisterFile_95.ngc	RegisterFile_95.prj
+target_dep	RegisterFile_95.prj	RegisterFile_95_Pack.vhdl RegisterFile_95.vhdl
+
+# RegisterFile_96
+target_dep	all	RegisterFile_96.ngc
+target_dep	RegisterFile_96.ngc	RegisterFile_96.prj
+target_dep	RegisterFile_96.prj	RegisterFile_96_Pack.vhdl RegisterFile_96.vhdl
+
+# RegisterFile_97
+target_dep	all	RegisterFile_97.ngc
+target_dep	RegisterFile_97.ngc	RegisterFile_97.prj
+target_dep	RegisterFile_97.prj	RegisterFile_97_Pack.vhdl RegisterFile_97.vhdl
+
+# RegisterFile_98
+target_dep	all	RegisterFile_98.ngc
+target_dep	RegisterFile_98.ngc	RegisterFile_98.prj
+target_dep	RegisterFile_98.prj	RegisterFile_98_Pack.vhdl RegisterFile_98.vhdl
+
+# RegisterFile_99
+target_dep	all	RegisterFile_99.ngc
+target_dep	RegisterFile_99.ngc	RegisterFile_99.prj
+target_dep	RegisterFile_99.prj	RegisterFile_99_Pack.vhdl RegisterFile_99.vhdl
+
+# RegisterFile_9
+target_dep	all	RegisterFile_9.ngc
+target_dep	RegisterFile_9.ngc	RegisterFile_9.prj
+target_dep	RegisterFile_9.prj	RegisterFile_90_Pack.vhdl RegisterFile_90.vhdl RegisterFile_91_Pack.vhdl RegisterFile_91.vhdl RegisterFile_92_Pack.vhdl RegisterFile_92.vhdl RegisterFile_93_Pack.vhdl RegisterFile_93.vhdl RegisterFile_94_Pack.vhdl RegisterFile_94.vhdl RegisterFile_95_Pack.vhdl RegisterFile_95.vhdl RegisterFile_96_Pack.vhdl RegisterFile_96.vhdl RegisterFile_97_Pack.vhdl RegisterFile_97.vhdl RegisterFile_98_Pack.vhdl RegisterFile_98.vhdl RegisterFile_99_Pack.vhdl RegisterFile_99.vhdl RegisterFile_9_Pack.vhdl RegisterFile_9.vhdl
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,46 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/SelfTest/include/test.h"
+
+#define NB_PARAMS 4
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - nb_port_read  (unsigned int)" << endl
+       << " - nb_port_write (unsigned int)" << endl
+       << " - nb_word       (unsigned int)" << endl
+       << " - size_word     (unsigned int)" << endl;
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc != 2+NB_PARAMS)
+    usage (argv[0]);
+
+  const string   name          = argv[1];
+  const uint32_t nb_port_read  = atoi(argv[2]);
+  const uint32_t nb_port_write = atoi(argv[3]);
+  const uint32_t nb_word       = atoi(argv[4]);
+  const uint32_t size_word     = atoi(argv[5]);
+  
+  morpheo::behavioural::generic::registerfile::Parameters param (nb_port_read ,
+								 nb_port_write,
+								 nb_word      ,
+								 size_word    );
+
+  test (name,param);
+
+  return (EXIT_SUCCESS);
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/test.cpp	(revision 3)
@@ -0,0 +1,191 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#include "Behavioural/Generic/RegisterFile/SelfTest/include/test.h"
+#include "Include/Test.h"
+
+void test (string name,
+	   morpheo::behavioural::generic::registerfile::Parameters param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  try 
+    {
+      cout << param.print(1);
+      param.test();
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      return;
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+
+  RegisterFile * registerfile = new RegisterFile (name.c_str(),
+#ifdef STATISTICS
+						  morpheo::behavioural::Parameters_Statistics(5,50),
+#endif
+						  param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                                 CLOCK ("clock", 1.0, 0.5);
+  
+  sc_signal<Tcontrol_t>                    READ_ENABLE   [param._nb_port_read];
+  sc_signal<Taddress_t>                    READ_ADDRESS  [param._nb_port_read];
+  sc_signal<Tdata_t>                       READ_DATA     [param._nb_port_read];
+
+  sc_signal<Tcontrol_t>                    WRITE_ENABLE  [param._nb_port_write];
+  sc_signal<Taddress_t>                    WRITE_ADDRESS [param._nb_port_write];
+  sc_signal<Tdata_t>                       WRITE_DATA    [param._nb_port_write];
+
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of registerFile" << endl;
+  
+  (*(registerfile->in_CLOCK))        (CLOCK);
+
+  for (uint32_t i=0; i<param._nb_port_read; i++)
+    {
+      (*(registerfile-> in_READ_ENABLE   [i]))        (READ_ENABLE   [i]);
+      (*(registerfile-> in_READ_ADDRESS  [i]))        (READ_ADDRESS  [i]);
+      (*(registerfile->out_READ_DATA     [i]))        (READ_DATA     [i]);
+    }
+
+  for (uint32_t i=0; i<param._nb_port_write; i++)
+    {
+      (*(registerfile-> in_WRITE_ENABLE  [i]))        (WRITE_ENABLE  [i]);
+      (*(registerfile-> in_WRITE_ADDRESS [i]))        (WRITE_ADDRESS [i]);
+      (*(registerfile-> in_WRITE_DATA    [i]))        (WRITE_DATA    [i]);
+    }
+  
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  // Initialisation
+
+  sc_start(0);
+  
+  for (uint32_t i=0; i<param._nb_port_write; i++)
+    WRITE_ENABLE [i] .write (0);
+
+  for (uint32_t i=0; i<param._nb_port_read; i++)
+    READ_ENABLE  [i] .write (0);
+
+  sc_start(5);
+
+  cout << "<" << name << "> Write the RegisterFile (no read)" << endl;
+
+  uint32_t grain = 0;
+  //uint32_t grain = static_cast<uint32_t>(time(NULL));
+  
+  srand(grain);
+  
+  Tdata_t    data, data_wait;
+  Taddress_t address = 0;
+
+  while (address < param._nb_word)
+    {
+      uint32_t num_port = 0;
+      
+      cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
+
+      while (num_port<param._nb_port_write)
+	{
+	  data = rand()%(1<<(param._size_word-1));
+
+	  cout << "(" << num_port << ") [" << address << "] <= " << data << endl;
+	  WRITE_ENABLE  [num_port] .write(1);
+	  WRITE_DATA    [num_port] .write(data);
+	  WRITE_ADDRESS [num_port] .write(address);
+
+	  address  ++;
+	  num_port ++;
+	  // Address can be not a multiple of nb_port_write
+	  if (address >= param._nb_word)
+	    break;
+	}
+
+      while (num_port<param._nb_port_write)
+	{
+	  WRITE_ENABLE  [num_port] .write(0);
+	  num_port ++;
+	}
+
+      sc_start(1);
+    }
+  cout << "<" << name << "> Read the RegisterFile (no write)" << endl;
+
+  srand(grain);
+
+  for (uint32_t i=0; i<param._nb_port_write; i++)
+    WRITE_ENABLE [i] .write (0);
+
+  sc_start(1);
+
+  address  = 0;
+  while (address < param._nb_word)
+    {
+      uint32_t num_port = 0;
+
+      cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
+      
+      while (num_port<param._nb_port_read)
+	{
+	  READ_ENABLE  [num_port] .write(1);
+	  READ_ADDRESS [num_port] .write(address);
+
+	  sc_start(0); // evaluation
+
+	  data_wait = rand()%(1<<(param._size_word-1));
+	  data      = READ_DATA    [num_port] .read();
+
+	  cout << "(" << num_port << ") [" << address << "] => " << data << endl;
+
+	  TEST(Tdata_t,data,data_wait);
+
+	  address  ++;
+	  num_port ++;
+	  if (address >= param._nb_word)
+	    break;
+	}
+
+      while (num_port<param._nb_port_read)
+	{
+	  READ_ENABLE  [num_port] .write(0);
+	  num_port ++;
+	}
+
+      sc_start(1);
+    }
+
+  for (uint32_t i=0; i<param._nb_port_read; i++)
+    READ_ENABLE  [i] .write (0);
+
+  sc_start(1);
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete registerfile;
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Parameters.h	(revision 3)
@@ -0,0 +1,46 @@
+#ifndef morpheo_behavioural_generic_registerfile_Parameters_h
+#define morpheo_behavioural_generic_registerfile_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+  public : const uint32_t _nb_port_read ;
+  public : const uint32_t _nb_port_write;
+  public : const uint32_t _nb_word      ;
+  public : const uint32_t _size_word    ;
+
+  public : Parameters (uint32_t nb_port_read ,
+		       uint32_t nb_port_write,
+		       uint32_t nb_word      ,
+		       uint32_t size_word    );
+  public : Parameters (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::generic::registerfile::Parameters & x);
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/RegisterFile.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/RegisterFile.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/RegisterFile.h	(revision 3)
@@ -0,0 +1,134 @@
+#ifndef morpheo_behavioural_generic_registerfile_RegisterFile
+#define morpheo_behavioural_generic_registerfile_RegisterFile
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include "Include/Debug.h"
+#include "Include/ToString.h"
+#include <iostream>
+using namespace std;
+
+#include "Behavioural/Generic/RegisterFile/include/Parameters.h"
+#include "Behavioural/Generic/RegisterFile/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/Generic/RegisterFile/include/Statistics.h"
+#endif
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#ifdef VHDL_TESTBENCH
+#include "Behavioural/include/Vhdl_Testbench.h"
+#endif
+
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  class RegisterFile 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string     _name;
+
+  protected : const Parameters _param;
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+    
+  private   : uint32_t                         _stat_nb_read;
+  private   : uint32_t                         _stat_nb_write;
+#endif
+
+#ifdef VHDL_TESTBENCH
+  private   : Vhdl_Testbench                 * _vhdl_testbench;
+#endif
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK        ;
+
+    // ----- Interface Read
+  public    : SC_IN       (Tcontrol_t)     **  in_READ_ENABLE  ;
+  public    : SC_IN       (Taddress_t)     **  in_READ_ADDRESS ;
+  public    : SC_OUT      (Tdata_t)        ** out_READ_DATA    ;
+
+    // ----- Interface Write
+  public    : SC_IN       (Tcontrol_t)     **  in_WRITE_ENABLE ;
+  public    : SC_IN       (Taddress_t)     **  in_WRITE_ADDRESS;
+  public    : SC_IN       (Tdata_t)        **  in_WRITE_DATA   ;
+
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+  private   : SC_REGISTER (Tdata_t)        ** reg_DATA         ;
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#endif
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (RegisterFile);
+#endif					       
+
+  public  :          RegisterFile              (
+#ifdef SYSTEMC
+						sc_module_name                              name,
+#else					       
+						string                                      name,
+#endif					       
+#ifdef STATISTICS
+						morpheo::behavioural::Parameters_Statistics param_statistics,
+#endif
+					        Parameters                                  param );
+					       
+  public  :          RegisterFile              (Parameters param );
+  public  :          ~RegisterFile             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+  public  : void     transition                (void);
+//public  : void     genMoore                  (void) {/* empty */};
+  public  : void     genMealy_read             (void);
+#endif					       
+
+#ifdef STATISTICS
+  public  : string  statistics                 (uint32_t depth);
+#endif					       
+#if VHDL				       
+  private : void     vhdl                      (void);
+  private : void     vhdl_port                 (Vhdl & vhdl);
+  private : void     vhdl_type                 (Vhdl & vhdl);
+  private : void     vhdl_signal               (Vhdl & vhdl);
+  private : void     vhdl_body                 (Vhdl & vhdl);
+#endif					       
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench            (Vhdl_Testbench & vhdl_testbench);
+  private : void     vhdl_testbench_port       (Vhdl_Testbench & vhdl_testbench);
+  private : void     vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench);
+#endif
+
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Statistics.h	(revision 3)
@@ -0,0 +1,56 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_generic_registerfile_Statistics_h
+#define morpheo_behavioural_generic_registerfile_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/Generic/RegisterFile/include/Parameters.h"
+
+using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                   _parameters;
+  private  : morpheo::behavioural::generic::group::Statistics * _stat_port_read;
+  private  : morpheo::behavioural::generic::group::Statistics * _stat_port_write;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics (string                                      name                       ,
+			 morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			 Parameters                                  parameters
+			 );
+//public   : Statistics (Statistics & stat);
+  public   : ~Statistics () ;
+    
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : void     add        (uint32_t nb_read,
+				  uint32_t nb_write);
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Types.h	(revision 3)
@@ -0,0 +1,28 @@
+#ifdef SYSTEMC
+#ifndef morpheo_behavioural_generic_registerfile_Type_h
+#define morpheo_behavioural_generic_registerfile_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Types.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  typedef uint32_t Taddress_t;
+  typedef uint32_t Tdata_t;
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,43 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/Parameters.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  Parameters::Parameters (uint32_t nb_port_read ,
+			  uint32_t nb_port_write,
+			  uint32_t nb_word      ,
+			  uint32_t size_word     
+			  ) :
+    _nb_port_read      (nb_port_read ),
+    _nb_port_write     (nb_port_write),
+    _nb_word           (nb_word      ),
+    _size_word         (size_word    )
+  { 
+    test();
+  };
+  
+  Parameters::Parameters (Parameters & param) :
+    _nb_port_read      (param._nb_port_read ),
+    _nb_port_write     (param._nb_port_write),
+    _nb_word           (param._nb_word      ),
+    _size_word         (param._size_word    )
+  {
+    test();
+  };
+
+  Parameters::~Parameters () 
+  { };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters_msg_error.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters_msg_error.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters_msg_error.cpp	(revision 3)
@@ -0,0 +1,50 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include "Behavioural/Generic/RegisterFile/include/Parameters.h"
+#include "Behavioural/Generic/RegisterFile/include/Types.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  string Parameters::msg_error(void)
+  {
+    string msg = "";
+
+    if ((8*sizeof(Tdata_t)) < _size_word)
+      {
+        msg += "  - type \"Tdata_t\" is too little to the size defined by size_word\n";
+        msg +=  "    * size_word                       : " + toString(_size_word) + "\n";
+	msg +=  "    * Tdata_t                   (bits): " + toString(8*(sizeof(Tdata_t))) + "\n";
+      }
+
+    if ((8*sizeof(Taddress_t)) < log2(_nb_word))
+      {
+        msg += "  - type \"Taddress_t\" is too little to the size defined by nb_word\n";
+        msg +=  "    * nb_word                         : " + toString(_nb_word)    + "\n";
+	msg +=  "      > size                   (bits) : " + toString(log2(_nb_word)) + "\n";
+	msg +=  "    * Taddress_t               (bits) : " + toString(8*(sizeof(Taddress_t))) + "\n";
+      }
+
+    if (_nb_word < 2)
+      {
+        msg += "  - nb_word must be >= 2\n";
+        msg +=  "    * nb_word                         : " + toString(_nb_word)    + "\n";
+      }
+
+    return msg;
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters_print.cpp	(revision 3)
@@ -0,0 +1,43 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include "Behavioural/Generic/RegisterFile/include/Parameters.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  string Parameters::print (uint32_t depth)
+  {
+    string tab = string(depth,'\t');
+    ostringstream msg;
+    msg << tab << "<registerfile>" << endl
+	<< tab << "\t<nb_port_read  value=\"" << _nb_port_read  << "\" />" << endl
+	<< tab << "\t<nb_port_write value=\"" << _nb_port_write << "\" />" << endl
+	<< tab << "\t<nb_word       value=\"" << _nb_word       << "\" />" << endl
+	<< tab << "\t<size_word     value=\"" << _size_word     << "\" />" << endl
+	<< tab << "</registerfile>" << endl;
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::generic::registerfile::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile.cpp	(revision 3)
@@ -0,0 +1,90 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+#ifdef SYSTEMC
+  RegisterFile::RegisterFile (sc_module_name name,
+#else
+  RegisterFile::RegisterFile (string name        ,
+#endif
+#ifdef STATISTICS
+			      morpheo::behavioural::Parameters_Statistics             param_statistics,
+#endif
+			      morpheo::behavioural::generic::registerfile::Parameters param ):
+			      _name   (name)
+			      ,_param (param)
+  {
+#ifdef STATISTICS
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL_TESTBENCH
+    _vhdl_testbench = new Vhdl_Testbench (_name);
+    vhdl_testbench_port           (*_vhdl_testbench);
+    _vhdl_testbench->set_clock    ("in_CLOCK",true);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    allocation ();
+
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+    
+    SC_METHOD (genMealy_read);
+    dont_initialize ();
+    sensitive_neg << *(in_CLOCK);
+    for (uint32_t i=0; i<_param._nb_port_read; i++)
+      sensitive << *(in_READ_ENABLE  [i])
+		<< *(in_READ_ADDRESS [i]);
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+    for (uint32_t i=0; i<_param._nb_port_read; i++)
+      {
+	(*(out_READ_DATA [i])) (*( in_READ_ENABLE  [i]));
+	(*(out_READ_DATA [i])) (*( in_READ_ADDRESS [i]));
+      }
+#endif    
+#endif
+  };
+  
+  RegisterFile::~RegisterFile (void)
+  {
+#ifdef SYSTEMC
+    deallocation ();
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // generate the test bench
+    _vhdl_testbench->generate_file();
+    delete _vhdl_testbench;
+#endif
+
+#ifdef STATISTICS
+    _stat->generate_file(statistics(0));
+    delete _stat;
+#endif
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_allocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_allocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_allocation.cpp	(revision 3)
@@ -0,0 +1,72 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::allocation (void)
+  {
+    in_CLOCK = new SC_CLOCK ("in_CLOCK");
+
+    // ----- Interface Read
+     in_READ_ENABLE      = new SC_IN (Tcontrol_t) * [_param._nb_port_read];
+     in_READ_ADDRESS     = new SC_IN (Taddress_t) * [_param._nb_port_read];
+    out_READ_DATA        = new SC_OUT(Tdata_t   ) * [_param._nb_port_read];
+
+    for (uint32_t i=0; i<_param._nb_port_read; i++)
+      {
+	string rename;
+
+	rename = "in_READ_ENABLE["  + toString(i) + "]";
+	in_READ_ENABLE  [i]  = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	rename = "in_READ_ADDRESS[" + toString(i) + "]";
+	in_READ_ADDRESS [i]  = new SC_IN (Taddress_t) (rename.c_str());
+
+	rename = "out_READ_DATA["    + toString(i) + "]";
+	out_READ_DATA   [i]  = new SC_OUT(Tdata_t)    (rename.c_str());
+      }
+
+    // ----- Interface Write
+     in_WRITE_ENABLE     = new SC_IN (Tcontrol_t) * [_param._nb_port_write];
+     in_WRITE_ADDRESS    = new SC_IN (Taddress_t) * [_param._nb_port_write];
+     in_WRITE_DATA       = new SC_IN (Tdata_t   ) * [_param._nb_port_write];
+    
+    for (uint32_t i=0; i<_param._nb_port_write; i++)
+      {
+	string rename;
+
+	rename = "in_WRITE_ENABLE["  + toString(i) + "]";
+	in_WRITE_ENABLE  [i]  = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	rename = "in_WRITE_ADDRESS[" + toString(i) + "]";
+	in_WRITE_ADDRESS [i]  = new SC_IN (Taddress_t) (rename.c_str());
+
+	rename = "in_WRITE_DATA["    + toString(i) + "]";
+	in_WRITE_DATA    [i]  = new SC_IN (Tdata_t)    (rename.c_str());
+      }
+
+    // ----- Register
+    reg_DATA = new SC_REGISTER (Tdata_t) * [_param._nb_word];
+    
+    for (uint32_t i=0; i<_param._nb_word; i++)
+      {
+	string rename = "reg_DATA["  + toString(i) + "]";
+	reg_DATA [i]  = new SC_REGISTER (Tdata_t) (rename.c_str());
+      }    
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_deallocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_deallocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_deallocation.cpp	(revision 3)
@@ -0,0 +1,57 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::deallocation (void)
+  {
+    delete in_CLOCK;
+
+    // ----- Interface Read
+    for (uint32_t i=0; i<_param._nb_port_read; i++)
+      {
+	delete in_READ_ENABLE  [i];
+	delete in_READ_ADDRESS [i];
+	delete out_READ_DATA   [i];
+      }
+
+    delete  in_READ_ENABLE ;
+    delete  in_READ_ADDRESS;
+    delete out_READ_DATA   ;
+
+    // ----- Interface Write
+    for (uint32_t i=0; i<_param._nb_port_write; i++)
+      {
+	delete in_WRITE_ENABLE  [i];
+	delete in_WRITE_ADDRESS [i];
+	delete in_WRITE_DATA    [i];
+      }
+
+    delete in_WRITE_ENABLE ;
+    delete in_WRITE_ADDRESS;
+    delete in_WRITE_DATA   ;
+
+    // ----- Register
+    for (uint32_t i=0; i<_param._nb_word; i++)
+      {
+	delete reg_DATA [i];
+      }    
+
+    delete reg_DATA;
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_genMealy_read.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_genMealy_read.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_genMealy_read.cpp	(revision 3)
@@ -0,0 +1,54 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::genMealy_read (void)
+  {
+    log_printf(FUNC,Register_File,"genMealy_read","Begin");
+
+#ifdef STATISTICS
+    _stat_nb_read = 0;
+#endif    
+
+    for (uint32_t i=0; i<_param._nb_port_read; i++)
+      {
+	// Have a write?
+ 	if ( PORT_READ(in_READ_ENABLE[i]) == 1)
+ 	  {
+	    Taddress_t address = PORT_READ(in_READ_ADDRESS[i]);
+	    Tdata_t    data    = REGISTER_READ(reg_DATA[address]);
+
+	    log_printf(TRACE,Register_File,"genMealy_read","[%d] -> %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
+
+#ifdef STATISTICS
+	    _stat_nb_read ++;
+#endif    
+	    // Write in registerFile
+	    PORT_WRITE(out_READ_DATA[i],data);
+ 	  }
+	else
+	  {
+	    //log_printf(TRACE,Register_File,"genMealy_read","Read  [%d] : No   transaction",i);
+	    PORT_WRITE(out_READ_DATA[i],0);
+	  }
+      }
+    log_printf(FUNC,Register_File,"genMealy_read","End");
+	
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_statistics.cpp	(revision 3)
@@ -0,0 +1,25 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  string RegisterFile::statistics (uint32_t depth)
+  {
+    return _stat->print(depth);
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_transition.cpp	(revision 3)
@@ -0,0 +1,56 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::transition (void)
+  {
+    log_printf(FUNC,Register_File,"transition","Begin");
+#ifdef STATISTICS
+    _stat_nb_write = 0;
+#endif    
+
+    for (uint32_t i=0; i<_param._nb_port_write; i++)
+      {
+	// Have a write?
+ 	if ( PORT_READ(in_WRITE_ENABLE[i]) == true)
+ 	  {
+#ifdef STATISTICS
+	    _stat_nb_write ++;
+#endif    
+
+	    Taddress_t address = PORT_READ(in_WRITE_ADDRESS[i]);
+	    Tdata_t    data    = PORT_READ(in_WRITE_DATA   [i]);
+	    
+	    log_printf(TRACE,Register_File,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
+
+	    // Write in registerFile
+	    REGISTER_WRITE(reg_DATA[address],data);
+ 	  }
+      }
+
+#ifdef STATISTICS
+    _stat->add(_stat_nb_read,_stat_nb_write);
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition (*_vhdl_testbench);
+#endif
+    log_printf(FUNC,Register_File,"transition","End");
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+#include "Behavioural/include/Vhdl.h"
+#include "Include/ToString.h"
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::vhdl (void)
+  {
+    Vhdl vhdl (_name);
+
+    vhdl.set_library_work (_name + "_Pack");
+
+    vhdl_port   (vhdl);
+    vhdl_type   (vhdl);
+    vhdl_signal (vhdl);
+    vhdl_body   (vhdl);
+
+    vhdl.generate_file();
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_body.cpp	(revision 3)
@@ -0,0 +1,52 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::vhdl_body (Vhdl & vhdl)
+  {
+    vhdl.set_body ("");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("-- Read RegisterFile");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("");
+    
+    for (uint32_t i = 0; i < _param._nb_port_read; i++)
+      vhdl.set_body ("out_READ_DATA_"+toString(i)+" <= reg_DATA (conv_integer(in_READ_ADDRESS_"+toString(i)+")) when in_READ_ENABLE_"+toString(i)+" = '1' else "+std_logic_others(_param._size_word,0)+";");
+
+    vhdl.set_body ("");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("-- Write RegisterFile");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("");
+
+    vhdl.set_body ("RegisterFile_write: process (in_CLOCK)");
+    vhdl.set_body ("begin  -- process RegisterFile_write");
+    vhdl.set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then");
+    
+    for (uint32_t i = 0; i < _param._nb_port_write; i++)
+      {
+      vhdl.set_body ("\t\tif (in_WRITE_ENABLE_"+toString(i)+" = '1') then");
+      vhdl.set_body ("\t\t\treg_DATA(conv_integer(in_WRITE_ADDRESS_"+toString(i)+")) <= in_WRITE_DATA_"+toString(i)+";");
+      vhdl.set_body ("\t\tend if;");
+      }
+
+    vhdl.set_body ("\tend if;");
+    vhdl.set_body ("end process RegisterFile_write;");
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_port.cpp	(revision 3)
@@ -0,0 +1,39 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::vhdl_port (Vhdl & vhdl)
+  {
+    vhdl.set_port ("in_CLOCK", IN, "std_logic");
+
+    for (uint32_t i = 0; i < _param._nb_port_read; i ++)
+      {
+	vhdl.set_port (" in_READ_ENABLE_"+toString(i)+" ",IN ,std_logic(1)                    );
+	vhdl.set_port (" in_READ_ADDRESS_"+toString(i)+"",IN ,std_logic(static_cast<uint32_t>(log2(_param._nb_word))));
+	vhdl.set_port ("out_READ_DATA_"+toString(i)+"   ",OUT,std_logic(_param._size_word    ));
+      }
+
+    for (uint32_t i = 0; i < _param._nb_port_write; i ++)
+      {
+	vhdl.set_port (" in_WRITE_ENABLE_"+toString(i)+" ",IN ,std_logic(1)                    );
+	vhdl.set_port (" in_WRITE_ADDRESS_"+toString(i)+"",IN ,std_logic(static_cast<uint32_t>(log2(_param._nb_word))));
+	vhdl.set_port (" in_WRITE_DATA_"+toString(i)+"   ",IN ,std_logic(_param._size_word    ));
+      }
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_signal.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_signal.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_signal.cpp	(revision 3)
@@ -0,0 +1,25 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::vhdl_signal (Vhdl & vhdl)
+  {
+    vhdl.set_signal ("reg_DATA", "Tregfile");
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_testbench_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_testbench_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_testbench_port.cpp	(revision 3)
@@ -0,0 +1,37 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::vhdl_testbench_port (Vhdl_Testbench & vhdl_testbench)
+  {
+    for (uint32_t i = 0; i < _param._nb_port_read; i ++)
+      {
+	vhdl_testbench.set_port (" in_READ_ENABLE_"+toString(i)+" ",IN ,1);
+	vhdl_testbench.set_port (" in_READ_ADDRESS_"+toString(i)+"",IN ,static_cast<uint32_t>(log2(_param._nb_word)));
+	vhdl_testbench.set_port ("out_READ_DATA_"+toString(i)+"   ",OUT,_param._size_word);
+      }
+
+    for (uint32_t i = 0; i < _param._nb_port_write; i ++)
+      {
+	vhdl_testbench.set_port (" in_WRITE_ENABLE_"+toString(i)+" ",IN ,1);
+	vhdl_testbench.set_port (" in_WRITE_ADDRESS_"+toString(i)+"",IN ,static_cast<uint32_t>(log2(_param._nb_word)));
+	vhdl_testbench.set_port (" in_WRITE_DATA_"+toString(i)+"   ",IN ,_param._size_word    );
+      }
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_testbench_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_testbench_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_testbench_transition.cpp	(revision 3)
@@ -0,0 +1,47 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench)
+  {
+#ifndef SYSTEMCASS_SPECIFIC
+    sc_cycle(0);
+#endif
+
+    for (uint32_t i = 0; i < _param._nb_port_read ; i ++)
+      {
+	vhdl_testbench.add_input (PORT_READ( in_READ_ENABLE  [i]));
+	vhdl_testbench.add_input (PORT_READ( in_READ_ADDRESS [i]));
+      }
+    for (uint32_t i = 0; i < _param._nb_port_write; i ++)
+      {
+	vhdl_testbench.add_input (PORT_READ( in_WRITE_ENABLE [i]));
+	vhdl_testbench.add_input (PORT_READ( in_WRITE_ADDRESS[i]));
+	vhdl_testbench.add_input (PORT_READ( in_WRITE_DATA   [i]));
+      }
+    for (uint32_t i = 0; i < _param._nb_port_read ; i ++)
+      {
+	vhdl_testbench.add_output(PORT_READ(out_READ_DATA    [i]));
+      }
+
+    vhdl_testbench.add_test(true);
+
+    vhdl_testbench.new_cycle (); // always at the end
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_type.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_type.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/RegisterFile_vhdl_type.cpp	(revision 3)
@@ -0,0 +1,25 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void RegisterFile::vhdl_type (Vhdl & vhdl)
+  {
+    vhdl.set_type ("Tregfile", "array (" + toString(_param._nb_word-1) + " downto 0) of " + std_logic(_param._size_word));
+  };
+
+}; // end namespace registerfile 
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,49 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+    _stat_port_read  = new morpheo::behavioural::generic::group::Statistics (name + "_port_read"   ,
+									     parameters_statistics ,
+									     morpheo::behavioural::generic::group::Parameters(_parameters._nb_port_read));
+    _stat_port_write = new morpheo::behavioural::generic::group::Statistics (name + "_port_write"   ,
+									     parameters_statistics ,
+									     morpheo::behavioural::generic::group::Parameters(_parameters._nb_port_write));
+  };
+  
+  //   Statistics::Statistics (Statistics & stat) :
+  // 		       _nb_port_read      (param._nb_port_read ),
+  // 		       _nb_port_write     (param._nb_port_write),
+  // 		       _nb_word           (param._nb_word      ),
+  // 		       _size_word         (param._size_word    )
+  //     { };
+  
+  Statistics::~Statistics () 
+  { 
+    delete _stat_port_read ;
+    delete _stat_port_write;
+  };
+
+}; // end namespace registerfile
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,30 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  void Statistics::add (uint32_t nb_read,
+			uint32_t nb_write)
+  {
+    _stat_port_read ->add(nb_read );
+    _stat_port_write->add(nb_write);
+  };
+
+}; // end namespace registerfile
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,43 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  string Statistics::print (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<registerfile name=\"" << _name << "\" >" << endl
+	<< print_body(depth+1)
+	<< tab << "</registerfile>" << endl;
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::generic::registerfile::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace registerfile
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,33 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/RegisterFile/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural                {
+namespace generic                    {
+namespace registerfile               {
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << _stat_port_read ->print(depth+1);
+    msg << _stat_port_write->print(depth+1);
+    
+    return msg.str();
+  };
+}; // end namespace registerfile
+}; // end namespace generic
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/Makefile	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../..
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libPseudo_LRU.a
+
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/Makefile.deps	(revision 3)
@@ -0,0 +1,37 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+ifndef Group
+include 			$(DIR_MORPHEO)/Behavioural/Generic/Group/Makefile.deps
+endif
+
+Pseudo_LRU			= yes
+#-----[ Library ]------------------------------------------
+Pseudo_LRU_LIBRARY		= 	-lPseudo_LRU		\
+					$(Group_LIBRARY)	\
+					$(Behavioural_LIBRARY)	
+
+Pseudo_LRU_DIR_LIBRARY		=	-L$(DIR_MORPHEO)/Behavioural/Generic/Select/Pseudo_LRU/lib	\
+					$(Group_DIR_LIBRARY)						\
+					$(Behavioural_DIR_LIBRARY)	
+
+#-----[ Rules ]--------------------------------------------
+
+Pseudo_LRU_library		:
+				@$(MAKE)  Behavioural_library
+				@$(MAKE)  Group_library
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Select/Pseudo_LRU --makefile=Makefile 
+				
+Pseudo_LRU_library_clean	:
+				@$(MAKE)  Behavioural_library_clean
+				@$(MAKE)  Group_library_clean
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Select/Pseudo_LRU --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,29 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../../..
+
+LIBRARY				= $(Pseudo_LRU_LIBRARY)
+
+DIR_LIBRARY			= $(Pseudo_LRU_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				: library
+				@$(MAKE) all_selftest
+
+library				: Pseudo_LRU_library
+
+library_clean			: Pseudo_LRU_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/configuration.cfg	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/configuration.cfg	(revision 3)
@@ -0,0 +1,5 @@
+Pseudo_LRU
+4	4 	*2	# nb_entity 
+1	1	+2	# nb_access 
+1	1	+2	# nb_update 
+1	1 	*2	# size_table
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/configuration.cfg.save
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/configuration.cfg.save	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/configuration.cfg.save	(revision 3)
@@ -0,0 +1,5 @@
+Pseudo_LRU
+4	16	*2	# nb_entity 
+1	4	+2	# nb_access 
+1	4	+2	# nb_update 
+1	16	*2	# size_table
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/include/test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/include/test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/include/test.h	(revision 3)
@@ -0,0 +1,27 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::generic;
+using namespace morpheo::behavioural::generic::select;
+
+using namespace morpheo::behavioural::generic::select::pseudo_lru;
+
+void test   (string name,
+	     morpheo::behavioural::generic::select::pseudo_lru::Parameters param);
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,46 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/SelfTest/include/test.h"
+
+#define NB_PARAMS 4
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - nb_entity  (unsigned int)" << endl
+       << " - nb_access  (unsigned int)" << endl
+       << " - nb_update  (unsigned int)" << endl
+       << " - size_table (unsigned int)" << endl;
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc != 2+NB_PARAMS)
+    usage (argv[0]);
+
+  const string   name       = argv[1];
+  const uint32_t nb_entity  = atoi(argv[2]);
+  const uint32_t nb_access  = atoi(argv[3]);
+  const uint32_t nb_update  = atoi(argv[4]);
+  const uint32_t size_table = atoi(argv[5]);
+  
+  morpheo::behavioural::generic::select::pseudo_lru::Parameters param (nb_entity ,
+								       nb_access ,
+								       nb_update ,
+								       size_table);
+
+  test (name,param);
+
+  return (EXIT_SUCCESS);
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/src/test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/SelfTest/src/test.cpp	(revision 3)
@@ -0,0 +1,207 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/SelfTest/include/test.h"
+#include "Include/Test.h"
+
+void test (string name,
+	   morpheo::behavioural::generic::select::pseudo_lru::Parameters param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  if (param._nb_update < 1)
+    {
+      cerr << "<" << name << "> : To test, need a less one update's port" << endl;
+      exit (EXIT_FAILURE);
+    }
+  
+  try 
+    {
+      cout << param.print(1);
+      param.test();
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      return;
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+  Pseudo_LRU * _Pseudo_LRU = new Pseudo_LRU (name.c_str(),
+#ifdef STATISTICS
+					     morpheo::behavioural::Parameters_Statistics(5,50),
+#endif
+					     param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                                 CLOCK ("clock", 1.0, 0.5);
+
+  sc_signal<Tcontrol_t>                    ACCESS_VAL     [param._nb_access];
+  sc_signal<Tcontrol_t>                    ACCESS_ACK     [param._nb_access];
+  sc_signal<Taddress_t>                    ACCESS_ADDRESS [param._nb_access];
+  sc_signal<Tentity_t >                    ACCESS_ENTITY  [param._nb_access];
+  
+  sc_signal<Tcontrol_t>                    UPDATE_VAL     [param._nb_update];
+  sc_signal<Tcontrol_t>                    UPDATE_ACK     [param._nb_update];
+  sc_signal<Taddress_t>                    UPDATE_ADDRESS [param._nb_update];
+  sc_signal<Tentity_t >                    UPDATE_ENTITY  [param._nb_update];
+  
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Pseudo_LRU" << endl;
+  
+  (*(_Pseudo_LRU->in_CLOCK))        (CLOCK);
+
+    for (uint32_t i=0; i<param._nb_access; i++)
+      {
+	(*(_Pseudo_LRU-> in_ACCESS_VAL     [i])) (ACCESS_VAL     [i]);
+	(*(_Pseudo_LRU->out_ACCESS_ACK     [i])) (ACCESS_ACK     [i]);
+	if (param._size_table>1)
+	(*(_Pseudo_LRU-> in_ACCESS_ADDRESS [i])) (ACCESS_ADDRESS [i]);
+	(*(_Pseudo_LRU->out_ACCESS_ENTITY  [i])) (ACCESS_ENTITY  [i]);
+      }
+
+    for (uint32_t i=0; i<param._nb_update; i++)
+      {
+	(*(_Pseudo_LRU-> in_UPDATE_VAL     [i])) (UPDATE_VAL     [i]);
+	(*(_Pseudo_LRU->out_UPDATE_ACK     [i])) (UPDATE_ACK     [i]);
+	if (param._size_table>1)
+	(*(_Pseudo_LRU-> in_UPDATE_ADDRESS [i])) (UPDATE_ADDRESS [i]);
+	(*(_Pseudo_LRU-> in_UPDATE_ENTITY  [i])) (UPDATE_ENTITY  [i]);
+      }
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  // Initialisation
+
+  sc_start(0);
+
+  bool array [param._nb_access][param._nb_entity];
+
+  for (uint32_t i=0; i<param._nb_access; i++)
+    {
+      ACCESS_VAL[i].write(0);
+    }
+  for (uint32_t i=0; i<param._nb_update; i++)
+    {
+      UPDATE_VAL[i].write(0);
+    }
+
+  sc_start(5);
+  cout << "-----[ Test Update ]------------------------------" << endl;
+  for (uint32_t i=0; i<param._nb_update; i++)
+    {
+      UPDATE_VAL[i].write(1);
+    }
+  
+  for (uint32_t j=0; j<param._size_table; j+=param._nb_update)
+    for (uint32_t k=0; k<param._nb_entity; k++)
+      {
+	cout << "time : " << static_cast<uint32_t>(sc_simulation_time()) << endl;
+	for (uint32_t i=0; i<param._nb_update; i++)
+	  {
+	    
+	    Tcontrol_t val     = static_cast<Tcontrol_t>((j+i)<param._size_table);
+	    Taddress_t addr;
+	    if (param._size_table>1)
+	      addr = static_cast<Taddress_t>((j+i)%param._size_table);
+	    else
+	      addr = 0;
+	    Tentity_t  entity  = (k+1)%param._nb_entity;
+	    UPDATE_VAL     [i].write(val );
+	    if (param._size_table>1)
+	      UPDATE_ADDRESS [i].write(addr);
+	    UPDATE_ENTITY  [i].write(entity);
+	    
+	    sc_start(0);
+	    cout << "\t[" << i << "] " << val << " - " << UPDATE_ACK[i].read() << " addr : " << addr << " -> " << entity << endl;
+	  }
+	sc_start(1);
+      }
+		    
+
+  for (uint32_t i=0; i<param._nb_update; i++)
+    {
+      UPDATE_VAL[i].write(0);
+    }
+
+  sc_start(5);
+
+  cout << "-----[ Test Access ]------------------------------" << endl;
+  
+  
+  for (uint32_t j=0; j<param._size_table; j+=param._nb_access)
+    {
+      // init
+      memset(static_cast<void*>(array),0,param._nb_access*param._nb_entity*sizeof(bool));
+      
+      for (uint32_t k=0; k<param._nb_entity; k++)
+	{
+	  
+	  cout << "time : " << static_cast<uint32_t>(sc_simulation_time()) << endl;
+	  for (uint32_t i=0; i<param._nb_access; i++)
+	    {
+	      Tcontrol_t val     = static_cast<Tcontrol_t>((j+i)<param._size_table);
+	      Taddress_t addr    ;
+	      if (param._size_table>1)
+		addr = static_cast<Taddress_t>((j+i)%param._size_table);
+	      else
+		addr = 0;
+	      ACCESS_VAL     [i].write(val );
+	      if (param._size_table>1)
+		ACCESS_ADDRESS [i].write(addr);
+	      
+	      sc_start(0);
+	      
+	      Tentity_t  entity  = ACCESS_ENTITY [i].read();
+	      
+	      cout << "\t[" << i << "] " << val << " - " << ACCESS_ACK[i].read() << " addr : " << addr << " -> " << entity << endl;
+	      
+	      TEST(bool,false,((val == true) && (array[i][entity] == true)));
+
+// 	      if ((val == true) && (array[i][entity] == true))
+// 		{
+// 		  cout << "Test KO : Have already give this way" << endl;
+// 		  exit (1);
+// 		}
+// 	      else
+		array[i][entity] = true;
+	    }
+	  
+	  sc_start(1);
+	  
+	}
+    }
+
+  for (uint32_t i=0; i<param._nb_access; i++)
+    {
+      ACCESS_VAL[i].write(0);
+    }
+
+  sc_start(0);
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete _Pseudo_LRU;
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/TODO
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/TODO	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/TODO	(revision 3)
@@ -0,0 +1,2 @@
+* Un paramètre en + : quantum_time. La selection est bufferisé sauvegarder est une nouvelle élections aura lieu après la fin de quantum de temps
+  -> Ajout d'un registre, la sortie de out_access_entity est égal à ce registre.
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Parameters.h	(revision 3)
@@ -0,0 +1,51 @@
+#ifndef morpheo_behavioural_generic_select_pseudo_lru_Parameters_h
+#define morpheo_behavioural_generic_select_pseudo_lru_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+    //-----[ fields ]------------------------------------------------------------
+  public : const uint32_t _nb_entity ; // number of entity
+  public : const uint32_t _nb_access ; // number of port to select an entity
+  public : const uint32_t _nb_update ; // number of port to update the internal entity
+  public : const uint32_t _size_table; // Size of pseudo_LRU's table
+
+    //-----[ methods ]-----------------------------------------------------------
+  public : Parameters  (uint32_t nb_entity ,
+			uint32_t nb_access ,
+			uint32_t nb_update ,
+			uint32_t size_table);
+  public : Parameters  (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::generic::select::pseudo_lru::Parameters & x);
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h	(revision 3)
@@ -0,0 +1,258 @@
+#ifndef morpheo_behavioural_generic_select_pseudo_lru_Pseudo_LRU_h
+#define morpheo_behavioural_generic_select_pseudo_lru_Pseudo_LRU_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+    // Tree of Pseudo-LRU
+    //
+    // |               4-5-6-7?              |
+    // |          0_______|_______1	     |
+    // |          |               |	     |
+    // |         2-3?            6-7?        |
+    // |      0___|___1       0___|___1      |
+    // |      |       |       |       |      |
+    // |      1?      3?      5?      7?     |
+    // |    0_|_1   0_|_1   0_|_1   0_|_1    |
+    // |    |   |   |   |   |   |   |   |    |
+    // |   Way Way Way Way Way Way Way Way   |
+    // |    0   1   2   3   4   5   6   7    |
+
+
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <iostream>
+#include "Include/ToString.h"
+#include "Include/Debug.h"
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Parameters.h"
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Statistics.h"
+#endif
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#ifdef VHDL_TESTBENCH
+#include "Behavioural/include/Vhdl_Testbench.h"
+#endif
+
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  class Pseudo_LRU 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ internal class ]--------------------------------------------
+  protected : class entry_t
+  {
+    // Numerotation of pseudo_LRU's tree
+    // Tree of Pseudo-LRU
+    //
+    // | d2              [3]                 |
+    // |          0_______|_______1	     |
+    // |          |               |	     |
+    // | d1      [1]             [5]         |
+    // |      0___|___1       0___|___1      |
+    // |      |       |       |       |      |
+    // | d0  [0]     [2]     [4]     [6]     |
+    // |    0_|_1   0_|_1   0_|_1   0_|_1    |
+    // |    |   |   |   |   |   |   |   |    |
+    // |   Way Way Way Way Way Way Way Way   |
+    // |    0   1   2   3   4   5   6   7    |
+    //
+    // Access :  Way N with N=2*n   -> bit 2*n = 0
+    //                 with N=2*n+1 -> bit 2*n = 1
+    //
+    // if bit = B, depth = D, next_B = B+D if B==1
+    //                               = B-D if B==0
+    //
+    // Update : 
+
+  private : bool    * _entry;
+  private : uint32_t  _size;
+
+  public  : entry_t () 
+    {
+    };
+  public  : entry_t (uint32_t size) : _size (size)
+    {
+      _entry = new bool [size];
+      
+      // initialisation
+      for (uint32_t i=0; i<size; i++)
+	_entry [i] = false;
+    }
+    
+  public : ~entry_t ()
+    {
+      delete _entry;
+    }
+    
+  private : uint32_t one_access (uint32_t index, uint32_t offset)
+    {
+      bool val = _entry[index];
+      
+      // Compute next slot
+      if (val == true)
+	return index + offset;
+      else
+	return index - offset;
+    }
+
+  public : uint32_t access ()
+    {
+      uint32_t index = (_size>>1)-1; // medium
+
+      for (int32_t i=static_cast<uint32_t>(log2(_size)-1); i>= 1; i--)
+	{
+	  index = one_access (index,(1<<(i-1)));
+	}
+      index = one_access (index,0);
+      
+      // reverse by one_access make always a reverse
+      uint32_t offset = (_entry[index]==true)?1:0; 
+
+      return index+offset;
+    }
+
+  private : uint32_t one_update (uint32_t index, uint32_t offset, uint32_t value)
+    {
+      uint32_t mask = (offset==0)?1:(offset<<1);
+      bool     val  = ((value & mask) != 0);
+
+      // reverse 
+      _entry[index] = not val;
+
+      if (val == true)
+      // Compute next slot
+	return index + offset;
+      else
+	return index - offset;
+    }
+  public : void update (uint32_t value)
+    {
+      uint32_t index = (_size>>1)-1; // medium
+
+      for (int32_t i=static_cast<uint32_t>(log2(_size)-1); i>=1; i--)
+	{
+	  index = one_update (index,1<<(i-1),value);
+	}
+      index = one_update (index,0,value);
+    }
+
+  public : string print ()
+    {
+      string res = "";
+
+      for (int32_t i=static_cast<int32_t>(_size)-1; i>=0; i--)
+	res += toString(_entry[i]) + " ";
+
+      return res;
+    }
+
+  };
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string     _name;
+
+  protected : const Parameters _param;
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+#endif
+
+#ifdef VHDL_TESTBENCH
+  private   : Vhdl_Testbench                 * _vhdl_testbench;
+#endif
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK         ;
+
+    // Interface access
+  public    : SC_IN (Tcontrol_t)           **  in_ACCESS_VAL    ;
+  public    : SC_OUT(Tcontrol_t)           ** out_ACCESS_ACK    ;
+  public    : SC_IN (Taddress_t)           **  in_ACCESS_ADDRESS;
+  public    : SC_OUT(Tentity_t )           ** out_ACCESS_ENTITY ;
+    // Interface update
+  public    : SC_IN (Tcontrol_t)           **  in_UPDATE_VAL    ;
+  public    : SC_OUT(Tcontrol_t)           ** out_UPDATE_ACK    ;
+  public    : SC_IN (Taddress_t)           **  in_UPDATE_ADDRESS;
+  public    : SC_IN (Tentity_t )           **  in_UPDATE_ENTITY ;
+
+    // Interface update
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+  private   : entry_t                      ** reg_TABLE;
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  private   : Tentity_t                     * internal_ACCESS_ENTITY;
+#endif
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (Pseudo_LRU);
+#endif
+
+  public  :          Pseudo_LRU              (
+#ifdef SYSTEMC
+					      sc_module_name                              name,
+#else					       
+					      string                                      name,
+#endif					       
+#ifdef STATISTICS
+					      morpheo::behavioural::Parameters_Statistics param_statistics,
+#endif
+					      Parameters                                  param );
+					       
+  public  :          Pseudo_LRU              (Parameters param );
+  public  :          ~Pseudo_LRU             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+  public  : void     transition                (void);
+  public  : void     genMealy_access           (void);
+#endif					       
+#ifdef STATISTICS
+  public  : string   statistics                (uint32_t depth);
+#endif
+					       
+#if VHDL				       
+  public  : void     vhdl                      (void);
+  private : void     vhdl_port                 (Vhdl & vhdl);
+  private : void     vhdl_declaration          (Vhdl & vhdl);
+  private : void     vhdl_body                 (Vhdl & vhdl);
+#endif					       
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench            (Vhdl_Testbench & vhdl_testbench);
+  private : void     vhdl_testbench_port       (Vhdl_Testbench & vhdl_testbench);
+  private : void     vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench);
+#endif
+
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Statistics.h	(revision 3)
@@ -0,0 +1,59 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_generic_select_pseudo_lru_Statistics_h
+#define morpheo_behavioural_generic_select_pseudo_lru_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Parameters.h"
+
+using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                   _parameters;
+  private  : morpheo::behavioural::generic::group::Statistics * _stat_port_access;
+  private  : morpheo::behavioural::generic::group::Statistics * _stat_port_update;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics  (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  );
+//public   : Statistics  (Statistics & stat);
+  public   : ~Statistics () ;
+    
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : void     add        (uint32_t nb_access ,
+				  uint32_t nb_update );
+    
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/include/Types.h	(revision 3)
@@ -0,0 +1,30 @@
+#ifdef SYSTEMC
+#ifndef morpheo_behavioural_generic_select_pseudo_lru_Type_h
+#define morpheo_behavioural_generic_select_pseudo_lru_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Types.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  typedef uint32_t Taddress_t;
+  typedef uint32_t Tentity_t;
+
+}; // end namespace pseudo._lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,46 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Parameters.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  Parameters::Parameters (uint32_t nb_entity ,
+			  uint32_t nb_access ,
+			  uint32_t nb_update ,
+			  uint32_t size_table):
+    _nb_entity  (nb_entity ),
+    _nb_access  (nb_access ),
+    _nb_update  (nb_update ),
+    _size_table (size_table)
+  {
+    test();
+  };
+  
+  Parameters::Parameters (Parameters & param):
+    _nb_entity  (param._nb_entity ),
+    _nb_access  (param._nb_access ),
+    _nb_update  (param._nb_update ),
+    _size_table (param._size_table)
+  { 
+    test();
+  };
+
+  Parameters::~Parameters () 
+  { };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Parameters_msg_error.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Parameters_msg_error.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Parameters_msg_error.cpp	(revision 3)
@@ -0,0 +1,72 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Parameters.h"
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Types.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  string Parameters::msg_error(void)
+  {
+    string msg = "";
+
+    if (_nb_entity < 2)
+      {
+        msg += "  - nb_entity must be >= 2\n";
+        msg += "    * nb_entity                       : " + toString(_nb_entity) + "\n";
+      }
+
+    if (is_positive(log2(_nb_entity)) == false)
+      {
+        msg += "  - nb_entity is not a power of 2\n";
+        msg += "    * nb_entity                       : " + toString(_nb_entity) + "\n";
+      }
+
+    if (_nb_access <  1)
+      {
+        msg += "  - nb_access must be >= 1\n";
+        msg += "    * nb_access                       : " + toString(_nb_access) + "\n";
+      }
+
+    if (_size_table < 1)
+      {
+        msg += "  - size_table must be >= 1\n";
+        msg += "    * size_table                      : " + toString(_size_table) + "\n";
+      }
+
+    if (is_between_inclusive (static_cast<uint32_t>(log2(_nb_entity)),0 ,(8*sizeof(Tentity_t))) == false)
+      {
+        msg += "  - type \"Tentity_t\" is too little to the size defined by nb_entity\n";
+        msg += "    * nb_entity                       : " + toString(_nb_entity) + "\n";
+	msg += "    * Tentity_t                (bits) : " + toString(8*(sizeof(Tentity_t))) + "\n";
+      }
+
+    if (is_between_inclusive (static_cast<uint32_t>(log2(_size_table)),0 ,(8*sizeof(Taddress_t))) == false)
+      {
+        msg += "  - type \"Taddress_t\" is too little to the size defined by size_table\n";
+        msg += "    * size_table                      : " + toString(_size_table)    + "\n";
+	msg += "      > size                   (bits) : " + toString(log2(_size_table)) + "\n";
+	msg += "    * Taddress_t               (bits) : " + toString(8*(sizeof(Taddress_t))) + "\n";
+      }
+
+
+
+    return msg;
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Parameters_print.cpp	(revision 3)
@@ -0,0 +1,44 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Parameters.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  string Parameters::print (uint32_t depth)
+  {
+    string tab = string(depth,'\t');
+    ostringstream msg;
+    msg << tab << "<pseudo_lru>" << endl
+	<< tab << "\t<nb_entity  value=\"" << _nb_entity  << "\" />" << endl
+	<< tab << "\t<nb_access  value=\"" << _nb_access  << "\" />" << endl
+	<< tab << "\t<nb_update  value=\"" << _nb_update  << "\" />" << endl
+	<< tab << "\t<size_table value=\"" << _size_table << "\" />" << endl
+	<< tab << "</pseudo_lru>" << endl;
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::generic::select::pseudo_lru::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU.cpp	(revision 3)
@@ -0,0 +1,120 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+#ifdef SYSTEMC
+  Pseudo_LRU::Pseudo_LRU (sc_module_name name,
+#else
+  Pseudo_LRU::Pseudo_LRU (string name,
+#endif
+#ifdef STATISTICS
+			  morpheo::behavioural::Parameters_Statistics             param_statistics,
+#endif
+			  morpheo::behavioural::generic::select::pseudo_lru::Parameters param ):
+			  _name   (name)
+			  ,_param (param)
+  {
+    log_printf(FUNC,Pseudo_LRU,"Pseudo_LRU","Begin");
+
+#ifdef STATISTICS
+    log_printf(TRACE,Pseudo_LRU,"Pseudo_LRU","Allocation of statistics");
+    
+    // Allocation of statistics
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // Creation of a testbench
+    //  -> port
+    //  -> clock's signals
+    log_printf(TRACE,Pseudo_LRU,"Pseudo_LRU","Creation of Testbench");
+    _vhdl_testbench = new Vhdl_Testbench (_name);
+    vhdl_testbench_port           (*_vhdl_testbench);
+    _vhdl_testbench->set_clock    ("in_CLOCK",true);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    log_printf(TRACE,Pseudo_LRU,"Pseudo_LRU","Generation of VHDL");
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    log_printf(TRACE,Pseudo_LRU,"Pseudo_LRU","Allocation");
+    allocation ();
+
+    log_printf(TRACE,Pseudo_LRU,"Pseudo_LRU","Definition of sc_method");
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+
+    SC_METHOD (genMealy_access);
+    dont_initialize ();
+    sensitive_neg << *(in_CLOCK);
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+	sensitive << *(in_ACCESS_VAL     [i]);
+	if (_param._size_table>1)
+	  sensitive << *(in_ACCESS_ADDRESS [i]);
+      }
+
+#ifdef SYSTEMCASS_SPECIFIC
+    log_printf(TRACE,Pseudo_LRU,"Pseudo_LRU","List dependency information");
+    // List dependency information
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+	(*(out_ACCESS_ENTITY [i])) (*( in_ACCESS_VAL     [i]));
+	if (_param._size_table>1)
+	  (*(out_ACCESS_ENTITY [i])) (*( in_ACCESS_ADDRESS [i]));
+      }
+#endif    
+
+    // Constant - ack is always at one
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      PORT_WRITE (out_ACCESS_ACK [i], 1);
+    for (uint32_t i=0; i<_param._nb_update; i++)
+      PORT_WRITE (out_UPDATE_ACK [i], 1);
+
+#endif
+    log_printf(FUNC,Pseudo_LRU,"Pseudo_LRU","End");
+  };
+  
+  Pseudo_LRU::~Pseudo_LRU (void)
+  {
+    log_printf(FUNC,Pseudo_LRU,"~Pseudo_LRU","Begin");
+#ifdef SYSTEMC
+    deallocation ();
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // generate the test bench
+    _vhdl_testbench->generate_file();
+    delete _vhdl_testbench;
+#endif
+
+#ifdef STATISTICS
+    _stat->generate_file(statistics(0));
+    
+    delete _stat;
+#endif
+    log_printf(FUNC,Pseudo_LRU,"~Pseudo_LRU","End");
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_allocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_allocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_allocation.cpp	(revision 3)
@@ -0,0 +1,90 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  void Pseudo_LRU::allocation (void)
+  {
+    in_CLOCK  = new SC_CLOCK           ("in_CLOCK");
+
+    // -----[ Interface access ]-------------------------------------------
+     in_ACCESS_VAL     = new SC_IN (Tcontrol_t) * [_param._nb_access];
+    out_ACCESS_ACK     = new SC_OUT(Tcontrol_t) * [_param._nb_access];
+    if (_param._size_table>1)
+      in_ACCESS_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_access];
+    out_ACCESS_ENTITY  = new SC_OUT(Tentity_t ) * [_param._nb_access];
+    
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+        string rename;
+
+	rename = "in_ACCESS_VAL["     + toString(i) + "]";
+	 in_ACCESS_VAL     [i] = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	rename = "out_ACCESS_ACK["    + toString(i) + "]";
+	out_ACCESS_ACK     [i] = new SC_OUT(Tcontrol_t) (rename.c_str());
+
+	if (_param._size_table>1)
+	  {
+	    rename = "in_ACCESS_ADDRESS[" + toString(i) + "]";
+	    in_ACCESS_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());
+	  }
+	rename = "out_ACCESS_ENTITY[" + toString(i) + "]";
+	out_ACCESS_ENTITY  [i] = new SC_OUT(Tentity_t ) (rename.c_str());
+      }
+
+    // -----[ Interface update ]-------------------------------------------
+     in_UPDATE_VAL     = new SC_IN (Tcontrol_t) *  [_param._nb_update];
+    out_UPDATE_ACK     = new SC_OUT(Tcontrol_t) *  [_param._nb_update];
+    if (_param._size_table>1)
+      in_UPDATE_ADDRESS = new SC_IN (Taddress_t) *  [_param._nb_update];
+     in_UPDATE_ENTITY  = new SC_IN (Tentity_t ) *  [_param._nb_update];
+
+    for (uint32_t i=0; i<_param._nb_update; i++)
+      {
+        string rename;
+
+	rename = "in_UPDATE_VAL["     + toString(i) + "]";
+ 	 in_UPDATE_VAL     [i] = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	rename = "out_UPDATE_ACK["    + toString(i) + "]";;
+	out_UPDATE_ACK     [i] = new SC_OUT(Tcontrol_t) (rename.c_str());
+
+	if (_param._size_table>1)
+	  {
+	    rename = "in_UPDATE_ADDRESS[" + toString(i) + "]";
+	    in_UPDATE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());
+	  }
+
+	rename = "in_UPDATE_ENTITY["  + toString(i) + "]";
+	 in_UPDATE_ENTITY  [i] = new SC_IN (Tentity_t ) (rename.c_str());
+      }
+
+    // -----[ Register ]---------------------------------------------------
+    reg_TABLE = new entry_t *  [_param._size_table];
+
+    for (uint32_t i=0; i<_param._size_table; i++)
+      reg_TABLE [i] = new entry_t (_param._nb_entity);
+    
+    // -----[ Internal ]---------------------------------------------------
+    internal_ACCESS_ENTITY = new Tentity_t [_param._nb_entity];
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_deallocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_deallocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_deallocation.cpp	(revision 3)
@@ -0,0 +1,68 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  void Pseudo_LRU::deallocation (void)
+  {
+    delete in_CLOCK;
+
+    // -----[ Interface access ]-------------------------------------------
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+	delete  in_ACCESS_VAL     [i];
+	delete out_ACCESS_ACK     [i];
+	if (_param._size_table>1)
+ 	delete  in_ACCESS_ADDRESS [i];
+	delete out_ACCESS_ENTITY  [i];
+      }
+
+    delete  in_ACCESS_VAL    ;
+    delete out_ACCESS_ACK    ;
+    if (_param._size_table>1)
+    delete  in_ACCESS_ADDRESS;
+    delete out_ACCESS_ENTITY ;
+    
+    // -----[ Interface update ]-------------------------------------------
+    for (uint32_t i=0; i<_param._nb_update; i++)
+      {
+ 	delete  in_UPDATE_VAL     [i];
+	delete out_UPDATE_ACK     [i];
+	if (_param._size_table>1)
+ 	delete  in_UPDATE_ADDRESS [i];
+	delete  in_UPDATE_ENTITY  [i];
+      }
+    delete  in_UPDATE_VAL    ;
+    delete out_UPDATE_ACK    ;
+    if (_param._size_table>1)
+    delete  in_UPDATE_ADDRESS;
+    delete  in_UPDATE_ENTITY ;
+
+    // -----[ Register ]---------------------------------------------------
+    for (uint32_t i=0; i<_param._size_table; i++)
+      {
+ 	delete reg_TABLE [i];
+      }
+    delete reg_TABLE;
+
+    // -----[ Internal ]---------------------------------------------------
+    delete internal_ACCESS_ENTITY;
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_genMealy_access.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_genMealy_access.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_genMealy_access.cpp	(revision 3)
@@ -0,0 +1,46 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  void Pseudo_LRU::genMealy_access (void)
+  {
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+	if (PORT_READ (in_ACCESS_VAL[i]) == 1)
+	  {
+	    Taddress_t address;
+
+	    if (_param._size_table>1)
+	      address = PORT_READ     (in_ACCESS_ADDRESS[i]);
+	    else
+	      address = 0;
+	    
+	    internal_ACCESS_ENTITY[i] = reg_TABLE[address]->access();
+	  }
+	else
+	  {
+	    internal_ACCESS_ENTITY[i] = 0;
+	  }
+
+	PORT_WRITE(out_ACCESS_ENTITY[i], internal_ACCESS_ENTITY[i]);
+      }//end for i
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_statistics.cpp	(revision 3)
@@ -0,0 +1,28 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  
+  string Pseudo_LRU::statistics (uint32_t depth)
+  {
+    return _stat->print(depth);
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_transition.cpp	(revision 3)
@@ -0,0 +1,79 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  void Pseudo_LRU::transition (void)
+  {
+#ifdef STATISTICS
+    uint32_t _stat_nb_access = 0;
+    uint32_t _stat_nb_update = 0;
+#endif
+
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+	// Access ... (ack is always at 1)
+	if (PORT_READ (in_ACCESS_VAL[i]) == 1)
+	  {
+#ifdef STATISTICS
+	    _stat_nb_access ++;
+#endif
+	    Taddress_t address;
+
+	    if (_param._size_table>1)
+	      address = PORT_READ     (in_ACCESS_ADDRESS[i]);
+	    else
+	      address = 0;
+	    
+	    reg_TABLE[address]->update(internal_ACCESS_ENTITY[i]);
+	  }
+      }//end for i
+    
+    for (uint32_t i=0; i<_param._nb_update; i++)
+      {
+	// Update ... (ack is always at 1)
+	if (PORT_READ (in_UPDATE_VAL[i]) == 1)
+	  {
+#ifdef STATISTICS
+	    _stat_nb_update ++;
+#endif
+	    
+	    Taddress_t address;
+	    
+	    if (_param._size_table>1)
+	      address = PORT_READ     (in_UPDATE_ADDRESS[i]);
+	    else
+	      address = 0;
+	    
+	    reg_TABLE[address]->update(PORT_READ(in_UPDATE_ENTITY[i]));
+	  }
+      }//end for i
+
+#ifdef STATISTICS
+    _stat->add(_stat_nb_access,
+	       _stat_nb_update);
+#endif    
+    
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition (*_vhdl_testbench);
+#endif
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  void Pseudo_LRU::vhdl (void)
+  {
+    log_printf(FUNC,Pseudo_LRU,"vhdl","Begin");
+
+    log_printf(TRACE,Pseudo_LRU,"vhdl","Construction of vhdl");
+    Vhdl vhdl (_name);
+
+    log_printf(TRACE,Pseudo_LRU,"vhdl","Set library");
+    vhdl.set_library_work (_name + "_Pack");
+
+    log_printf(TRACE,Pseudo_LRU,"vhdl","Set port");
+    vhdl_port        (vhdl);
+    log_printf(TRACE,Pseudo_LRU,"vhdl","Set declaration");
+    vhdl_declaration (vhdl);
+    log_printf(TRACE,Pseudo_LRU,"vhdl","Set body");
+    vhdl_body        (vhdl);
+    log_printf(TRACE,Pseudo_LRU,"vhdl","Generate File");
+    vhdl.generate_file();
+    log_printf(FUNC,Pseudo_LRU,"vhdl","End");
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_body.cpp	(revision 3)
@@ -0,0 +1,227 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  void Pseudo_LRU::vhdl_body (Vhdl & vhdl)
+  {
+    vhdl.set_body ("");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("-- Access");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("");
+    vhdl.set_body ("-- Tree of Pseudo-LRU - example to 8 entity");
+    vhdl.set_body ("--");
+    vhdl.set_body ("--                4-5-6-7?              ");
+    vhdl.set_body ("--           0_______|_______1	    ");
+    vhdl.set_body ("--           |               |	    ");
+    vhdl.set_body ("--          2-3?            6-7?        ");
+    vhdl.set_body ("--       0___|___1       0___|___1      ");
+    vhdl.set_body ("--       |       |       |       |      ");
+    vhdl.set_body ("--       1?      3?      5?      7?     ");
+    vhdl.set_body ("--     0_|_1   0_|_1   0_|_1   0_|_1    ");
+    vhdl.set_body ("--     |   |   |   |   |   |   |   |    ");
+    vhdl.set_body ("--    Way Way Way Way Way Way Way Way   ");
+    vhdl.set_body ("--     0   1   2   3   4   5   6   7    ");
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+	vhdl.set_body ("");
+	// Read the table
+	
+	string access_address;
+
+	if (_param._size_table>1)
+	  access_address = "conv_integer(in_ACCESS_ADDRESS_"+toString(i)+")";
+	else
+	  access_address = "0";
+
+	vhdl.set_body ("access_entry_"+toString(i)+" <= reg_TABLE ("+access_address+");");
+	vhdl.set_body ("");
+
+	for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--)
+	  {
+ 	    vhdl.set_body ("access_entity_"+toString(i)+"("+toString(j)+") <= ");
+
+	    uint32_t cpt=0;
+
+	    for (int32_t k=(1<<j)-1; k<static_cast<int32_t>(_param._nb_entity-1); k+=(1<<(j+1)))
+	      {
+		string cond = "";
+		
+		// Create the condition
+		for (uint32_t l=j+1; l<static_cast<uint32_t>(log2(_param._nb_entity));l++)
+		  {
+		    if (l==static_cast<uint32_t>(j+1))
+		      cond += "when";
+		    else
+		      cond += " and";
+		    cond += " access_entity_"+toString(i)+"("+toString(l)+") = '"+toString((cpt>>(l-(j+1)))&1)+"'";
+		  }
+		
+		string print_else = (k==(1<<j)-1)?"     ":"else ";
+
+		vhdl.set_body ("\t"+print_else+"access_entry_"+toString(i)+"("+toString(k)+") "+cond);
+		cpt ++;
+	      }
+	    vhdl.set_body ("\t;");
+	  }
+      }
+
+    vhdl.set_body ("");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("-- Update");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("");
+    vhdl.set_body ("-- port access");
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--)
+	{
+	  uint32_t cpt=0;
+	  
+	  for (int32_t k=(1<<j)-1; k<static_cast<int32_t>(_param._nb_entity-1); k+=(1<<(j+1)))
+	    {
+	      bool   have_cond = false;
+	      string cond      = "";
+	      
+	      // condition to change the bit
+	      for (uint32_t l=j+1; l<static_cast<uint32_t>(log2(_param._nb_entity));l++)
+		{
+		  have_cond = true;
+
+		  if (l==static_cast<uint32_t>(j+1))
+		    cond += "when";
+		  else
+		    cond += " and";
+		  cond += " access_entity_"+toString(i)+"("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'";
+		}
+	      
+	      vhdl.set_body ("access_next_entry_"+toString(i)+"("+toString(k)+") <=");
+	      vhdl.set_body ("\tnot access_entity_"+toString(i)+"("+toString(j)+") "+cond);
+	      if (have_cond == true)
+		vhdl.set_body ("\telse access_entry_"+toString(i)+"("+toString(k)+")");
+	      vhdl.set_body ("\t;");	      
+	      cpt ++;
+	    }
+	}
+
+    vhdl.set_body ("");
+    vhdl.set_body ("-- port update");
+    for (uint32_t i=0; i<_param._nb_update; i++)
+      for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--)
+	{
+	  uint32_t cpt=0;
+	  
+	  for (int32_t k=(1<<j)-1; k<static_cast<int32_t>(_param._nb_entity-1); k+=(1<<(j+1)))
+	    {
+	      bool   have_cond = false;
+	      string cond      = "";
+	      
+	      // condition to change the bit
+	      for (uint32_t l=j+1; l<static_cast<uint32_t>(log2(_param._nb_entity));l++)
+		{
+		  have_cond = true;
+
+		  if (l==static_cast<uint32_t>(j+1))
+		    cond += "when";
+		  else
+		    cond += " and";
+		  cond += " in_UPDATE_ENTITY_"+toString(i)+"("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'";
+		}
+	      
+	      vhdl.set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <=");
+	      vhdl.set_body ("\tnot in_UPDATE_ENTITY_"+toString(i)+"("+toString(j)+") "+cond);
+	      if (have_cond == true)
+		{
+		  string update_address;
+
+		  if (_param._size_table>1)
+		    update_address = "conv_integer(in_UPDATE_ADDRESS_"+toString(i)+")";
+		  else
+		    update_address = "0";
+		  
+		  vhdl.set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")");
+		}
+	      vhdl.set_body ("\t;");	      
+	      cpt ++;
+	    }
+	}
+
+    vhdl.set_body ("");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("-- Transition");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("");
+
+    vhdl.set_body ("reg_TABLE_write: process (in_CLOCK)");
+    vhdl.set_body ("begin");
+    vhdl.set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then");
+    vhdl.set_body ("\t\t-- Access port");
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+	string access_address;
+
+	if (_param._size_table>1)
+	  access_address = "conv_integer(in_ACCESS_ADDRESS_"+toString(i)+")";
+	else
+	  access_address = "0";
+
+	vhdl.set_body ("\t\tif (in_ACCESS_VAL_"+toString(i)+" = '1') then");
+	vhdl.set_body ("\t\t\treg_TABLE ("+access_address+") <= access_next_entry_"+toString(i)+";");
+	vhdl.set_body ("\t\tend if;");
+      }
+
+    vhdl.set_body ("\t\t-- Update port");
+    for (uint32_t i=0; i<_param._nb_update; i++)
+      {
+	string update_address;
+
+	if (_param._size_table>1)
+	  update_address = "conv_integer(in_UPDATE_ADDRESS_"+toString(i)+")";
+	else
+	  update_address = "0";
+		  
+	vhdl.set_body ("\t\tif (in_UPDATE_VAL_"+toString(i)+" = '1') then");
+	vhdl.set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";");
+	vhdl.set_body ("\t\tend if;");
+      }
+
+    vhdl.set_body ("\tend if;");
+    vhdl.set_body ("end process reg_TABLE_write;");
+
+    vhdl.set_body ("");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("-- Output");
+    vhdl.set_body ("-----------------------------------------------------------------------------");
+    vhdl.set_body ("");
+    vhdl.set_body ("-- Ack is always ");
+    vhdl.set_body ("");
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+	vhdl.set_body ("out_ACCESS_ACK_"+toString(i)+"    <= '1';");
+	vhdl.set_body ("out_ACCESS_ENTITY_"+toString(i)+" <= access_entity_"+toString(i)+" when in_ACCESS_VAL_"+toString(i)+" = '1' else (others => '0');");
+      }
+    vhdl.set_body ("");
+    for (uint32_t i=0; i<_param._nb_update; i++)
+      {
+	vhdl.set_body ("out_UPDATE_ACK_"+toString(i)+"    <= '1';");
+      }
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_declaration.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_declaration.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_declaration.cpp	(revision 3)
@@ -0,0 +1,42 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  void Pseudo_LRU::vhdl_declaration (Vhdl & vhdl)
+  {
+    vhdl.set_type ("Ttable", "array (" + toString(_param._size_table-1) + " downto 0) of "+std_logic(_param._nb_entity-1));
+
+
+    vhdl.set_signal ("reg_TABLE", "Ttable");
+    for (uint32_t i=0; i<_param._nb_access; i++)
+      {
+	vhdl.set_signal ("access_entry_"+toString(i)+"     ",std_logic(_param._nb_entity-1));
+	vhdl.set_signal ("access_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1));
+	vhdl.set_signal ("access_entity_"+toString(i)+"    ",std_logic(static_cast<uint32_t>(log2(_param._nb_entity))));
+      }
+
+    for (uint32_t i=0; i<_param._nb_update; i++)
+      {
+	vhdl.set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1));
+      }
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_port.cpp	(revision 3)
@@ -0,0 +1,47 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  void Pseudo_LRU::vhdl_port (Vhdl & vhdl)
+  {
+    vhdl.set_port ("in_CLOCK" , IN, "std_logic");
+
+    for (uint32_t i = 0; i < _param._nb_access; i ++)
+      {
+	vhdl.set_port (" in_ACCESS_VAL_"+toString(i)+"     ",IN ,std_logic(1));
+	vhdl.set_port ("out_ACCESS_ACK_"+toString(i)+"     ",OUT,std_logic(1));
+	if (_param._size_table>1)
+	  vhdl.set_port (" in_ACCESS_ADDRESS_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._size_table))));
+	vhdl.set_port ("out_ACCESS_ENTITY_"+toString(i)+"  ",OUT,std_logic(static_cast<uint32_t>(log2(_param._nb_entity))));
+      }
+
+    for (uint32_t i = 0; i < _param._nb_update; i ++)
+      {
+	vhdl.set_port (" in_UPDATE_VAL_"+toString(i)+"     ",IN ,std_logic(1));
+	vhdl.set_port ("out_UPDATE_ACK_"+toString(i)+"     ",OUT,std_logic(1));
+	if (_param._size_table>1)
+	  vhdl.set_port (" in_UPDATE_ADDRESS_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._size_table))));
+	vhdl.set_port (" in_UPDATE_ENTITY_"+toString(i)+"  ",IN ,std_logic(static_cast<uint32_t>(log2(_param._nb_entity))));
+      }
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_testbench_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_testbench_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_testbench_port.cpp	(revision 3)
@@ -0,0 +1,44 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  void Pseudo_LRU::vhdl_testbench_port (Vhdl_Testbench & vhdl_testbench)
+  {
+    for (uint32_t i = 0; i < _param._nb_access; i ++)
+      {
+	vhdl_testbench.set_port (" in_ACCESS_VAL_"+toString(i)+"     ",IN ,1);
+	vhdl_testbench.set_port ("out_ACCESS_ACK_"+toString(i)+"     ",OUT,1);
+	if (_param._size_table>1)
+	  vhdl_testbench.set_port (" in_ACCESS_ADDRESS_"+toString(i)+" ",IN ,static_cast<uint32_t>(log2(_param._size_table)));
+	vhdl_testbench.set_port ("out_ACCESS_ENTITY_"+toString(i)+"  ",OUT,static_cast<uint32_t>(log2(_param._nb_entity)));
+      }
+
+    for (uint32_t i = 0; i < _param._nb_update; i ++)
+      {
+	vhdl_testbench.set_port (" in_UPDATE_VAL_"+toString(i)+"     ",IN ,1);
+	vhdl_testbench.set_port ("out_UPDATE_ACK_"+toString(i)+"     ",OUT,1);
+	if (_param._size_table>1)
+	  vhdl_testbench.set_port (" in_UPDATE_ADDRESS_"+toString(i)+" ",IN ,static_cast<uint32_t>(log2(_param._size_table)));
+	vhdl_testbench.set_port (" in_UPDATE_ENTITY_"+toString(i)+"  ",IN ,static_cast<uint32_t>(log2(_param._nb_entity)));
+      }
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_testbench_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_testbench_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Pseudo_LRU_vhdl_testbench_transition.cpp	(revision 3)
@@ -0,0 +1,52 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Pseudo_LRU.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  void Pseudo_LRU::vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench)
+  {
+#ifndef SYSTEMCASS_SPECIFIC
+    sc_cycle(0);
+#endif
+
+    for (uint32_t i = 0; i < _param._nb_access; i ++)
+      {
+	vhdl_testbench.add_input  (PORT_READ( in_ACCESS_VAL     [i]));
+	vhdl_testbench.add_output (PORT_READ(out_ACCESS_ACK     [i]));
+	if (_param._size_table>1)
+	  vhdl_testbench.add_input  (PORT_READ( in_ACCESS_ADDRESS [i]));
+	vhdl_testbench.add_output (PORT_READ(out_ACCESS_ENTITY  [i]));
+      }
+
+    for (uint32_t i = 0; i < _param._nb_update; i ++)
+      {
+	vhdl_testbench.add_input  (PORT_READ( in_UPDATE_VAL     [i]));
+	vhdl_testbench.add_output (PORT_READ(out_UPDATE_ACK     [i]));
+	if (_param._size_table>1)
+	  vhdl_testbench.add_input  (PORT_READ( in_UPDATE_ADDRESS [i]));
+	vhdl_testbench.add_input  (PORT_READ( in_UPDATE_ENTITY  [i]));
+      }
+
+    vhdl_testbench.add_test(true);
+
+    vhdl_testbench.new_cycle (); // always at the end
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,46 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+    _stat_port_access = new morpheo::behavioural::generic::group::Statistics (name + "_port_access" ,
+									      parameters_statistics ,
+									      morpheo::behavioural::generic::group::Parameters(_parameters._nb_access));
+    _stat_port_update = new morpheo::behavioural::generic::group::Statistics (name + "_port_update"   ,
+									      parameters_statistics ,
+									      morpheo::behavioural::generic::group::Parameters(_parameters._nb_update));
+  };
+  
+  Statistics::~Statistics () 
+  { 
+    delete _stat_port_access;
+    delete _stat_port_update;
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,32 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+  void Statistics::add (uint32_t nb_access,
+			uint32_t nb_update)
+  {
+    _stat_port_access->add(nb_access);
+    _stat_port_update->add(nb_update);
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,47 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  string Statistics::print (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<pseudo_lru name=\"" << _name << "\" >" << endl
+	<< print_body (depth+1)
+	<< tab << "</pseudo_lru>" << endl;
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::generic::select::pseudo_lru::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Pseudo_LRU/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,38 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Select/Pseudo_LRU/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace select {
+namespace pseudo_lru {
+
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << _stat_port_access->print(depth+1);
+    msg << _stat_port_update->print(depth+1);
+    
+    return msg.str();
+  };
+
+}; // end namespace pseudo_lru
+}; // end namespace select
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/TODO
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/TODO	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/TODO	(revision 3)
@@ -0,0 +1,7 @@
+- Ajouter quelques algorithme de selection
+  * Round Robin
+    -> simple compteur de log2(N) bits
+  * True LRU
+    -> fifo matériel. Un élément accéder sera placer en fin de fifo. 
+  * Random
+    -> LFSR (?) qui ne tourne pas à chaque cycle mais à chaque in_access_val = '1'
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/Makefile	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../..
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libShifter.a
+
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/Makefile.deps	(revision 3)
@@ -0,0 +1,31 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+
+Shifter				= yes
+
+#-----[ Library ]------------------------------------------
+Shifter_LIBRARY			= 	-lShifter	\
+					$(Behavioural_LIBRARY)	
+
+Shifter_DIR_LIBRARY		=	-L$(DIR_MORPHEO)/Behavioural/Generic/Shifter/lib	\
+					$(Behavioural_DIR_LIBRARY)
+
+#-----[ Rules ]--------------------------------------------
+
+Shifter_library		: 
+				@$(MAKE) Behavioural_library
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Shifter --makefile=Makefile 
+	
+Shifter_library_clean	: 
+				@$(MAKE) Behavioural_library_clean
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Shifter --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,29 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../..
+
+LIBRARY				= $(Shifter_LIBRARY)
+
+DIR_LIBRARY			= $(Shifter_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				: library
+				@$(MAKE) all_selftest
+
+library				: Shifter_library
+
+library_clean			: Shifter_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration.cfg	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/configuration.cfg	(revision 3)
@@ -0,0 +1,7 @@
+Shifter
+16	16	*4	# size_data  
+1	2	+1	# nb_port    
+0	2	+1	# shift_value
+0	0	+1	# rotate     
+0	2	+1	# direction  
+0	2	+1	# carry      
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/include/test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/include/test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/include/test.h	(revision 3)
@@ -0,0 +1,26 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::generic;
+
+using namespace morpheo::behavioural::generic::shifter;
+
+void test   (string name,
+	     morpheo::behavioural::generic::shifter::Parameters param);
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/mkf.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/mkf.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/mkf.info	(revision 3)
@@ -0,0 +1,271 @@
+
+# Shifter_0
+target_dep	all	Shifter_0.ngc
+target_dep	Shifter_0.ngc	Shifter_0.prj
+target_dep	Shifter_0.prj	Shifter_0_Pack.vhdl Shifter_0.vhdl
+
+# Shifter_10
+target_dep	all	Shifter_10.ngc
+target_dep	Shifter_10.ngc	Shifter_10.prj
+target_dep	Shifter_10.prj	Shifter_10_Pack.vhdl Shifter_10.vhdl
+
+# Shifter_11
+target_dep	all	Shifter_11.ngc
+target_dep	Shifter_11.ngc	Shifter_11.prj
+target_dep	Shifter_11.prj	Shifter_11_Pack.vhdl Shifter_11.vhdl
+
+# Shifter_12
+target_dep	all	Shifter_12.ngc
+target_dep	Shifter_12.ngc	Shifter_12.prj
+target_dep	Shifter_12.prj	Shifter_12_Pack.vhdl Shifter_12.vhdl
+
+# Shifter_13
+target_dep	all	Shifter_13.ngc
+target_dep	Shifter_13.ngc	Shifter_13.prj
+target_dep	Shifter_13.prj	Shifter_13_Pack.vhdl Shifter_13.vhdl
+
+# Shifter_14
+target_dep	all	Shifter_14.ngc
+target_dep	Shifter_14.ngc	Shifter_14.prj
+target_dep	Shifter_14.prj	Shifter_14_Pack.vhdl Shifter_14.vhdl
+
+# Shifter_15
+target_dep	all	Shifter_15.ngc
+target_dep	Shifter_15.ngc	Shifter_15.prj
+target_dep	Shifter_15.prj	Shifter_15_Pack.vhdl Shifter_15.vhdl
+
+# Shifter_16
+target_dep	all	Shifter_16.ngc
+target_dep	Shifter_16.ngc	Shifter_16.prj
+target_dep	Shifter_16.prj	Shifter_16_Pack.vhdl Shifter_16.vhdl
+
+# Shifter_17
+target_dep	all	Shifter_17.ngc
+target_dep	Shifter_17.ngc	Shifter_17.prj
+target_dep	Shifter_17.prj	Shifter_17_Pack.vhdl Shifter_17.vhdl
+
+# Shifter_18
+target_dep	all	Shifter_18.ngc
+target_dep	Shifter_18.ngc	Shifter_18.prj
+target_dep	Shifter_18.prj	Shifter_18_Pack.vhdl Shifter_18.vhdl
+
+# Shifter_19
+target_dep	all	Shifter_19.ngc
+target_dep	Shifter_19.ngc	Shifter_19.prj
+target_dep	Shifter_19.prj	Shifter_19_Pack.vhdl Shifter_19.vhdl
+
+# Shifter_1
+target_dep	all	Shifter_1.ngc
+target_dep	Shifter_1.ngc	Shifter_1.prj
+target_dep	Shifter_1.prj	Shifter_10_Pack.vhdl Shifter_10.vhdl Shifter_11_Pack.vhdl Shifter_11.vhdl Shifter_12_Pack.vhdl Shifter_12.vhdl Shifter_13_Pack.vhdl Shifter_13.vhdl Shifter_14_Pack.vhdl Shifter_14.vhdl Shifter_15_Pack.vhdl Shifter_15.vhdl Shifter_16_Pack.vhdl Shifter_16.vhdl Shifter_17_Pack.vhdl Shifter_17.vhdl Shifter_18_Pack.vhdl Shifter_18.vhdl Shifter_19_Pack.vhdl Shifter_19.vhdl Shifter_1_Pack.vhdl Shifter_1.vhdl
+
+# Shifter_20
+target_dep	all	Shifter_20.ngc
+target_dep	Shifter_20.ngc	Shifter_20.prj
+target_dep	Shifter_20.prj	Shifter_20_Pack.vhdl Shifter_20.vhdl
+
+# Shifter_21
+target_dep	all	Shifter_21.ngc
+target_dep	Shifter_21.ngc	Shifter_21.prj
+target_dep	Shifter_21.prj	Shifter_21_Pack.vhdl Shifter_21.vhdl
+
+# Shifter_22
+target_dep	all	Shifter_22.ngc
+target_dep	Shifter_22.ngc	Shifter_22.prj
+target_dep	Shifter_22.prj	Shifter_22_Pack.vhdl Shifter_22.vhdl
+
+# Shifter_23
+target_dep	all	Shifter_23.ngc
+target_dep	Shifter_23.ngc	Shifter_23.prj
+target_dep	Shifter_23.prj	Shifter_23_Pack.vhdl Shifter_23.vhdl
+
+# Shifter_24
+target_dep	all	Shifter_24.ngc
+target_dep	Shifter_24.ngc	Shifter_24.prj
+target_dep	Shifter_24.prj	Shifter_24_Pack.vhdl Shifter_24.vhdl
+
+# Shifter_25
+target_dep	all	Shifter_25.ngc
+target_dep	Shifter_25.ngc	Shifter_25.prj
+target_dep	Shifter_25.prj	Shifter_25_Pack.vhdl Shifter_25.vhdl
+
+# Shifter_26
+target_dep	all	Shifter_26.ngc
+target_dep	Shifter_26.ngc	Shifter_26.prj
+target_dep	Shifter_26.prj	Shifter_26_Pack.vhdl Shifter_26.vhdl
+
+# Shifter_27
+target_dep	all	Shifter_27.ngc
+target_dep	Shifter_27.ngc	Shifter_27.prj
+target_dep	Shifter_27.prj	Shifter_27_Pack.vhdl Shifter_27.vhdl
+
+# Shifter_28
+target_dep	all	Shifter_28.ngc
+target_dep	Shifter_28.ngc	Shifter_28.prj
+target_dep	Shifter_28.prj	Shifter_28_Pack.vhdl Shifter_28.vhdl
+
+# Shifter_29
+target_dep	all	Shifter_29.ngc
+target_dep	Shifter_29.ngc	Shifter_29.prj
+target_dep	Shifter_29.prj	Shifter_29_Pack.vhdl Shifter_29.vhdl
+
+# Shifter_2
+target_dep	all	Shifter_2.ngc
+target_dep	Shifter_2.ngc	Shifter_2.prj
+target_dep	Shifter_2.prj	Shifter_20_Pack.vhdl Shifter_20.vhdl Shifter_21_Pack.vhdl Shifter_21.vhdl Shifter_22_Pack.vhdl Shifter_22.vhdl Shifter_23_Pack.vhdl Shifter_23.vhdl Shifter_24_Pack.vhdl Shifter_24.vhdl Shifter_25_Pack.vhdl Shifter_25.vhdl Shifter_26_Pack.vhdl Shifter_26.vhdl Shifter_27_Pack.vhdl Shifter_27.vhdl Shifter_28_Pack.vhdl Shifter_28.vhdl Shifter_29_Pack.vhdl Shifter_29.vhdl Shifter_2_Pack.vhdl Shifter_2.vhdl
+
+# Shifter_30
+target_dep	all	Shifter_30.ngc
+target_dep	Shifter_30.ngc	Shifter_30.prj
+target_dep	Shifter_30.prj	Shifter_30_Pack.vhdl Shifter_30.vhdl
+
+# Shifter_31
+target_dep	all	Shifter_31.ngc
+target_dep	Shifter_31.ngc	Shifter_31.prj
+target_dep	Shifter_31.prj	Shifter_31_Pack.vhdl Shifter_31.vhdl
+
+# Shifter_32
+target_dep	all	Shifter_32.ngc
+target_dep	Shifter_32.ngc	Shifter_32.prj
+target_dep	Shifter_32.prj	Shifter_32_Pack.vhdl Shifter_32.vhdl
+
+# Shifter_33
+target_dep	all	Shifter_33.ngc
+target_dep	Shifter_33.ngc	Shifter_33.prj
+target_dep	Shifter_33.prj	Shifter_33_Pack.vhdl Shifter_33.vhdl
+
+# Shifter_34
+target_dep	all	Shifter_34.ngc
+target_dep	Shifter_34.ngc	Shifter_34.prj
+target_dep	Shifter_34.prj	Shifter_34_Pack.vhdl Shifter_34.vhdl
+
+# Shifter_35
+target_dep	all	Shifter_35.ngc
+target_dep	Shifter_35.ngc	Shifter_35.prj
+target_dep	Shifter_35.prj	Shifter_35_Pack.vhdl Shifter_35.vhdl
+
+# Shifter_36
+target_dep	all	Shifter_36.ngc
+target_dep	Shifter_36.ngc	Shifter_36.prj
+target_dep	Shifter_36.prj	Shifter_36_Pack.vhdl Shifter_36.vhdl
+
+# Shifter_37
+target_dep	all	Shifter_37.ngc
+target_dep	Shifter_37.ngc	Shifter_37.prj
+target_dep	Shifter_37.prj	Shifter_37_Pack.vhdl Shifter_37.vhdl
+
+# Shifter_38
+target_dep	all	Shifter_38.ngc
+target_dep	Shifter_38.ngc	Shifter_38.prj
+target_dep	Shifter_38.prj	Shifter_38_Pack.vhdl Shifter_38.vhdl
+
+# Shifter_39
+target_dep	all	Shifter_39.ngc
+target_dep	Shifter_39.ngc	Shifter_39.prj
+target_dep	Shifter_39.prj	Shifter_39_Pack.vhdl Shifter_39.vhdl
+
+# Shifter_3
+target_dep	all	Shifter_3.ngc
+target_dep	Shifter_3.ngc	Shifter_3.prj
+target_dep	Shifter_3.prj	Shifter_30_Pack.vhdl Shifter_30.vhdl Shifter_31_Pack.vhdl Shifter_31.vhdl Shifter_32_Pack.vhdl Shifter_32.vhdl Shifter_33_Pack.vhdl Shifter_33.vhdl Shifter_34_Pack.vhdl Shifter_34.vhdl Shifter_35_Pack.vhdl Shifter_35.vhdl Shifter_36_Pack.vhdl Shifter_36.vhdl Shifter_37_Pack.vhdl Shifter_37.vhdl Shifter_38_Pack.vhdl Shifter_38.vhdl Shifter_39_Pack.vhdl Shifter_39.vhdl Shifter_3_Pack.vhdl Shifter_3.vhdl
+
+# Shifter_40
+target_dep	all	Shifter_40.ngc
+target_dep	Shifter_40.ngc	Shifter_40.prj
+target_dep	Shifter_40.prj	Shifter_40_Pack.vhdl Shifter_40.vhdl
+
+# Shifter_41
+target_dep	all	Shifter_41.ngc
+target_dep	Shifter_41.ngc	Shifter_41.prj
+target_dep	Shifter_41.prj	Shifter_41_Pack.vhdl Shifter_41.vhdl
+
+# Shifter_42
+target_dep	all	Shifter_42.ngc
+target_dep	Shifter_42.ngc	Shifter_42.prj
+target_dep	Shifter_42.prj	Shifter_42_Pack.vhdl Shifter_42.vhdl
+
+# Shifter_43
+target_dep	all	Shifter_43.ngc
+target_dep	Shifter_43.ngc	Shifter_43.prj
+target_dep	Shifter_43.prj	Shifter_43_Pack.vhdl Shifter_43.vhdl
+
+# Shifter_44
+target_dep	all	Shifter_44.ngc
+target_dep	Shifter_44.ngc	Shifter_44.prj
+target_dep	Shifter_44.prj	Shifter_44_Pack.vhdl Shifter_44.vhdl
+
+# Shifter_45
+target_dep	all	Shifter_45.ngc
+target_dep	Shifter_45.ngc	Shifter_45.prj
+target_dep	Shifter_45.prj	Shifter_45_Pack.vhdl Shifter_45.vhdl
+
+# Shifter_46
+target_dep	all	Shifter_46.ngc
+target_dep	Shifter_46.ngc	Shifter_46.prj
+target_dep	Shifter_46.prj	Shifter_46_Pack.vhdl Shifter_46.vhdl
+
+# Shifter_47
+target_dep	all	Shifter_47.ngc
+target_dep	Shifter_47.ngc	Shifter_47.prj
+target_dep	Shifter_47.prj	Shifter_47_Pack.vhdl Shifter_47.vhdl
+
+# Shifter_48
+target_dep	all	Shifter_48.ngc
+target_dep	Shifter_48.ngc	Shifter_48.prj
+target_dep	Shifter_48.prj	Shifter_48_Pack.vhdl Shifter_48.vhdl
+
+# Shifter_49
+target_dep	all	Shifter_49.ngc
+target_dep	Shifter_49.ngc	Shifter_49.prj
+target_dep	Shifter_49.prj	Shifter_49_Pack.vhdl Shifter_49.vhdl
+
+# Shifter_4
+target_dep	all	Shifter_4.ngc
+target_dep	Shifter_4.ngc	Shifter_4.prj
+target_dep	Shifter_4.prj	Shifter_40_Pack.vhdl Shifter_40.vhdl Shifter_41_Pack.vhdl Shifter_41.vhdl Shifter_42_Pack.vhdl Shifter_42.vhdl Shifter_43_Pack.vhdl Shifter_43.vhdl Shifter_44_Pack.vhdl Shifter_44.vhdl Shifter_45_Pack.vhdl Shifter_45.vhdl Shifter_46_Pack.vhdl Shifter_46.vhdl Shifter_47_Pack.vhdl Shifter_47.vhdl Shifter_48_Pack.vhdl Shifter_48.vhdl Shifter_49_Pack.vhdl Shifter_49.vhdl Shifter_4_Pack.vhdl Shifter_4.vhdl
+
+# Shifter_50
+target_dep	all	Shifter_50.ngc
+target_dep	Shifter_50.ngc	Shifter_50.prj
+target_dep	Shifter_50.prj	Shifter_50_Pack.vhdl Shifter_50.vhdl
+
+# Shifter_51
+target_dep	all	Shifter_51.ngc
+target_dep	Shifter_51.ngc	Shifter_51.prj
+target_dep	Shifter_51.prj	Shifter_51_Pack.vhdl Shifter_51.vhdl
+
+# Shifter_52
+target_dep	all	Shifter_52.ngc
+target_dep	Shifter_52.ngc	Shifter_52.prj
+target_dep	Shifter_52.prj	Shifter_52_Pack.vhdl Shifter_52.vhdl
+
+# Shifter_53
+target_dep	all	Shifter_53.ngc
+target_dep	Shifter_53.ngc	Shifter_53.prj
+target_dep	Shifter_53.prj	Shifter_53_Pack.vhdl Shifter_53.vhdl
+
+# Shifter_5
+target_dep	all	Shifter_5.ngc
+target_dep	Shifter_5.ngc	Shifter_5.prj
+target_dep	Shifter_5.prj	Shifter_50_Pack.vhdl Shifter_50.vhdl Shifter_51_Pack.vhdl Shifter_51.vhdl Shifter_52_Pack.vhdl Shifter_52.vhdl Shifter_53_Pack.vhdl Shifter_53.vhdl Shifter_5_Pack.vhdl Shifter_5.vhdl
+
+# Shifter_6
+target_dep	all	Shifter_6.ngc
+target_dep	Shifter_6.ngc	Shifter_6.prj
+target_dep	Shifter_6.prj	Shifter_6_Pack.vhdl Shifter_6.vhdl
+
+# Shifter_7
+target_dep	all	Shifter_7.ngc
+target_dep	Shifter_7.ngc	Shifter_7.prj
+target_dep	Shifter_7.prj	Shifter_7_Pack.vhdl Shifter_7.vhdl
+
+# Shifter_8
+target_dep	all	Shifter_8.ngc
+target_dep	Shifter_8.ngc	Shifter_8.prj
+target_dep	Shifter_8.prj	Shifter_8_Pack.vhdl Shifter_8.vhdl
+
+# Shifter_9
+target_dep	all	Shifter_9.ngc
+target_dep	Shifter_9.ngc	Shifter_9.prj
+target_dep	Shifter_9.prj	Shifter_9_Pack.vhdl Shifter_9.vhdl
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,52 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/SelfTest/include/test.h"
+
+#define NB_PARAMS 6
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - size_data   (unsigned int)" << endl
+       << " - nb_port     (unsigned int)" << endl
+       << " - shift_value (unsigned int)" << endl
+       << " - rotate      (unsigned int)" << endl
+       << " - direction   (unsigned int)" << endl
+       << " - carry       (unsigned int)" << endl;
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc != 2+NB_PARAMS)
+    usage (argv[0]);
+
+  const string                                              name        = argv[1];
+  const uint32_t                                            size_data   = atoi(argv[2]);
+  const uint32_t                                            nb_port     = atoi(argv[3]);
+  const uint32_t                                            shift_value = atoi(argv[4]);
+  const morpheo::behavioural::generic::shifter::rotate_t    rotate      = static_cast<morpheo::behavioural::generic::shifter::rotate_t   >(atoi(argv[5]));
+  const morpheo::behavioural::generic::shifter::direction_t direction   = static_cast<morpheo::behavioural::generic::shifter::direction_t>(atoi(argv[6]));
+  const morpheo::behavioural::generic::shifter::carry_t     carry       = static_cast<morpheo::behavioural::generic::shifter::carry_t    >(atoi(argv[7]));
+
+  morpheo::behavioural::generic::shifter::Parameters param (size_data  ,
+							    nb_port    ,
+							    shift_value,
+							    rotate     ,
+							    direction  ,
+							    carry      );
+
+  test (name,param);
+
+  return (EXIT_SUCCESS);
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp	(revision 3)
@@ -0,0 +1,296 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#include "Behavioural/Generic/Shifter/SelfTest/include/test.h"
+#include "Include/BitManipulation.h"
+#include "Include/Test.h"
+
+#define NB_ITERATION 64
+
+void test (string name,
+	   morpheo::behavioural::generic::shifter::Parameters param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  try 
+    {
+      cout << param.print(1);
+      param.test();
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      return;
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+  Shifter * _Shifter = new Shifter (name.c_str(),
+#ifdef STATISTICS
+					     morpheo::behavioural::Parameters_Statistics(5,50),
+#endif
+					     param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                                 CLOCK ("clock", 1.0, 0.5);
+  sc_signal <Tdata_t     >                 SHIFTER_DATA_IN   [param._nb_port];
+  sc_signal <Tshift_t    >                 SHIFTER_SHIFT     [param._nb_port];
+  sc_signal <Tdirection_t>                 SHIFTER_DIRECTION [param._nb_port];
+  sc_signal <Ttype_t     >                 SHIFTER_TYPE      [param._nb_port];
+  sc_signal <Tcarry_t    >                 SHIFTER_CARRY     [param._nb_port];
+  sc_signal <Tcontrol_t  >                 SHIFTER_CARRY_IN  [param._nb_port];
+  sc_signal <Tdata_t     >                 SHIFTER_COMPLETION[param._nb_port];
+  sc_signal <Tdata_t     >                 SHIFTER_DATA_OUT  [param._nb_port];
+  
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Shifter" << endl;
+  
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+  (*(_Shifter->in_CLOCK))        (CLOCK);
+#endif
+  for (uint32_t i=0; i<param._nb_port; i++)
+    {
+      (*(_Shifter-> in_SHIFTER_DATA      [i])) (SHIFTER_DATA_IN   [i]);
+      if (param._shift_value == 0)
+      (*(_Shifter-> in_SHIFTER_SHIFT     [i])) (SHIFTER_SHIFT     [i]);
+      if (param._direction   == external_direction)
+      (*(_Shifter-> in_SHIFTER_DIRECTION [i])) (SHIFTER_DIRECTION [i]);
+      if (param._rotate      == external_rotate)
+      (*(_Shifter-> in_SHIFTER_TYPE      [i])) (SHIFTER_TYPE      [i]);
+      if (param._carry       == external_carry)
+      (*(_Shifter-> in_SHIFTER_CARRY     [i])) (SHIFTER_CARRY     [i]);
+      if (param._carry       == external_completion)
+      if (param._type_completion_bool == true)
+      (*(_Shifter-> in_SHIFTER_CARRY_IN  [i])) (SHIFTER_CARRY_IN  [i]);
+      else
+      (*(_Shifter-> in_SHIFTER_COMPLETION[i])) (SHIFTER_COMPLETION[i]);
+      (*(_Shifter->out_SHIFTER_DATA      [i])) (SHIFTER_DATA_OUT  [i]);
+    }
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  // Initialisation
+
+  srand (0);
+  //srand (time(NULL));
+  
+  const uint32_t iteration        = NB_ITERATION;
+
+  Tdirection_t   direction       ;
+  Ttype_t        type            ;
+  Tcarry_t       carry           ; 
+  const Tdata_t  data_max        = (1<<param._size_data);
+  Tdata_t        data_in         [param._nb_port];
+  Tdata_t        data_completion [param._nb_port];
+  Tshift_t       shift_min       ;
+  Tshift_t       shift_max       ;
+  Tdata_t        data_out        [param._nb_port];
+  string         op              ;
+
+  if (param._shift_value != 0)
+    {
+      shift_min = param._shift_value;
+      shift_max = param._shift_value;
+    }
+  else
+    {
+      shift_min = 0;
+      shift_max = param._size_data-1;
+    }
+
+  sc_start(0);
+  
+  for (uint32_t x=0; x<6; x++)
+    {
+      switch (x)
+	{
+	case 0 :
+	  if (param._have_shift_logic_left)
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} Test    Shift   Left  Logic" << endl;
+	      direction = _left ;
+	      type      = _shift;
+	      carry     = _logic;
+	      op        = " sll " ;	
+	      break;
+	    }
+	  else
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} No Test Shift   Left  Logic" << endl;
+	      continue;
+	    }
+	case 1 :
+	  if (param._have_shift_logic_right)
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} Test    Shift   Right Logic" << endl;
+	      direction = _right;
+	      type      = _shift;
+	      carry     = _logic;
+	      op        = " srl " ;
+	      break;
+	    }
+	  else
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} No Test Shift   Right Logic" << endl;
+	      continue;
+	    }
+	case 2 :
+	  if (param._have_shift_arithmetic_left)
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} Test    Shift   Left  Arithmetic" << endl;
+	      direction = _left      ;
+	      type      = _shift     ;
+	      carry     = _arithmetic;
+	      op        = " sla "    ;
+	      break;
+	    }
+	  else
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} No Test Shift   Left  Arithmetic" << endl;
+	      continue;
+	    }
+	case 3 :
+	  if (param._have_shift_arithmetic_right)
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} Test    Shift   Right Arithmetic" << endl;
+	      direction = _right;
+	      type      = _shift;
+	      carry     = _arithmetic;
+	      op        = " sra "    ;
+	      break;
+	    }
+	  else
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} No Test Shift   Right Arithmetic" << endl;
+	      continue;
+	    }
+	case 4 :
+	  if ( param._have_rotate_left)
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} Test    Rotate  Left" << endl;
+	      direction = _left  ;
+	      type      = _rotate;
+	      carry     = _logic ; 
+	      op        = " rol "; 
+	      break;
+	    }
+	  else
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} No Test Rotate  Left" << endl;
+	      continue;
+	    }
+	case 5 :
+	  if (param._have_rotate_right)
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} Test    Rotate  Right" << endl;
+	      direction = _right;
+	      type      = _rotate;
+	      carry     = _logic ; 
+	      op        = " ror "; 
+	      break;
+	    }
+	  else
+	    {
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} No Test Rotate  Right" << endl;
+	      continue;
+	    }
+	default : 
+	  continue;
+	}
+
+      for (uint32_t i=0; i<param._nb_port; i++)
+	{
+	  SHIFTER_DIRECTION [i].write(direction );
+	  SHIFTER_TYPE      [i].write(type      ); 
+	  SHIFTER_CARRY     [i].write(carry     );
+	}
+
+      for (uint32_t it=0; it < iteration; it++)
+	{
+	  for (Tshift_t shift=shift_min; shift<=shift_max; shift++)
+	    {
+	      Tdata_t mask_left  = 0;
+	      Tdata_t mask_right = 0;
+	      
+	      if (param._size_data_completion > 0)
+		{
+		  mask_left  = gen_mask<Tdata_t> (shift);
+		  mask_right = mask_left << (param._size_data - shift);
+		}
+	      
+	      for (uint32_t i=0; i<param._nb_port; i++)
+		{
+		  data_in         [i] = rand() % data_max;
+		  data_completion [i] = (rand() % data_max) & gen_mask<Tdata_t>(param._size_data_completion); 
+
+		  switch (x)
+		    {
+		    case 0  : data_out [i] =((shift_logic_left       <Tdata_t>(param._size_data, data_in[i], shift) & ~mask_left ) | (data_completion [i] & mask_left )); break;
+		    case 1  : data_out [i] =((shift_logic_right      <Tdata_t>(param._size_data, data_in[i], shift) & ~mask_right) | (data_completion [i] & mask_right)); break;
+		    case 2  : data_out [i] = shift_arithmetic_left  <Tdata_t>(param._size_data, data_in[i], shift); break;
+		    case 3  : data_out [i] = shift_arithmetic_right <Tdata_t>(param._size_data, data_in[i], shift); break;
+		    case 4  : data_out [i] = rotate_left            <Tdata_t>(param._size_data, data_in[i], shift); break;
+		    case 5  : data_out [i] = rotate_right           <Tdata_t>(param._size_data, data_in[i], shift); break;
+		    default : break;
+		  }
+		  SHIFTER_DATA_IN   [i].write(data_in         [i]);
+		  SHIFTER_SHIFT     [i].write(shift              );  
+		  if (param._type_completion_bool == true)
+		    SHIFTER_CARRY_IN  [i].write(data_completion [i]!=0);
+		  else
+		    SHIFTER_COMPLETION[i].write(data_completion [i]);
+		}
+	      
+	      sc_start(0);
+	      
+	      cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "}" << endl;
+	      
+	      for (uint32_t i=0; i<param._nb_port; i++)
+		{
+		  cout << "\t[" << i << "] " 
+		       << hex
+		       << data_in[i] << op
+		       << dec 
+		       << shift      << " = " 
+		       << hex
+		       << SHIFTER_DATA_OUT [i].read()
+		       << " - completion : "
+		       << data_completion [i]
+		       << dec ;
+		  
+		  TEST(Tdata_t,SHIFTER_DATA_OUT [i].read(),data_out[i]);
+		}
+	      sc_start(1);
+	    }
+	}
+    }
+  
+  sc_start(0);
+  
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete _Shifter;
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Parameters.h	(revision 3)
@@ -0,0 +1,107 @@
+#ifndef morpheo_behavioural_generic_shifter_Parameters_h
+#define morpheo_behavioural_generic_shifter_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Parameters.h"
+#include "Behavioural/Generic/Shifter/include/Types.h"
+#include <math.h>
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+    //-----[ fields ]------------------------------------------------------------
+  public : const uint32_t    _size_data           ;
+  public : const uint32_t    _nb_port             ;
+  public : const uint32_t    _shift_value         ; // 0 = external shifter's value 
+  public : const rotate_t    _rotate              ;
+  public : const direction_t _direction           ;
+  public : const carry_t     _carry               ;
+  public : const uint32_t    _size_data_completion;
+  public : const bool        _type_completion_bool;
+
+  public : const bool        _internal_direction;
+  public : const bool        _internal_type     ;
+  public : const bool        _internal_carry    ;
+
+  public : const bool        _have_shift_logic_left        ;
+  public : const bool        _have_shift_logic_right       ;
+  public : const bool        _have_shift_logic             ;
+  public : const bool        _have_shift_arithmetic_left   ;
+  public : const bool        _have_shift_arithmetic_right  ;
+  public : const bool        _have_shift_arithmetic        ;
+  public : const bool        _have_shift                   ;
+  public : const bool        _have_rotate_left             ;
+  public : const bool        _have_rotate_right            ;
+  public : const bool        _have_rotate                  ;
+    
+  public : const bool        _have_direction_left          ;
+  public : const bool        _have_direction_right         ;
+
+    string toString_rotate    (rotate_t x)
+    {
+      switch (x)
+	{
+	case without_rotate            : return "without_rotate" ;
+	case internal_rotate           : return "internal_rotate";
+	case external_rotate           : return "external_rotate";     
+	default                        : return "";
+	}
+    };
+    
+    string toString_direction (direction_t x) 
+    {
+      switch (x)
+	{
+	case internal_right_shift      : return "internal_right_shift";
+	case internal_left_shift       : return "internal_left_shift" ;
+	case external_direction        : return "external_direction"  ;
+	default                        : return "";
+	}
+    };
+    
+    string toString_carry (carry_t x)
+    {
+      switch (x)
+	{
+	case internal_logic            : return "internal_logic"       ;
+	case internal_arithmetic       : return "internal_arithmetic"  ;
+	case external_carry            : return "external_carry"       ;
+	case external_completion       : return "external_completion"  ;
+	default                        : return "";
+	}
+    };
+    
+    //-----[ methods ]-----------------------------------------------------------
+  public : Parameters  (uint32_t    size_data           ,
+			uint32_t    nb_port             ,
+			uint32_t    shift_value         ,
+			rotate_t    rotate              ,
+			direction_t direction           ,
+			carry_t     carry               ,
+			bool        type_completion_bool = false);
+  public : Parameters  (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::generic::shifter::Parameters & x);
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Shifter.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Shifter.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Shifter.h	(revision 3)
@@ -0,0 +1,128 @@
+#ifndef morpheo_behavioural_generic_shifter_Shifter_h
+#define morpheo_behavioural_generic_shifter_Shifter_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <iostream>
+#include "Include/ToString.h"
+
+#include "Behavioural/Generic/Shifter/include/Parameters.h"
+#include "Behavioural/Generic/Shifter/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/Generic/Shifter/include/Statistics.h"
+#endif
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#ifdef VHDL_TESTBENCH
+#include "Behavioural/include/Vhdl_Testbench.h"
+#endif
+
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  class Shifter 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string     _name;
+
+  protected : const Parameters _param;
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+#endif
+
+#ifdef VHDL_TESTBENCH
+  private   : Vhdl_Testbench                 * _vhdl_testbench;
+#endif
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_CLOCK                      *  in_CLOCK             ;
+    // Interface "shifter"
+  public    : SC_IN (Tdata_t)              **  in_SHIFTER_DATA      ;
+  public    : SC_IN (Tshift_t)             **  in_SHIFTER_SHIFT     ;
+  public    : SC_IN (Tdirection_t)         **  in_SHIFTER_DIRECTION ;
+  public    : SC_IN (Ttype_t)              **  in_SHIFTER_TYPE      ;
+  public    : SC_IN (Tcarry_t)             **  in_SHIFTER_CARRY     ;
+  public    : SC_IN (Tcontrol_t)           **  in_SHIFTER_CARRY_IN  ; // Completion == type bool
+  public    : SC_IN (Tdata_t)              **  in_SHIFTER_COMPLETION; // Completion != type bool
+  public    : SC_OUT(Tdata_t)              ** out_SHIFTER_DATA      ;
+    
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#endif
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (Shifter);
+#endif
+
+  public  :          Shifter              (
+#ifdef SYSTEMC
+					   sc_module_name                              name,
+#else					       
+					   string                                      name,
+#endif					       
+#ifdef STATISTICS
+					   morpheo::behavioural::Parameters_Statistics param_statistics,
+#endif
+					   Parameters                                  param );
+    
+  public  :          Shifter              (Parameters param );
+  public  :          ~Shifter             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+  public  : void     transition                (void);
+#endif
+  public  : void     genMealy_shift            (void);
+#endif					       
+					       
+#if VHDL				       
+  public  : void     vhdl                      (void);
+  private : void     vhdl_port                 (Vhdl & vhdl);
+  private : void     vhdl_declaration          (Vhdl & vhdl);
+  private : void     vhdl_body                 (Vhdl & vhdl);
+#endif					       
+#ifdef STATISTICS
+  public  : string   statistics                (uint32_t depth);
+#endif
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench            (Vhdl_Testbench & vhdl_testbench);
+  private : void     vhdl_testbench_port       (Vhdl_Testbench & vhdl_testbench);
+  private : void     vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench);
+#endif
+
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Statistics.h	(revision 3)
@@ -0,0 +1,54 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_generic_shifter_Statistics_h
+#define morpheo_behavioural_generic_shifter_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+//#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/Generic/Shifter/include/Parameters.h"
+
+//using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                   _parameters;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics  (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  );
+//public   : Statistics  (Statistics & stat);
+  public   : ~Statistics () ;
+    
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : void     add        ();
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Types.h	(revision 3)
@@ -0,0 +1,54 @@
+#ifdef SYSTEMC
+#ifndef morpheo_behavioural_generic_shifter_Type_h
+#define morpheo_behavioural_generic_shifter_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Types.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+  typedef enum { without_rotate      ,
+		 internal_rotate     ,
+		 external_rotate     } rotate_t;
+
+  typedef enum { internal_right_shift,
+		 internal_left_shift ,
+		 external_direction  } direction_t;
+
+  typedef enum { internal_logic      ,
+		 internal_arithmetic ,
+		 external_carry      ,
+		 external_completion } carry_t;       
+
+  typedef uint32_t     Tdata_t     ;
+  typedef uint32_t     Tshift_t    ;
+  typedef bool         Tdirection_t;
+  typedef bool         Ttype_t     ;
+  typedef bool         Tcarry_t    ;
+
+  // A lot of constant
+  const   Tdirection_t _right      = false;
+  const   Tdirection_t _left       = true ;
+
+  const   Ttype_t      _shift      = false;
+  const   Ttype_t      _rotate     = true ;
+
+  const   Tcarry_t     _logic      = false;
+  const   Tcarry_t     _arithmetic = true ;
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,120 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Parameters.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  Parameters::Parameters  (uint32_t    size_data           ,
+			   uint32_t    nb_port             ,
+			   uint32_t    shift_value         ,
+			   rotate_t    rotate              ,
+			   direction_t direction           ,
+			   carry_t     carry               ,
+			   bool        type_completion_bool):
+    _size_data                     (size_data     ),
+    _nb_port                       (nb_port       ),
+    _shift_value                   (shift_value   ),
+    _rotate                        (rotate        ),
+    _direction                     (direction     ),
+    _carry                         (carry         ),
+    _size_data_completion          ((carry != external_completion)?0:((_shift_value==0)?size_data:_shift_value)),
+    _type_completion_bool          (type_completion_bool),
+
+    _internal_direction            ((direction == internal_right_shift)?_right :_left      ),
+    _internal_type                 ((rotate    == internal_rotate     )?_rotate:_shift     ),
+    _internal_carry                ((carry     == internal_logic      )?_logic :_arithmetic),
+
+    _have_shift_logic_left         ((rotate != internal_rotate)         &&
+				    (((carry     == external_carry     ) ||
+				      (carry     == external_completion) ||
+				      (carry     == internal_logic     )) && 
+				    ((direction == external_direction ) ||
+				     (direction == internal_left_shift)))),
+    _have_shift_logic_right        ((rotate != internal_rotate)         &&
+				    (((carry     == external_carry     ) ||
+				      (carry     == external_completion) ||
+				      (carry     == internal_logic     )) && 
+				    ((direction == external_direction ) ||
+				     (direction == internal_right_shift)))),
+    _have_shift_logic              (_have_shift_logic_left || _have_shift_logic_right),
+
+    _have_shift_arithmetic_left    ((rotate != internal_rotate)         &&
+				    (((carry    == external_carry     ) ||
+				      (carry    == internal_arithmetic )) && 
+				    ((direction == external_direction ) ||
+				     (direction == internal_left_shift)))),
+    _have_shift_arithmetic_right   ((rotate != internal_rotate)         &&
+				    (((carry     == external_carry     ) ||
+				      (carry     == internal_arithmetic     )) && 
+				     ((direction == external_direction ) ||
+				      (direction == internal_right_shift)))),
+    _have_shift_arithmetic         (_have_shift_arithmetic_left || _have_shift_arithmetic_right),
+
+    _have_shift                    (_have_shift_logic || _have_shift_arithmetic),
+
+    _have_rotate_left              ((rotate != without_rotate)         &&
+				    ((direction == external_direction ) ||
+				     (direction == internal_left_shift))),
+    _have_rotate_right             ((rotate != without_rotate)         &&
+				    ((direction == external_direction ) || 
+				     (direction == internal_right_shift))),
+    _have_rotate                   ( _have_rotate_left || _have_rotate_right),
+
+    _have_direction_left           (_have_shift_logic_left       ||
+				    _have_shift_arithmetic_left  ||
+				    _have_rotate_left            ),
+    _have_direction_right          (_have_shift_logic_right      ||
+				    _have_shift_arithmetic_right ||
+				    _have_rotate_right           )
+  {
+    test();
+  };
+  
+  Parameters::Parameters (Parameters & param):
+    _size_data                   (param._size_data                   ),
+    _nb_port                     (param._nb_port                     ),
+    _shift_value                 (param._shift_value                 ),
+    _rotate                      (param._rotate                      ),
+    _direction                   (param._direction                   ),
+    _carry                       (param._carry                       ),
+    _size_data_completion        (param._size_data_completion        ),
+    _type_completion_bool        (param._type_completion_bool        ),
+
+    _internal_direction          (param._internal_direction          ),
+    _internal_type               (param._internal_type               ),
+    _internal_carry              (param._internal_carry              ),
+    
+    _have_shift_logic_left       (param._have_shift_logic_left       ),
+    _have_shift_logic_right      (param._have_shift_logic_right      ),
+    _have_shift_logic            (param._have_shift_logic            ),
+    _have_shift_arithmetic_left  (param._have_shift_arithmetic_left  ),
+    _have_shift_arithmetic_right (param._have_shift_arithmetic_right ),
+    _have_shift_arithmetic       (param._have_shift_arithmetic       ),
+    _have_shift                  (param._have_shift                  ),
+    _have_rotate_left            (param._have_rotate_left            ),
+    _have_rotate_right           (param._have_rotate_right           ),
+    _have_rotate                 (param._have_rotate                 ),
+
+    _have_direction_left         (param._have_direction_left         ),
+    _have_direction_right        (param._have_direction_right        )
+
+  {
+    test();
+  };
+
+  Parameters::~Parameters () 
+  { };
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters_msg_error.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters_msg_error.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters_msg_error.cpp	(revision 3)
@@ -0,0 +1,60 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Parameters.h"
+#include "Behavioural/Generic/Shifter/include/Types.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+  string Parameters::msg_error(void)
+  {
+    string msg = "";
+
+    if (_size_data < 2)
+      {
+        msg += "  - size_data must be > 1\n";
+        msg += "    * size_data                       : " + toString(_size_data) + "\n";
+      }
+
+    if (is_positive(_nb_port) == false)
+      {
+        msg += "  - nb_port must be > 0\n";
+        msg += "    * nb_port                         : " + toString(_nb_port) + "\n";
+      }
+
+    if (_shift_value > _size_data) 
+      {
+	msg += "  - shift_value must be < size_data\n";	
+        msg += "    * shift_value                     : " + toString(_shift_value) + "\n";
+        msg += "    * size_data                       : " + toString(_size_data)   + "\n";
+      }    
+
+    if ( (_rotate == internal_rotate) && (_carry != internal_logic))
+      {
+	msg += "  - Incompatible parameters : internal_rotate have never carry (must be set at \"internal_logic\"\n";
+        msg += "    * rotate                          : " + toString_rotate(_rotate) + "\n";
+        msg += "    * carry                           : " + toString_carry (_carry ) + "\n";
+      }    
+
+    if (_type_completion_bool && (_size_data_completion != 1))
+      {
+	msg += "  - Incompatible parameters : you can't have the type of port in_SHIFTER_COMPLETION at bool. Because, This port must be more bits\n";
+	msg += "    * size_data_completion            : " + toString (_size_data_completion) + "\n";
+      }
+      
+    return msg;
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters_print.cpp	(revision 3)
@@ -0,0 +1,47 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Parameters.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  string Parameters::print (uint32_t depth)
+  {
+    string tab = string(depth,'\t');
+    ostringstream msg;
+    msg << tab << "<shifter>" << endl
+	<< tab << "\t<size_data   value=\"" << _size_data   << "\" />" << endl
+	<< tab << "\t<nb_port     value=\"" << _nb_port     << "\" />" << endl
+	<< tab << "\t<shift_value value=\"" << _shift_value << "\" />" << endl
+	<< tab << "\t<rotate      value=\"" << toString_rotate    (_rotate   ) << "\" />" << endl
+	<< tab << "\t<direction   value=\"" << toString_direction (_direction) << "\" />" << endl
+	<< tab << "\t<carry       value=\"" << toString_carry     (_carry    ) << "\" />" << endl
+	<< tab << "\t<!-- port_completion is type bool : " << toString(_type_completion_bool) << " -->" << endl
+      	<< tab << "</shifter>" << endl;
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::generic::shifter::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter.cpp	(revision 3)
@@ -0,0 +1,126 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+#ifdef SYSTEMC
+  Shifter::Shifter (sc_module_name name,
+#else
+  Shifter::Shifter (string name,
+#endif
+#ifdef STATISTICS
+		    morpheo::behavioural::Parameters_Statistics             param_statistics,
+#endif
+		    morpheo::behavioural::generic::shifter::Parameters param ):
+		    _name   (name)
+		    ,_param (param)
+  {
+#ifdef STATISTICS
+    // Allocation of statistics
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // Creation of a testbench
+    //  -> port
+    //  -> clock's signals
+    _vhdl_testbench = new Vhdl_Testbench (_name);
+    vhdl_testbench_port           (*_vhdl_testbench);
+    _vhdl_testbench->set_clock    ("in_CLOCK",false);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    allocation ();
+
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+#endif
+
+    SC_METHOD (genMealy_shift);
+    dont_initialize ();
+    sensitive_neg << *(in_CLOCK);
+    for (uint32_t i=0; i<param._nb_port; i++)
+      {
+	sensitive << (*(in_SHIFTER_DATA      [i]));
+	if (param._shift_value == 0)
+	sensitive << (*(in_SHIFTER_SHIFT     [i]));
+	if (param._direction   == external_direction)
+	sensitive << (*(in_SHIFTER_DIRECTION [i]));
+	if (_param._rotate     == external_rotate)
+	sensitive << (*(in_SHIFTER_TYPE      [i]));
+	if (param._carry       == external_carry)
+	sensitive << (*(in_SHIFTER_CARRY     [i]));
+	if (param._carry       == external_completion)
+	  if (_param._type_completion_bool == true)
+	    sensitive << (*(in_SHIFTER_CARRY_IN  [i]));
+	  else
+	    sensitive << (*(in_SHIFTER_COMPLETION[i]));
+      }
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+    for (uint32_t i=0; i<param._nb_port; i++)
+      {
+	(*(out_SHIFTER_DATA [i])) (*(in_SHIFTER_DATA      [i]));
+	if (param._shift_value == 0)
+	(*(out_SHIFTER_DATA [i])) (*(in_SHIFTER_SHIFT     [i]));
+	if (param._direction   == external_direction)
+	(*(out_SHIFTER_DATA [i])) (*(in_SHIFTER_DIRECTION [i]));
+	if (_param._rotate     == external_rotate)
+	(*(out_SHIFTER_DATA [i])) (*(in_SHIFTER_TYPE      [i]));
+	if (param._carry       == external_carry)
+	(*(out_SHIFTER_DATA [i])) (*(in_SHIFTER_CARRY     [i]));
+	if (param._carry       == external_completion)
+	if (_param._type_completion_bool == true)
+	(*(out_SHIFTER_DATA [i])) (*(in_SHIFTER_CARRY_IN  [i]));
+	else
+	(*(out_SHIFTER_DATA [i])) (*(in_SHIFTER_COMPLETION[i]));
+      }
+#endif    
+
+#endif
+  };
+  
+  Shifter::~Shifter (void)
+  {
+#ifdef SYSTEMC
+    deallocation ();
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // generate the test bench
+    _vhdl_testbench->generate_file();
+    delete _vhdl_testbench;
+#endif
+
+#ifdef STATISTICS
+    _stat->generate_file(statistics(0));
+    
+    delete _stat;
+#endif
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp	(revision 3)
@@ -0,0 +1,88 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Shifter::allocation (void)
+  {
+    string rename;
+
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+     in_CLOCK           = new SC_CLOCK ("SC_CLOCK");
+#endif
+    // Interface "shifter"
+     in_SHIFTER_DATA      = new SC_IN (Tdata_t)      * [_param._nb_port];
+    if (_param._shift_value == 0)
+     in_SHIFTER_SHIFT     = new SC_IN (Tshift_t)     * [_param._nb_port];
+    if (_param._direction   == external_direction)
+     in_SHIFTER_DIRECTION = new SC_IN (Tdirection_t) * [_param._nb_port];
+    if (_param._rotate      == external_rotate)
+     in_SHIFTER_TYPE      = new SC_IN (Ttype_t)      * [_param._nb_port];
+    if (_param._carry       == external_carry)
+     in_SHIFTER_CARRY     = new SC_IN (Tcarry_t)     * [_param._nb_port];
+    if (_param._carry       == external_completion)
+    if (_param._type_completion_bool == true)
+     in_SHIFTER_CARRY_IN  = new SC_IN (Tcontrol_t)   * [_param._nb_port];
+    else
+     in_SHIFTER_COMPLETION= new SC_IN (Tdata_t)      * [_param._nb_port];
+    out_SHIFTER_DATA      = new SC_OUT(Tdata_t)      * [_param._nb_port];
+    
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	rename = "in_SHIFTER_DATA["      + toString(i) + "]";
+	 in_SHIFTER_DATA      [i] = new SC_IN (Tdata_t)      (rename.c_str());
+
+	if (_param._shift_value == 0)
+	  {
+	rename = "in_SHIFTER_SHIFT["     + toString(i) + "]";
+	 in_SHIFTER_SHIFT     [i] = new SC_IN (Tshift_t)     (rename.c_str());
+	  }
+	if (_param._direction == external_direction)
+	  {
+	rename = "in_SHIFTER_DIRECTION[" + toString(i) + "]";
+	 in_SHIFTER_DIRECTION [i] = new SC_IN (Tdirection_t) (rename.c_str());
+	  }
+	if (_param._rotate  == external_rotate)
+	  {
+	rename = "in_SHIFTER_TYPE["      + toString(i) + "]";
+	 in_SHIFTER_TYPE     [i]      = new SC_IN (Ttype_t)  (rename.c_str());
+	  }
+	if (_param._carry == external_carry)
+	  {
+	rename = "in_SHIFTER_CARRY["    + toString(i) + "]";
+	 in_SHIFTER_CARRY    [i] = new SC_IN (Tcarry_t)      (rename.c_str());
+	  }
+
+	if (_param._carry       == external_completion)
+	if (_param._type_completion_bool == true)
+	  {
+	 rename = "in_SHIFTER_CARRY_IN["      + toString(i) + "]";
+	 in_SHIFTER_CARRY_IN   [i] = new SC_IN (Tcontrol_t)  (rename.c_str());	  
+	  }
+	else
+	  {
+	 rename = "in_SHIFTER_COMPLETION["    + toString(i) + "]";
+	 in_SHIFTER_COMPLETION [i] = new SC_IN (Tdata_t)     (rename.c_str());
+	  }
+	
+	rename = "out_SHIFTER_DATA["    + toString(i) + "]";
+	out_SHIFTER_DATA     [i] = new SC_OUT(Tdata_t)       (rename.c_str());
+      }
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp	(revision 3)
@@ -0,0 +1,65 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Shifter::deallocation (void)
+  {
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+    delete in_CLOCK;
+#endif
+
+    // Interface "shifter"
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	delete  in_SHIFTER_DATA      [i];
+	if (_param._shift_value == 0)
+	delete  in_SHIFTER_SHIFT     [i];
+	if (_param._direction   == external_direction)
+	delete  in_SHIFTER_DIRECTION [i];
+	if (_param._rotate      == external_rotate)
+	delete  in_SHIFTER_TYPE      [i];
+	if (_param._carry       == external_carry)
+	delete  in_SHIFTER_CARRY     [i];
+	if (_param._carry       == external_completion)
+	if (_param._type_completion_bool == true)
+	delete  in_SHIFTER_CARRY_IN  [i];	  
+	else
+	delete  in_SHIFTER_COMPLETION[i];
+	delete out_SHIFTER_DATA      [i];
+      }
+
+    delete  in_SHIFTER_DATA      ;
+    if (_param._shift_value == 0)
+    delete  in_SHIFTER_SHIFT     ;
+    if (_param._direction   == external_direction )
+    delete  in_SHIFTER_DIRECTION ;
+    if (_param._rotate      == external_rotate    )
+    delete  in_SHIFTER_TYPE      ;
+    if (_param._carry       == external_carry     )
+    delete  in_SHIFTER_CARRY     ;
+    if (_param._carry       == external_completion)
+      if (_param._type_completion_bool == true)
+	delete  in_SHIFTER_CARRY_IN  ;
+      else
+	delete  in_SHIFTER_COMPLETION;
+    delete out_SHIFTER_DATA      ;
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_genMealy_shift.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_genMealy_shift.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_genMealy_shift.cpp	(revision 3)
@@ -0,0 +1,87 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+#include "Include/BitManipulation.h"
+#include <bitset>
+
+using namespace std;
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+  void Shifter::genMealy_shift (void)
+  {
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	// Read
+	Tdata_t      data_in     = PORT_READ(in_SHIFTER_DATA [i]);
+	Tdata_t      data_out    = data_in;
+	Tshift_t     shift_value = _param._shift_value;
+	if (shift_value == 0)
+	  shift_value = PORT_READ(in_SHIFTER_SHIFT [i]);
+
+ 	Tdirection_t direction; 
+ 	if (_param._direction == external_direction)
+	  direction = PORT_READ(in_SHIFTER_DIRECTION [i]);
+	else
+	  direction = _param._internal_direction;
+
+	Ttype_t      type;
+	if (_param._rotate    == external_rotate)
+	  type      = PORT_READ(in_SHIFTER_TYPE      [i]);
+	else
+	  type      = _param._internal_type; 
+
+	Tcarry_t     carry;	
+	if (_param._carry     == external_carry)
+	  carry     = PORT_READ(in_SHIFTER_CARRY     [i]);
+	else
+	  carry     = _param._internal_carry; 
+	
+	if (type == _shift)
+	  {
+	    data_out = shift  <Tdata_t> (_param._size_data, data_in, shift_value, direction == _left, carry == _arithmetic);
+
+	    if (_param._size_data_completion > 0)
+	      {
+		Tdata_t completion;
+
+		if (_param._type_completion_bool == true)
+		  completion = (PORT_READ(in_SHIFTER_CARRY_IN   [i])==true)?1:0;
+		else
+		  completion = PORT_READ(in_SHIFTER_COMPLETION [i]);
+
+		Tdata_t mask       ;
+
+		if (direction == _left)
+		  {
+		    mask       = gen_mask<Tdata_t> (shift_value);
+		  }
+		else
+		  {
+		    mask       = gen_mask<Tdata_t> (shift_value)      << (_param._size_data-shift_value);
+		  }
+		  
+		data_out = (data_out & ~mask) | (completion & mask);
+	      }
+	  }
+	else
+	  data_out = rotate <Tdata_t> (_param._size_data, data_in, shift_value, direction == _left);
+
+	// Write
+	PORT_WRITE(out_SHIFTER_DATA [i], data_out);
+      }
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_statistics.cpp	(revision 3)
@@ -0,0 +1,27 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  string Shifter::statistics (uint32_t depth)
+  {
+    return _stat->print(depth);
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_transition.cpp	(revision 3)
@@ -0,0 +1,34 @@
+#ifdef SYSTEMC
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Shifter::transition (void)
+  {
+#ifdef STATISTICS
+    _stat->add();
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition (*_vhdl_testbench);
+#endif
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl.cpp	(revision 3)
@@ -0,0 +1,36 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Shifter::vhdl (void)
+  {
+    Vhdl vhdl (_name);
+
+    vhdl.set_library_work (_name + "_Pack");
+
+    vhdl_port        (vhdl);
+    vhdl_declaration (vhdl);
+    vhdl_body        (vhdl);
+
+    vhdl.generate_file();
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_body.cpp	(revision 3)
@@ -0,0 +1,322 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Shifter::vhdl_body (Vhdl & vhdl)
+  {
+    //uint32_t log2_size_data = static_cast<uint32_t>(ceil(log2(_param._size_data)));
+
+    vhdl.set_body ("-- Compute all case of shift");
+
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	//-----[ Shift logic Left ]--------------------------------------------
+	if (_param._have_shift_logic_left)
+	  vhdl.set_body ("shift_logic_left_"+toString(i)+"        <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") sll CONV_INTEGER(shift_"+toString(i)+"));");
+	//-----[ Shift logic Right ]-------------------------------------------
+	if (_param._have_shift_logic_right)
+	  vhdl.set_body ("shift_logic_right_"+toString(i)+"       <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") srl CONV_INTEGER(shift_"+toString(i)+"));");
+	//-----[ Shift arithmetic Left ]---------------------------------------
+	if (_param._have_shift_arithmetic_left)
+	  vhdl.set_body ("shift_arithmetic_left_"+toString(i)+"   <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") sla CONV_INTEGER(shift_"+toString(i)+"));");
+	//-----[ Shift arithmetic Right ]--------------------------------------
+	if (_param._have_shift_arithmetic_right)
+	  vhdl.set_body ("shift_arithmetic_right_"+toString(i)+"  <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") sra CONV_INTEGER(shift_"+toString(i)+"));");
+	//-----[ Rotate Left ]-------------------------------------------------
+	if (_param._have_rotate_left)
+	  vhdl.set_body ("rotate_left_"+toString(i)+"             <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") rol CONV_INTEGER(shift_"+toString(i)+"));");
+	//-----[ Rotate Right ]------------------------------------------------
+	if (_param._have_rotate_right)
+	  vhdl.set_body ("rotate_right_"+toString(i)+"            <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") ror CONV_INTEGER(shift_"+toString(i)+"));");
+      }
+
+    if (_param._size_data_completion > 0)
+      {
+	vhdl.set_body ("");
+	vhdl.set_body ("-- Mask");
+
+	for (uint32_t i=0; i<_param._nb_port; i++)
+	  {
+	    string print_shifter_completion;
+	    
+	    if (_param._type_completion_bool == true)
+	      print_shifter_completion = "in_SHIFTER_CARRY_IN";
+	    else
+	      print_shifter_completion = "in_SHIFTER_COMPLETION";
+
+	    if (_param._size_data == _param._size_data_completion)
+	      {
+		vhdl.set_body ("shifter_completion_left_"+toString(i)+"  <= "+print_shifter_completion+"_"+toString(i)+";");
+		vhdl.set_body ("shifter_completion_right_"+toString(i)+" <= "+print_shifter_completion+"_"+toString(i)+";");
+	      }
+	    else
+	      {
+		vhdl.set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data_completion)+"  <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";");
+		vhdl.set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data_completion                    )+"  <= "+print_shifter_completion+"_"+toString(i)+";");
+
+		vhdl.set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data-_param._size_data_completion)+" <= "+print_shifter_completion+"_"+toString(i)+";");
+		vhdl.set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-_param._size_data_completion                    )+" <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";");
+	      }
+	    
+ 	    vhdl.set_body ("mask_completion_left_"+toString(i)+"     <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) sll CONV_INTEGER(shift_"+toString(i)+"));");
+ 	    vhdl.set_body ("mask_completion_right_"+toString(i)+"    <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) srl CONV_INTEGER(shift_"+toString(i)+"));");
+	  }
+      }
+	      
+
+    vhdl.set_body ("");
+    vhdl.set_body ("-- Multiplexor");
+
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	vhdl.set_body ("out_SHIFTER_DATA_"+toString(i)+"       <=");
+	string print_else = "    ";
+
+	//-----[ Shift arithmetic Left ]---------------------------------------
+	if (_param._have_shift_arithmetic_left)
+	  {
+	    bool   have_when  = false;
+	    string print_when = "";
+	    string print_and  = "";
+	    
+	    if (_param._direction   == external_direction)
+	      {
+		have_when = true;
+		print_when += " in_SHIFTER_DIRECTION_"+toString(i)+" = cst_is_direction_left ";
+		print_and = " and ";
+	      }
+	    if (_param._rotate      == external_rotate)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_TYPE_"+toString(i)+" = cst_is_type_shift ";
+		print_and = " and ";
+	      }
+	    if (_param._carry       == external_carry)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_CARRY_"+toString(i)+" = cst_is_carry_arithmetic";
+	      }
+
+	    if (have_when)
+	      print_when = "when " + print_when;
+
+	    vhdl.set_body ("\t"+print_else+" shift_arithmetic_left_"+toString(i)+"   "+print_when);
+	    print_else = "else";
+	  }
+	//-----[ Shift arithmetic Right ]--------------------------------------
+	if (_param._have_shift_arithmetic_right)
+	  {
+	    bool   have_when  = false;
+	    string print_when = "";
+	    string print_and  = "";
+	    
+	    if (_param._direction   == external_direction)
+	      {
+		have_when = true;
+		print_when += " in_SHIFTER_DIRECTION_"+toString(i)+" = cst_is_direction_right";
+		print_and = " and ";
+	      }
+	    if (_param._rotate      == external_rotate)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_TYPE_"+toString(i)+" = cst_is_type_shift ";
+		print_and = " and ";
+	      }
+	    if (_param._carry       == external_carry)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_CARRY_"+toString(i)+" = cst_is_carry_arithmetic";
+	      }
+
+	    if (have_when)
+	      print_when = "when " + print_when;
+
+	    vhdl.set_body ("\t"+print_else+" shift_arithmetic_right_"+toString(i)+"  "+print_when);
+	    print_else = "else";
+	  }
+	//-----[ Shift logic Left ]--------------------------------------------
+	if (_param._have_shift_logic_left)
+	  {
+	    bool   have_when  = false;
+	    string print_when = "";
+	    string print_and  = "";
+	    
+	    if (_param._direction   == external_direction)
+	      {
+		have_when = true;
+		print_when += " in_SHIFTER_DIRECTION_"+toString(i)+" = cst_is_direction_left ";
+		print_and = " and ";
+	      }
+	    if (_param._rotate      == external_rotate)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_TYPE_"+toString(i)+" = cst_is_type_shift ";
+		print_and = " and ";
+	      }
+	    if (_param._carry       == external_carry)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_CARRY_"+toString(i)+" = cst_is_carry_logic     ";
+	      }
+
+	    if (have_when)
+	      print_when = "when " + print_when;
+
+	    string print_expr_completion;
+
+	    if (_param._size_data_completion == 0)
+	      print_expr_completion = "shift_logic_left_"+toString(i)+" ";
+	    else
+	      print_expr_completion = "(shift_logic_left_"+toString(i)+"  and mask_completion_left_"+toString(i)+" ) or ( shifter_completion_left_"+toString(i)+"  and not mask_completion_left_"+toString(i)+" )";
+
+	    vhdl.set_body ("\t"+print_else+" "+print_expr_completion+"        "+print_when);
+	    print_else = "else";
+	  }
+	//-----[ Shift logic Right ]-------------------------------------------
+	if (_param._have_shift_logic_right)
+	  {
+	    bool   have_when  = false;
+	    string print_when = "";
+	    string print_and  = "";
+	    
+	    if (_param._direction   == external_direction)
+	      {
+		have_when = true;
+		print_when += " in_SHIFTER_DIRECTION_"+toString(i)+" = cst_is_direction_right";
+		print_and = " and ";
+	      }
+	    if (_param._rotate      == external_rotate)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_TYPE_"+toString(i)+" = cst_is_type_shift ";
+		print_and = " and ";
+	      }
+	    if (_param._carry       == external_carry)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_CARRY_"+toString(i)+" = cst_is_carry_logic     ";
+	      }
+
+	    if (have_when)
+	      print_when = "when " + print_when;
+
+	    string print_expr_completion;
+
+	    if (_param._size_data_completion == 0)
+	      print_expr_completion = "shift_logic_right_"+toString(i);
+	    else
+	      print_expr_completion = "(shift_logic_right_"+toString(i)+" and mask_completion_right_"+toString(i)+") or ( shifter_completion_right_"+toString(i)+" and not mask_completion_right_"+toString(i)+")";
+
+	    vhdl.set_body ("\t"+print_else+" "+print_expr_completion+"        "+print_when);
+	    print_else = "else";
+	  }
+	//-----[ Rotate Left ]-------------------------------------------------
+	if (_param._have_rotate_left)
+	  {
+	    bool   have_when  = false;
+	    string print_when = "";
+	    string print_and  = "";
+	    
+	    if (_param._direction   == external_direction)
+	      {
+		have_when = true;
+		print_when += " in_SHIFTER_DIRECTION_"+toString(i)+" = cst_is_direction_left ";
+		print_and = " and ";
+	      }
+	    if (_param._rotate      == external_rotate)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_TYPE_"+toString(i)+" = cst_is_type_rotate";
+		print_and = " and ";
+	      }
+
+	    if (have_when)
+	      print_when = "when " + print_when;
+
+	    vhdl.set_body ("\t"+print_else+" rotate_left_"+toString(i)+"             "+print_when);
+	    print_else = "else";
+	  }
+	//-----[ Rotate Right ]------------------------------------------------
+	if (_param._have_rotate_right)
+	  {
+	    bool   have_when  = false;
+	    string print_when = "";
+	    string print_and  = "";
+	    
+	    if (_param._direction   == external_direction)
+	      {
+		have_when = true;
+		print_when += " in_SHIFTER_DIRECTION_"+toString(i)+" = cst_is_direction_right";
+		print_and = " and ";
+	      }
+	    if (_param._rotate      == external_rotate)
+	      {
+		have_when = true;
+		print_when += print_and+" in_SHIFTER_TYPE_"+toString(i)+" = cst_is_type_rotate";
+		print_and = " and ";
+	      }
+
+	    if (have_when)
+	      print_when = "when " + print_when;
+
+	    vhdl.set_body ("\t"+print_else+" rotate_right_"+toString(i)+"            "+print_when);
+	    print_else = "else";
+	  }
+	vhdl.set_body (";");
+      }
+    
+  };
+  /*
+  //-----[ Shift logic Left ]--------------------------------------------
+  if (_param._have_shift_logic_left)
+    {
+
+    }
+
+  //-----[ Shift logic Right ]-------------------------------------------
+  if (_param._have_shift_logic_right)
+    {
+      
+    }
+
+  //-----[ Shift arithmetic Left ]---------------------------------------
+  if (_param._have_shift_arithmetic_left)
+    {
+
+    }
+
+  //-----[ Shift arithmetic Right ]--------------------------------------
+  if (_param._have_shift_arithmetic_right)
+    {
+      
+    }
+  
+  //-----[ Rotate Left ]-------------------------------------------------
+  if (_param._have_rotate_left)
+    {
+      
+    }
+  
+  //-----[ Rotate Right ]------------------------------------------------
+  if (_param._have_rotate_right)
+    {
+      
+    }
+  */
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_declaration.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_declaration.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_declaration.cpp	(revision 3)
@@ -0,0 +1,74 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Shifter::vhdl_declaration (Vhdl & vhdl)
+  {
+    uint32_t log2_size_data = static_cast<uint32_t>(ceil(log2(_param._size_data)));
+
+    vhdl.set_constant("cst_is_direction_left  ",1,_left      );
+    vhdl.set_constant("cst_is_direction_right ",1,_right     );
+    vhdl.set_constant("cst_is_type_shift      ",1,_shift     );
+    vhdl.set_constant("cst_is_type_rotate     ",1,_rotate    );
+    vhdl.set_constant("cst_is_carry_arithmetic",1,_arithmetic);
+    vhdl.set_constant("cst_is_carry_logic     ",1,_logic     );
+    vhdl.set_constant("cst_completion         ",_param._size_data,"(others => '1')");
+    
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	if (_param._shift_value != 0)
+	  vhdl.set_constant("shift_"+toString(i),log2_size_data, _param._shift_value);
+	else
+	  vhdl.set_alias   ("shift_"+toString(i),std_logic(log2_size_data), "in_SHIFTER_SHIFT_"+toString(i),std_logic_range(log2_size_data));
+	
+	if (_param._size_data_completion > 0)
+	  {
+	    vhdl.set_signal ("shifter_completion_left_"+toString(i)+" ",_param._size_data);
+	    vhdl.set_signal ("shifter_completion_right_"+toString(i)+"",_param._size_data);
+	    vhdl.set_signal ("mask_completion_left_"+toString(i)+"    ",_param._size_data);
+	    vhdl.set_signal ("mask_completion_right_"+toString(i)+"   ",_param._size_data);
+	  }
+	
+	//-----[ Shift logic Left ]--------------------------------------------
+	if (_param._have_shift_logic_left)
+	  vhdl.set_signal ("shift_logic_left_"+toString(i)+"      ",_param._size_data);
+	
+	//-----[ Shift logic Right ]-------------------------------------------
+	if (_param._have_shift_logic_right)
+	  vhdl.set_signal ("shift_logic_right_"+toString(i)+"     ",_param._size_data);
+	
+	//-----[ Shift arithmetic Left ]---------------------------------------
+	if (_param._have_shift_arithmetic_left)
+	  vhdl.set_signal ("shift_arithmetic_left_"+toString(i)+" ",_param._size_data);
+	
+	//-----[ Shift arithmetic Right ]--------------------------------------
+	if (_param._have_shift_arithmetic_right)
+	  vhdl.set_signal ("shift_arithmetic_right_"+toString(i)+"",_param._size_data);
+	
+	//-----[ Rotate Left ]-------------------------------------------------
+	if (_param._have_rotate_left)
+	  vhdl.set_signal ("rotate_left_"+toString(i)+"           ",_param._size_data);
+	
+	//-----[ Rotate Right ]------------------------------------------------
+	if (_param._have_rotate_right)
+	  vhdl.set_signal ("rotate_right_"+toString(i)+"          ",_param._size_data);
+      }
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_port.cpp	(revision 3)
@@ -0,0 +1,44 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Shifter::vhdl_port (Vhdl & vhdl)
+  {
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	vhdl.set_port (" in_SHIFTER_DATA_"+toString(i)+"      ", IN, _param._size_data);
+	if (_param._shift_value == 0)
+	vhdl.set_port (" in_SHIFTER_SHIFT_"+toString(i)+"     ", IN, static_cast<uint32_t>(ceil(log2(_param._size_data))));
+	if (_param._direction   == external_direction)
+	vhdl.set_port (" in_SHIFTER_DIRECTION_"+toString(i)+" ", IN, 1);
+	if (_param._rotate      == external_rotate)
+	vhdl.set_port (" in_SHIFTER_TYPE_"+toString(i)+"      ", IN, 1);
+	if (_param._carry       == external_carry)
+	vhdl.set_port (" in_SHIFTER_CARRY_"+toString(i)+"     ", IN, 1);
+	if (_param._carry       == external_completion)
+	if (_param._type_completion_bool == true)
+	vhdl.set_port (" in_SHIFTER_CARRY_IN_"+toString(i)+"  ", IN, 1);
+	else
+	vhdl.set_port (" in_SHIFTER_COMPLETION_"+toString(i)+"", IN, _param._size_data_completion);
+
+	vhdl.set_port ("out_SHIFTER_DATA_"+toString(i)+"      ",OUT, _param._size_data);
+      }
+  };
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_testbench_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_testbench_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_testbench_port.cpp	(revision 3)
@@ -0,0 +1,44 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Shifter::vhdl_testbench_port (Vhdl_Testbench & vhdl_testbench)
+  {
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	vhdl_testbench.set_port (" in_SHIFTER_DATA_"+toString(i)      , IN, _param._size_data);
+	if (_param._shift_value == 0)
+	vhdl_testbench.set_port (" in_SHIFTER_SHIFT_"+toString(i)     , IN, static_cast<uint32_t>(ceil(log2(_param._size_data))));
+	if (_param._direction   == external_direction)
+	vhdl_testbench.set_port (" in_SHIFTER_DIRECTION_"+toString(i) , IN, 1);
+	if (_param._rotate      == external_rotate)
+	vhdl_testbench.set_port (" in_SHIFTER_TYPE_"+toString(i)      , IN, 1);
+	if (_param._carry       == external_carry)
+	vhdl_testbench.set_port (" in_SHIFTER_CARRY_"+toString(i)     , IN, 1);
+	if (_param._carry       == external_completion)
+	if (_param._type_completion_bool == true)
+	vhdl_testbench.set_port (" in_SHIFTER_CARRY_IN_"+toString(i)  , IN, 1);
+	else
+	vhdl_testbench.set_port (" in_SHIFTER_COMPLETION_"+toString(i), IN, _param._size_data_completion);
+	vhdl_testbench.set_port ("out_SHIFTER_DATA_"+toString(i)      ,OUT, _param._size_data);
+      }
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_testbench_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_testbench_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_testbench_transition.cpp	(revision 3)
@@ -0,0 +1,57 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Shifter::vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench)
+  {
+#ifndef SYSTEMCASS_SPECIFIC
+    sc_cycle(0);
+#endif
+
+    // In order with file Shifter_vhdl_testbench_port.cpp
+
+    for (uint32_t i=0; i<_param._nb_port; i++)
+      {
+	vhdl_testbench.add_input  (PORT_READ( in_SHIFTER_DATA      [i]));
+	if (_param._shift_value == 0)
+	vhdl_testbench.add_input  (PORT_READ( in_SHIFTER_SHIFT     [i]));
+	if (_param._direction   == external_direction)
+	vhdl_testbench.add_input  (PORT_READ( in_SHIFTER_DIRECTION [i]));
+	if (_param._rotate      == external_rotate)
+	vhdl_testbench.add_input  (PORT_READ( in_SHIFTER_TYPE      [i]));
+	if (_param._carry       == external_carry)
+	vhdl_testbench.add_input  (PORT_READ( in_SHIFTER_CARRY     [i]));
+	if (_param._carry       == external_completion)
+	if (_param._type_completion_bool == true)
+	vhdl_testbench.add_input  (PORT_READ( in_SHIFTER_CARRY_IN  [i]));
+	else
+	vhdl_testbench.add_input  (PORT_READ( in_SHIFTER_COMPLETION[i]));
+	vhdl_testbench.add_output (PORT_READ(out_SHIFTER_DATA      [i]));
+      }
+    
+    // add_test :
+    //  - True  : the cycle must be compare with the output of systemC
+    //  - False : no test
+    vhdl_testbench.add_test(true);
+
+    vhdl_testbench.new_cycle (); // always at the end
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,36 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+  };
+  
+  Statistics::~Statistics () 
+  { 
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,29 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+
+  void Statistics::add ()
+  {
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,43 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+  string Statistics::print (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<shifter name=\"" << _name << "\" >" << endl
+	<< print_body (depth+1)
+	<< tab << "</shifter>" << endl;
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::generic::shifter::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,33 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Generic/Shifter/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace generic {
+namespace shifter {
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "";
+    
+    return msg.str();
+  };
+
+}; // end namespace shifter
+}; // end namespace generic
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile	(revision 3)
@@ -0,0 +1,22 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libBehavioural.a
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common	(revision 3)
@@ -0,0 +1,132 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_INC				= include
+DIR_SRC				= src
+DIR_OBJ				= obj
+DIR_SCRIPT			= $(DIR_MORPHEO)/Script
+
+#-----[ Commands ]-----------------------------------------
+ECHO				= echo
+EXPORT				= export
+MKDIR				= mkdir -p
+TEST				= test
+READ				= read
+DATE				= date +%Y%m%d-%H%M%S
+CD				= cd
+CP				= cp
+CAT				= cat
+LS				= ls
+RM				= rm -fr
+PWD				= `pwd`
+MAKE				= make -s
+AR				= ar -v
+RANLIB				= ranlib
+BASENAME			= basename
+GREP				= grep
+GREP_NOT			= egrep -v
+TR				= tr
+UPPERtoLOWER			= $(TR) [:lower:] [:upper:]
+
+#-----[ Compilation ]--------------------------------------
+
+SYSTEMC_systemc			= $(TOOLS)/systemc
+SYSTEMC_systemcass 		= $(TOOLS)/systemcass
+SYSTEMC_systemcass_deps 	= $(SYSTEMC_systemcass)
+
+SYSTEMC				= $(SYSTEMC_$(SIMULATOR))
+
+INCDIR 				= -I$(SYSTEMC)/include 	\
+				  -I$(DIR_MORPHEO) 
+
+DIRLIB_systemc			= lib-$(TARGET_ARCH) 	
+DIRLIB_systemcass 		= lib
+DIRLIB_systemcass_deps         	= $(DIRLIB_systemcass)
+
+LIBDIR 				= $(DIR_LIBRARY)			\
+		 		  -L$(SYSTEMC)/$(DIRLIB_$(SIMULATOR))  	\
+				  -L$(TOOLS)/soclib/lib 		\
+				  -L$(TOOLS)/or1k/lib 				
+
+LIBS		   		= $(LIBRARY) -lm -lsystemc -lsoclib -lbfd -liberty -ldl
+# target architecture
+TARGET_ARCH	 		= linux
+
+XX_systemc			=
+XX_systemcass			= -rdynamic				\
+				  -ansi                       		\
+   	                	  -Wno-long-long
+
+XX_systemcass_deps		= $(XX_systemcass)
+
+EXEC_PARAMS_systemc		= 
+EXEC_PARAMS_systemcass 		= --nobanner 
+EXEC_PARAMS_systemcass_deps     = --nobanner --p
+
+
+XX_COMMON			= -O3					\
+				  -g3   				\
+				  -Wall					\
+				  -Wunused
+#				  -Wno-deprecated 			\
+#				  -Wno-non-template-friend		\
+#				  -Wno-pmf-conversions 			\
+#				  -Wfatal-errors 			\
+# 		                  -pedantic                   		\
+# 				  -Werror				\
+
+XX_OPT    			= $(XX_COMMON) $(XX_$(SIMULATOR))
+
+CXX				= export LANG=C; g++
+CXX_OPT				= $(XX_OPT) $(FLAGS) $(INCDIR)
+LXX_OPT				= $(XX_OPT) $(FLAGS) $(LIBDIR)
+
+EXEC_PARAMS 			= $(EXEC_PARAMS_$(SIMULATOR))
+
+#-----[ Variable ]-----------------------------------------
+
+ENTITY				= `$(BASENAME) $$PWD`
+
+OBJECTS_COMMON			= $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp))
+
+HEADERS  			= $(wildcard $(DIR_INC)/*.h)
+
+#-----[ Rules ]--------------------------------------------
+.PRECIOUS			: $(DIR_OBJ)/%.o
+
+test_env			:
+				@$(ECHO) "-------------------[ $(ENTITY) ]"
+ifeq ($(origin TOOLS), undefined)
+				$(error "variable TOOLS       is undefined");
+endif
+ifeq ($(origin DIR_MORPHEO), undefined)
+				$(error "variable DIR_MORPHEO is undefined");
+endif
+
+$(DIR_OBJ)/%.o			: $(DIR_SRC)/%.cpp $(HEADERS)
+				@$(ECHO) "Compilation        : $*"
+				@$(CXX) $(CXX_OPT) -c -o $@ $<
+
+$(DIR_OBJ)			:
+				@$(ECHO) "Create directory   : $@"
+				@$(MKDIR) $@
+
+common_clean			:
+				@$(ECHO) "Delete     temporary files in directory "$(PWD)
+				@$(RM) 	$(DIR_OBJ) 	\
+					$(DIR_BIN) 	\
+					*~ 		\
+					$(DIR_SRC)/*~	\
+					$(DIR_INC)/*~
+
+common_help			:
+				@$(ECHO) " -----[ Common ]-------------------------------------"
+				@$(ECHO) ""
+				@$(ECHO) " * test_env             : test if environnment's variable is set"
+				@$(ECHO) ""
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Component
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Component	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Component	(revision 3)
@@ -0,0 +1,41 @@
+#-----[ Variable ]-----------------------------------------
+DIR_LIB				= lib
+DIR_TEST			= SelfTest
+
+OBJECTS				= $(OBJECTS_COMMON)
+
+#-----[ Directory ]----------------------------------------
+.PRECIOUS			: $(DIR_LIB)/%.a
+.NOPARALLEL			: clean help
+
+all_component			: test_env $(DIR_OBJ) $(DIR_LIB) $(OBJECTS) $(HEADERS)
+				@$(MAKE) $(LIBRARY)
+
+$(DIR_LIB)/%.a			: $(OBJECTS) $(HEADERS)
+				@$(ECHO) "Archive            : $*"
+				@$(AR)  -r $@ $(OBJECTS)
+				@$(RANLIB) $@
+
+$(DIR_LIB)			:
+				@$(ECHO) "Create directory   : $@"
+				@$(MKDIR) $@
+
+component_clean			:
+				@$(RM) $(DIR_LIB)
+				
+component_help			:
+				@$(ECHO) " -----[ Component ]----------------------------------"
+				@$(ECHO) ""
+				@$(ECHO) " * all_component        : compile all c++ file and generate library"
+				@$(ECHO) " * clean                : Erase all generate files"
+				@$(ECHO) " * help                 : print this text"
+				@$(ECHO) ""
+				
+
+help				: 
+				@$(MAKE) common_help
+				@$(MAKE) component_help
+clean				: 
+				@$(MAKE) common_clean 
+				@$(MAKE) component_clean
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest	(revision 3)
@@ -0,0 +1,171 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Variables ]----------------------------------------
+DIR_BIN				= bin
+DIR_LIB				= ../lib
+DIR_CFG				= configuration
+DIR_LOG				= log
+
+CFG_FILE			= configuration.cfg
+
+OBJECTS      			= $(OBJECTS_COMMON)
+
+EXEC_LOG			= $(patsubst $(DIR_CFG)/%.cfg,$(DIR_LOG)/%.exec.log,$(wildcard $(DIR_CFG)/*.cfg))
+EXEC				= soft
+
+#-----[ Rules ]--------------------------------------------
+.PRECIOUS			: $(DIR_BIN)/%.x $(DIR_LOG)/%.exec.log
+.NOPARALLEL			: clean clean_all help
+
+all_selftest   			: test_env $(DIR_OBJ) $(DIR_BIN) $(DIR_LOG)
+				@$(MAKE) library
+				@$(MAKE) $(DIR_BIN)/$(EXEC).x
+
+execute				: all_selftest
+				@$(MAKE) $(EXEC_LOG)
+
+reconfig			:
+				@$(MAKE) config_clean
+				@$(MAKE) config
+
+config_clean			:
+				@													\
+				declare     NAME;											\
+				declare -i  CPT=0;											\
+				declare -ai PERIOD;											\
+				declare -a  RANGE_LOCAL;										\
+				PERIOD[0]=1;												\
+																	\
+				while $(READ) line; do											\
+				        LINE=($$line);											\
+																	\
+					if $(TEST) $$CPT -eq 0; then 									\
+						NAME=$${LINE[0]};									\
+					else												\
+						RANGE_LOCAL=($$($(DIR_SCRIPT)/range.sh $${LINE[0]} $${LINE[1]} $${LINE[2]}));		\
+						PERIOD[$$CPT]=$$(($${PERIOD[$$(($$CPT-1))]}*$${#RANGE_LOCAL[*]}));			\
+					fi;												\
+																	\
+					CPT=$$(($$CPT+1));										\
+				done < $(CFG_FILE);											\
+																	\
+				declare -i NB_CONFIG=$${PERIOD[$$(($$CPT-1))]};								\
+																	\
+				for i in $$($(DIR_SCRIPT)/range.sh 0 $$(($$NB_CONFIG-1))); do						\
+					$(RM) "$(DIR_CFG)/$${NAME}_$${i}.cfg";								\
+				done;
+
+config        			:
+				@$(ECHO) "Generate configuration"
+				@													\
+				declare     NAME;											\
+				declare -ai MIN ;											\
+				declare -ai MAX ;											\
+				declare -a  STEP; 											\
+				declare -a  LINE; 											\
+				declare -i  CPT=0;											\
+				declare -ai PERIOD;											\
+				declare -a  RANGE;											\
+				declare -a  RANGE_LOCAL;										\
+				declare -a  SIZE;											\
+				PERIOD[0]=1;												\
+																	\
+				while $(READ) line; do											\
+				        LINE=($$line);											\
+																	\
+					if $(TEST) $$CPT -eq 0; then 									\
+						NAME=$${LINE[0]};									\
+					else												\
+						MIN[$$CPT]=$${LINE[0]};									\
+						MAX[$$CPT]=$${LINE[1]};									\
+						STEP[$$CPT]=$${LINE[2]};								\
+						RANGE[$$CPT]=$$($(DIR_SCRIPT)/range.sh $${LINE[0]} $${LINE[1]} $${LINE[2]});		\
+						RANGE_LOCAL=($${RANGE[$$CPT]});								\
+						SIZE[$$CPT]=$${#RANGE_LOCAL[*]};							\
+						PERIOD[$$CPT]=$$(($${PERIOD[$$(($$CPT-1))]}*$${SIZE[$$CPT]}));				\
+					fi;												\
+																	\
+					CPT=$$(($$CPT+1));										\
+				done < $(CFG_FILE);											\
+																	\
+				declare -i x;												\
+				declare -a DATA;											\
+				declare -ai ENUM_CONFIG=($$($(DIR_SCRIPT)/range.sh 0 $$(($${PERIOD[$$(($$CPT-1))]}-1))));		\
+				declare -ai ENUM_PARAM=($$($(DIR_SCRIPT)/range.sh 1 $${#MIN[*]}));            				\
+																	\
+ 				$(ECHO) " * they are $${#MIN[*]} parameters";								\
+ 				$(ECHO) " * generate $${PERIOD[$$(($$CPT-1))]} configurations";						\
+																	\
+				for i in $${ENUM_CONFIG[*]}; do										\
+					x=$$i;												\
+					for j in $${ENUM_PARAM[*]}; do									\
+						RANGE_LOCAL=($${RANGE[$$j]});								\
+						DATA[$$j]="$${RANGE_LOCAL[$$((($$x % $${SIZE[$$j]})))]} ";				\
+						x=$$(($$x/$${SIZE[$$j]})); 								\
+					done;												\
+					$(ECHO) $${DATA[*]} > "$(DIR_CFG)/$${NAME}_$${i}.cfg";						\
+					$(ECHO) "  - {$$i} $${DATA[*]}";								\
+				done;
+
+$(DIR_LOG)/%.exec.log		: $(DIR_CFG)/%.cfg $(DIR_BIN)/$(EXEC).x
+				@$(ECHO) "Execute            : $*"
+				@$(EXPORT) SYSTEMC=$(SYSTEMC) ; ./$(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` > $@
+				declare -i count=`$(GREP) -ch "Test KO" $@`;		\
+				if $(TEST) $$count -eq 0;       			\
+				then echo "                     $* ... OK";           	\
+				else echo "                     $* ... KO"; exit 1;     \
+				fi;
+
+$(DIR_BIN)/%.x			: $(OBJECTS) $(HEADERS) $(DIR_LIB)
+				@$(ECHO) "Linkage            : $*"
+				@$(CXX) $(LXX_OPT) -o $@ $(OBJECTS) $(LIBS)
+
+$(DIR_BIN)			:
+				@$(ECHO) "Create directory   : $@"
+				@$(MKDIR) $@
+
+$(DIR_LOG)			:
+				@$(ECHO) "Create directory   : $@"
+				@$(MKDIR) $@
+
+selftest_clean_all		: library_clean config_clean
+				
+selftest_clean			: 
+				@$(RM) 	$(DIR_LOG)		\
+					$(DIR_CFG)/*~		\
+					*.vhdl			\
+					*.stat			\
+					generated_by_systemcass \
+					core*
+
+selftest_help			:
+				@$(ECHO) " -----[ Selftest ]-----------------------------------"
+				@$(ECHO) ""
+				@$(ECHO) " * all_selftest         : compile all c++ file and execute"
+				@$(ECHO) " * execute              : execute all instance"
+				@$(ECHO) " * config               : generate configuration with configuration's file" 
+				@$(ECHO) " * reconfig             : regenerate configuration with configuration's file" 
+				@$(ECHO) " * clean                : Erase all generate files"
+				@$(ECHO) " * clean_all            : Clean + Erase all dependant library"
+				@$(ECHO) " * help                 : print this text"
+				@$(ECHO) ""
+
+help				: 
+				@$(MAKE) common_help  
+				@$(MAKE) synthesis_help  
+				@$(MAKE) selftest_help
+
+clean				: 
+				@$(MAKE) common_clean 
+				@$(MAKE) synthesis_clean 
+				@$(MAKE) selftest_clean
+
+clean_all			: 
+				@$(MAKE) clean 
+				@$(MAKE) selftest_clean_all
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis	(revision 3)
@@ -0,0 +1,88 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Variables ]----------------------------------------
+
+DIR_VHDL			= .
+DIR_WORK			= work
+
+FPGA_CFG_FILE_LOCAL		= mkf.info
+FPGA_CFG_FILE_GLOBAL_DIR	= $(DIR_MORPHEO)/Behavioural
+FPGA_CFG_FILE_GLOBAL   		= configure.mkf 
+
+#-----[ Tools ]--------------------------------------------
+VLIB				= vlib
+VCOM				= vcom
+VSIM				= vsim -c -do "run -all; quit"
+
+ENV_XILINX			= source $(TOOLS)/xilinx/settings.sh
+
+#-----[ Rules ]--------------------------------------------
+.PRECIOUS			: $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.vhdl_sim.log
+
+vhdl				: execute $(DIR_WORK)
+				@declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl));						\
+				declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log});						\
+				$(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)};
+				@declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl));					\
+				declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log});						\
+				$(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)};
+				@declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)"));		\
+				declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log});						\
+				$(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)};
+
+vhdl_sim			: vhdl
+				@declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl));					\
+				declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl_sim.log});						\
+				$(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)};
+
+fpga				: vhdl_sim
+				@$(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL)
+				@for file in $(patsubst $(DIR_CFG)/%.cfg,%,$(wildcard $(DIR_CFG)/*.cfg)); do				\
+					declare -a files=($$($(LS) $$file*.vhdl|$(GREP_NOT) "(_Testbench\.)"));				\
+					$(ECHO) -e "# $$file"                             >> $(FPGA_CFG_FILE_LOCAL);			\
+					$(ECHO) -e "target_dep\tall\t$$file.ngc"          >> $(FPGA_CFG_FILE_LOCAL);			\
+					$(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj"	  >> $(FPGA_CFG_FILE_LOCAL);			\
+					$(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL);			\
+					$(ECHO) -e ""                                     >> $(FPGA_CFG_FILE_LOCAL);			\
+				done
+				@($(ENV_XILINX); $(CD) $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL))	
+				@$(MAKE) $(patsubst $(DIR_CFG)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG)/*.cfg))
+
+$(DIR_LOG)/%.fpga.log     	: 
+				@$(ECHO) "Synthetis on FPGA  : $*"
+				@$(ENV_XILINX); $(MAKE) -f Makefile.mkf $*.ngc > $@
+
+$(DIR_WORK)			:
+				@$(ECHO) "Create work-space  : $@"
+				@$(VLIB) $@
+
+$(DIR_LOG)/%.vhdl_sim.log	: $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
+				@$(ECHO) "VHDL's Simulation: $*"
+				@$(VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" > $@
+				declare -i count=`$(GREP) -ch "Test KO" $@`;		\
+				if $(TEST) $$count -eq 0;       			\
+				then echo "                     $* ... OK";           	\
+				else echo "                     $* ... KO"; exit 1;     \
+				fi;
+
+$(DIR_LOG)/%.vhdl.log		: $(DIR_VHDL)/%.vhdl
+				@$(ECHO) "VHDL's Compilation : $*"
+				@$(VCOM) $< > $@
+
+synthesis_clean			:
+				@if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi
+				@$(RM) $(DIR_WORK) transcript Makefile.mkf
+
+synthesis_help			:
+				@$(ECHO) " -----[ Synthesis ]----------------------------------"
+				@$(ECHO) ""
+				@$(ECHO) " * vhdl                 : compile all vhdl's file"
+				@$(ECHO) " * vhdl_sim             : simulate all testbench's file"
+				@$(ECHO) " * fpga                 : synthetis with fpga's tools"
+				@$(ECHO) ""
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.defs
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.defs	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.defs	(revision 3)
@@ -0,0 +1,30 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+
+#-----[ Simulator ]----------------------------------------
+SIMULATOR			= systemcass_deps
+
+# 3 simulators :
+# systemc			- SystemC    
+# systemcass 			- SystemCASS
+# systemcass_deps		- SystemCASS, and use port dependency information instead of sensitivity list
+
+#-----[ Flags ]--------------------------------------------
+FLAGS				=	-DSYSTEMC		\
+					-DCONFIGURATION		\
+					-DSTATISTICS 		\
+					-DVHDL			\
+					-DVHDL_TESTBENCH
+# 					-DDEBUG=DEBUG_TRACE
+
+# Flags :
+# DEBUG={level}                 - Print Debug Message
+# VHDL                          - To generate a vhdl's    model
+# SYSTEMC                       - To generate a systemc's model
+# CONFIGURATION			- To generate a configuration file (it's input of viewer)
+# STATISTICS     (need SYSTEMC) - In the simulation, generate a statistics's file
+# VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+Behavioural			= yes
+
+#-----[ Library ]------------------------------------------
+Behavioural_LIBRARY		= 	-lBehavioural
+
+Behavioural_DIR_LIBRARY		=	-L$(DIR_MORPHEO)/Behavioural/lib
+
+#-----[ Rules ]--------------------------------------------
+
+Behavioural_library		:
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural --makefile=Makefile 
+	
+Behavioural_library_clean	:
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf	(revision 3)
@@ -0,0 +1,47 @@
+#
+# Makefile generated by MKF configure script
+#
+
+all: _Generic/Counter/SelfTest _Generic/RegisterFile/SelfTest _Generic/Shifter/SelfTest _Generic/Select/Pseudo_LRU/SelfTest _Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest _Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest _Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest
+
+_Generic/Counter/SelfTest:
+	gmake all -C Generic/Counter/SelfTest
+
+_Generic/RegisterFile/SelfTest:
+	gmake all -C Generic/RegisterFile/SelfTest
+
+_Generic/Shifter/SelfTest:
+	gmake all -C Generic/Shifter/SelfTest
+
+_Generic/Select/Pseudo_LRU/SelfTest:
+	gmake all -C Generic/Select/Pseudo_LRU/SelfTest
+
+_Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest:
+	gmake all -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest
+
+_Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest:
+	gmake all -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest
+
+_Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest:
+	gmake all -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest
+
+clean:
+	gmake clean -C Generic/Counter/SelfTest
+	gmake clean -C Generic/RegisterFile/SelfTest
+	gmake clean -C Generic/Shifter/SelfTest
+	gmake clean -C Generic/Select/Pseudo_LRU/SelfTest
+	gmake clean -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest
+	gmake clean -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest
+	gmake clean -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest
+
+re: clean all
+
+install:
+	gmake install -C Generic/Counter/SelfTest
+	gmake install -C Generic/RegisterFile/SelfTest
+	gmake install -C Generic/Shifter/SelfTest
+	gmake install -C Generic/Select/Pseudo_LRU/SelfTest
+	gmake install -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest
+	gmake install -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest
+	gmake install -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component.sh
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component.sh	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component.sh	(revision 3)
@@ -0,0 +1,290 @@
+#!/bin/sh
+
+SED_SCRIPT=".sed_script";
+SED_FILE=".sed_file";
+SOURCE_FILE="New_Component";
+SOURCE_DIR="./$SOURCE_FILE";
+
+#-----[ usage ]------------------------------------------------------
+# input  : -
+# output : -
+
+function usage ()
+{
+    echo "";
+    echo "usage : $0 <directory> <name>";
+    echo " - <directory> : localisation of component";
+    echo " - <name>      : name of component";
+    echo "";
+    echo " Note : This script must be execute in directory's script";
+    echo "";
+    
+    exit;
+}
+
+#-----[ test_usage ]-------------------------------------------------
+# input  : all parameters
+# output : -
+
+function test_usage ()
+{
+    if test ! -d $SOURCE_DIR; then
+	echo "Source directory \"$SOURCE_DIR\" invalid";
+	usage;
+    fi;
+
+    if test -f $SED_SCRIPT; then
+	echo "File \"$SED_SCRIPT\" exist"; 
+	usage;
+    fi;
+    if test -f $SED_FILE; then
+	echo "File \"$SED_FILE\" exist"; 
+	usage;
+    fi;
+
+    if test $# -ne 2; then
+	usage;
+    fi;
+
+#    if test -d $1/$2; then
+#	echo "Component in Directory \"$1/$2\" already exist";
+#	usage;
+#    fi;
+}
+
+#-----[ rename_file ]------------------------------------------------
+# input  : file_old name_old name_new
+# output : -
+
+function rename_file ()
+{
+    FILE_OLD=$1;
+    NAME_OLD=$2;
+    NAME_NEW=$3;
+
+    FILE_NEW="`dirname  $FILE_OLD`/`basename $FILE_OLD |sed s/"$NAME_OLD"/"$NAME_NEW"/`";
+
+    if test $FILE_NEW != $FILE_OLD; then
+	mv $FILE_OLD $FILE_NEW;
+    fi;
+}
+
+#-----[ rename_directory ]-------------------------------------------
+# input  : dir name_old name_new
+# output : -
+
+function rename_directory ()
+{
+    NAME_OLD=$2;
+    NAME_NEW=$3;
+
+    # recursion
+    for ENTRY in $1/*; do
+
+	if test -d $ENTRY; then
+	    rename_directory $ENTRY $2 $3;
+	else
+	    rename_file      $ENTRY $2 $3;
+	fi;
+    done;
+}
+
+#-----[ directory_to ]-----------------------------------------------
+# input  : directory cmd
+# output : -
+
+function directory_to ()
+{
+    res="";
+
+    for i in `echo "$1" |tr \/ ' '`; do
+	j=`echo $i |tr [:upper:]  [:lower:]`;
+	case $2 in
+	    "dir_morpheo")
+		if test -z "$res"; then
+		    res="..\/..";
+		else
+		    res="..\/$res";
+		fi;
+		;;
+	    "component_lower")
+		res="$j";
+		;;
+	    "component")
+		res="$i";
+		;;
+	    "directory")
+		if test -z "$res"; then
+		    res=$i;
+		else
+		    res="$res\/$i";
+		fi;
+		;;
+	    "define")
+		if test -z "$res"; then
+		    res=$j;
+		else
+		    res="${res}_${j}";
+		fi;
+		;;
+	    "namespace_begin")
+		prefixe="namespace ";
+		postfixe=" {\n";
+		if test -z "$res"; then
+		    res="$prefixe$j$postfixe";
+		else
+		    res="$res$prefixe$j$postfixe";
+		fi;
+		;;
+	    "namespace_end")
+		prefixe="}; \/\/ end namespace ";
+		postfixe="\n";
+		if test -z "$res"; then
+		    res="$prefixe$j$postfixe";
+		else
+		    res="$prefixe$j$postfixe$res";
+		fi;
+		;;
+	    "namespace_use")
+		if test -z "$res"; then
+		    res="$j";
+		else
+		    res="$res::$j";
+		fi;
+		;;
+	    "namespace_using")
+		prefixe="using namespace morpheo::behavioural::";
+		postfixe=";\n";
+		if test -z "$res"; then
+		    res="$prefixe$j$postfixe";
+		    namespace="$j";
+		else
+		    res="$res$prefixe$namespace::$j$postfixe";
+		    namespace="$namespace::$j";
+		fi;
+		;;
+	    *)
+	esac;
+    done;
+
+    echo $res;
+}
+
+#-----[ translation_script ]-----------------------------------------
+# input  : dir component 
+# output : -
+
+function translation_script ()
+{
+    # All example is the component Generic/RegisterFile
+    
+    #@DIR_MORPHEO	../../
+    SED=`directory_to $1/$2 "dir_morpheo"`;
+    echo "s/@DIR_MORPHEO/$SED/g" >> $SED_SCRIPT;
+
+    #@COMPONENT_LOWER	registerfile
+    SED=`directory_to $2 "component_lower"`;
+    echo "s/@COMPONENT_LOWER/$SED/g" >> $SED_SCRIPT;
+
+    #@COMPONENT		RegisterFile
+    SED=`directory_to $2 "component"`;
+    echo "s/@COMPONENT/$SED/g" >> $SED_SCRIPT;
+
+    #@DIRECTORY		Generic/RegisterFile
+    SED=`directory_to $1/$2 "directory"`;
+    echo "s/@DIRECTORY/$SED/g" >> $SED_SCRIPT;
+
+    #@DEFINE		generic_registerfile		
+    SED=`directory_to $1/$2 "define"`;
+    echo "s/@DEFINE/$SED/g" >> $SED_SCRIPT;
+
+    #@NAMESPACE_BEGIN	namespace generic                    {		
+    #			namespace registerfile               {		
+    SED=`directory_to $1/$2 "namespace_begin"`;
+    echo "s/@NAMESPACE_BEGIN/$SED/g" >> $SED_SCRIPT;
+
+    #@NAMESPACE_END	}; // end namespace registerfile 		
+    #			}; // end namespace generic			
+    SED=`directory_to $1/$2 "namespace_end"`;
+    echo "s/@NAMESPACE_END/$SED/g" >> $SED_SCRIPT;
+
+    #@NAMESPACE_USE	generic::registerfile		
+    SED=`directory_to $1/$2 "namespace_use"`;
+    echo "s/@NAMESPACE_USE/$SED/g" >> $SED_SCRIPT;
+
+    #@NAMESPACE_USING	using namespace morpheo::behavioural::generic;	
+    SED=`directory_to $1    "namespace_using"`;
+    echo "s/@NAMESPACE_USING/$SED/g" >> $SED_SCRIPT;
+
+}
+
+
+
+#-----[ translation_file ]-------------------------------------------
+# input  : file
+# output : -
+
+function translation_file ()
+{
+    echo "Translation     : $1";
+    
+    cat $1 |sed -f $SED_SCRIPT $1 > $SED_FILE;
+    mv $SED_FILE $1;
+}
+
+#-----[ translation_directory_rec ]----------------------------------
+# input  : dir
+# output : -
+
+function translation_directory_rec
+{
+    # recursion
+    for ENTRY in $1/*; do
+
+	if test -d $ENTRY; then
+	    translation_directory_rec $ENTRY;
+	else
+	    translation_file          $ENTRY
+	fi;
+    done;
+}
+
+#-----[ translation_directory ]--------------------------------------
+# input  : dir component
+# output : -
+
+function translation_directory ()
+{
+    touch $SED_SCRIPT;
+
+    translation_script        $1 $2;  
+    translation_directory_rec $1/$2;
+
+    #cat   $SED_SCRIPT;
+    rm    $SED_SCRIPT;
+}
+
+
+#-----[ main ]-------------------------------------------------------
+# input  : all parameters
+# output : -
+
+function main ()
+{
+    test_usage $*;
+
+    echo "New             : $2";
+    
+    # Create directory
+    mkdir -p $1/$2;
+    
+    #Copy
+    cp -r $SOURCE_DIR/* $1/$2/;
+    
+    #translation
+    rename_directory      "$1/$2" $SOURCE_FILE $2;
+    translation_directory $1 $2;
+}
+
+#-----[ body ]-------------------------------------------------------
+main $*;
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/Makefile	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= @DIR_MORPHEO
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/lib@COMPONENT.a
+
+
+#-----[ include ]------------------------------------------
+
+all				:
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/Makefile.deps	(revision 3)
@@ -0,0 +1,31 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+
+@COMPONENT			= yes
+
+#-----[ Library ]------------------------------------------
+@COMPONENT_LIBRARY		= 	-l@COMPONENT	\
+					$(Behavioural_LIBRARY)	
+
+@COMPONENT_DIR_LIBRARY		=	-L$(DIR_MORPHEO)/Behavioural/@DIRECTORY/lib	\
+					$(Behavioural_DIR_LIBRARY)
+
+#-----[ Rules ]--------------------------------------------
+
+@COMPONENT_library		: 
+				@$(MAKE) Behavioural_library
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/@DIRECTORY --makefile=Makefile 
+	
+@COMPONENT_library_clean	: 
+				@$(MAKE) Behavioural_library_clean
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/@DIRECTORY --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,29 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../@DIR_MORPHEO
+
+LIBRARY				= $(@COMPONENT_LIBRARY)
+
+DIR_LIBRARY			= $(@COMPONENT_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				:
+				@$(MAKE) all_selftest
+
+library				: @COMPONENT_library
+
+library_clean			: @COMPONENT_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/configuration.cfg	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/configuration.cfg	(revision 3)
@@ -0,0 +1,1 @@
+@COMPONENT
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/include/test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/include/test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/include/test.h	(revision 3)
@@ -0,0 +1,25 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+@NAMESPACE_USING
+using namespace morpheo::behavioural::@NAMESPACE_USE;
+
+void test    (string name,
+	      morpheo::behavioural::@NAMESPACE_USE::Parameters param);
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,58 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/SelfTest/include/test.h"
+
+#define NB_PARAMS 0
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl;
+//     << " - size_data     (unsigned int)" << endl
+//     << " - nb_port       (unsigned int)" << endl;
+
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc != 2+NB_PARAMS)
+    usage (argv[0]);
+
+  const string   name      = argv[1];
+//const uint32_t size_data = atoi(argv[2]);
+//const uint32_t nb_port   = atoi(argv[3]);
+
+  try 
+    {
+      morpheo::behavioural::@NAMESPACE_USE::Parameters param (//size_data,
+							      //nb_port  
+							     );
+      
+      cout << param.print(1);
+      
+      test (name,param);
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      return;
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+
+  return (EXIT_SUCCESS);
+}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/src/test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/SelfTest/src/test.cpp	(revision 3)
@@ -0,0 +1,80 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#define NB_ITERATION 1
+
+#include "Behavioural/@DIRECTORY/SelfTest/include/test.h"
+#include "Include/Test.h"
+
+void test (string name,
+	   morpheo::behavioural::@NAMESPACE_USE::Parameters param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  @COMPONENT * _@COMPONENT = new @COMPONENT (name.c_str(),
+#ifdef STATISTICS
+					     morpheo::behavioural::Parameters_Statistics(5,50),
+#endif
+					     param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                               * CLOCK;
+
+
+  string rename;
+
+  CLOCK                                  = new sc_clock ("clock", 1.0, 0.5);
+  
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _@COMPONENT" << endl;
+  
+  (*(_@COMPONENT->in_CLOCK))        (*(CLOCK));
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  // Initialisation
+
+  const uint32_t seed = 0;
+//const uint32_t seed = static_cast<uint32_t>(time(NULL));
+
+  srand(seed);
+
+  sc_start(0);
+  _@COMPONENT->vhdl_testbench_label("Initialisation");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl;
+
+
+  _@COMPONENT->vhdl_testbench_label("Loop of Test");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl;
+
+  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+    {
+      _@COMPONENT->vhdl_testbench_label("Iteration "+toString(iteration));
+
+      sc_start(1);
+    }
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete _@COMPONENT;
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/VERSION
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/VERSION	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/VERSION	(revision 3)
@@ -0,0 +1,1 @@
+v0.4
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/New_Component.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/New_Component.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/New_Component.h	(revision 3)
@@ -0,0 +1,120 @@
+#ifndef morpheo_behavioural_@DEFINE_@COMPONENT_h
+#define morpheo_behavioural_@DEFINE_@COMPONENT_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <iostream>
+#include "Include/ToString.h"
+#include "Include/Debug.h"
+
+#include "Behavioural/@DIRECTORY/include/Parameters.h"
+#include "Behavioural/@DIRECTORY/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/@DIRECTORY/include/Statistics.h"
+#endif
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#ifdef VHDL_TESTBENCH
+#include "Behavioural/include/Vhdl_Testbench.h"
+#endif
+
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  class @COMPONENT 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string     _name;
+
+  protected : const Parameters _param;
+//#ifdef STATISTICS
+//  protected : const morpheo::behavioural::Parameters_Statistics _param_statistics;
+//#endif
+
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+#endif
+
+#ifdef VHDL_TESTBENCH
+  private   : Vhdl_Testbench                 * _vhdl_testbench;
+#endif
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK        ;
+  public    : SC_IN (Tcontrol_t)            *  in_NRESET       ;
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#endif
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (@COMPONENT);
+#endif
+  public  :          @COMPONENT              (
+#ifdef SYSTEMC
+					      sc_module_name                              name,
+#else					       
+					      string                                      name,
+#endif					       
+#ifdef STATISTICS
+					      morpheo::behavioural::Parameters_Statistics param_statistics,
+#endif
+					      Parameters                                  param );
+					       
+  public  :          @COMPONENT              (Parameters param );
+  public  :          ~@COMPONENT             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+  public  : void     transition                (void);
+//public  : void     genMoore                  (void) {/* empty */};
+#endif					       
+#ifdef STATISTICS
+  public  : string   statistics                (uint32_t depth);
+#endif
+					       
+#if VHDL				       
+  public  : void     vhdl                      (void);
+  private : void     vhdl_port                 (Vhdl & vhdl);
+  private : void     vhdl_declaration          (Vhdl & vhdl);
+  private : void     vhdl_body                 (Vhdl & vhdl);
+#endif					       
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench_port       (void);
+  private : void     vhdl_testbench_transition (void);
+#endif
+  public  : void     vhdl_testbench_label      (string label);
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Parameters.h	(revision 3)
@@ -0,0 +1,39 @@
+#ifndef morpheo_behavioural_@DEFINE_Parameters_h
+#define morpheo_behavioural_@DEFINE_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+    //-----[ fields ]------------------------------------------------------------
+
+    //-----[ methods ]-----------------------------------------------------------
+  public : Parameters  ();
+  public : Parameters  (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::@NAMESPACE_USE::Parameters & x);
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Statistics.h	(revision 3)
@@ -0,0 +1,51 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_@DEFINE_Statistics_h
+#define morpheo_behavioural_@DEFINE_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+//#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/@DIRECTORY/include/Parameters.h"
+
+//using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                   _parameters;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics  (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  );
+//public   : Statistics  (Statistics & stat);
+  public   : ~Statistics () ;
+    
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : void     add        ();
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/Types.h	(revision 3)
@@ -0,0 +1,23 @@
+#ifdef SYSTEMC
+#ifndef morpheo_behavioural_@DEFINE_Type_h
+#define morpheo_behavioural_@DEFINE_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Types.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component.cpp	(revision 3)
@@ -0,0 +1,96 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+#ifdef SYSTEMC
+  @COMPONENT::@COMPONENT (sc_module_name name,
+#else
+  @COMPONENT::@COMPONENT (string name,
+#endif
+#ifdef STATISTICS
+			      morpheo::behavioural::Parameters_Statistics             param_statistics,
+#endif
+			      morpheo::behavioural::@NAMESPACE_USE::Parameters param ):
+			      _name              (name)
+			      ,_param            (param)
+// #ifdef STATISTICS
+// 			      ,_param_statistics (param_statistics)
+// #endif
+  {
+    log_printf(FUNC,@COMPONENT,"@COMPONENT","Begin");
+
+#ifdef STATISTICS
+    // Allocation of statistics
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // Creation of a testbench
+    //  -> port
+    //  -> clock's signals
+    _vhdl_testbench = new Vhdl_Testbench (_name);
+    vhdl_testbench_port           ();
+    _vhdl_testbench->set_clock    ("in_CLOCK",true);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    allocation ();
+
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+
+//     SC_METHOD (genMoore);
+//     dont_initialize ();
+//     sensitive_neg << *(in_CLOCK);
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+#endif    
+
+#endif
+    log_printf(FUNC,@COMPONENT,"@COMPONENT","End");
+  };
+  
+  @COMPONENT::~@COMPONENT (void)
+  {
+    log_printf(FUNC,@COMPONENT,"~@COMPONENT","Begin");
+
+#ifdef VHDL_TESTBENCH
+    // generate the test bench
+    _vhdl_testbench->generate_file();
+    delete _vhdl_testbench;
+#endif
+
+#ifdef STATISTICS
+    _stat->generate_file(statistics(0));
+    
+    delete _stat;
+#endif
+
+#ifdef SYSTEMC
+    deallocation ();
+#endif
+
+    log_printf(FUNC,@COMPONENT,"~@COMPONENT","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_allocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_allocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_allocation.cpp	(revision 3)
@@ -0,0 +1,32 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::allocation (void)
+  {
+    string rename;
+
+    log_printf(FUNC,@COMPONENT,"allocation","Begin");
+
+    in_CLOCK  = new SC_CLOCK           ("in_CLOCK");
+    in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET");
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    log_printf(FUNC,@COMPONENT,"allocation","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_deallocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_deallocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_deallocation.cpp	(revision 3)
@@ -0,0 +1,30 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::deallocation (void)
+  {
+    log_printf(FUNC,@COMPONENT,"deallocation","Begin");
+
+    delete in_CLOCK;
+    delete in_NRESET;
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    log_printf(FUNC,@COMPONENT,"deallocation","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_statistics.cpp	(revision 3)
@@ -0,0 +1,29 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  string @COMPONENT::statistics (uint32_t depth)
+  {
+    log_printf(FUNC,@COMPONENT,"statistics","Begin");
+
+    string txt = _stat->print(depth);
+    
+    log_printf(FUNC,@COMPONENT,"statistics","End");
+
+    return txt;
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_transition.cpp	(revision 3)
@@ -0,0 +1,33 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::transition (void)
+  {
+    log_printf(FUNC,@COMPONENT,"transition","Begin");
+
+#ifdef STATISTICS
+    _stat->add();
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition ();
+#endif
+
+    log_printf(FUNC,@COMPONENT,"transition","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::vhdl (void)
+  {
+    log_printf(FUNC,@COMPONENT,"vhdl","Begin");
+    Vhdl vhdl (_name);
+
+    vhdl.set_library_work (_name + "_Pack");
+
+    vhdl_port        (vhdl);
+    vhdl_declaration (vhdl);
+    vhdl_body        (vhdl);
+
+    vhdl.generate_file();
+    log_printf(FUNC,@COMPONENT,"vhdl","End");
+
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_body.cpp	(revision 3)
@@ -0,0 +1,25 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::vhdl_body (Vhdl & vhdl)
+  {
+    log_printf(FUNC,@COMPONENT,"vhdl_body","Begin");
+    vhdl.set_body ("");
+    log_printf(FUNC,@COMPONENT,"vhdl_body","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_declaration.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_declaration.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_declaration.cpp	(revision 3)
@@ -0,0 +1,24 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::vhdl_declaration (Vhdl & vhdl)
+  {
+    log_printf(FUNC,@COMPONENT,"vhdl_declaration","Begin");
+    log_printf(FUNC,@COMPONENT,"vhdl_declaration","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_port.cpp	(revision 3)
@@ -0,0 +1,28 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::vhdl_port (Vhdl & vhdl)
+  {
+    log_printf(FUNC,@COMPONENT,"vhdl_port","Begin");
+
+    vhdl.set_port (" in_CLOCK" , IN, 1);
+    vhdl.set_port (" in_NRESET", IN, 1);
+
+    log_printf(FUNC,@COMPONENT,"vhdl_port","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_label.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_label.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_label.cpp	(revision 3)
@@ -0,0 +1,27 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::vhdl_testbench_label (string label)
+  {
+    log_printf(FUNC,@COMPONENT,"vhdl_testbench_label","Begin");
+
+#ifdef VHDL_TESTBENCH
+    _vhdl_testbench->add_label(label);
+#endif
+    
+    log_printf(FUNC,@COMPONENT,"vhdl_testbench_label","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_port.cpp	(revision 3)
@@ -0,0 +1,25 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::vhdl_testbench_port ()
+  {
+    log_printf(FUNC,@COMPONENT,"vhdl_testbench_port","Begin");
+    _vhdl_testbench->set_port (" in_NRESET",IN ,1);
+    log_printf(FUNC,@COMPONENT,"vhdl_testbench_port","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_transition.cpp	(revision 3)
@@ -0,0 +1,41 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/@COMPONENT.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void @COMPONENT::vhdl_testbench_transition ()
+  {
+    log_printf(FUNC,@COMPONENT,"vhdl_testbench_transition","Begin");
+
+    // Evaluation before read the ouput signal
+    sc_start(0);
+
+    // In order with file @COMPONENT_vhdl_testbench_port.cpp
+    // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
+    // (because we have no control on the ordonnancer's policy)
+
+    _vhdl_testbench->add_input (PORT_READ( in_NRESET));
+    
+    // add_test :
+    //  - True  : the cycle must be compare with the output of systemC
+    //  - False : no test
+    _vhdl_testbench->add_test(true);
+
+    _vhdl_testbench->new_cycle (); // always at the end
+
+    log_printf(FUNC,@COMPONENT,"vhdl_testbench_transition","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,36 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/Parameters.h"
+
+namespace morpheo {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  Parameters::Parameters ()
+  {
+    log_printf(FUNC,@COMPONENT,"Parameters","Begin");
+    test();
+    log_printf(FUNC,@COMPONENT,"Parameters","End");
+  };
+  
+  Parameters::Parameters (Parameters & param)
+  {
+    log_printf(FUNC,@COMPONENT,"Parameters","Begin");
+    test();
+    log_printf(FUNC,@COMPONENT,"Parameters","End");
+  };
+
+  Parameters::~Parameters () 
+  {
+    log_printf(FUNC,@COMPONENT,"~Parameters","Begin");
+    log_printf(FUNC,@COMPONENT,"~Parameters","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters_msg_error.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters_msg_error.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters_msg_error.cpp	(revision 3)
@@ -0,0 +1,30 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/Parameters.h"
+#include "Behavioural/@DIRECTORY/include/Types.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  string Parameters::msg_error(void)
+  {
+    log_printf(FUNC,@COMPONENT,"msg_error","Begin");
+
+    string msg = "";
+
+    return msg;
+
+    log_printf(FUNC,@COMPONENT,"msg_error","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Parameters_print.cpp	(revision 3)
@@ -0,0 +1,46 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/Parameters.h"
+#include "Behavioural/include/XML.h"
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  string Parameters::print (uint32_t depth)
+  {
+    log_printf(FUNC,@COMPONENT,"print","Begin");
+
+    XML xml ("@COMPONENT_LOWER");
+
+    xml.balise_open("@COMPONENT_LOWER");
+//  xml.  singleton_begin("size_data");
+//  xml.    attribut("value",toString(_size_data));
+//  xml.  singleton_end();
+//  xml.  singleton_begin("nb_port  ");
+//  xml.    attribut("value",toString(_nb_port));
+//  xml.  singleton_end();
+    xml.balise_close();
+
+    log_printf(FUNC,@COMPONENT,"print","End");
+    
+    return xml.get_body(depth);
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::@NAMESPACE_USE::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,36 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+    log_printf(FUNC,@COMPONENT,"Statistics","Begin");
+    log_printf(FUNC,@COMPONENT,"Statistics","End");
+  };
+  
+  Statistics::~Statistics () 
+  { 
+    log_printf(FUNC,@COMPONENT,"~Statistics","Begin");
+    log_printf(FUNC,@COMPONENT,"~Statistics","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,27 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  void Statistics::add ()
+  {
+    log_printf(FUNC,@COMPONENT,"add","Begin");
+    log_printf(FUNC,@COMPONENT,"add","End");
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  string Statistics::print (uint32_t depth)
+  {
+    log_printf(FUNC,@COMPONENT,"print","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<@COMPONENT_LOWER name=\"" << _name << "\" >" << endl
+        << print_body(depth+1) << endl
+	<< tab << "</@COMPONENT_LOWER>" << endl;
+    
+    log_printf(FUNC,@COMPONENT,"print","End");
+
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::@NAMESPACE_USE::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/@DIRECTORY/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+@NAMESPACE_BEGIN
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    log_printf(FUNC,@COMPONENT,"print_body","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "";
+    
+    log_printf(FUNC,@COMPONENT,"print_body","End");
+
+    return msg.str();
+  };
+
+@NAMESPACE_END
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/Makefile	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../../../..
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libBranch_History_Table.a
+
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.deps	(revision 3)
@@ -0,0 +1,45 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+ifndef Shifter
+include 			$(DIR_MORPHEO)/Behavioural/Generic/Shifter/Makefile.deps
+endif
+ifndef RegisterFile
+include 			$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/Makefile.deps
+endif
+
+Branch_History_Table			= yes
+
+#-----[ Library ]------------------------------------------
+Branch_History_Table_LIBRARY		= 	-lBranch_History_Table	\
+						$(RegisterFile_LIBRARY)	\
+						$(Shifter_LIBRARY)	\
+						$(Behavioural_LIBRARY)	
+
+Branch_History_Table_DIR_LIBRARY	=	-L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/lib	\
+						$(RegisterFile_DIR_LIBRARY)	\
+						$(Shifter_DIR_LIBRARY)		\
+						$(Behavioural_DIR_LIBRARY)
+
+#-----[ Rules ]--------------------------------------------
+
+Branch_History_Table_library		: 
+					@$(MAKE) Behavioural_library
+					@$(MAKE) Shifter_library
+					@$(MAKE) RegisterFile_library
+					@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table --makefile=Makefile 
+
+Branch_History_Table_library_clean	: 
+					@$(MAKE) Behavioural_library_clean
+					@$(MAKE) Shifter_library_clean
+					@$(MAKE) RegisterFile_library_clean
+					@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,29 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../../../../..
+
+LIBRARY				= $(Branch_History_Table_LIBRARY)
+
+DIR_LIBRARY			= $(Branch_History_Table_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				: library
+				@$(MAKE) all_selftest
+
+library				: Branch_History_Table_library
+
+library_clean			: Branch_History_Table_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/configuration.cfg	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/configuration.cfg	(revision 3)
@@ -0,0 +1,5 @@
+Branch_History_Table
+2	8	*2	# size_shifter      	
+2	64	*4	# nb_shifter        
+1	2	+1	# nb_prediction     
+1	2	+1	# nb_branch_complete
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h	(revision 3)
@@ -0,0 +1,29 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::stage_1_ifetch;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor;
+
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table;
+
+void test   (string name,
+	     morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters param);
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/mkf.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/mkf.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/mkf.info	(revision 3)
@@ -0,0 +1,181 @@
+
+# Branch_History_Table_0
+target_dep	all	Branch_History_Table_0.ngc
+target_dep	Branch_History_Table_0.ngc	Branch_History_Table_0.prj
+target_dep	Branch_History_Table_0.prj	Branch_History_Table_0_Pack.vhdl Branch_History_Table_0_RegisterFile_Pack.vhdl Branch_History_Table_0_RegisterFile.vhdl Branch_History_Table_0_Shifter_Pack.vhdl Branch_History_Table_0_Shifter.vhdl Branch_History_Table_0.vhdl
+
+# Branch_History_Table_10
+target_dep	all	Branch_History_Table_10.ngc
+target_dep	Branch_History_Table_10.ngc	Branch_History_Table_10.prj
+target_dep	Branch_History_Table_10.prj	Branch_History_Table_10_Pack.vhdl Branch_History_Table_10_RegisterFile_Pack.vhdl Branch_History_Table_10_RegisterFile.vhdl Branch_History_Table_10_Shifter_Pack.vhdl Branch_History_Table_10_Shifter.vhdl Branch_History_Table_10.vhdl
+
+# Branch_History_Table_11
+target_dep	all	Branch_History_Table_11.ngc
+target_dep	Branch_History_Table_11.ngc	Branch_History_Table_11.prj
+target_dep	Branch_History_Table_11.prj	Branch_History_Table_11_Pack.vhdl Branch_History_Table_11_RegisterFile_Pack.vhdl Branch_History_Table_11_RegisterFile.vhdl Branch_History_Table_11_Shifter_Pack.vhdl Branch_History_Table_11_Shifter.vhdl Branch_History_Table_11.vhdl
+
+# Branch_History_Table_12
+target_dep	all	Branch_History_Table_12.ngc
+target_dep	Branch_History_Table_12.ngc	Branch_History_Table_12.prj
+target_dep	Branch_History_Table_12.prj	Branch_History_Table_12_Pack.vhdl Branch_History_Table_12_RegisterFile_Pack.vhdl Branch_History_Table_12_RegisterFile.vhdl Branch_History_Table_12_Shifter_Pack.vhdl Branch_History_Table_12_Shifter.vhdl Branch_History_Table_12.vhdl
+
+# Branch_History_Table_13
+target_dep	all	Branch_History_Table_13.ngc
+target_dep	Branch_History_Table_13.ngc	Branch_History_Table_13.prj
+target_dep	Branch_History_Table_13.prj	Branch_History_Table_13_Pack.vhdl Branch_History_Table_13_RegisterFile_Pack.vhdl Branch_History_Table_13_RegisterFile.vhdl Branch_History_Table_13_Shifter_Pack.vhdl Branch_History_Table_13_Shifter.vhdl Branch_History_Table_13.vhdl
+
+# Branch_History_Table_14
+target_dep	all	Branch_History_Table_14.ngc
+target_dep	Branch_History_Table_14.ngc	Branch_History_Table_14.prj
+target_dep	Branch_History_Table_14.prj	Branch_History_Table_14_Pack.vhdl Branch_History_Table_14_RegisterFile_Pack.vhdl Branch_History_Table_14_RegisterFile.vhdl Branch_History_Table_14_Shifter_Pack.vhdl Branch_History_Table_14_Shifter.vhdl Branch_History_Table_14.vhdl
+
+# Branch_History_Table_15
+target_dep	all	Branch_History_Table_15.ngc
+target_dep	Branch_History_Table_15.ngc	Branch_History_Table_15.prj
+target_dep	Branch_History_Table_15.prj	Branch_History_Table_15_Pack.vhdl Branch_History_Table_15_RegisterFile_Pack.vhdl Branch_History_Table_15_RegisterFile.vhdl Branch_History_Table_15_Shifter_Pack.vhdl Branch_History_Table_15_Shifter.vhdl Branch_History_Table_15.vhdl
+
+# Branch_History_Table_16
+target_dep	all	Branch_History_Table_16.ngc
+target_dep	Branch_History_Table_16.ngc	Branch_History_Table_16.prj
+target_dep	Branch_History_Table_16.prj	Branch_History_Table_16_Pack.vhdl Branch_History_Table_16_RegisterFile_Pack.vhdl Branch_History_Table_16_RegisterFile.vhdl Branch_History_Table_16_Shifter_Pack.vhdl Branch_History_Table_16_Shifter.vhdl Branch_History_Table_16.vhdl
+
+# Branch_History_Table_17
+target_dep	all	Branch_History_Table_17.ngc
+target_dep	Branch_History_Table_17.ngc	Branch_History_Table_17.prj
+target_dep	Branch_History_Table_17.prj	Branch_History_Table_17_Pack.vhdl Branch_History_Table_17_RegisterFile_Pack.vhdl Branch_History_Table_17_RegisterFile.vhdl Branch_History_Table_17_Shifter_Pack.vhdl Branch_History_Table_17_Shifter.vhdl Branch_History_Table_17.vhdl
+
+# Branch_History_Table_18
+target_dep	all	Branch_History_Table_18.ngc
+target_dep	Branch_History_Table_18.ngc	Branch_History_Table_18.prj
+target_dep	Branch_History_Table_18.prj	Branch_History_Table_18_Pack.vhdl Branch_History_Table_18_RegisterFile_Pack.vhdl Branch_History_Table_18_RegisterFile.vhdl Branch_History_Table_18_Shifter_Pack.vhdl Branch_History_Table_18_Shifter.vhdl Branch_History_Table_18.vhdl
+
+# Branch_History_Table_19
+target_dep	all	Branch_History_Table_19.ngc
+target_dep	Branch_History_Table_19.ngc	Branch_History_Table_19.prj
+target_dep	Branch_History_Table_19.prj	Branch_History_Table_19_Pack.vhdl Branch_History_Table_19_RegisterFile_Pack.vhdl Branch_History_Table_19_RegisterFile.vhdl Branch_History_Table_19_Shifter_Pack.vhdl Branch_History_Table_19_Shifter.vhdl Branch_History_Table_19.vhdl
+
+# Branch_History_Table_1
+target_dep	all	Branch_History_Table_1.ngc
+target_dep	Branch_History_Table_1.ngc	Branch_History_Table_1.prj
+target_dep	Branch_History_Table_1.prj	Branch_History_Table_10_Pack.vhdl Branch_History_Table_10_RegisterFile_Pack.vhdl Branch_History_Table_10_RegisterFile.vhdl Branch_History_Table_10_Shifter_Pack.vhdl Branch_History_Table_10_Shifter.vhdl Branch_History_Table_10.vhdl Branch_History_Table_11_Pack.vhdl Branch_History_Table_11_RegisterFile_Pack.vhdl Branch_History_Table_11_RegisterFile.vhdl Branch_History_Table_11_Shifter_Pack.vhdl Branch_History_Table_11_Shifter.vhdl Branch_History_Table_11.vhdl Branch_History_Table_12_Pack.vhdl Branch_History_Table_12_RegisterFile_Pack.vhdl Branch_History_Table_12_RegisterFile.vhdl Branch_History_Table_12_Shifter_Pack.vhdl Branch_History_Table_12_Shifter.vhdl Branch_History_Table_12.vhdl Branch_History_Table_13_Pack.vhdl Branch_History_Table_13_RegisterFile_Pack.vhdl Branch_History_Table_13_RegisterFile.vhdl Branch_History_Table_13_Shifter_Pack.vhdl Branch_History_Table_13_Shifter.vhdl Branch_History_Table_13.vhdl Branch_History_Table_14_Pack.vhdl Branch_History_Table_14_RegisterFile_Pack.vhdl Branch_History_Table_14_RegisterFile.vhdl Branch_History_Table_14_Shifter_Pack.vhdl Branch_History_Table_14_Shifter.vhdl Branch_History_Table_14.vhdl Branch_History_Table_15_Pack.vhdl Branch_History_Table_15_RegisterFile_Pack.vhdl Branch_History_Table_15_RegisterFile.vhdl Branch_History_Table_15_Shifter_Pack.vhdl Branch_History_Table_15_Shifter.vhdl Branch_History_Table_15.vhdl Branch_History_Table_16_Pack.vhdl Branch_History_Table_16_RegisterFile_Pack.vhdl Branch_History_Table_16_RegisterFile.vhdl Branch_History_Table_16_Shifter_Pack.vhdl Branch_History_Table_16_Shifter.vhdl Branch_History_Table_16.vhdl Branch_History_Table_17_Pack.vhdl Branch_History_Table_17_RegisterFile_Pack.vhdl Branch_History_Table_17_RegisterFile.vhdl Branch_History_Table_17_Shifter_Pack.vhdl Branch_History_Table_17_Shifter.vhdl Branch_History_Table_17.vhdl Branch_History_Table_18_Pack.vhdl Branch_History_Table_18_RegisterFile_Pack.vhdl Branch_History_Table_18_RegisterFile.vhdl Branch_History_Table_18_Shifter_Pack.vhdl Branch_History_Table_18_Shifter.vhdl Branch_History_Table_18.vhdl Branch_History_Table_19_Pack.vhdl Branch_History_Table_19_RegisterFile_Pack.vhdl Branch_History_Table_19_RegisterFile.vhdl Branch_History_Table_19_Shifter_Pack.vhdl Branch_History_Table_19_Shifter.vhdl Branch_History_Table_19.vhdl Branch_History_Table_1_Pack.vhdl Branch_History_Table_1_RegisterFile_Pack.vhdl Branch_History_Table_1_RegisterFile.vhdl Branch_History_Table_1_Shifter_Pack.vhdl Branch_History_Table_1_Shifter.vhdl Branch_History_Table_1.vhdl
+
+# Branch_History_Table_20
+target_dep	all	Branch_History_Table_20.ngc
+target_dep	Branch_History_Table_20.ngc	Branch_History_Table_20.prj
+target_dep	Branch_History_Table_20.prj	Branch_History_Table_20_Pack.vhdl Branch_History_Table_20_RegisterFile_Pack.vhdl Branch_History_Table_20_RegisterFile.vhdl Branch_History_Table_20_Shifter_Pack.vhdl Branch_History_Table_20_Shifter.vhdl Branch_History_Table_20.vhdl
+
+# Branch_History_Table_21
+target_dep	all	Branch_History_Table_21.ngc
+target_dep	Branch_History_Table_21.ngc	Branch_History_Table_21.prj
+target_dep	Branch_History_Table_21.prj	Branch_History_Table_21_Pack.vhdl Branch_History_Table_21_RegisterFile_Pack.vhdl Branch_History_Table_21_RegisterFile.vhdl Branch_History_Table_21_Shifter_Pack.vhdl Branch_History_Table_21_Shifter.vhdl Branch_History_Table_21.vhdl
+
+# Branch_History_Table_22
+target_dep	all	Branch_History_Table_22.ngc
+target_dep	Branch_History_Table_22.ngc	Branch_History_Table_22.prj
+target_dep	Branch_History_Table_22.prj	Branch_History_Table_22_Pack.vhdl Branch_History_Table_22_RegisterFile_Pack.vhdl Branch_History_Table_22_RegisterFile.vhdl Branch_History_Table_22_Shifter_Pack.vhdl Branch_History_Table_22_Shifter.vhdl Branch_History_Table_22.vhdl
+
+# Branch_History_Table_23
+target_dep	all	Branch_History_Table_23.ngc
+target_dep	Branch_History_Table_23.ngc	Branch_History_Table_23.prj
+target_dep	Branch_History_Table_23.prj	Branch_History_Table_23_Pack.vhdl Branch_History_Table_23_RegisterFile_Pack.vhdl Branch_History_Table_23_RegisterFile.vhdl Branch_History_Table_23_Shifter_Pack.vhdl Branch_History_Table_23_Shifter.vhdl Branch_History_Table_23.vhdl
+
+# Branch_History_Table_24
+target_dep	all	Branch_History_Table_24.ngc
+target_dep	Branch_History_Table_24.ngc	Branch_History_Table_24.prj
+target_dep	Branch_History_Table_24.prj	Branch_History_Table_24_Pack.vhdl Branch_History_Table_24_RegisterFile_Pack.vhdl Branch_History_Table_24_RegisterFile.vhdl Branch_History_Table_24_Shifter_Pack.vhdl Branch_History_Table_24_Shifter.vhdl Branch_History_Table_24.vhdl
+
+# Branch_History_Table_25
+target_dep	all	Branch_History_Table_25.ngc
+target_dep	Branch_History_Table_25.ngc	Branch_History_Table_25.prj
+target_dep	Branch_History_Table_25.prj	Branch_History_Table_25_Pack.vhdl Branch_History_Table_25_RegisterFile_Pack.vhdl Branch_History_Table_25_RegisterFile.vhdl Branch_History_Table_25_Shifter_Pack.vhdl Branch_History_Table_25_Shifter.vhdl Branch_History_Table_25.vhdl
+
+# Branch_History_Table_26
+target_dep	all	Branch_History_Table_26.ngc
+target_dep	Branch_History_Table_26.ngc	Branch_History_Table_26.prj
+target_dep	Branch_History_Table_26.prj	Branch_History_Table_26_Pack.vhdl Branch_History_Table_26_RegisterFile_Pack.vhdl Branch_History_Table_26_RegisterFile.vhdl Branch_History_Table_26_Shifter_Pack.vhdl Branch_History_Table_26_Shifter.vhdl Branch_History_Table_26.vhdl
+
+# Branch_History_Table_27
+target_dep	all	Branch_History_Table_27.ngc
+target_dep	Branch_History_Table_27.ngc	Branch_History_Table_27.prj
+target_dep	Branch_History_Table_27.prj	Branch_History_Table_27_Pack.vhdl Branch_History_Table_27_RegisterFile_Pack.vhdl Branch_History_Table_27_RegisterFile.vhdl Branch_History_Table_27_Shifter_Pack.vhdl Branch_History_Table_27_Shifter.vhdl Branch_History_Table_27.vhdl
+
+# Branch_History_Table_28
+target_dep	all	Branch_History_Table_28.ngc
+target_dep	Branch_History_Table_28.ngc	Branch_History_Table_28.prj
+target_dep	Branch_History_Table_28.prj	Branch_History_Table_28_Pack.vhdl Branch_History_Table_28_RegisterFile_Pack.vhdl Branch_History_Table_28_RegisterFile.vhdl Branch_History_Table_28_Shifter_Pack.vhdl Branch_History_Table_28_Shifter.vhdl Branch_History_Table_28.vhdl
+
+# Branch_History_Table_29
+target_dep	all	Branch_History_Table_29.ngc
+target_dep	Branch_History_Table_29.ngc	Branch_History_Table_29.prj
+target_dep	Branch_History_Table_29.prj	Branch_History_Table_29_Pack.vhdl Branch_History_Table_29_RegisterFile_Pack.vhdl Branch_History_Table_29_RegisterFile.vhdl Branch_History_Table_29_Shifter_Pack.vhdl Branch_History_Table_29_Shifter.vhdl Branch_History_Table_29.vhdl
+
+# Branch_History_Table_2
+target_dep	all	Branch_History_Table_2.ngc
+target_dep	Branch_History_Table_2.ngc	Branch_History_Table_2.prj
+target_dep	Branch_History_Table_2.prj	Branch_History_Table_20_Pack.vhdl Branch_History_Table_20_RegisterFile_Pack.vhdl Branch_History_Table_20_RegisterFile.vhdl Branch_History_Table_20_Shifter_Pack.vhdl Branch_History_Table_20_Shifter.vhdl Branch_History_Table_20.vhdl Branch_History_Table_21_Pack.vhdl Branch_History_Table_21_RegisterFile_Pack.vhdl Branch_History_Table_21_RegisterFile.vhdl Branch_History_Table_21_Shifter_Pack.vhdl Branch_History_Table_21_Shifter.vhdl Branch_History_Table_21.vhdl Branch_History_Table_22_Pack.vhdl Branch_History_Table_22_RegisterFile_Pack.vhdl Branch_History_Table_22_RegisterFile.vhdl Branch_History_Table_22_Shifter_Pack.vhdl Branch_History_Table_22_Shifter.vhdl Branch_History_Table_22.vhdl Branch_History_Table_23_Pack.vhdl Branch_History_Table_23_RegisterFile_Pack.vhdl Branch_History_Table_23_RegisterFile.vhdl Branch_History_Table_23_Shifter_Pack.vhdl Branch_History_Table_23_Shifter.vhdl Branch_History_Table_23.vhdl Branch_History_Table_24_Pack.vhdl Branch_History_Table_24_RegisterFile_Pack.vhdl Branch_History_Table_24_RegisterFile.vhdl Branch_History_Table_24_Shifter_Pack.vhdl Branch_History_Table_24_Shifter.vhdl Branch_History_Table_24.vhdl Branch_History_Table_25_Pack.vhdl Branch_History_Table_25_RegisterFile_Pack.vhdl Branch_History_Table_25_RegisterFile.vhdl Branch_History_Table_25_Shifter_Pack.vhdl Branch_History_Table_25_Shifter.vhdl Branch_History_Table_25.vhdl Branch_History_Table_26_Pack.vhdl Branch_History_Table_26_RegisterFile_Pack.vhdl Branch_History_Table_26_RegisterFile.vhdl Branch_History_Table_26_Shifter_Pack.vhdl Branch_History_Table_26_Shifter.vhdl Branch_History_Table_26.vhdl Branch_History_Table_27_Pack.vhdl Branch_History_Table_27_RegisterFile_Pack.vhdl Branch_History_Table_27_RegisterFile.vhdl Branch_History_Table_27_Shifter_Pack.vhdl Branch_History_Table_27_Shifter.vhdl Branch_History_Table_27.vhdl Branch_History_Table_28_Pack.vhdl Branch_History_Table_28_RegisterFile_Pack.vhdl Branch_History_Table_28_RegisterFile.vhdl Branch_History_Table_28_Shifter_Pack.vhdl Branch_History_Table_28_Shifter.vhdl Branch_History_Table_28.vhdl Branch_History_Table_29_Pack.vhdl Branch_History_Table_29_RegisterFile_Pack.vhdl Branch_History_Table_29_RegisterFile.vhdl Branch_History_Table_29_Shifter_Pack.vhdl Branch_History_Table_29_Shifter.vhdl Branch_History_Table_29.vhdl Branch_History_Table_2_Pack.vhdl Branch_History_Table_2_RegisterFile_Pack.vhdl Branch_History_Table_2_RegisterFile.vhdl Branch_History_Table_2_Shifter_Pack.vhdl Branch_History_Table_2_Shifter.vhdl Branch_History_Table_2.vhdl
+
+# Branch_History_Table_30
+target_dep	all	Branch_History_Table_30.ngc
+target_dep	Branch_History_Table_30.ngc	Branch_History_Table_30.prj
+target_dep	Branch_History_Table_30.prj	Branch_History_Table_30_Pack.vhdl Branch_History_Table_30_RegisterFile_Pack.vhdl Branch_History_Table_30_RegisterFile.vhdl Branch_History_Table_30_Shifter_Pack.vhdl Branch_History_Table_30_Shifter.vhdl Branch_History_Table_30.vhdl
+
+# Branch_History_Table_31
+target_dep	all	Branch_History_Table_31.ngc
+target_dep	Branch_History_Table_31.ngc	Branch_History_Table_31.prj
+target_dep	Branch_History_Table_31.prj	Branch_History_Table_31_Pack.vhdl Branch_History_Table_31_RegisterFile_Pack.vhdl Branch_History_Table_31_RegisterFile.vhdl Branch_History_Table_31_Shifter_Pack.vhdl Branch_History_Table_31_Shifter.vhdl Branch_History_Table_31.vhdl
+
+# Branch_History_Table_32
+target_dep	all	Branch_History_Table_32.ngc
+target_dep	Branch_History_Table_32.ngc	Branch_History_Table_32.prj
+target_dep	Branch_History_Table_32.prj	Branch_History_Table_32_Pack.vhdl Branch_History_Table_32_RegisterFile_Pack.vhdl Branch_History_Table_32_RegisterFile.vhdl Branch_History_Table_32_Shifter_Pack.vhdl Branch_History_Table_32_Shifter.vhdl Branch_History_Table_32.vhdl
+
+# Branch_History_Table_33
+target_dep	all	Branch_History_Table_33.ngc
+target_dep	Branch_History_Table_33.ngc	Branch_History_Table_33.prj
+target_dep	Branch_History_Table_33.prj	Branch_History_Table_33_Pack.vhdl Branch_History_Table_33_RegisterFile_Pack.vhdl Branch_History_Table_33_RegisterFile.vhdl Branch_History_Table_33_Shifter_Pack.vhdl Branch_History_Table_33_Shifter.vhdl Branch_History_Table_33.vhdl
+
+# Branch_History_Table_34
+target_dep	all	Branch_History_Table_34.ngc
+target_dep	Branch_History_Table_34.ngc	Branch_History_Table_34.prj
+target_dep	Branch_History_Table_34.prj	Branch_History_Table_34_Pack.vhdl Branch_History_Table_34_RegisterFile_Pack.vhdl Branch_History_Table_34_RegisterFile.vhdl Branch_History_Table_34_Shifter_Pack.vhdl Branch_History_Table_34_Shifter.vhdl Branch_History_Table_34.vhdl
+
+# Branch_History_Table_35
+target_dep	all	Branch_History_Table_35.ngc
+target_dep	Branch_History_Table_35.ngc	Branch_History_Table_35.prj
+target_dep	Branch_History_Table_35.prj	Branch_History_Table_35_Pack.vhdl Branch_History_Table_35_RegisterFile_Pack.vhdl Branch_History_Table_35_RegisterFile.vhdl Branch_History_Table_35_Shifter_Pack.vhdl Branch_History_Table_35_Shifter.vhdl Branch_History_Table_35.vhdl
+
+# Branch_History_Table_3
+target_dep	all	Branch_History_Table_3.ngc
+target_dep	Branch_History_Table_3.ngc	Branch_History_Table_3.prj
+target_dep	Branch_History_Table_3.prj	Branch_History_Table_30_Pack.vhdl Branch_History_Table_30_RegisterFile_Pack.vhdl Branch_History_Table_30_RegisterFile.vhdl Branch_History_Table_30_Shifter_Pack.vhdl Branch_History_Table_30_Shifter.vhdl Branch_History_Table_30.vhdl Branch_History_Table_31_Pack.vhdl Branch_History_Table_31_RegisterFile_Pack.vhdl Branch_History_Table_31_RegisterFile.vhdl Branch_History_Table_31_Shifter_Pack.vhdl Branch_History_Table_31_Shifter.vhdl Branch_History_Table_31.vhdl Branch_History_Table_32_Pack.vhdl Branch_History_Table_32_RegisterFile_Pack.vhdl Branch_History_Table_32_RegisterFile.vhdl Branch_History_Table_32_Shifter_Pack.vhdl Branch_History_Table_32_Shifter.vhdl Branch_History_Table_32.vhdl Branch_History_Table_33_Pack.vhdl Branch_History_Table_33_RegisterFile_Pack.vhdl Branch_History_Table_33_RegisterFile.vhdl Branch_History_Table_33_Shifter_Pack.vhdl Branch_History_Table_33_Shifter.vhdl Branch_History_Table_33.vhdl Branch_History_Table_34_Pack.vhdl Branch_History_Table_34_RegisterFile_Pack.vhdl Branch_History_Table_34_RegisterFile.vhdl Branch_History_Table_34_Shifter_Pack.vhdl Branch_History_Table_34_Shifter.vhdl Branch_History_Table_34.vhdl Branch_History_Table_35_Pack.vhdl Branch_History_Table_35_RegisterFile_Pack.vhdl Branch_History_Table_35_RegisterFile.vhdl Branch_History_Table_35_Shifter_Pack.vhdl Branch_History_Table_35_Shifter.vhdl Branch_History_Table_35.vhdl Branch_History_Table_3_Pack.vhdl Branch_History_Table_3_RegisterFile_Pack.vhdl Branch_History_Table_3_RegisterFile.vhdl Branch_History_Table_3_Shifter_Pack.vhdl Branch_History_Table_3_Shifter.vhdl Branch_History_Table_3.vhdl
+
+# Branch_History_Table_4
+target_dep	all	Branch_History_Table_4.ngc
+target_dep	Branch_History_Table_4.ngc	Branch_History_Table_4.prj
+target_dep	Branch_History_Table_4.prj	Branch_History_Table_4_Pack.vhdl Branch_History_Table_4_RegisterFile_Pack.vhdl Branch_History_Table_4_RegisterFile.vhdl Branch_History_Table_4_Shifter_Pack.vhdl Branch_History_Table_4_Shifter.vhdl Branch_History_Table_4.vhdl
+
+# Branch_History_Table_5
+target_dep	all	Branch_History_Table_5.ngc
+target_dep	Branch_History_Table_5.ngc	Branch_History_Table_5.prj
+target_dep	Branch_History_Table_5.prj	Branch_History_Table_5_Pack.vhdl Branch_History_Table_5_RegisterFile_Pack.vhdl Branch_History_Table_5_RegisterFile.vhdl Branch_History_Table_5_Shifter_Pack.vhdl Branch_History_Table_5_Shifter.vhdl Branch_History_Table_5.vhdl
+
+# Branch_History_Table_6
+target_dep	all	Branch_History_Table_6.ngc
+target_dep	Branch_History_Table_6.ngc	Branch_History_Table_6.prj
+target_dep	Branch_History_Table_6.prj	Branch_History_Table_6_Pack.vhdl Branch_History_Table_6_RegisterFile_Pack.vhdl Branch_History_Table_6_RegisterFile.vhdl Branch_History_Table_6_Shifter_Pack.vhdl Branch_History_Table_6_Shifter.vhdl Branch_History_Table_6.vhdl
+
+# Branch_History_Table_7
+target_dep	all	Branch_History_Table_7.ngc
+target_dep	Branch_History_Table_7.ngc	Branch_History_Table_7.prj
+target_dep	Branch_History_Table_7.prj	Branch_History_Table_7_Pack.vhdl Branch_History_Table_7_RegisterFile_Pack.vhdl Branch_History_Table_7_RegisterFile.vhdl Branch_History_Table_7_Shifter_Pack.vhdl Branch_History_Table_7_Shifter.vhdl Branch_History_Table_7.vhdl
+
+# Branch_History_Table_8
+target_dep	all	Branch_History_Table_8.ngc
+target_dep	Branch_History_Table_8.ngc	Branch_History_Table_8.prj
+target_dep	Branch_History_Table_8.prj	Branch_History_Table_8_Pack.vhdl Branch_History_Table_8_RegisterFile_Pack.vhdl Branch_History_Table_8_RegisterFile.vhdl Branch_History_Table_8_Shifter_Pack.vhdl Branch_History_Table_8_Shifter.vhdl Branch_History_Table_8.vhdl
+
+# Branch_History_Table_9
+target_dep	all	Branch_History_Table_9.ngc
+target_dep	Branch_History_Table_9.ngc	Branch_History_Table_9.prj
+target_dep	Branch_History_Table_9.prj	Branch_History_Table_9_Pack.vhdl Branch_History_Table_9_RegisterFile_Pack.vhdl Branch_History_Table_9_RegisterFile.vhdl Branch_History_Table_9_Shifter_Pack.vhdl Branch_History_Table_9_Shifter.vhdl Branch_History_Table_9.vhdl
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,47 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test 0
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h"
+
+#define NB_PARAMS 4
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - size_shifter       (unsigned int)" << endl
+       << " - nb_shifter         (unsigned int)" << endl
+       << " - nb_prediction      (unsigned int)" << endl
+       << " - nb_branch_complete (unsigned int)" << endl;
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc != 2+NB_PARAMS)
+    usage (argv[0]);
+
+  const string   name               = argv[1];
+  const uint32_t size_shifter       = atoi(argv[2]);
+  const uint32_t nb_shifter         = atoi(argv[3]);
+  const uint32_t nb_prediction      = atoi(argv[4]);
+  const uint32_t nb_branch_complete = atoi(argv[5]);
+
+  morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters param (size_shifter       ,
+																       nb_shifter         ,
+																       nb_prediction      ,
+																       nb_branch_complete );
+
+  test (name,param);
+
+  return (EXIT_SUCCESS);
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/test.cpp	(revision 3)
@@ -0,0 +1,190 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#define NB_ITERATION 1024
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h"
+#include "Include/BitManipulation.h"
+#include "Include/Test.h"
+
+void test (string name,
+	   morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  try 
+    {
+      cout << param.print(1);
+      param.test();
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      return;
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+
+  Branch_History_Table * _Branch_History_Table = new Branch_History_Table (name.c_str(),
+#ifdef STATISTICS
+					     morpheo::behavioural::Parameters_Statistics(5,50),
+#endif
+					     param);
+  
+#ifdef SYSTEMC
+
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                                 CLOCK ("clock", 1.0, 0.5);
+  sc_signal<Tcontrol_t>                    PREDICT_VAL               [param._nb_prediction];
+  sc_signal<Tcontrol_t>                    PREDICT_ACK               [param._nb_prediction];
+  sc_signal<Taddress_t>                    PREDICT_ADDRESS           [param._nb_prediction];
+  sc_signal<Thistory_t>                    PREDICT_HISTORY           [param._nb_prediction];
+				           			     
+  sc_signal<Tcontrol_t>                    BRANCH_COMPLETE_VAL       [param._nb_branch_complete];
+  sc_signal<Tcontrol_t>                    BRANCH_COMPLETE_ACK       [param._nb_branch_complete];
+  sc_signal<Taddress_t>                    BRANCH_COMPLETE_ADDRESS   [param._nb_branch_complete];
+  sc_signal<Thistory_t>                    BRANCH_COMPLETE_HISTORY   [param._nb_branch_complete];
+  sc_signal<Tcontrol_t>                    BRANCH_COMPLETE_DIRECTION [param._nb_branch_complete];
+  
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Branch_History_Table" << endl;
+  
+  (*(_Branch_History_Table->in_CLOCK))        (CLOCK);
+
+  for (uint32_t i=0; i<param._nb_prediction; i++)
+    {
+      (*(_Branch_History_Table-> in_PREDICT_VAL     [i]))        (PREDICT_VAL     [i]);
+      (*(_Branch_History_Table->out_PREDICT_ACK     [i]))        (PREDICT_ACK     [i]);
+      (*(_Branch_History_Table-> in_PREDICT_ADDRESS [i]))        (PREDICT_ADDRESS [i]);
+      (*(_Branch_History_Table->out_PREDICT_HISTORY [i]))        (PREDICT_HISTORY [i]);
+    }
+
+  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+    {
+      (*(_Branch_History_Table-> in_BRANCH_COMPLETE_VAL       [i]))        (BRANCH_COMPLETE_VAL       [i]);
+      (*(_Branch_History_Table->out_BRANCH_COMPLETE_ACK       [i]))        (BRANCH_COMPLETE_ACK       [i]);
+      (*(_Branch_History_Table-> in_BRANCH_COMPLETE_ADDRESS   [i]))        (BRANCH_COMPLETE_ADDRESS   [i]);
+      (*(_Branch_History_Table-> in_BRANCH_COMPLETE_HISTORY   [i]))        (BRANCH_COMPLETE_HISTORY   [i]);
+      (*(_Branch_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i]))        (BRANCH_COMPLETE_DIRECTION [i]);
+    }
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  // Initialisation
+  sc_start(0);
+
+  srand(0);
+  //srand(time(NULL));
+
+  
+  _Branch_History_Table->vhdl_testbench_label("Initialisation");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl;
+
+  for (uint32_t i=0; i<param._nb_prediction; i++)
+    PREDICT_VAL         [i].write(0);
+  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+    BRANCH_COMPLETE_VAL [i].write(0);
+
+  // Initialisation of Register
+  uint32_t   num_port_branch_complete = 0;
+  uint32_t   num_port_predict         = 0;
+  Taddress_t address                  = 0;
+  Thistory_t history                  = 0;
+  Thistory_t mask                     = gen_mask <Thistory_t> (param._size_shifter);
+  Tcontrol_t direction                = 0;
+
+  while (address<param._nb_shifter)
+    {
+      BRANCH_COMPLETE_VAL       [0].write(1);
+      BRANCH_COMPLETE_ADDRESS   [0].write(address);
+      BRANCH_COMPLETE_HISTORY   [0].write(0);
+      BRANCH_COMPLETE_DIRECTION [0].write(0);
+
+      sc_start(1);
+      
+      if (BRANCH_COMPLETE_ACK[0].read()==1)
+	address++;
+    }
+ 
+  BRANCH_COMPLETE_VAL     [0].write(0);
+  sc_start(0);
+
+  _Branch_History_Table->vhdl_testbench_label("Loop of Test");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl;
+
+  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+    {
+      _Branch_History_Table->vhdl_testbench_label("Iteration "+toString(iteration));
+      num_port_branch_complete = rand() % param._nb_branch_complete;
+      num_port_predict         = rand() % param._nb_prediction     ;
+      address                  = rand() % param._nb_shifter        ;
+      history                  = rand() % (1<<param._size_shifter) ;
+      direction                = rand() % 2;
+
+      cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} ["+toString(num_port_branch_complete)+"]" << endl
+	   << hex
+	   << " - address     : " << address  << endl
+	   << " - history old : " << history  << endl
+	   << " - direction   : " << direction<< endl;
+
+      BRANCH_COMPLETE_VAL       [num_port_branch_complete].write(1);
+      BRANCH_COMPLETE_ADDRESS   [num_port_branch_complete].write(address);
+      BRANCH_COMPLETE_HISTORY   [num_port_branch_complete].write(history);
+      BRANCH_COMPLETE_DIRECTION [num_port_branch_complete].write(direction);
+
+      // Wait Ack
+      do
+	{
+	  sc_start(1);
+	}
+      while (BRANCH_COMPLETE_ACK[num_port_branch_complete].read()!=1);
+
+      BRANCH_COMPLETE_VAL     [num_port_branch_complete].write(0);
+      PREDICT_VAL             [num_port_predict        ].write(1);
+      PREDICT_ADDRESS         [num_port_predict        ].write(address);
+      
+      history                  = ((history<<1)&mask)|direction;
+      
+      // Wait Ack
+      do
+	{
+	  sc_start(1);
+	}
+      while (PREDICT_ACK        [num_port_predict        ].read()!=1);
+
+      PREDICT_VAL             [num_port_predict        ].write(0);
+
+      cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} ["+toString(num_port_predict)+"]" << endl
+	   << " - history new : " << PREDICT_HISTORY [num_port_predict].read() << endl;
+
+      TEST(Thistory_t,PREDICT_HISTORY [num_port_predict].read(),history);
+
+      cout << dec;
+    }
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete _Branch_History_Table;
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/VERSION
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/VERSION	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/VERSION	(revision 3)
@@ -0,0 +1,1 @@
+v0.1
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h	(revision 3)
@@ -0,0 +1,147 @@
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Branch_History_Table_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Branch_History_Table_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include "Include/ToString.h"
+#include "Include/Debug.h"
+
+// Internal structure
+#include "Behavioural/Generic/Shifter/include/Shifter.h"
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h"
+#endif
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#ifdef VHDL_TESTBENCH
+#include "Behavioural/include/Vhdl_Testbench.h"
+#endif
+
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  class Branch_History_Table 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string     _name;
+
+  protected : const Parameters _param;
+#ifdef STATISTICS
+  protected : const morpheo::behavioural::Parameters_Statistics _param_statistics;
+#endif
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+#endif
+
+#ifdef VHDL_TESTBENCH
+  private   : Vhdl_Testbench                 * _vhdl_testbench;
+#endif
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK                  ;
+ 
+  public    : SC_IN (Tcontrol_t)           **  in_PREDICT_VAL            ;
+  public    : SC_OUT(Tcontrol_t)           ** out_PREDICT_ACK            ;
+  public    : SC_IN (Taddress_t)           **  in_PREDICT_ADDRESS        ;
+  public    : SC_OUT(Thistory_t)           ** out_PREDICT_HISTORY        ;
+
+  public    : SC_IN (Tcontrol_t)           **  in_BRANCH_COMPLETE_VAL    ;
+  public    : SC_OUT(Tcontrol_t)           ** out_BRANCH_COMPLETE_ACK    ;
+  public    : SC_IN (Taddress_t)           **  in_BRANCH_COMPLETE_ADDRESS;
+  public    : SC_IN (Thistory_t)           **  in_BRANCH_COMPLETE_HISTORY;
+  public    : SC_IN (Tcontrol_t)           **  in_BRANCH_COMPLETE_DIRECTION;
+
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_SIGNAL(Thistory_t)        ** signal_BRANCH_COMPLETE_HISTORY;
+#endif
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+  public    : morpheo::behavioural::generic::shifter::Shifter           * component_Shifter     ;
+  public    : morpheo::behavioural::generic::registerfile::RegisterFile * component_RegisterFile;
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (Branch_History_Table);
+#endif					       
+  public  :          Branch_History_Table              (
+#ifdef SYSTEMC
+							sc_module_name                              name,
+#else					       
+							string                                      name,
+#endif					       
+#ifdef STATISTICS
+							morpheo::behavioural::Parameters_Statistics param_statistics,
+#endif
+							Parameters                                  param );
+					       
+  public  :          Branch_History_Table              (Parameters param );
+  public  :          ~Branch_History_Table             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+  public  : void     transition                (void);
+#endif
+#endif					       
+					       
+#if VHDL				       
+  public  : void     vhdl                      (void);
+  private : void     vhdl_port                 (Vhdl & vhdl);
+  private : void     vhdl_type                 (Vhdl & vhdl);
+  private : void     vhdl_signal               (Vhdl & vhdl);
+  private : void     vhdl_body                 (Vhdl & vhdl);
+#endif					       
+#ifdef STATISTICS
+  public  : string   statistics                (uint32_t depth);
+#endif
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench_port       (void);
+  private : void     vhdl_testbench_transition (void);
+#endif
+  public  : void     vhdl_testbench_label      (string label);
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h	(revision 3)
@@ -0,0 +1,61 @@
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Parameters_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Parameters.h"
+// Internal structure
+#include "Behavioural/Generic/Shifter/include/Parameters.h"
+#include "Behavioural/Generic/RegisterFile/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+    //-----[ fields ]------------------------------------------------------------
+  public : const uint32_t _size_shifter      ;
+  public : const uint32_t _nb_shifter        ;
+  public : const uint32_t _nb_prediction     ;
+  public : const uint32_t _nb_branch_complete;
+
+  public :       morpheo::behavioural::generic::shifter::Parameters      * _param_shifter;
+  public :       morpheo::behavioural::generic::registerfile::Parameters * _param_registerfile;
+
+    //-----[ methods ]-----------------------------------------------------------
+  public : Parameters  (uint32_t size_shifter      ,
+ 			uint32_t nb_shifter        ,
+			uint32_t nb_prediction     ,
+			uint32_t nb_branch_complete);
+  public : Parameters  (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters & x);
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h	(revision 3)
@@ -0,0 +1,65 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Statistics_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+#include "Behavioural/Generic/Shifter/include/Statistics.h"
+#include "Behavioural/Generic/RegisterFile/include/Statistics.h"
+//#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h"
+
+//using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                   _parameters;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics  (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  );
+//public   : Statistics  (Statistics & stat);
+  public   : ~Statistics () ;
+
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : string   print      (uint32_t depth          ,
+				  string   component_stat );
+  public   : void     add        ();
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h	(revision 3)
@@ -0,0 +1,34 @@
+#ifdef SYSTEMC
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Type_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_branch_history_table_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Types.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+  typedef uint32_t Thistory_t;
+  typedef uint32_t Taddress_t;
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp	(revision 3)
@@ -0,0 +1,104 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+#ifdef SYSTEMC
+  Branch_History_Table::Branch_History_Table (sc_module_name name,
+#else
+  Branch_History_Table::Branch_History_Table (string name,
+#endif
+#ifdef STATISTICS
+					      morpheo::behavioural::Parameters_Statistics             param_statistics,
+#endif
+					      morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters param ):
+					       _name             (name)
+					      ,_param            (param)
+#ifdef STATISTICS
+					      ,_param_statistics (param_statistics)
+#endif
+  {
+#ifdef STATISTICS
+    // Allocation of statistics
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // Creation of a testbench
+    //  -> port
+    //  -> clock's signals
+    _vhdl_testbench = new Vhdl_Testbench (_name);
+    vhdl_testbench_port           ();
+    _vhdl_testbench->set_clock    ("in_CLOCK",true);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    allocation ();
+
+    // Constant
+    for (uint32_t i=0; i<_param._nb_prediction     ; i++)
+      PORT_WRITE(out_PREDICT_ACK         [i],1);
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1);
+
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+#endif
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+#endif    
+
+#endif
+  };
+  
+  Branch_History_Table::~Branch_History_Table (void)
+  {
+#ifdef VHDL_TESTBENCH
+    // generate the test bench
+    _vhdl_testbench->generate_file();
+    delete _vhdl_testbench;
+#endif
+
+#ifdef STATISTICS
+
+    _stat->generate_file(statistics(0));
+
+    delete _stat;
+#endif
+
+#ifdef SYSTEMC
+    deallocation ();
+#endif
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp	(revision 3)
@@ -0,0 +1,135 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  void Branch_History_Table::allocation (void)
+  {
+    string rename;
+
+     in_CLOCK           = new SC_CLOCK           ("in_CLOCK");
+
+     in_PREDICT_VAL     = new SC_IN (Tcontrol_t) * [_param._nb_prediction];
+    out_PREDICT_ACK     = new SC_OUT(Tcontrol_t) * [_param._nb_prediction];
+     in_PREDICT_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_prediction];
+    out_PREDICT_HISTORY = new SC_OUT(Thistory_t) * [_param._nb_prediction];
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	rename = "in_PREDICT_VAL["     +toString(i)+"]";
+	 in_PREDICT_VAL     [i] = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	rename = "out_PREDICT_ACK["    +toString(i)+"]";
+	out_PREDICT_ACK     [i] = new SC_OUT(Tcontrol_t) (rename.c_str());
+
+	rename = "in_PREDICT_ADDRESS["+toString(i)+"]";
+	 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());
+
+	rename = "out_PREDICT_HISTORY["+toString(i)+"]";
+	out_PREDICT_HISTORY [i] = new SC_OUT(Thistory_t) (rename.c_str());
+      }
+
+        in_BRANCH_COMPLETE_VAL     = new SC_IN     (Tcontrol_t) * [_param._nb_branch_complete];
+       out_BRANCH_COMPLETE_ACK     = new SC_OUT    (Tcontrol_t) * [_param._nb_branch_complete];
+        in_BRANCH_COMPLETE_ADDRESS = new SC_IN     (Taddress_t) * [_param._nb_branch_complete];
+        in_BRANCH_COMPLETE_HISTORY = new SC_IN     (Thistory_t) * [_param._nb_branch_complete];
+        in_BRANCH_COMPLETE_DIRECTION= new SC_IN     (Tcontrol_t) * [_param._nb_branch_complete];
+    signal_BRANCH_COMPLETE_HISTORY = new SC_SIGNAL (Thistory_t) * [_param._nb_branch_complete];
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	 rename = "in_BRANCH_COMPLETE_VAL["    +toString(i)+"]";
+	  in_BRANCH_COMPLETE_VAL     [i] = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	 rename = "out_BRANCH_COMPLETE_ACK["   +toString(i)+"]";
+	 out_BRANCH_COMPLETE_ACK     [i] = new SC_OUT(Tcontrol_t) (rename.c_str());
+
+	 rename = "in_BRANCH_COMPLETE_ADDRESS["+toString(i)+"]";
+	  in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());
+
+	 rename = "in_BRANCH_COMPLETE_HISTORY["+toString(i)+"]";
+	  in_BRANCH_COMPLETE_HISTORY [i] = new SC_IN (Thistory_t) (rename.c_str());
+
+	 rename = "in_BRANCH_COMPLETE_DIRECTION["    +toString(i)+"]";
+	  in_BRANCH_COMPLETE_DIRECTION[i] = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	 rename = "signal_BRANCH_COMPLETE_HISTORY["+toString(i)+"]";
+	 signal_BRANCH_COMPLETE_HISTORY [i] = new SC_SIGNAL (Thistory_t) (rename.c_str());
+
+      }
+    
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    string name_component;
+    // =====[ component_Shifter ]=========================================    
+    
+    name_component = _name+"_Shifter";
+
+    component_Shifter = new morpheo::behavioural::generic::shifter::Shifter (name_component.c_str(),
+#ifdef STATISTICS
+									     _param_statistics             ,
+#endif
+									     *(_param._param_shifter)      );
+    
+    
+    // Instantiation
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+    (*(component_Shifter->in_CLOCK))        (*(in_CLOCK));
+#endif
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	(*(component_Shifter-> in_SHIFTER_DATA       [i]))    (*(    in_BRANCH_COMPLETE_HISTORY  [i]));
+	(*(component_Shifter-> in_SHIFTER_CARRY_IN   [i]))    (*(    in_BRANCH_COMPLETE_DIRECTION[i]));
+	(*(component_Shifter->out_SHIFTER_DATA       [i]))    (*(signal_BRANCH_COMPLETE_HISTORY  [i]));
+      }
+    
+     // =====[ component_RegisterFile ]====================================    
+    
+    name_component = _name+"_RegisterFile";
+    
+    component_RegisterFile = new morpheo::behavioural::generic::registerfile::RegisterFile (name_component.c_str(),
+#ifdef STATISTICS
+											    _param_statistics            ,
+#endif
+											    *(_param._param_registerfile));
+     
+    // Instantiation
+    (*(component_RegisterFile->in_CLOCK))        (*(in_CLOCK));
+    
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	(*(component_RegisterFile-> in_READ_ENABLE   [i])) (*( in_PREDICT_VAL      [i]));
+	(*(component_RegisterFile-> in_READ_ADDRESS  [i])) (*( in_PREDICT_ADDRESS  [i]));
+	(*(component_RegisterFile->out_READ_DATA     [i])) (*(out_PREDICT_HISTORY  [i]));    
+      }
+    
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	(*(component_RegisterFile-> in_WRITE_ENABLE  [i])) (*(    in_BRANCH_COMPLETE_VAL      [i]));
+	(*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*(    in_BRANCH_COMPLETE_ADDRESS  [i]));
+	(*(component_RegisterFile-> in_WRITE_DATA    [i])) (*(signal_BRANCH_COMPLETE_HISTORY  [i]));    
+      }
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp	(revision 3)
@@ -0,0 +1,62 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+  void Branch_History_Table::deallocation (void)
+  {
+    delete in_CLOCK;
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	delete  in_PREDICT_VAL     [i];
+	delete out_PREDICT_ACK     [i];
+	delete  in_PREDICT_ADDRESS [i];
+	delete out_PREDICT_HISTORY [i];
+      }
+
+    delete  in_PREDICT_VAL    ;
+    delete out_PREDICT_ACK    ;
+    delete  in_PREDICT_ADDRESS;
+    delete out_PREDICT_HISTORY;
+
+     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+       {
+	 delete  in_BRANCH_COMPLETE_VAL     [i];
+	 delete out_BRANCH_COMPLETE_ACK     [i];
+	 delete  in_BRANCH_COMPLETE_ADDRESS [i];
+	 delete  in_BRANCH_COMPLETE_HISTORY [i];
+	 delete  in_BRANCH_COMPLETE_DIRECTION[i];
+       }
+    delete  in_BRANCH_COMPLETE_VAL    ;
+    delete out_BRANCH_COMPLETE_ACK    ;
+    delete  in_BRANCH_COMPLETE_ADDRESS;
+    delete  in_BRANCH_COMPLETE_HISTORY;
+    delete  in_BRANCH_COMPLETE_DIRECTION;
+
+     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    delete component_Shifter;
+    delete component_RegisterFile;
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_statistics.cpp	(revision 3)
@@ -0,0 +1,36 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  string Branch_History_Table::statistics (uint32_t depth)
+  {
+    return _stat->print(depth,
+			component_Shifter     ->statistics(depth+1) +
+			component_RegisterFile->statistics(depth+1) 
+			);
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_transition.cpp	(revision 3)
@@ -0,0 +1,41 @@
+#ifdef SYSTEMC
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  void Branch_History_Table::transition (void)
+  {
+#ifdef STATISTICS
+    _stat->add();
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition ();
+#endif
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  void Branch_History_Table::vhdl (void)
+  {
+    Vhdl vhdl (_name);
+
+    vhdl.set_library_work (_name + "_Pack");
+    vhdl.set_library_work (_name + "_RegisterFile_Pack");
+    vhdl.set_library_work (_name + "_Shifter_Pack");
+
+    vhdl_port   (vhdl);
+    vhdl_type   (vhdl);
+    vhdl_signal (vhdl);
+    vhdl_body   (vhdl);
+
+    vhdl.generate_file();
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp	(revision 3)
@@ -0,0 +1,66 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  void Branch_History_Table::vhdl_body (Vhdl & vhdl)
+  {
+    vhdl.set_body ("-- Output : always at '1'");
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");
+    for (uint32_t i=0; i<_param._nb_prediction     ; i++)
+      vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+"         <= '1';");
+    vhdl.set_body ("");
+
+    list<string> list_port_map;
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	vhdl.set_body_component_port_map (list_port_map," in_SHIFTER_DATA_"+toString(i)+"     ","    in_BRANCH_COMPLETE_HISTORY_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map," in_SHIFTER_CARRY_IN_"+toString(i)+" ","    in_BRANCH_COMPLETE_DIRECTION_"+toString(i)    );
+	vhdl.set_body_component_port_map (list_port_map,"out_SHIFTER_DATA_"+toString(i)+"     ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
+      }
+
+    vhdl.set_body_component ("component_Shifter",_name+"_Shifter",list_port_map);
+
+    list_port_map.clear();
+    vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK");
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	vhdl.set_body_component_port_map (list_port_map," in_READ_ENABLE_"+toString(i)+"  "," in_PREDICT_VAL_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+"    ","out_PREDICT_HISTORY_"+toString(i));    
+      }
+    
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	vhdl.set_body_component_port_map (list_port_map," in_WRITE_ENABLE_"+toString(i)+" ","    in_BRANCH_COMPLETE_VAL_"+toString(i)+"");
+	vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+"","    in_BRANCH_COMPLETE_ADDRESS_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+"   ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
+      }
+    vhdl.set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map);
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_port.cpp	(revision 3)
@@ -0,0 +1,48 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  void Branch_History_Table::vhdl_port (Vhdl & vhdl)
+  {
+    vhdl.set_port (" in_CLOCK" , IN, 1);
+    
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	vhdl.set_port(" in_PREDICT_VAL_"+toString(i)+"               ", IN, 1);
+	vhdl.set_port("out_PREDICT_ACK_"+toString(i)+"               ",OUT, 1);
+	vhdl.set_port(" in_PREDICT_ADDRESS_"+toString(i)+"           ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter))));
+	vhdl.set_port("out_PREDICT_HISTORY_"+toString(i)+"           ",OUT, _param._size_shifter);
+      }
+     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+       {
+	 vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+"      ", IN, 1);
+	 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+"      ",OUT, 1);
+	 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+"  ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter))));
+	 vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+"  ", IN, _param._size_shifter);
+	 vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1);
+       }
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_signal.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_signal.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_signal.cpp	(revision 3)
@@ -0,0 +1,32 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+  void Branch_History_Table::vhdl_signal (Vhdl & vhdl)
+  {
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      vhdl.set_signal  ("signal_BRANCH_COMPLETE_HISTORY_"+toString(i), _param._size_shifter);
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_label.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_label.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_label.cpp	(revision 3)
@@ -0,0 +1,31 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+  void Branch_History_Table::vhdl_testbench_label (string label)
+  {
+#ifdef VHDL_TESTBENCH
+    _vhdl_testbench->add_label(label);
+#endif
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_port.cpp	(revision 3)
@@ -0,0 +1,46 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+  void Branch_History_Table::vhdl_testbench_port (void)
+  {
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	_vhdl_testbench->set_port (" in_PREDICT_VAL_"+toString(i)+"               ", IN, 1);
+	_vhdl_testbench->set_port ("out_PREDICT_ACK_"+toString(i)+"               ",OUT, 1);
+	_vhdl_testbench->set_port (" in_PREDICT_ADDRESS_"+toString(i)+"           ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter))));
+	_vhdl_testbench->set_port ("out_PREDICT_HISTORY_"+toString(i)+"           ",OUT, _param._size_shifter);
+      }
+
+     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+       {
+	 _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+"      ", IN, 1);
+	 _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+"      ",OUT, 1);
+	 _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+"  ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter))));
+	 _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+"  ", IN, _param._size_shifter);
+	 _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1);
+       }
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp	(revision 3)
@@ -0,0 +1,61 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  void Branch_History_Table::vhdl_testbench_transition (void)
+  {
+    // In order with file Branch_History_Table_vhdl_testbench_port.cpp
+#ifndef SYSTEMCASS_SPECIFIC
+    sc_cycle(0);
+#endif    
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	_vhdl_testbench->add_input  (PORT_READ( in_PREDICT_VAL     [i]));
+	_vhdl_testbench->add_output (PORT_READ(out_PREDICT_ACK     [i]));
+	_vhdl_testbench->add_input  (PORT_READ( in_PREDICT_ADDRESS [i]));
+	_vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i]));
+      //_vhdl_testbench->add_output (PORT_READ(out_PREDICT_HISTORY [i]));
+      }
+
+     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+       {
+	 _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_VAL     [i]));
+	 _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_ACK     [i]));
+	 _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i]));
+	 _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i]));
+	 _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_DIRECTION[i]));
+       }
+    
+    // add_test :
+    //  - True  : the cycle must be compare with the output of systemC
+    //  - False : no test
+    _vhdl_testbench->add_test(true);
+
+    _vhdl_testbench->new_cycle (); // always at the end
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_type.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_type.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_type.cpp	(revision 3)
@@ -0,0 +1,32 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  void Branch_History_Table::vhdl_type (Vhdl & vhdl)
+  {
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,78 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  Parameters::Parameters (uint32_t size_shifter      ,
+ 			  uint32_t nb_shifter        ,
+			  uint32_t nb_prediction     ,
+			  uint32_t nb_branch_complete) :
+    _size_shifter       (size_shifter      ),
+    _nb_shifter         (nb_shifter        ),
+    _nb_prediction      (nb_prediction     ),
+    _nb_branch_complete (nb_branch_complete)
+  {
+    _param_shifter = new morpheo::behavioural::generic::shifter::Parameters (size_shifter       ,
+									     nb_branch_complete ,
+									     1                  ,
+									     morpheo::behavioural::generic::shifter::without_rotate     ,
+									     morpheo::behavioural::generic::shifter::internal_left_shift,
+									     morpheo::behavioural::generic::shifter::external_completion),
+    _param_registerfile = new morpheo::behavioural::generic::registerfile::Parameters (nb_prediction      ,
+										       nb_branch_complete ,
+										       nb_shifter         ,
+										       size_shifter       );
+    
+    test();
+  };
+  
+  Parameters::Parameters (Parameters & param) :
+    _size_shifter       (param._size_shifter      ),
+    _nb_shifter         (param._nb_shifter        ),
+    _nb_prediction      (param._nb_prediction     ),
+    _nb_branch_complete (param._nb_branch_complete)
+  {
+    _param_shifter = new morpheo::behavioural::generic::shifter::Parameters (param._size_shifter       ,
+									     param._nb_branch_complete ,
+									     1                         ,
+									     morpheo::behavioural::generic::shifter::without_rotate     ,
+									     morpheo::behavioural::generic::shifter::internal_left_shift,
+									     morpheo::behavioural::generic::shifter::external_completion,
+									     true),
+
+    _param_registerfile = new morpheo::behavioural::generic::registerfile::Parameters (param._nb_prediction      ,
+										       param._nb_branch_complete ,
+										       param._nb_shifter         ,
+										       param._size_shifter       );
+      
+
+
+    test();
+  };
+
+  Parameters::~Parameters () 
+  {
+    delete _param_shifter;
+    delete _param_registerfile;
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_msg_error.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_msg_error.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_msg_error.cpp	(revision 3)
@@ -0,0 +1,54 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  string Parameters::msg_error(void)
+  {
+    string msg = "";
+
+    if (is_positive (_size_shifter) == false)
+      {
+	msg += "  - size_shifter must be > 0\n";
+	msg += "    * size_shifter                    : " + toString(_size_shifter) + "\n";
+      }
+
+    if (is_positive (_nb_prediction) == false)
+      {
+	msg += "  - nb_prediction must be > 0\n";
+	msg += "    * nb_prediction                   : " + toString(_nb_prediction) + "\n";
+      }
+
+    if (is_positive (_nb_branch_complete) == false)
+      {
+	msg += "  - nb_branch_complete must be > 0\n";
+	msg += "    * nb_branch_complete              : " + toString(_nb_branch_complete) + "\n";
+      }
+
+    return msg;
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters_print.cpp	(revision 3)
@@ -0,0 +1,52 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  string Parameters::print (uint32_t depth)
+  {
+    string tab = string(depth,'\t');
+    ostringstream msg;
+    msg << tab << "<branch_history_table>" << endl
+	<< tab << "\t<size_shifter       value=\"" << _size_shifter       << "\" />" << endl
+ 	<< tab << "\t<nb_shifter         value=\"" << _nb_shifter         << "\" />" << endl
+	<< tab << "\t<nb_prediction      value=\"" << _nb_prediction      << "\" />" << endl
+	<< tab << "\t<nb_branch_complete value=\"" << _nb_branch_complete << "\" />" << endl;
+    msg << _param_shifter     ->print(depth+1);
+    msg << _param_registerfile->print(depth+1);
+    msg	<< tab << "</branch_history_table>" << endl;
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,42 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+  };
+  
+  Statistics::~Statistics () 
+  { 
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+
+  void Statistics::add ()
+  {
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,55 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+  string Statistics::print (uint32_t depth                ,
+			    string   component_statistics )
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<branch_history_table name=\"" << _name << "\" >" << endl
+	<< print_body(depth+1)
+	<< component_statistics
+	<< tab << "</branch_history_table>" << endl;
+    
+    return msg.str();
+  };
+
+  string Statistics::print (uint32_t depth)
+  {
+    return print(depth,"");
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,40 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace branch_history_table {
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "";
+    
+    return msg.str();
+  };
+
+}; // end namespace branch_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Makefile	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../../..
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libTwo_Level_Branch_Predictor.a
+
+
+#-----[ include ]------------------------------------------
+
+all				:
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Makefile.deps	(revision 3)
@@ -0,0 +1,52 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include $(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+ifndef Branch_History_Table
+include $(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.deps
+endif
+ifndef Pattern_History_Table
+include $(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.deps
+endif
+ifndef Two_Level_Branch_Predictor_Glue
+include $(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.deps
+endif
+
+Two_Level_Branch_Predictor			= yes
+
+#-----[ Library ]------------------------------------------
+Two_Level_Branch_Predictor_LIBRARY		= 	-lTwo_Level_Branch_Predictor			\
+							$(Two_Level_Branch_Predictor_Glue_LIBRARY)	\
+							$(Branch_History_Table_LIBRARY)			\
+							$(Pattern_History_Table_LIBRARY)		\
+							$(Behavioural_LIBRARY)	
+
+Two_Level_Branch_Predictor_DIR_LIBRARY		=	-L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/lib	\
+							$(Two_Level_Branch_Predictor_Glue_DIR_LIBRARY)	\
+							$(Branch_History_Table_DIR_LIBRARY)		\
+							$(Pattern_History_Table_DIR_LIBRARY)		\
+							$(Behavioural_DIR_LIBRARY)
+
+#-----[ Rules ]--------------------------------------------
+
+Two_Level_Branch_Predictor_library		: 
+						@$(MAKE) Behavioural_library
+						@$(MAKE) Branch_History_Table_library
+						@$(MAKE) Pattern_History_Table_library
+						@$(MAKE) Two_Level_Branch_Predictor_Glue_library
+						@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor --makefile=Makefile 
+	
+Two_Level_Branch_Predictor_library_clean	: 
+						@$(MAKE) Behavioural_library_clean
+						@$(MAKE) Branch_History_Table_library_clean
+						@$(MAKE) Pattern_History_Table_library_clean
+						@$(MAKE) Two_Level_Branch_Predictor_Glue_library_clean
+						@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../../../..
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libPattern_History_Table.a
+
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.deps	(revision 3)
@@ -0,0 +1,45 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+ifndef Counter
+include 			$(DIR_MORPHEO)/Behavioural/Generic/Counter/Makefile.deps
+endif
+ifndef RegisterFile
+include 			$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/Makefile.deps
+endif
+
+Pattern_History_Table			= yes
+
+#-----[ Library ]------------------------------------------
+Pattern_History_Table_LIBRARY		= 	-lPattern_History_Table	\
+						$(RegisterFile_LIBRARY)	\
+						$(Counter_LIBRARY)	\
+						$(Behavioural_LIBRARY)
+
+Pattern_History_Table_DIR_LIBRARY	=	-L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/lib	\
+						$(RegisterFile_DIR_LIBRARY)	\
+						$(Counter_DIR_LIBRARY)		\
+						$(Behavioural_DIR_LIBRARY)
+
+#-----[ Rules ]--------------------------------------------
+
+Pattern_History_Table_library		: 
+					@$(MAKE) Behavioural_library
+					@$(MAKE) Counter_library
+					@$(MAKE) RegisterFile_library
+					@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table --makefile=Makefile 
+	
+Pattern_History_Table_library_clean	: 
+					@$(MAKE) Behavioural_library_clean
+					@$(MAKE) Counter_library_clean
+					@$(MAKE) RegisterFile_library_clean
+					@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,29 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../../../../..
+
+LIBRARY				= $(Pattern_History_Table_LIBRARY)
+
+DIR_LIBRARY			= $(Pattern_History_Table_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				: library
+				@$(MAKE) all_selftest
+
+library				: Pattern_History_Table_library
+
+library_clean			: Pattern_History_Table_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/configuration.cfg	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/configuration.cfg	(revision 3)
@@ -0,0 +1,5 @@
+Pattern_History_Table
+2	8	*2	# size_counter      	
+2	64	*4	# nb_counter        
+1	2	+1	# nb_prediction     
+1	2	+1	# nb_branch_complete
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h	(revision 3)
@@ -0,0 +1,29 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::stage_1_ifetch;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor;
+
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table;
+
+void test   (string name,
+	     morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters param);
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info	(revision 3)
@@ -0,0 +1,181 @@
+
+# Pattern_History_Table_0
+target_dep	all	Pattern_History_Table_0.ngc
+target_dep	Pattern_History_Table_0.ngc	Pattern_History_Table_0.prj
+target_dep	Pattern_History_Table_0.prj	Pattern_History_Table_0_Counter_Pack.vhdl Pattern_History_Table_0_Counter.vhdl Pattern_History_Table_0_Pack.vhdl Pattern_History_Table_0_RegisterFile_Pack.vhdl Pattern_History_Table_0_RegisterFile.vhdl Pattern_History_Table_0.vhdl
+
+# Pattern_History_Table_10
+target_dep	all	Pattern_History_Table_10.ngc
+target_dep	Pattern_History_Table_10.ngc	Pattern_History_Table_10.prj
+target_dep	Pattern_History_Table_10.prj	Pattern_History_Table_10_Counter_Pack.vhdl Pattern_History_Table_10_Counter.vhdl Pattern_History_Table_10_Pack.vhdl Pattern_History_Table_10_RegisterFile_Pack.vhdl Pattern_History_Table_10_RegisterFile.vhdl Pattern_History_Table_10.vhdl
+
+# Pattern_History_Table_11
+target_dep	all	Pattern_History_Table_11.ngc
+target_dep	Pattern_History_Table_11.ngc	Pattern_History_Table_11.prj
+target_dep	Pattern_History_Table_11.prj	Pattern_History_Table_11_Counter_Pack.vhdl Pattern_History_Table_11_Counter.vhdl Pattern_History_Table_11_Pack.vhdl Pattern_History_Table_11_RegisterFile_Pack.vhdl Pattern_History_Table_11_RegisterFile.vhdl Pattern_History_Table_11.vhdl
+
+# Pattern_History_Table_12
+target_dep	all	Pattern_History_Table_12.ngc
+target_dep	Pattern_History_Table_12.ngc	Pattern_History_Table_12.prj
+target_dep	Pattern_History_Table_12.prj	Pattern_History_Table_12_Counter_Pack.vhdl Pattern_History_Table_12_Counter.vhdl Pattern_History_Table_12_Pack.vhdl Pattern_History_Table_12_RegisterFile_Pack.vhdl Pattern_History_Table_12_RegisterFile.vhdl Pattern_History_Table_12.vhdl
+
+# Pattern_History_Table_13
+target_dep	all	Pattern_History_Table_13.ngc
+target_dep	Pattern_History_Table_13.ngc	Pattern_History_Table_13.prj
+target_dep	Pattern_History_Table_13.prj	Pattern_History_Table_13_Counter_Pack.vhdl Pattern_History_Table_13_Counter.vhdl Pattern_History_Table_13_Pack.vhdl Pattern_History_Table_13_RegisterFile_Pack.vhdl Pattern_History_Table_13_RegisterFile.vhdl Pattern_History_Table_13.vhdl
+
+# Pattern_History_Table_14
+target_dep	all	Pattern_History_Table_14.ngc
+target_dep	Pattern_History_Table_14.ngc	Pattern_History_Table_14.prj
+target_dep	Pattern_History_Table_14.prj	Pattern_History_Table_14_Counter_Pack.vhdl Pattern_History_Table_14_Counter.vhdl Pattern_History_Table_14_Pack.vhdl Pattern_History_Table_14_RegisterFile_Pack.vhdl Pattern_History_Table_14_RegisterFile.vhdl Pattern_History_Table_14.vhdl
+
+# Pattern_History_Table_15
+target_dep	all	Pattern_History_Table_15.ngc
+target_dep	Pattern_History_Table_15.ngc	Pattern_History_Table_15.prj
+target_dep	Pattern_History_Table_15.prj	Pattern_History_Table_15_Counter_Pack.vhdl Pattern_History_Table_15_Counter.vhdl Pattern_History_Table_15_Pack.vhdl Pattern_History_Table_15_RegisterFile_Pack.vhdl Pattern_History_Table_15_RegisterFile.vhdl Pattern_History_Table_15.vhdl
+
+# Pattern_History_Table_16
+target_dep	all	Pattern_History_Table_16.ngc
+target_dep	Pattern_History_Table_16.ngc	Pattern_History_Table_16.prj
+target_dep	Pattern_History_Table_16.prj	Pattern_History_Table_16_Counter_Pack.vhdl Pattern_History_Table_16_Counter.vhdl Pattern_History_Table_16_Pack.vhdl Pattern_History_Table_16_RegisterFile_Pack.vhdl Pattern_History_Table_16_RegisterFile.vhdl Pattern_History_Table_16.vhdl
+
+# Pattern_History_Table_17
+target_dep	all	Pattern_History_Table_17.ngc
+target_dep	Pattern_History_Table_17.ngc	Pattern_History_Table_17.prj
+target_dep	Pattern_History_Table_17.prj	Pattern_History_Table_17_Counter_Pack.vhdl Pattern_History_Table_17_Counter.vhdl Pattern_History_Table_17_Pack.vhdl Pattern_History_Table_17_RegisterFile_Pack.vhdl Pattern_History_Table_17_RegisterFile.vhdl Pattern_History_Table_17.vhdl
+
+# Pattern_History_Table_18
+target_dep	all	Pattern_History_Table_18.ngc
+target_dep	Pattern_History_Table_18.ngc	Pattern_History_Table_18.prj
+target_dep	Pattern_History_Table_18.prj	Pattern_History_Table_18_Counter_Pack.vhdl Pattern_History_Table_18_Counter.vhdl Pattern_History_Table_18_Pack.vhdl Pattern_History_Table_18_RegisterFile_Pack.vhdl Pattern_History_Table_18_RegisterFile.vhdl Pattern_History_Table_18.vhdl
+
+# Pattern_History_Table_19
+target_dep	all	Pattern_History_Table_19.ngc
+target_dep	Pattern_History_Table_19.ngc	Pattern_History_Table_19.prj
+target_dep	Pattern_History_Table_19.prj	Pattern_History_Table_19_Counter_Pack.vhdl Pattern_History_Table_19_Counter.vhdl Pattern_History_Table_19_Pack.vhdl Pattern_History_Table_19_RegisterFile_Pack.vhdl Pattern_History_Table_19_RegisterFile.vhdl Pattern_History_Table_19.vhdl
+
+# Pattern_History_Table_1
+target_dep	all	Pattern_History_Table_1.ngc
+target_dep	Pattern_History_Table_1.ngc	Pattern_History_Table_1.prj
+target_dep	Pattern_History_Table_1.prj	Pattern_History_Table_10_Counter_Pack.vhdl Pattern_History_Table_10_Counter.vhdl Pattern_History_Table_10_Pack.vhdl Pattern_History_Table_10_RegisterFile_Pack.vhdl Pattern_History_Table_10_RegisterFile.vhdl Pattern_History_Table_10.vhdl Pattern_History_Table_11_Counter_Pack.vhdl Pattern_History_Table_11_Counter.vhdl Pattern_History_Table_11_Pack.vhdl Pattern_History_Table_11_RegisterFile_Pack.vhdl Pattern_History_Table_11_RegisterFile.vhdl Pattern_History_Table_11.vhdl Pattern_History_Table_12_Counter_Pack.vhdl Pattern_History_Table_12_Counter.vhdl Pattern_History_Table_12_Pack.vhdl Pattern_History_Table_12_RegisterFile_Pack.vhdl Pattern_History_Table_12_RegisterFile.vhdl Pattern_History_Table_12.vhdl Pattern_History_Table_13_Counter_Pack.vhdl Pattern_History_Table_13_Counter.vhdl Pattern_History_Table_13_Pack.vhdl Pattern_History_Table_13_RegisterFile_Pack.vhdl Pattern_History_Table_13_RegisterFile.vhdl Pattern_History_Table_13.vhdl Pattern_History_Table_14_Counter_Pack.vhdl Pattern_History_Table_14_Counter.vhdl Pattern_History_Table_14_Pack.vhdl Pattern_History_Table_14_RegisterFile_Pack.vhdl Pattern_History_Table_14_RegisterFile.vhdl Pattern_History_Table_14.vhdl Pattern_History_Table_15_Counter_Pack.vhdl Pattern_History_Table_15_Counter.vhdl Pattern_History_Table_15_Pack.vhdl Pattern_History_Table_15_RegisterFile_Pack.vhdl Pattern_History_Table_15_RegisterFile.vhdl Pattern_History_Table_15.vhdl Pattern_History_Table_16_Counter_Pack.vhdl Pattern_History_Table_16_Counter.vhdl Pattern_History_Table_16_Pack.vhdl Pattern_History_Table_16_RegisterFile_Pack.vhdl Pattern_History_Table_16_RegisterFile.vhdl Pattern_History_Table_16.vhdl Pattern_History_Table_17_Counter_Pack.vhdl Pattern_History_Table_17_Counter.vhdl Pattern_History_Table_17_Pack.vhdl Pattern_History_Table_17_RegisterFile_Pack.vhdl Pattern_History_Table_17_RegisterFile.vhdl Pattern_History_Table_17.vhdl Pattern_History_Table_18_Counter_Pack.vhdl Pattern_History_Table_18_Counter.vhdl Pattern_History_Table_18_Pack.vhdl Pattern_History_Table_18_RegisterFile_Pack.vhdl Pattern_History_Table_18_RegisterFile.vhdl Pattern_History_Table_18.vhdl Pattern_History_Table_19_Counter_Pack.vhdl Pattern_History_Table_19_Counter.vhdl Pattern_History_Table_19_Pack.vhdl Pattern_History_Table_19_RegisterFile_Pack.vhdl Pattern_History_Table_19_RegisterFile.vhdl Pattern_History_Table_19.vhdl Pattern_History_Table_1_Counter_Pack.vhdl Pattern_History_Table_1_Counter.vhdl Pattern_History_Table_1_Pack.vhdl Pattern_History_Table_1_RegisterFile_Pack.vhdl Pattern_History_Table_1_RegisterFile.vhdl Pattern_History_Table_1.vhdl
+
+# Pattern_History_Table_20
+target_dep	all	Pattern_History_Table_20.ngc
+target_dep	Pattern_History_Table_20.ngc	Pattern_History_Table_20.prj
+target_dep	Pattern_History_Table_20.prj	Pattern_History_Table_20_Counter_Pack.vhdl Pattern_History_Table_20_Counter.vhdl Pattern_History_Table_20_Pack.vhdl Pattern_History_Table_20_RegisterFile_Pack.vhdl Pattern_History_Table_20_RegisterFile.vhdl Pattern_History_Table_20.vhdl
+
+# Pattern_History_Table_21
+target_dep	all	Pattern_History_Table_21.ngc
+target_dep	Pattern_History_Table_21.ngc	Pattern_History_Table_21.prj
+target_dep	Pattern_History_Table_21.prj	Pattern_History_Table_21_Counter_Pack.vhdl Pattern_History_Table_21_Counter.vhdl Pattern_History_Table_21_Pack.vhdl Pattern_History_Table_21_RegisterFile_Pack.vhdl Pattern_History_Table_21_RegisterFile.vhdl Pattern_History_Table_21.vhdl
+
+# Pattern_History_Table_22
+target_dep	all	Pattern_History_Table_22.ngc
+target_dep	Pattern_History_Table_22.ngc	Pattern_History_Table_22.prj
+target_dep	Pattern_History_Table_22.prj	Pattern_History_Table_22_Counter_Pack.vhdl Pattern_History_Table_22_Counter.vhdl Pattern_History_Table_22_Pack.vhdl Pattern_History_Table_22_RegisterFile_Pack.vhdl Pattern_History_Table_22_RegisterFile.vhdl Pattern_History_Table_22.vhdl
+
+# Pattern_History_Table_23
+target_dep	all	Pattern_History_Table_23.ngc
+target_dep	Pattern_History_Table_23.ngc	Pattern_History_Table_23.prj
+target_dep	Pattern_History_Table_23.prj	Pattern_History_Table_23_Counter_Pack.vhdl Pattern_History_Table_23_Counter.vhdl Pattern_History_Table_23_Pack.vhdl Pattern_History_Table_23_RegisterFile_Pack.vhdl Pattern_History_Table_23_RegisterFile.vhdl Pattern_History_Table_23.vhdl
+
+# Pattern_History_Table_24
+target_dep	all	Pattern_History_Table_24.ngc
+target_dep	Pattern_History_Table_24.ngc	Pattern_History_Table_24.prj
+target_dep	Pattern_History_Table_24.prj	Pattern_History_Table_24_Counter_Pack.vhdl Pattern_History_Table_24_Counter.vhdl Pattern_History_Table_24_Pack.vhdl Pattern_History_Table_24_RegisterFile_Pack.vhdl Pattern_History_Table_24_RegisterFile.vhdl Pattern_History_Table_24.vhdl
+
+# Pattern_History_Table_25
+target_dep	all	Pattern_History_Table_25.ngc
+target_dep	Pattern_History_Table_25.ngc	Pattern_History_Table_25.prj
+target_dep	Pattern_History_Table_25.prj	Pattern_History_Table_25_Counter_Pack.vhdl Pattern_History_Table_25_Counter.vhdl Pattern_History_Table_25_Pack.vhdl Pattern_History_Table_25_RegisterFile_Pack.vhdl Pattern_History_Table_25_RegisterFile.vhdl Pattern_History_Table_25.vhdl
+
+# Pattern_History_Table_26
+target_dep	all	Pattern_History_Table_26.ngc
+target_dep	Pattern_History_Table_26.ngc	Pattern_History_Table_26.prj
+target_dep	Pattern_History_Table_26.prj	Pattern_History_Table_26_Counter_Pack.vhdl Pattern_History_Table_26_Counter.vhdl Pattern_History_Table_26_Pack.vhdl Pattern_History_Table_26_RegisterFile_Pack.vhdl Pattern_History_Table_26_RegisterFile.vhdl Pattern_History_Table_26.vhdl
+
+# Pattern_History_Table_27
+target_dep	all	Pattern_History_Table_27.ngc
+target_dep	Pattern_History_Table_27.ngc	Pattern_History_Table_27.prj
+target_dep	Pattern_History_Table_27.prj	Pattern_History_Table_27_Counter_Pack.vhdl Pattern_History_Table_27_Counter.vhdl Pattern_History_Table_27_Pack.vhdl Pattern_History_Table_27_RegisterFile_Pack.vhdl Pattern_History_Table_27_RegisterFile.vhdl Pattern_History_Table_27.vhdl
+
+# Pattern_History_Table_28
+target_dep	all	Pattern_History_Table_28.ngc
+target_dep	Pattern_History_Table_28.ngc	Pattern_History_Table_28.prj
+target_dep	Pattern_History_Table_28.prj	Pattern_History_Table_28_Counter_Pack.vhdl Pattern_History_Table_28_Counter.vhdl Pattern_History_Table_28_Pack.vhdl Pattern_History_Table_28_RegisterFile_Pack.vhdl Pattern_History_Table_28_RegisterFile.vhdl Pattern_History_Table_28.vhdl
+
+# Pattern_History_Table_29
+target_dep	all	Pattern_History_Table_29.ngc
+target_dep	Pattern_History_Table_29.ngc	Pattern_History_Table_29.prj
+target_dep	Pattern_History_Table_29.prj	Pattern_History_Table_29_Counter_Pack.vhdl Pattern_History_Table_29_Counter.vhdl Pattern_History_Table_29_Pack.vhdl Pattern_History_Table_29_RegisterFile_Pack.vhdl Pattern_History_Table_29_RegisterFile.vhdl Pattern_History_Table_29.vhdl
+
+# Pattern_History_Table_2
+target_dep	all	Pattern_History_Table_2.ngc
+target_dep	Pattern_History_Table_2.ngc	Pattern_History_Table_2.prj
+target_dep	Pattern_History_Table_2.prj	Pattern_History_Table_20_Counter_Pack.vhdl Pattern_History_Table_20_Counter.vhdl Pattern_History_Table_20_Pack.vhdl Pattern_History_Table_20_RegisterFile_Pack.vhdl Pattern_History_Table_20_RegisterFile.vhdl Pattern_History_Table_20.vhdl Pattern_History_Table_21_Counter_Pack.vhdl Pattern_History_Table_21_Counter.vhdl Pattern_History_Table_21_Pack.vhdl Pattern_History_Table_21_RegisterFile_Pack.vhdl Pattern_History_Table_21_RegisterFile.vhdl Pattern_History_Table_21.vhdl Pattern_History_Table_22_Counter_Pack.vhdl Pattern_History_Table_22_Counter.vhdl Pattern_History_Table_22_Pack.vhdl Pattern_History_Table_22_RegisterFile_Pack.vhdl Pattern_History_Table_22_RegisterFile.vhdl Pattern_History_Table_22.vhdl Pattern_History_Table_23_Counter_Pack.vhdl Pattern_History_Table_23_Counter.vhdl Pattern_History_Table_23_Pack.vhdl Pattern_History_Table_23_RegisterFile_Pack.vhdl Pattern_History_Table_23_RegisterFile.vhdl Pattern_History_Table_23.vhdl Pattern_History_Table_24_Counter_Pack.vhdl Pattern_History_Table_24_Counter.vhdl Pattern_History_Table_24_Pack.vhdl Pattern_History_Table_24_RegisterFile_Pack.vhdl Pattern_History_Table_24_RegisterFile.vhdl Pattern_History_Table_24.vhdl Pattern_History_Table_25_Counter_Pack.vhdl Pattern_History_Table_25_Counter.vhdl Pattern_History_Table_25_Pack.vhdl Pattern_History_Table_25_RegisterFile_Pack.vhdl Pattern_History_Table_25_RegisterFile.vhdl Pattern_History_Table_25.vhdl Pattern_History_Table_26_Counter_Pack.vhdl Pattern_History_Table_26_Counter.vhdl Pattern_History_Table_26_Pack.vhdl Pattern_History_Table_26_RegisterFile_Pack.vhdl Pattern_History_Table_26_RegisterFile.vhdl Pattern_History_Table_26.vhdl Pattern_History_Table_27_Counter_Pack.vhdl Pattern_History_Table_27_Counter.vhdl Pattern_History_Table_27_Pack.vhdl Pattern_History_Table_27_RegisterFile_Pack.vhdl Pattern_History_Table_27_RegisterFile.vhdl Pattern_History_Table_27.vhdl Pattern_History_Table_28_Counter_Pack.vhdl Pattern_History_Table_28_Counter.vhdl Pattern_History_Table_28_Pack.vhdl Pattern_History_Table_28_RegisterFile_Pack.vhdl Pattern_History_Table_28_RegisterFile.vhdl Pattern_History_Table_28.vhdl Pattern_History_Table_29_Counter_Pack.vhdl Pattern_History_Table_29_Counter.vhdl Pattern_History_Table_29_Pack.vhdl Pattern_History_Table_29_RegisterFile_Pack.vhdl Pattern_History_Table_29_RegisterFile.vhdl Pattern_History_Table_29.vhdl Pattern_History_Table_2_Counter_Pack.vhdl Pattern_History_Table_2_Counter.vhdl Pattern_History_Table_2_Pack.vhdl Pattern_History_Table_2_RegisterFile_Pack.vhdl Pattern_History_Table_2_RegisterFile.vhdl Pattern_History_Table_2.vhdl
+
+# Pattern_History_Table_30
+target_dep	all	Pattern_History_Table_30.ngc
+target_dep	Pattern_History_Table_30.ngc	Pattern_History_Table_30.prj
+target_dep	Pattern_History_Table_30.prj	Pattern_History_Table_30_Counter_Pack.vhdl Pattern_History_Table_30_Counter.vhdl Pattern_History_Table_30_Pack.vhdl Pattern_History_Table_30_RegisterFile_Pack.vhdl Pattern_History_Table_30_RegisterFile.vhdl Pattern_History_Table_30.vhdl
+
+# Pattern_History_Table_31
+target_dep	all	Pattern_History_Table_31.ngc
+target_dep	Pattern_History_Table_31.ngc	Pattern_History_Table_31.prj
+target_dep	Pattern_History_Table_31.prj	Pattern_History_Table_31_Counter_Pack.vhdl Pattern_History_Table_31_Counter.vhdl Pattern_History_Table_31_Pack.vhdl Pattern_History_Table_31_RegisterFile_Pack.vhdl Pattern_History_Table_31_RegisterFile.vhdl Pattern_History_Table_31.vhdl
+
+# Pattern_History_Table_32
+target_dep	all	Pattern_History_Table_32.ngc
+target_dep	Pattern_History_Table_32.ngc	Pattern_History_Table_32.prj
+target_dep	Pattern_History_Table_32.prj	Pattern_History_Table_32_Counter_Pack.vhdl Pattern_History_Table_32_Counter.vhdl Pattern_History_Table_32_Pack.vhdl Pattern_History_Table_32_RegisterFile_Pack.vhdl Pattern_History_Table_32_RegisterFile.vhdl Pattern_History_Table_32.vhdl
+
+# Pattern_History_Table_33
+target_dep	all	Pattern_History_Table_33.ngc
+target_dep	Pattern_History_Table_33.ngc	Pattern_History_Table_33.prj
+target_dep	Pattern_History_Table_33.prj	Pattern_History_Table_33_Counter_Pack.vhdl Pattern_History_Table_33_Counter.vhdl Pattern_History_Table_33_Pack.vhdl Pattern_History_Table_33_RegisterFile_Pack.vhdl Pattern_History_Table_33_RegisterFile.vhdl Pattern_History_Table_33.vhdl
+
+# Pattern_History_Table_34
+target_dep	all	Pattern_History_Table_34.ngc
+target_dep	Pattern_History_Table_34.ngc	Pattern_History_Table_34.prj
+target_dep	Pattern_History_Table_34.prj	Pattern_History_Table_34_Counter_Pack.vhdl Pattern_History_Table_34_Counter.vhdl Pattern_History_Table_34_Pack.vhdl Pattern_History_Table_34_RegisterFile_Pack.vhdl Pattern_History_Table_34_RegisterFile.vhdl Pattern_History_Table_34.vhdl
+
+# Pattern_History_Table_35
+target_dep	all	Pattern_History_Table_35.ngc
+target_dep	Pattern_History_Table_35.ngc	Pattern_History_Table_35.prj
+target_dep	Pattern_History_Table_35.prj	Pattern_History_Table_35_Counter_Pack.vhdl Pattern_History_Table_35_Counter.vhdl Pattern_History_Table_35_Pack.vhdl Pattern_History_Table_35_RegisterFile_Pack.vhdl Pattern_History_Table_35_RegisterFile.vhdl Pattern_History_Table_35.vhdl
+
+# Pattern_History_Table_3
+target_dep	all	Pattern_History_Table_3.ngc
+target_dep	Pattern_History_Table_3.ngc	Pattern_History_Table_3.prj
+target_dep	Pattern_History_Table_3.prj	Pattern_History_Table_30_Counter_Pack.vhdl Pattern_History_Table_30_Counter.vhdl Pattern_History_Table_30_Pack.vhdl Pattern_History_Table_30_RegisterFile_Pack.vhdl Pattern_History_Table_30_RegisterFile.vhdl Pattern_History_Table_30.vhdl Pattern_History_Table_31_Counter_Pack.vhdl Pattern_History_Table_31_Counter.vhdl Pattern_History_Table_31_Pack.vhdl Pattern_History_Table_31_RegisterFile_Pack.vhdl Pattern_History_Table_31_RegisterFile.vhdl Pattern_History_Table_31.vhdl Pattern_History_Table_32_Counter_Pack.vhdl Pattern_History_Table_32_Counter.vhdl Pattern_History_Table_32_Pack.vhdl Pattern_History_Table_32_RegisterFile_Pack.vhdl Pattern_History_Table_32_RegisterFile.vhdl Pattern_History_Table_32.vhdl Pattern_History_Table_33_Counter_Pack.vhdl Pattern_History_Table_33_Counter.vhdl Pattern_History_Table_33_Pack.vhdl Pattern_History_Table_33_RegisterFile_Pack.vhdl Pattern_History_Table_33_RegisterFile.vhdl Pattern_History_Table_33.vhdl Pattern_History_Table_34_Counter_Pack.vhdl Pattern_History_Table_34_Counter.vhdl Pattern_History_Table_34_Pack.vhdl Pattern_History_Table_34_RegisterFile_Pack.vhdl Pattern_History_Table_34_RegisterFile.vhdl Pattern_History_Table_34.vhdl Pattern_History_Table_35_Counter_Pack.vhdl Pattern_History_Table_35_Counter.vhdl Pattern_History_Table_35_Pack.vhdl Pattern_History_Table_35_RegisterFile_Pack.vhdl Pattern_History_Table_35_RegisterFile.vhdl Pattern_History_Table_35.vhdl Pattern_History_Table_3_Counter_Pack.vhdl Pattern_History_Table_3_Counter.vhdl Pattern_History_Table_3_Pack.vhdl Pattern_History_Table_3_RegisterFile_Pack.vhdl Pattern_History_Table_3_RegisterFile.vhdl Pattern_History_Table_3.vhdl
+
+# Pattern_History_Table_4
+target_dep	all	Pattern_History_Table_4.ngc
+target_dep	Pattern_History_Table_4.ngc	Pattern_History_Table_4.prj
+target_dep	Pattern_History_Table_4.prj	Pattern_History_Table_4_Counter_Pack.vhdl Pattern_History_Table_4_Counter.vhdl Pattern_History_Table_4_Pack.vhdl Pattern_History_Table_4_RegisterFile_Pack.vhdl Pattern_History_Table_4_RegisterFile.vhdl Pattern_History_Table_4.vhdl
+
+# Pattern_History_Table_5
+target_dep	all	Pattern_History_Table_5.ngc
+target_dep	Pattern_History_Table_5.ngc	Pattern_History_Table_5.prj
+target_dep	Pattern_History_Table_5.prj	Pattern_History_Table_5_Counter_Pack.vhdl Pattern_History_Table_5_Counter.vhdl Pattern_History_Table_5_Pack.vhdl Pattern_History_Table_5_RegisterFile_Pack.vhdl Pattern_History_Table_5_RegisterFile.vhdl Pattern_History_Table_5.vhdl
+
+# Pattern_History_Table_6
+target_dep	all	Pattern_History_Table_6.ngc
+target_dep	Pattern_History_Table_6.ngc	Pattern_History_Table_6.prj
+target_dep	Pattern_History_Table_6.prj	Pattern_History_Table_6_Counter_Pack.vhdl Pattern_History_Table_6_Counter.vhdl Pattern_History_Table_6_Pack.vhdl Pattern_History_Table_6_RegisterFile_Pack.vhdl Pattern_History_Table_6_RegisterFile.vhdl Pattern_History_Table_6.vhdl
+
+# Pattern_History_Table_7
+target_dep	all	Pattern_History_Table_7.ngc
+target_dep	Pattern_History_Table_7.ngc	Pattern_History_Table_7.prj
+target_dep	Pattern_History_Table_7.prj	Pattern_History_Table_7_Counter_Pack.vhdl Pattern_History_Table_7_Counter.vhdl Pattern_History_Table_7_Pack.vhdl Pattern_History_Table_7_RegisterFile_Pack.vhdl Pattern_History_Table_7_RegisterFile.vhdl Pattern_History_Table_7.vhdl
+
+# Pattern_History_Table_8
+target_dep	all	Pattern_History_Table_8.ngc
+target_dep	Pattern_History_Table_8.ngc	Pattern_History_Table_8.prj
+target_dep	Pattern_History_Table_8.prj	Pattern_History_Table_8_Counter_Pack.vhdl Pattern_History_Table_8_Counter.vhdl Pattern_History_Table_8_Pack.vhdl Pattern_History_Table_8_RegisterFile_Pack.vhdl Pattern_History_Table_8_RegisterFile.vhdl Pattern_History_Table_8.vhdl
+
+# Pattern_History_Table_9
+target_dep	all	Pattern_History_Table_9.ngc
+target_dep	Pattern_History_Table_9.ngc	Pattern_History_Table_9.prj
+target_dep	Pattern_History_Table_9.prj	Pattern_History_Table_9_Counter_Pack.vhdl Pattern_History_Table_9_Counter.vhdl Pattern_History_Table_9_Pack.vhdl Pattern_History_Table_9_RegisterFile_Pack.vhdl Pattern_History_Table_9_RegisterFile.vhdl Pattern_History_Table_9.vhdl
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,47 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test 0
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h"
+
+#define NB_PARAMS 4
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - size_counter       (unsigned int)" << endl
+       << " - nb_counter         (unsigned int)" << endl
+       << " - nb_prediction      (unsigned int)" << endl
+       << " - nb_branch_complete (unsigned int)" << endl;
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc != 2+NB_PARAMS)
+    usage (argv[0]);
+
+  const string   name               = argv[1];
+  const uint32_t size_counter       = atoi(argv[2]);
+  const uint32_t nb_counter         = atoi(argv[3]);
+  const uint32_t nb_prediction      = atoi(argv[4]);
+  const uint32_t nb_branch_complete = atoi(argv[5]);
+
+  morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters param (size_counter       ,
+																       nb_counter         ,
+																       nb_prediction      ,
+																       nb_branch_complete );
+
+  test (name,param);
+
+  return (EXIT_SUCCESS);
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp	(revision 3)
@@ -0,0 +1,186 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#define NB_ITERATION 1024
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h"
+#include "Include/Test.h"
+
+void test (string name,
+	   morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  try 
+    {
+      cout << param.print(1);
+      param.test();
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      return;
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+  Pattern_History_Table * _Pattern_History_Table = new Pattern_History_Table (name.c_str(),
+#ifdef STATISTICS
+					     morpheo::behavioural::Parameters_Statistics(5,50),
+#endif
+					     param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                                 CLOCK ("clock", 1.0, 0.5);
+  sc_signal<Tcontrol_t>                    PREDICT_VAL               [param._nb_prediction];
+  sc_signal<Tcontrol_t>                    PREDICT_ACK               [param._nb_prediction];
+  sc_signal<Taddress_t>                    PREDICT_ADDRESS           [param._nb_prediction];
+  sc_signal<Thistory_t>                    PREDICT_HISTORY           [param._nb_prediction];
+				           			     
+  sc_signal<Tcontrol_t>                    BRANCH_COMPLETE_VAL       [param._nb_branch_complete];
+  sc_signal<Tcontrol_t>                    BRANCH_COMPLETE_ACK       [param._nb_branch_complete];
+  sc_signal<Taddress_t>                    BRANCH_COMPLETE_ADDRESS   [param._nb_branch_complete];
+  sc_signal<Thistory_t>                    BRANCH_COMPLETE_HISTORY   [param._nb_branch_complete];
+  sc_signal<Tcontrol_t>                    BRANCH_COMPLETE_DIRECTION [param._nb_branch_complete];
+  
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Pattern_History_Table" << endl;
+  
+  (*(_Pattern_History_Table->in_CLOCK))        (CLOCK);
+
+  for (uint32_t i=0; i<param._nb_prediction; i++)
+    {
+      (*(_Pattern_History_Table-> in_PREDICT_VAL     [i]))        (PREDICT_VAL     [i]);
+      (*(_Pattern_History_Table->out_PREDICT_ACK     [i]))        (PREDICT_ACK     [i]);
+      (*(_Pattern_History_Table-> in_PREDICT_ADDRESS [i]))        (PREDICT_ADDRESS [i]);
+      (*(_Pattern_History_Table->out_PREDICT_HISTORY [i]))        (PREDICT_HISTORY [i]);
+    }
+
+  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+    {
+      (*(_Pattern_History_Table-> in_BRANCH_COMPLETE_VAL       [i]))        (BRANCH_COMPLETE_VAL       [i]);
+      (*(_Pattern_History_Table->out_BRANCH_COMPLETE_ACK       [i]))        (BRANCH_COMPLETE_ACK       [i]);
+      (*(_Pattern_History_Table-> in_BRANCH_COMPLETE_ADDRESS   [i]))        (BRANCH_COMPLETE_ADDRESS   [i]);
+      (*(_Pattern_History_Table-> in_BRANCH_COMPLETE_HISTORY   [i]))        (BRANCH_COMPLETE_HISTORY   [i]);
+      (*(_Pattern_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i]))        (BRANCH_COMPLETE_DIRECTION [i]);
+    }
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  // Initialisation
+
+  srand(0);
+  //srand(TIME(NULL));
+
+  sc_start(0);
+  _Pattern_History_Table->vhdl_testbench_label("Initialisation");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl;
+
+
+  for (uint32_t i=0; i<param._nb_prediction; i++)
+    PREDICT_VAL         [i].write(0);
+  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+    BRANCH_COMPLETE_VAL [i].write(0);
+
+  // Initialisation of Register
+  uint32_t   num_port_branch_complete = 0;
+  uint32_t   num_port_predict         = 0;
+  Taddress_t address                  = 0;
+  Thistory_t history_max              = (1<<param._size_counter)-1;
+  Thistory_t history                  = 0;
+  Tcontrol_t direction                = 0;
+
+  while (address<param._nb_counter)
+    {
+      BRANCH_COMPLETE_VAL       [0].write(1);
+      BRANCH_COMPLETE_ADDRESS   [0].write(address);
+      BRANCH_COMPLETE_HISTORY   [0].write(0);
+      BRANCH_COMPLETE_DIRECTION [0].write(0);
+
+      sc_start(1);
+      
+      if (BRANCH_COMPLETE_ACK[0].read()==1)
+	address++;
+    }
+ 
+  BRANCH_COMPLETE_VAL     [0].write(0);
+  sc_start(0);
+
+  _Pattern_History_Table->vhdl_testbench_label("Loop of Test");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl;
+
+  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+    {
+      _Pattern_History_Table->vhdl_testbench_label("Iteration "+toString(iteration));
+      num_port_branch_complete = rand() % param._nb_branch_complete;
+      num_port_predict         = rand() % param._nb_prediction     ;
+      address                  = rand() % param._nb_counter        ;
+      history                  = rand() % (1<<param._size_counter) ;
+      direction                = rand() % 2;
+
+      cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} ["+toString(num_port_branch_complete)+"]" << endl
+	   << hex
+	   << " - address     : " << address   << endl
+	   << " - history old : " << history   << endl
+	   << " - direction   : " << direction << endl;
+
+      BRANCH_COMPLETE_VAL       [num_port_branch_complete].write(1);
+      BRANCH_COMPLETE_ADDRESS   [num_port_branch_complete].write(address);
+      BRANCH_COMPLETE_HISTORY   [num_port_branch_complete].write(history);
+      BRANCH_COMPLETE_DIRECTION [num_port_branch_complete].write(direction);
+
+      // Wait Ack
+      do
+	{
+	  sc_start(1);
+	}
+      while (BRANCH_COMPLETE_ACK[num_port_branch_complete].read()!=1);
+
+      BRANCH_COMPLETE_VAL     [num_port_branch_complete].write(0);
+      PREDICT_VAL             [num_port_predict        ].write(1);
+      PREDICT_ADDRESS         [num_port_predict        ].write(address);
+      
+      history                  = (direction==1)?((history<history_max)?history+1:history):((history>0)?history-1:history);
+      
+      // Wait Ack
+      do
+	{
+	  sc_start(1);
+	}
+      while (PREDICT_ACK        [num_port_predict        ].read()!=1);
+
+      PREDICT_VAL             [num_port_predict        ].write(0);
+
+      cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} ["+toString(num_port_predict)+"]" << endl
+	   << " - history new : " << PREDICT_HISTORY [num_port_predict].read() << endl
+	   << dec;
+
+      TEST(Thistory_t,PREDICT_HISTORY [num_port_predict].read(),history);
+    }
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete _Pattern_History_Table;
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/VERSION
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/VERSION	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/VERSION	(revision 3)
@@ -0,0 +1,1 @@
+v0.2
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h	(revision 3)
@@ -0,0 +1,62 @@
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Parameters_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Parameters.h"
+// Internal structure
+#include "Behavioural/Generic/Counter/include/Parameters.h"
+#include "Behavioural/Generic/RegisterFile/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+    //-----[ fields ]------------------------------------------------------------
+  public : const uint32_t _size_counter      ;
+  public : const uint32_t _nb_counter        ;
+  public : const uint32_t _nb_prediction     ;
+  public : const uint32_t _nb_branch_complete;
+
+  public :       morpheo::behavioural::generic::counter::Parameters      * _param_counter;
+  public :       morpheo::behavioural::generic::registerfile::Parameters * _param_registerfile;
+
+    //-----[ methods ]-----------------------------------------------------------
+  public : Parameters  (uint32_t size_counter      ,
+ 			uint32_t nb_counter        ,
+			uint32_t nb_prediction     ,
+			uint32_t nb_branch_complete);
+  public : Parameters  (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters & x);
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h	(revision 3)
@@ -0,0 +1,150 @@
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Pattern_History_Table_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Pattern_History_Table_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <iostream>
+#include "Include/ToString.h"
+#include "Include/Debug.h"
+
+// Internal structure
+#include "Behavioural/Generic/Counter/include/Counter.h"
+#include "Behavioural/Generic/RegisterFile/include/RegisterFile.h"
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h"
+#endif
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#ifdef VHDL_TESTBENCH
+#include "Behavioural/include/Vhdl_Testbench.h"
+#endif
+
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  class Pattern_History_Table 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string     _name;
+
+  protected : const Parameters _param;
+#ifdef STATISTICS
+ protected : const morpheo::behavioural::Parameters_Statistics _param_statistics;
+#endif
+
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+#endif
+
+#ifdef VHDL_TESTBENCH
+  private   : Vhdl_Testbench                 * _vhdl_testbench;
+#endif
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK        ;
+
+  public    : SC_IN (Tcontrol_t)           **  in_PREDICT_VAL            ;
+  public    : SC_OUT(Tcontrol_t)           ** out_PREDICT_ACK            ;
+  public    : SC_IN (Taddress_t)           **  in_PREDICT_ADDRESS        ;
+  public    : SC_OUT(Thistory_t)           ** out_PREDICT_HISTORY        ;
+
+  public    : SC_IN (Tcontrol_t)           **  in_BRANCH_COMPLETE_VAL    ;
+  public    : SC_OUT(Tcontrol_t)           ** out_BRANCH_COMPLETE_ACK    ;
+  public    : SC_IN (Taddress_t)           **  in_BRANCH_COMPLETE_ADDRESS;
+  public    : SC_IN (Thistory_t)           **  in_BRANCH_COMPLETE_HISTORY;
+  public    : SC_IN (Tcontrol_t)           **  in_BRANCH_COMPLETE_DIRECTION;
+
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_SIGNAL(Thistory_t)        ** signal_BRANCH_COMPLETE_HISTORY;
+#endif
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+  public    : morpheo::behavioural::generic::counter::Counter           * component_Counter     ;
+  public    : morpheo::behavioural::generic::registerfile::RegisterFile * component_RegisterFile;
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (Pattern_History_Table);
+#endif					       
+
+  public  :          Pattern_History_Table              (
+#ifdef SYSTEMC
+							 sc_module_name                              name,
+#else					       
+							 string                                      name,
+#endif					       
+#ifdef STATISTICS
+							 morpheo::behavioural::Parameters_Statistics param_statistics,
+#endif
+							 Parameters                                  param );
+    
+  public  :          Pattern_History_Table              (Parameters param );
+  public  :          ~Pattern_History_Table             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+  public  : void     transition                (void);
+#endif
+#endif					       
+
+#ifdef STATISTICS
+  public  : string   statistics                (uint32_t depth);
+#endif
+					       
+#if VHDL				       
+  public  : void     vhdl                      (void);
+  private : void     vhdl_port                 (Vhdl & vhdl);
+  private : void     vhdl_declaration          (Vhdl & vhdl);
+  private : void     vhdl_body                 (Vhdl & vhdl);
+#endif					       
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench_port       (void);
+  private : void     vhdl_testbench_transition (void);
+#endif
+  public  : void     vhdl_testbench_label      (string label);
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h	(revision 3)
@@ -0,0 +1,65 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Statistics_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+#include "Behavioural/Generic/Counter/include/Statistics.h"
+#include "Behavioural/Generic/RegisterFile/include/Statistics.h"
+//#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h"
+
+//using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                   _parameters;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics  (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  );
+//public   : Statistics  (Statistics & stat);
+  public   : ~Statistics () ;
+    
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : string   print      (uint32_t depth,
+				  string   component_stat);
+  public   : void     add        ();
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h	(revision 3)
@@ -0,0 +1,34 @@
+#ifdef SYSTEMC
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Type_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_pattern_history_table_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Types.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+  typedef uint32_t Thistory_t;
+  typedef uint32_t Taddress_t;
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,76 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  Parameters::Parameters (uint32_t size_counter      ,
+ 			  uint32_t nb_counter        ,
+			  uint32_t nb_prediction     ,
+			  uint32_t nb_branch_complete) :
+    _size_counter       (size_counter      ),
+    _nb_counter         (nb_counter        ),
+    _nb_prediction      (nb_prediction     ),
+    _nb_branch_complete (nb_branch_complete)
+  {
+    log_printf(FUNC,Pattern_History_Table,"Parameters","Begin");
+
+    _param_counter      = new morpheo::behavioural::generic::counter::Parameters (size_counter       ,
+										  nb_branch_complete );
+    _param_registerfile = new morpheo::behavioural::generic::registerfile::Parameters (nb_prediction      ,
+										       nb_branch_complete ,
+										       nb_counter         ,
+										       size_counter       );
+    
+
+    test();
+    log_printf(FUNC,Pattern_History_Table,"Parameters","End");
+  };
+  
+  Parameters::Parameters (Parameters & param) :
+    _size_counter       (param._size_counter      ),
+    _nb_counter         (param._nb_counter        ),
+    _nb_prediction      (param._nb_prediction     ),
+    _nb_branch_complete (param._nb_branch_complete)
+  {
+    log_printf(FUNC,Pattern_History_Table,"Parameters","Begin");
+
+    _param_counter = new morpheo::behavioural::generic::counter::Parameters (param._size_counter       ,
+									     param._nb_branch_complete );
+
+    _param_registerfile = new morpheo::behavioural::generic::registerfile::Parameters (param._nb_prediction      ,
+										       param._nb_branch_complete ,
+										       param._nb_counter         ,
+										       param._size_counter       );
+
+    test();
+    log_printf(FUNC,Pattern_History_Table,"Parameters","End");
+  };
+
+  Parameters::~Parameters () 
+  {
+    log_printf(FUNC,Pattern_History_Table,"~Parameters","Begin");
+    delete _param_counter;
+    delete _param_registerfile;
+    log_printf(FUNC,Pattern_History_Table,"~Parameters","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_msg_error.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_msg_error.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_msg_error.cpp	(revision 3)
@@ -0,0 +1,58 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Types.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  string Parameters::msg_error(void)
+  {
+    log_printf(FUNC,Pattern_History_Table,"msg_error","Begin");
+
+    string msg = "";
+
+    if (is_positive (_size_counter) == false)
+      {
+	msg += "  - size_counter must be > 0\n";
+	msg += "    * size_counter                    : " + toString(_size_counter) + "\n";
+      }
+
+    if (is_positive (_nb_prediction) == false)
+      {
+	msg += "  - nb_prediction must be > 0\n";
+	msg += "    * nb_prediction                   : " + toString(_nb_prediction) + "\n";
+      }
+
+    if (is_positive (_nb_branch_complete) == false)
+      {
+	msg += "  - nb_branch_complete must be > 0\n";
+	msg += "    * nb_branch_complete              : " + toString(_nb_branch_complete) + "\n";
+      }
+
+    return msg;
+
+    log_printf(FUNC,Pattern_History_Table,"msg_error","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters_print.cpp	(revision 3)
@@ -0,0 +1,56 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  string Parameters::print (uint32_t depth)
+  {
+    log_printf(FUNC,Pattern_History_Table,"print","Begin");
+
+    string tab = string(depth,'\t');
+    ostringstream msg;
+    msg << tab << "<pattern_history_table>" << endl
+	<< tab << "\t<size_counter       value=\"" << _size_counter       << "\" />" << endl
+ 	<< tab << "\t<nb_counter         value=\"" << _nb_counter         << "\" />" << endl
+	<< tab << "\t<nb_prediction      value=\"" << _nb_prediction      << "\" />" << endl
+	<< tab << "\t<nb_branch_complete value=\"" << _nb_branch_complete << "\" />" << endl;
+    msg << _param_counter     ->print(depth+1);
+    msg << _param_registerfile->print(depth+1);
+    msg << tab << "</pattern_history_table>" << endl;
+
+    log_printf(FUNC,Pattern_History_Table,"print","End");
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp	(revision 3)
@@ -0,0 +1,110 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+#ifdef SYSTEMC
+  Pattern_History_Table::Pattern_History_Table (sc_module_name name,
+#else
+  Pattern_History_Table::Pattern_History_Table (string name,
+#endif
+#ifdef STATISTICS
+			      morpheo::behavioural::Parameters_Statistics             param_statistics,
+#endif
+			      morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters param ):
+			      _name              (name)
+			      ,_param            (param)
+#ifdef STATISTICS
+			      ,_param_statistics (param_statistics)
+#endif
+  {
+    log_printf(FUNC,Pattern_History_Table,"Pattern_History_Table","Begin");
+    
+#ifdef STATISTICS
+    // Allocation of statistics
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // Creation of a testbench
+    //  -> port
+    //  -> clock's signals
+    _vhdl_testbench = new Vhdl_Testbench (_name);
+    vhdl_testbench_port           ();
+    _vhdl_testbench->set_clock    ("in_CLOCK",true);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    allocation ();
+
+    // Constant
+    for (uint32_t i=0; i<_param._nb_prediction     ; i++)
+      PORT_WRITE(out_PREDICT_ACK         [i],1);
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1);
+
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+#endif
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+#endif    
+
+#endif
+    log_printf(FUNC,Pattern_History_Table,"Pattern_History_Table","End");
+  };
+  
+  Pattern_History_Table::~Pattern_History_Table (void)
+  {
+    log_printf(FUNC,Pattern_History_Table,"~Pattern_History_Table","Begin");
+
+#ifdef VHDL_TESTBENCH
+    // generate the test bench
+    _vhdl_testbench->generate_file();
+    delete _vhdl_testbench;
+#endif
+
+#ifdef STATISTICS
+    _stat->generate_file(statistics(0));
+    
+    delete _stat;
+#endif
+
+#ifdef SYSTEMC
+    deallocation ();
+#endif
+
+    log_printf(FUNC,Pattern_History_Table,"~Pattern_History_Table","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp	(revision 3)
@@ -0,0 +1,140 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::allocation (void)
+  {
+    string rename;
+
+    log_printf(FUNC,Pattern_History_Table,"allocation","Begin");
+
+    in_CLOCK  = new SC_CLOCK           ("in_CLOCK");
+
+     in_PREDICT_VAL     = new SC_IN (Tcontrol_t) * [_param._nb_prediction];
+    out_PREDICT_ACK     = new SC_OUT(Tcontrol_t) * [_param._nb_prediction];
+     in_PREDICT_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_prediction];
+    out_PREDICT_HISTORY = new SC_OUT(Thistory_t) * [_param._nb_prediction];
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	rename = "in_PREDICT_VAL["     +toString(i)+"]";
+	 in_PREDICT_VAL     [i] = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	rename = "out_PREDICT_ACK["    +toString(i)+"]";
+	out_PREDICT_ACK     [i] = new SC_OUT(Tcontrol_t) (rename.c_str());
+
+	rename = "in_PREDICT_ADDRESS["+toString(i)+"]";
+	 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());
+
+	rename = "out_PREDICT_HISTORY["+toString(i)+"]";
+	out_PREDICT_HISTORY [i] = new SC_OUT(Thistory_t) (rename.c_str());
+      }
+
+        in_BRANCH_COMPLETE_VAL       = new SC_IN     (Tcontrol_t) * [_param._nb_branch_complete];
+       out_BRANCH_COMPLETE_ACK       = new SC_OUT    (Tcontrol_t) * [_param._nb_branch_complete];
+        in_BRANCH_COMPLETE_ADDRESS   = new SC_IN     (Taddress_t) * [_param._nb_branch_complete];
+        in_BRANCH_COMPLETE_HISTORY   = new SC_IN     (Thistory_t) * [_param._nb_branch_complete];
+        in_BRANCH_COMPLETE_DIRECTION = new SC_IN     (Tcontrol_t) * [_param._nb_branch_complete];
+    signal_BRANCH_COMPLETE_HISTORY   = new SC_SIGNAL (Thistory_t) * [_param._nb_branch_complete];
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	 rename = "in_BRANCH_COMPLETE_VAL["    +toString(i)+"]";
+	  in_BRANCH_COMPLETE_VAL     [i] = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	 rename = "out_BRANCH_COMPLETE_ACK["   +toString(i)+"]";
+	 out_BRANCH_COMPLETE_ACK     [i] = new SC_OUT(Tcontrol_t) (rename.c_str());
+
+	 rename = "in_BRANCH_COMPLETE_ADDRESS["+toString(i)+"]";
+	  in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());
+
+	 rename = "in_BRANCH_COMPLETE_HISTORY["+toString(i)+"]";
+	  in_BRANCH_COMPLETE_HISTORY [i] = new SC_IN (Thistory_t) (rename.c_str());
+
+	 rename = "in_BRANCH_COMPLETE_DIRECTION["    +toString(i)+"]";
+	  in_BRANCH_COMPLETE_DIRECTION [i] = new SC_IN (Tcontrol_t) (rename.c_str());
+
+	 rename = "signal_BRANCH_COMPLETE_HISTORY["+toString(i)+"]";
+	 signal_BRANCH_COMPLETE_HISTORY [i] = new SC_SIGNAL (Thistory_t) (rename.c_str());
+
+      }
+    
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    string name_component;
+    // =====[ component_Counter ]=========================================    
+    
+    name_component = _name+"_Counter";
+
+    component_Counter = new morpheo::behavioural::generic::counter::Counter (name_component.c_str(),
+#ifdef STATISTICS
+									     _param_statistics             ,
+#endif
+									     *(_param._param_counter)      );
+    
+    
+    // Instantiation
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+    (*(component_Counter->in_CLOCK))        (*(in_CLOCK));
+#endif
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	(*(component_Counter-> in_COUNTER_DATA       [i]))    (*(    in_BRANCH_COMPLETE_HISTORY   [i]));
+	(*(component_Counter-> in_COUNTER_ADDSUB     [i]))    (*(    in_BRANCH_COMPLETE_DIRECTION [i]));
+	(*(component_Counter->out_COUNTER_DATA       [i]))    (*(signal_BRANCH_COMPLETE_HISTORY   [i]));
+      }
+    
+     // =====[ component_RegisterFile ]====================================    
+    
+    name_component = _name+"_RegisterFile";
+    
+    component_RegisterFile = new morpheo::behavioural::generic::registerfile::RegisterFile (name_component.c_str(),
+#ifdef STATISTICS
+											    _param_statistics            ,
+#endif
+											    *(_param._param_registerfile));
+     
+    // Instantiation
+    (*(component_RegisterFile->in_CLOCK))        (*(in_CLOCK));
+    
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	(*(component_RegisterFile-> in_READ_ENABLE   [i])) (*( in_PREDICT_VAL      [i]));
+	(*(component_RegisterFile-> in_READ_ADDRESS  [i])) (*( in_PREDICT_ADDRESS  [i]));
+	(*(component_RegisterFile->out_READ_DATA     [i])) (*(out_PREDICT_HISTORY  [i]));    
+      }
+    
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	(*(component_RegisterFile-> in_WRITE_ENABLE  [i])) (*(    in_BRANCH_COMPLETE_VAL      [i]));
+	(*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*(    in_BRANCH_COMPLETE_ADDRESS  [i]));
+	(*(component_RegisterFile-> in_WRITE_DATA    [i])) (*(signal_BRANCH_COMPLETE_HISTORY  [i]));    
+      }
+
+    log_printf(FUNC,Pattern_History_Table,"allocation","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp	(revision 3)
@@ -0,0 +1,68 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::deallocation (void)
+  {
+    log_printf(FUNC,Pattern_History_Table,"deallocation","Begin");
+
+    delete in_CLOCK;
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	delete  in_PREDICT_VAL     [i];
+	delete out_PREDICT_ACK     [i];
+	delete  in_PREDICT_ADDRESS [i];
+	delete out_PREDICT_HISTORY [i];
+      }
+
+    delete  in_PREDICT_VAL    ;
+    delete out_PREDICT_ACK    ;
+    delete  in_PREDICT_ADDRESS;
+    delete out_PREDICT_HISTORY;
+
+     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+       {
+	 delete  in_BRANCH_COMPLETE_VAL       [i];
+	 delete out_BRANCH_COMPLETE_ACK       [i];
+	 delete  in_BRANCH_COMPLETE_ADDRESS   [i];
+	 delete  in_BRANCH_COMPLETE_HISTORY   [i];
+	 delete  in_BRANCH_COMPLETE_DIRECTION [i];
+       }
+    delete  in_BRANCH_COMPLETE_VAL    ;
+    delete out_BRANCH_COMPLETE_ACK    ;
+    delete  in_BRANCH_COMPLETE_ADDRESS;
+    delete  in_BRANCH_COMPLETE_HISTORY;
+    delete  in_BRANCH_COMPLETE_DIRECTION;
+
+     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    delete component_Counter;
+    delete component_RegisterFile;
+
+    log_printf(FUNC,Pattern_History_Table,"deallocation","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_statistics.cpp	(revision 3)
@@ -0,0 +1,41 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+  string Pattern_History_Table::statistics (uint32_t depth)
+  {
+    log_printf(FUNC,Pattern_History_Table,"statistics","Begin");
+
+    string stat_print = _stat->print(depth,
+				     component_Counter     ->statistics(depth+1) + 
+				     component_RegisterFile->statistics(depth+1)
+				     );
+
+    log_printf(FUNC,Pattern_History_Table,"statistics","End");
+
+    return stat_print;
+      
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_transition.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef SYSTEMC
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::transition (void)
+  {
+    log_printf(FUNC,Pattern_History_Table,"transition","Begin");
+
+#ifdef STATISTICS
+    _stat->add();
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition ();
+#endif
+
+    log_printf(FUNC,Pattern_History_Table,"transition","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl.cpp	(revision 3)
@@ -0,0 +1,47 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::vhdl (void)
+  {
+    log_printf(FUNC,Pattern_History_Table,"vhdl","Begin");
+    Vhdl vhdl (_name);
+
+    vhdl.set_library_work (_name + "_Pack");
+    vhdl.set_library_work (_name + "_RegisterFile_Pack");
+    vhdl.set_library_work (_name + "_Counter_Pack");
+
+    vhdl_port        (vhdl);
+    vhdl_declaration (vhdl);
+    vhdl_body        (vhdl);
+
+    vhdl.generate_file();
+    log_printf(FUNC,Pattern_History_Table,"vhdl","End");
+
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp	(revision 3)
@@ -0,0 +1,70 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::vhdl_body (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin");
+
+    vhdl.set_body ("-- Output : always at '1'");
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");
+    for (uint32_t i=0; i<_param._nb_prediction     ; i++)
+      vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+"         <= '1';");
+    vhdl.set_body ("");
+
+    list<string> list_port_map;
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	vhdl.set_body_component_port_map (list_port_map," in_COUNTER_DATA_"+toString(i)+"     ","    in_BRANCH_COMPLETE_HISTORY_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map," in_COUNTER_ADDSUB_"+toString(i)+"   ","    in_BRANCH_COMPLETE_DIRECTION_"+toString(i)    );
+	vhdl.set_body_component_port_map (list_port_map,"out_COUNTER_DATA_"+toString(i)+"     ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
+      }
+    vhdl.set_body_component ("component_Counter",_name+"_Counter",list_port_map);
+
+
+    list_port_map.clear();
+    vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK");
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	vhdl.set_body_component_port_map (list_port_map," in_READ_ENABLE_"+toString(i)+"  "," in_PREDICT_VAL_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+"    ","out_PREDICT_HISTORY_"+toString(i));    
+      }
+    
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	vhdl.set_body_component_port_map (list_port_map," in_WRITE_ENABLE_"+toString(i)+" ","    in_BRANCH_COMPLETE_VAL_"+toString(i)+"");
+	vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+"","    in_BRANCH_COMPLETE_ADDRESS_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+"   ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
+      }
+    vhdl.set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map);
+
+    log_printf(FUNC,Pattern_History_Table,"vhdl_body","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_port.cpp	(revision 3)
@@ -0,0 +1,53 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::vhdl_port (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Pattern_History_Table,"vhdl_port","Begin");
+
+    vhdl.set_port (" in_CLOCK" , IN, 1);
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	vhdl.set_port(" in_PREDICT_VAL_"+toString(i)+"               ", IN, 1);
+	vhdl.set_port("out_PREDICT_ACK_"+toString(i)+"               ",OUT, 1);
+	vhdl.set_port(" in_PREDICT_ADDRESS_"+toString(i)+"           ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter))));
+	vhdl.set_port("out_PREDICT_HISTORY_"+toString(i)+"           ",OUT, _param._size_counter);
+      }
+     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+       {
+	 vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+"      ", IN, 1);
+	 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+"      ",OUT, 1);
+	 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+"  ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter))));
+	 vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+"  ", IN, _param._size_counter);
+	 vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1);
+       }
+
+    log_printf(FUNC,Pattern_History_Table,"vhdl_port","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_signal.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_signal.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_signal.cpp	(revision 3)
@@ -0,0 +1,38 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::vhdl_declaration (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","Begin");
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      vhdl.set_signal  ("signal_BRANCH_COMPLETE_HISTORY_"+toString(i), _param._size_counter);
+
+    log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_label.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_label.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_label.cpp	(revision 3)
@@ -0,0 +1,33 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::vhdl_testbench_label (string label)
+  {
+#ifdef VHDL_TESTBENCH
+    _vhdl_testbench->add_label(label);
+#endif
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_port.cpp	(revision 3)
@@ -0,0 +1,52 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::vhdl_testbench_port ()
+  {
+    log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_port","Begin");
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	_vhdl_testbench->set_port (" in_PREDICT_VAL_"+toString(i)+"              ", IN, 1);
+	_vhdl_testbench->set_port ("out_PREDICT_ACK_"+toString(i)+"              ",OUT, 1);
+	_vhdl_testbench->set_port (" in_PREDICT_ADDRESS_"+toString(i)+"          ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter))));
+	_vhdl_testbench->set_port ("out_PREDICT_HISTORY_"+toString(i)+"          ",OUT, _param._size_counter);
+      }										  
+										  
+     for (uint32_t i=0; i<_param._nb_branch_complete; i++)			  
+       {									  
+	 _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+"      ", IN, 1);
+	 _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+"      ",OUT, 1);
+	 _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+"  ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter))));
+	 _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+"  ", IN, _param._size_counter);
+	 _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1);
+       }
+
+    log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_port","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp	(revision 3)
@@ -0,0 +1,68 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Pattern_History_Table::vhdl_testbench_transition ()
+  {
+    log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","Begin");
+
+#ifndef SYSTEMCASS_SPECIFIC
+    sc_cycle(0);
+#endif    
+
+    // In order with file Pattern_History_Table_vhdl_testbench_port.cpp
+    // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
+    // (because we have no control on the ordonnancer's policy)
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	_vhdl_testbench->add_input  (PORT_READ( in_PREDICT_VAL     [i]));
+	_vhdl_testbench->add_output (PORT_READ(out_PREDICT_ACK     [i]));
+	_vhdl_testbench->add_input  (PORT_READ( in_PREDICT_ADDRESS [i]));
+	_vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i]));
+      //_vhdl_testbench->add_output (PORT_READ(out_PREDICT_HISTORY [i]));
+      }
+
+     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+       {
+	 _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_VAL      [i]));
+	 _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_ACK      [i]));
+	 _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_ADDRESS  [i]));
+	 _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_HISTORY  [i]));
+	 _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_DIRECTION[i]));
+       }
+        
+    // add_test :
+    //  - True  : the cycle must be compare with the output of systemC
+    //  - False : no test
+    _vhdl_testbench->add_test(true);
+
+    _vhdl_testbench->new_cycle (); // always at the end
+
+    log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,46 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+    log_printf(FUNC,Pattern_History_Table,"Statistics","Begin");
+    log_printf(FUNC,Pattern_History_Table,"Statistics","End");
+  };
+  
+  Statistics::~Statistics () 
+  { 
+    log_printf(FUNC,Pattern_History_Table,"~Statistics","Begin");
+    log_printf(FUNC,Pattern_History_Table,"~Statistics","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,37 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  void Statistics::add ()
+  {
+    log_printf(FUNC,Pattern_History_Table,"add","Begin");
+    log_printf(FUNC,Pattern_History_Table,"add","End");
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,69 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  string Statistics::print (uint32_t depth ,
+			    string component_stat)
+  {
+    log_printf(FUNC,Pattern_History_Table,"print","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<pattern_history_table name=\"" << _name << "\" >" << endl
+        << print_body(depth+1)
+	<< component_stat
+	<< tab << "</pattern_history_table>" << endl;
+    
+    log_printf(FUNC,Pattern_History_Table,"print","End");
+
+    return msg.str();
+  };
+
+  string Statistics::print (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<pattern_history_table name=\"" << _name << "\" >" << endl
+	<< print_body(depth+1) << endl
+	<< tab << "</pattern_history_table>" << endl;
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace pattern_history_table {
+
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    log_printf(FUNC,Pattern_History_Table,"print_body","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "";
+    
+    log_printf(FUNC,Pattern_History_Table,"print_body","End");
+
+    return msg.str();
+  };
+
+}; // end namespace pattern_history_table
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,29 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../../../..
+
+LIBRARY				= $(Two_Level_Branch_Predictor_LIBRARY)
+
+DIR_LIBRARY			= $(Two_Level_Branch_Predictor_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				:
+				@$(MAKE) all_selftest
+
+library				: Two_Level_Branch_Predictor_library
+
+library_clean			: Two_Level_Branch_Predictor_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration.cfg	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/configuration.cfg	(revision 3)
@@ -0,0 +1,11 @@
+Two_Level_Branch_Predictor
+1	1	+1	# have_bht           
+6	8	+1	# bht_size_shifter   
+64	64	*2	# bht_nb_shifter     
+0	1	+1	# have_pht           
+4	4	+1	# pht_size_counter   
+256	512	*2	# pht_nb_counter     
+0	2	+1	# pht_size_address_share
+16	16	+1	# size_address      
+1	1	+1	# nb_prediction     
+1	1	+1	# nb_branch_complete
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/include/test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/include/test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/include/test.h	(revision 3)
@@ -0,0 +1,28 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::stage_1_ifetch;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor;
+
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor;
+
+void test   (string name,
+	     morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param);
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/mkf.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/mkf.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/mkf.info	(revision 3)
@@ -0,0 +1,6 @@
+
+# Two_Level_Branch_Predictor_0
+target_dep	all	Two_Level_Branch_Predictor_0.ngc
+target_dep	Two_Level_Branch_Predictor_0.ngc	Two_Level_Branch_Predictor_0.prj
+target_dep	Two_Level_Branch_Predictor_0.prj	Two_Level_Branch_Predictor_0_Branch_History_Table_Pack.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table_RegisterFile_Pack.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table_RegisterFile.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table_Shifter_Pack.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table_Shifter.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table.vhdl Two_Level_Branch_Predictor_0_Pack.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_Counter_Pack.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_Counter.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_Pack.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_RegisterFile_Pack.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_RegisterFile.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table.vhdl Two_Level_Branch_Predictor_0_Two_Level_Branch_Predictor_Glue_Pack.vhdl Two_Level_Branch_Predictor_0_Two_Level_Branch_Predictor_Glue.vhdl Two_Level_Branch_Predictor_0.vhdl
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,83 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/include/test.h"
+
+#define NB_PARAMS 10
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - have_bht               (boolean     )" << endl
+       << " - bht_size_shifter       (unsigned int)" << endl
+       << " - bht_nb_shifter         (unsigned int)" << endl
+       << " - have_pht               (boolean     )" << endl
+       << " - pht_size_counter       (unsigned int)" << endl
+       << " - pht_nb_counter         (unsigned int)" << endl
+       << " - pht_size_address_share (unsigned int)" << endl
+       << " - size_address           (unsigned int)" << endl
+       << " - nb_prediction          (unsigned int)" << endl
+       << " - nb_branch_complete     (unsigned int)" << endl;
+
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  cout << "<test0> : Classic usage" << endl;
+
+  if (argc != 2+NB_PARAMS)
+    usage (argv[0]);
+  
+  const string   name                     = argv[1];
+  const bool     have_bht                 = atoi(argv[ 2]);
+  const uint32_t bht_size_shifter         = atoi(argv[ 3]);
+  const uint32_t bht_nb_shifter           = atoi(argv[ 4]);
+  const bool     have_pht                 = atoi(argv[ 5]);
+  const uint32_t pht_size_counter         = atoi(argv[ 6]);
+  const uint32_t pht_nb_counter           = atoi(argv[ 7]);
+  const uint32_t pht_size_address_share   = atoi(argv[ 8]);
+  const uint32_t size_address             = atoi(argv[ 9]);
+  const uint32_t nb_prediction            = atoi(argv[10]);
+  const uint32_t nb_branch_complete       = atoi(argv[11]);
+
+  try 
+    {
+      morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param (have_bht               ,
+														     bht_size_shifter       ,
+														     bht_nb_shifter         ,
+														     have_pht               ,
+														     pht_size_counter       ,
+														     pht_nb_counter         ,
+														     pht_size_address_share ,
+														     size_address           ,
+														     nb_prediction          ,
+														     nb_branch_complete     );
+      
+      cout << param.print(1);
+      
+      test (name,param);
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      exit (EXIT_FAILURE);
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+
+  return (EXIT_SUCCESS);
+}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp	(revision 3)
@@ -0,0 +1,285 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#define NB_ITERATION 512
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/include/test.h"
+#include "Include/Test.h"
+#include "Include/BitManipulation.h"
+void test (string name,
+	   morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  Two_Level_Branch_Predictor * _Two_Level_Branch_Predictor = new Two_Level_Branch_Predictor (name.c_str(),
+#ifdef STATISTICS
+					     morpheo::behavioural::Parameters_Statistics(5,50),
+#endif
+					     param);
+  
+#ifdef SYSTEMC
+
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                              *  CLOCK;
+
+  sc_signal<Tcontrol_t>                 *  PREDICT_VAL                 [param._nb_prediction];
+  sc_signal<Tcontrol_t>                 *  PREDICT_ACK                 [param._nb_prediction];
+  sc_signal<Taddress_t>                 *  PREDICT_ADDRESS             [param._nb_prediction];
+  sc_signal<Tbht_history_t>             *  PREDICT_BHT_HISTORY         [param._nb_prediction];
+  sc_signal<Tpht_history_t>             *  PREDICT_PHT_HISTORY         [param._nb_prediction];
+				      	 
+  sc_signal<Tcontrol_t>                 *  BRANCH_COMPLETE_VAL         [param._nb_branch_complete];
+  sc_signal<Tcontrol_t>                 *  BRANCH_COMPLETE_ACK         [param._nb_branch_complete];
+  sc_signal<Taddress_t>                 *  BRANCH_COMPLETE_ADDRESS     [param._nb_branch_complete];
+  sc_signal<Tbht_history_t>             *  BRANCH_COMPLETE_BHT_HISTORY [param._nb_branch_complete];
+  sc_signal<Tpht_history_t>             *  BRANCH_COMPLETE_PHT_HISTORY [param._nb_branch_complete];
+  sc_signal<Tcontrol_t>                 *  BRANCH_COMPLETE_DIRECTION   [param._nb_branch_complete];
+
+  // Rename signal
+
+  string rename;
+
+  CLOCK = new sc_clock ("clock", 1.0, 0.5);
+
+  for (uint32_t i=0; i<param._nb_prediction; i++)
+    {
+      rename = "PREDICT_VAL_"        +toString(i);
+      PREDICT_VAL                 [i] = new sc_signal<Tcontrol_t>     (rename.c_str());
+      rename = "PREDICT_ACK_"        +toString(i);
+      PREDICT_ACK                 [i] = new sc_signal<Tcontrol_t>     (rename.c_str());
+      rename = "PREDICT_ADDRESS_"    +toString(i);
+      PREDICT_ADDRESS             [i] = new sc_signal<Taddress_t>     (rename.c_str());
+      rename = "PREDICT_BHT_HISTORY_"+toString(i);
+      PREDICT_BHT_HISTORY         [i] = new sc_signal<Tbht_history_t> (rename.c_str());
+      rename = "PREDICT_PHT_HISTORY_"+toString(i);
+      PREDICT_PHT_HISTORY         [i] = new sc_signal<Tpht_history_t> (rename.c_str());
+    }
+  
+  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+    {
+      rename = "BRANCH_COMPLETE_VAL_"        +toString(i);
+      BRANCH_COMPLETE_VAL         [i] = new sc_signal<Tcontrol_t>     (rename.c_str());
+      rename = "BRANCH_COMPLETE_ACK_"        +toString(i);
+      BRANCH_COMPLETE_ACK         [i] = new sc_signal<Tcontrol_t>     (rename.c_str());
+      rename = "BRANCH_COMPLETE_ADDRESS_"    +toString(i);
+      BRANCH_COMPLETE_ADDRESS     [i] = new sc_signal<Taddress_t>     (rename.c_str());
+      rename = "BRANCH_COMPLETE_BHT_HISTORY_"+toString(i);
+      BRANCH_COMPLETE_BHT_HISTORY [i] = new sc_signal<Tbht_history_t> (rename.c_str());
+      rename = "BRANCH_COMPLETE_PHT_HISTORY_"+toString(i);
+      BRANCH_COMPLETE_PHT_HISTORY [i] = new sc_signal<Tpht_history_t> (rename.c_str());
+      rename = "BRANCH_COMPLETE_DIRECTION_"  +toString(i);
+      BRANCH_COMPLETE_DIRECTION   [i] = new sc_signal<Tcontrol_t>     (rename.c_str());
+    }
+
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Two_Level_Branch_Predictor" << endl;
+  
+  (*(_Two_Level_Branch_Predictor->in_CLOCK))        (*(CLOCK));
+  
+  for (uint32_t i=0; i<param._nb_prediction; i++)
+    {
+      (*(_Two_Level_Branch_Predictor-> in_PREDICT_VAL                 [i])) (*(PREDICT_VAL                  [i]));
+      (*(_Two_Level_Branch_Predictor->out_PREDICT_ACK                 [i])) (*(PREDICT_ACK                  [i]));
+      (*(_Two_Level_Branch_Predictor-> in_PREDICT_ADDRESS             [i])) (*(PREDICT_ADDRESS              [i]));
+      if (param._have_bht)						       				       
+      (*(_Two_Level_Branch_Predictor->out_PREDICT_BHT_HISTORY         [i])) (*(PREDICT_BHT_HISTORY          [i]));
+      if (param._have_pht)
+      (*(_Two_Level_Branch_Predictor->out_PREDICT_PHT_HISTORY         [i])) (*(PREDICT_PHT_HISTORY          [i]));
+    }
+
+    for (uint32_t i=0; i<param._nb_branch_complete; i++)
+      {
+	(*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_VAL         [i])) (*(BRANCH_COMPLETE_VAL          [i]));
+	(*(_Two_Level_Branch_Predictor->out_BRANCH_COMPLETE_ACK         [i])) (*(BRANCH_COMPLETE_ACK          [i]));
+	(*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_ADDRESS     [i])) (*(BRANCH_COMPLETE_ADDRESS      [i]));
+	if (param._have_bht)						       					
+	(*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (*(BRANCH_COMPLETE_BHT_HISTORY  [i]));
+	if (param._have_pht)						       					
+	(*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_PHT_HISTORY [i])) (*(BRANCH_COMPLETE_PHT_HISTORY  [i]));
+	(*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_DIRECTION   [i])) (*(BRANCH_COMPLETE_DIRECTION    [i]));
+      }
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  // Initialisation
+
+  const uint32_t seed = 0;
+//const uint32_t seed = static_cast<uint32_t>(time(NULL));
+
+  srand(seed);
+
+  const uint32_t   num_port_predict         = rand()%param._nb_prediction;
+  const uint32_t   num_port_branch_complete = rand()%param._nb_branch_complete;
+  const Taddress_t address                  = rand()%param._size_address;
+        Tcontrol_t direction;
+
+  sc_start(0);
+
+  for (uint32_t i=0; i<param._nb_prediction; i++)
+    PREDICT_VAL                  [i]->write(0);
+  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+    BRANCH_COMPLETE_VAL          [i]->write(0);
+
+  _Two_Level_Branch_Predictor->vhdl_testbench_label("Initialisation");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl;
+
+  // Step 1
+  BRANCH_COMPLETE_VAL          [num_port_branch_complete]->write(1);
+  BRANCH_COMPLETE_DIRECTION    [num_port_branch_complete]->write(0);
+
+  if (param._have_pht)						       					
+    {
+      // Step 1.1 -> pattern_history_table
+
+      // Step 1.1.1 compute number of group.
+      uint32_t size_address_shift=0;
+
+      if (param._have_bht)
+	size_address_shift=param._param_two_level_branch_predictor_glue->_pht_size_address_shift;
+
+      uint32_t nb_group        = (1<<size_address_shift);
+      uint32_t nb_reg_by_group = (1<<(param._pht_size_address-size_address_shift));
+
+      _Two_Level_Branch_Predictor->vhdl_testbench_label("Init pht");
+      cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Init pht" << endl;
+      
+      BRANCH_COMPLETE_PHT_HISTORY  [num_port_branch_complete]->write(0);
+
+      // Step 1.1.2 for all group ...
+      for (uint32_t i=0; i<nb_group; i++)
+	{
+	  if (param._have_bht)
+	    BRANCH_COMPLETE_BHT_HISTORY  [num_port_branch_complete]->write(i);
+
+	  for (uint32_t j=0; j<nb_reg_by_group; j++)
+	    {
+	      BRANCH_COMPLETE_ADDRESS [num_port_branch_complete]->write(j);
+	      
+	      sc_start(1);
+
+	      // wait ackwolegde
+	      while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0)
+		sc_start(1);
+	    }
+	}
+    }
+
+  if (param._have_bht)						       					
+    {
+      // Step 1.2 -> branch_history_table
+      BRANCH_COMPLETE_BHT_HISTORY  [num_port_branch_complete]->write(0);
+      
+      _Two_Level_Branch_Predictor->vhdl_testbench_label("Init bht");
+      cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Init bht" << endl;
+      
+      for (uint32_t i=0; i<param._bht_nb_shifter; i++)
+	{
+	  BRANCH_COMPLETE_ADDRESS [num_port_branch_complete]->write(i);
+
+	  sc_start(1);
+	}
+
+      // wait ackwolegde
+      while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0)
+	sc_start(1);
+    }
+
+  // Step 2
+  BRANCH_COMPLETE_VAL          [num_port_branch_complete]->write(0);
+  PREDICT_ADDRESS              [num_port_predict        ]->write(address);
+  BRANCH_COMPLETE_ADDRESS      [num_port_branch_complete]->write(address);
+
+  _Two_Level_Branch_Predictor->vhdl_testbench_label("Loop of Test");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl
+       << " * predict_address : " << hex << address << dec << endl;
+  
+  // A lot of prediction
+  Tbht_history_t bht_history = 0;
+  Tpht_history_t pht_history [1<<param._bht_size_shifter];
+  
+  for (uint32_t i=0; i<static_cast<uint32_t>(1<<param._bht_size_shifter); i++)
+    pht_history [i] = 0;
+
+  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+    {
+      _Two_Level_Branch_Predictor->vhdl_testbench_label("Iteration "+toString(iteration));
+
+      cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Predict          : bht_history " << bht_history << " - pht_history " << pht_history[bht_history] << endl; 
+
+      // Ask a new prediction
+      PREDICT_VAL                  [num_port_predict        ]->write(1);
+
+      sc_start(1);
+
+      // wait ackwolegde
+      while (PREDICT_ACK [num_port_predict] -> read() == 0)
+	sc_start(1);
+      PREDICT_ACK                  [num_port_predict        ]->write(0);
+
+      sc_start(0);
+
+      // Test
+      if (param._have_bht)
+      TEST(Tbht_history_t,bht_history             ,PREDICT_BHT_HISTORY[num_port_predict]->read());
+      if (param._have_pht)
+      TEST(Tpht_history_t,pht_history[bht_history],PREDICT_PHT_HISTORY[num_port_predict]->read());
+
+      // update
+      direction = ((rand()%2)==1);
+
+      BRANCH_COMPLETE_VAL          [num_port_branch_complete]->write(1);
+      if (param._have_bht)
+      BRANCH_COMPLETE_BHT_HISTORY  [num_port_branch_complete]->write(bht_history             );
+
+
+      if (param._have_pht)
+      BRANCH_COMPLETE_PHT_HISTORY  [num_port_branch_complete]->write(pht_history[bht_history]);
+      BRANCH_COMPLETE_DIRECTION    [num_port_branch_complete]->write(direction);
+
+      if (param._have_pht)
+      if (direction == 0)
+	{
+	  if (pht_history[bht_history] > 0)
+	    pht_history[bht_history] --;
+	}
+      else
+	{
+	  if (pht_history[bht_history] < (static_cast<Tpht_history_t>(1<<param._pht_size_counter)-1))
+	    pht_history[bht_history] ++;
+	}
+
+      if (param._have_bht)
+      bht_history              = (((bht_history) << 1) | direction) & gen_mask<Tbht_history_t>(param._bht_size_shifter);
+
+      sc_start(1);
+
+      // wait ackwolegde
+      while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0)
+	sc_start(1);
+
+      BRANCH_COMPLETE_VAL          [num_port_branch_complete]->write(0);
+    }
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete _Two_Level_Branch_Predictor;
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile	(revision 3)
@@ -0,0 +1,23 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../../../..
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libTwo_Level_Branch_Predictor_Glue.a
+
+
+#-----[ include ]------------------------------------------
+
+all				: $(LIBRARY_NEED)
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.deps
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.deps	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/Makefile.deps	(revision 3)
@@ -0,0 +1,31 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+
+Two_Level_Branch_Predictor_Glue			= yes
+
+#-----[ Library ]------------------------------------------
+Two_Level_Branch_Predictor_Glue_LIBRARY		= 	-lTwo_Level_Branch_Predictor_Glue	\
+					$(Behavioural_LIBRARY)	
+
+Two_Level_Branch_Predictor_Glue_DIR_LIBRARY		=	-L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/lib	\
+					$(Behavioural_DIR_LIBRARY)
+
+#-----[ Rules ]--------------------------------------------
+
+Two_Level_Branch_Predictor_Glue_library		: 
+				@$(MAKE) Behavioural_library
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue --makefile=Makefile 
+	
+Two_Level_Branch_Predictor_Glue_library_clean	: 
+				@$(MAKE) Behavioural_library_clean
+				@$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue --makefile=Makefile clean
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,30 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_MORPHEO			= ../../../../../../..
+
+LIBRARY				= $(Two_Level_Branch_Predictor_Glue_LIBRARY)
+
+DIR_LIBRARY			= $(Two_Level_Branch_Predictor_Glue_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				: library
+				@$(MAKE) all_selftest
+
+library				: Two_Level_Branch_Predictor_Glue_library
+
+library_clean			: Two_Level_Branch_Predictor_Glue_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/configuration.cfg	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/configuration.cfg	(revision 3)
@@ -0,0 +1,10 @@
+Two_Level_Branch_Predictor_Glue
+1	1	+1	# have_bht           
+11	11	+1	# bht_size_history   
+4	4	+1	# bht_size_address   
+0	1	+1	# have_pht           
+13	13	+1	# pht_size_address   
+0	2	+1	# pht_size_address_share
+16	16	+1	# size_address       
+1	2	+1	# nb_prediction      
+1	2	+1	# nb_branch_complete 
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h	(revision 3)
@@ -0,0 +1,29 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::stage_1_ifetch;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor;
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor;
+
+using namespace morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue;
+
+void test   (string name,
+	     morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters param);
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/mkf.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/mkf.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/mkf.info	(revision 3)
@@ -0,0 +1,121 @@
+
+# Two_Level_Branch_Predictor_Glue_0
+target_dep	all	Two_Level_Branch_Predictor_Glue_0.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_0.ngc	Two_Level_Branch_Predictor_Glue_0.prj
+target_dep	Two_Level_Branch_Predictor_Glue_0.prj	Two_Level_Branch_Predictor_Glue_0_Pack.vhdl Two_Level_Branch_Predictor_Glue_0.vhdl
+
+# Two_Level_Branch_Predictor_Glue_10
+target_dep	all	Two_Level_Branch_Predictor_Glue_10.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_10.ngc	Two_Level_Branch_Predictor_Glue_10.prj
+target_dep	Two_Level_Branch_Predictor_Glue_10.prj	Two_Level_Branch_Predictor_Glue_10_Pack.vhdl Two_Level_Branch_Predictor_Glue_10.vhdl
+
+# Two_Level_Branch_Predictor_Glue_11
+target_dep	all	Two_Level_Branch_Predictor_Glue_11.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_11.ngc	Two_Level_Branch_Predictor_Glue_11.prj
+target_dep	Two_Level_Branch_Predictor_Glue_11.prj	Two_Level_Branch_Predictor_Glue_11_Pack.vhdl Two_Level_Branch_Predictor_Glue_11.vhdl
+
+# Two_Level_Branch_Predictor_Glue_12
+target_dep	all	Two_Level_Branch_Predictor_Glue_12.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_12.ngc	Two_Level_Branch_Predictor_Glue_12.prj
+target_dep	Two_Level_Branch_Predictor_Glue_12.prj	Two_Level_Branch_Predictor_Glue_12_Pack.vhdl Two_Level_Branch_Predictor_Glue_12.vhdl
+
+# Two_Level_Branch_Predictor_Glue_13
+target_dep	all	Two_Level_Branch_Predictor_Glue_13.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_13.ngc	Two_Level_Branch_Predictor_Glue_13.prj
+target_dep	Two_Level_Branch_Predictor_Glue_13.prj	Two_Level_Branch_Predictor_Glue_13_Pack.vhdl Two_Level_Branch_Predictor_Glue_13.vhdl
+
+# Two_Level_Branch_Predictor_Glue_14
+target_dep	all	Two_Level_Branch_Predictor_Glue_14.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_14.ngc	Two_Level_Branch_Predictor_Glue_14.prj
+target_dep	Two_Level_Branch_Predictor_Glue_14.prj	Two_Level_Branch_Predictor_Glue_14_Pack.vhdl Two_Level_Branch_Predictor_Glue_14.vhdl
+
+# Two_Level_Branch_Predictor_Glue_15
+target_dep	all	Two_Level_Branch_Predictor_Glue_15.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_15.ngc	Two_Level_Branch_Predictor_Glue_15.prj
+target_dep	Two_Level_Branch_Predictor_Glue_15.prj	Two_Level_Branch_Predictor_Glue_15_Pack.vhdl Two_Level_Branch_Predictor_Glue_15.vhdl
+
+# Two_Level_Branch_Predictor_Glue_16
+target_dep	all	Two_Level_Branch_Predictor_Glue_16.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_16.ngc	Two_Level_Branch_Predictor_Glue_16.prj
+target_dep	Two_Level_Branch_Predictor_Glue_16.prj	Two_Level_Branch_Predictor_Glue_16_Pack.vhdl Two_Level_Branch_Predictor_Glue_16.vhdl
+
+# Two_Level_Branch_Predictor_Glue_17
+target_dep	all	Two_Level_Branch_Predictor_Glue_17.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_17.ngc	Two_Level_Branch_Predictor_Glue_17.prj
+target_dep	Two_Level_Branch_Predictor_Glue_17.prj	Two_Level_Branch_Predictor_Glue_17_Pack.vhdl Two_Level_Branch_Predictor_Glue_17.vhdl
+
+# Two_Level_Branch_Predictor_Glue_18
+target_dep	all	Two_Level_Branch_Predictor_Glue_18.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_18.ngc	Two_Level_Branch_Predictor_Glue_18.prj
+target_dep	Two_Level_Branch_Predictor_Glue_18.prj	Two_Level_Branch_Predictor_Glue_18_Pack.vhdl Two_Level_Branch_Predictor_Glue_18.vhdl
+
+# Two_Level_Branch_Predictor_Glue_19
+target_dep	all	Two_Level_Branch_Predictor_Glue_19.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_19.ngc	Two_Level_Branch_Predictor_Glue_19.prj
+target_dep	Two_Level_Branch_Predictor_Glue_19.prj	Two_Level_Branch_Predictor_Glue_19_Pack.vhdl Two_Level_Branch_Predictor_Glue_19.vhdl
+
+# Two_Level_Branch_Predictor_Glue_1
+target_dep	all	Two_Level_Branch_Predictor_Glue_1.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_1.ngc	Two_Level_Branch_Predictor_Glue_1.prj
+target_dep	Two_Level_Branch_Predictor_Glue_1.prj	Two_Level_Branch_Predictor_Glue_10_Pack.vhdl Two_Level_Branch_Predictor_Glue_10.vhdl Two_Level_Branch_Predictor_Glue_11_Pack.vhdl Two_Level_Branch_Predictor_Glue_11.vhdl Two_Level_Branch_Predictor_Glue_12_Pack.vhdl Two_Level_Branch_Predictor_Glue_12.vhdl Two_Level_Branch_Predictor_Glue_13_Pack.vhdl Two_Level_Branch_Predictor_Glue_13.vhdl Two_Level_Branch_Predictor_Glue_14_Pack.vhdl Two_Level_Branch_Predictor_Glue_14.vhdl Two_Level_Branch_Predictor_Glue_15_Pack.vhdl Two_Level_Branch_Predictor_Glue_15.vhdl Two_Level_Branch_Predictor_Glue_16_Pack.vhdl Two_Level_Branch_Predictor_Glue_16.vhdl Two_Level_Branch_Predictor_Glue_17_Pack.vhdl Two_Level_Branch_Predictor_Glue_17.vhdl Two_Level_Branch_Predictor_Glue_18_Pack.vhdl Two_Level_Branch_Predictor_Glue_18.vhdl Two_Level_Branch_Predictor_Glue_19_Pack.vhdl Two_Level_Branch_Predictor_Glue_19.vhdl Two_Level_Branch_Predictor_Glue_1_Pack.vhdl Two_Level_Branch_Predictor_Glue_1.vhdl
+
+# Two_Level_Branch_Predictor_Glue_20
+target_dep	all	Two_Level_Branch_Predictor_Glue_20.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_20.ngc	Two_Level_Branch_Predictor_Glue_20.prj
+target_dep	Two_Level_Branch_Predictor_Glue_20.prj	Two_Level_Branch_Predictor_Glue_20_Pack.vhdl Two_Level_Branch_Predictor_Glue_20.vhdl
+
+# Two_Level_Branch_Predictor_Glue_21
+target_dep	all	Two_Level_Branch_Predictor_Glue_21.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_21.ngc	Two_Level_Branch_Predictor_Glue_21.prj
+target_dep	Two_Level_Branch_Predictor_Glue_21.prj	Two_Level_Branch_Predictor_Glue_21_Pack.vhdl Two_Level_Branch_Predictor_Glue_21.vhdl
+
+# Two_Level_Branch_Predictor_Glue_22
+target_dep	all	Two_Level_Branch_Predictor_Glue_22.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_22.ngc	Two_Level_Branch_Predictor_Glue_22.prj
+target_dep	Two_Level_Branch_Predictor_Glue_22.prj	Two_Level_Branch_Predictor_Glue_22_Pack.vhdl Two_Level_Branch_Predictor_Glue_22.vhdl
+
+# Two_Level_Branch_Predictor_Glue_23
+target_dep	all	Two_Level_Branch_Predictor_Glue_23.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_23.ngc	Two_Level_Branch_Predictor_Glue_23.prj
+target_dep	Two_Level_Branch_Predictor_Glue_23.prj	Two_Level_Branch_Predictor_Glue_23_Pack.vhdl Two_Level_Branch_Predictor_Glue_23.vhdl
+
+# Two_Level_Branch_Predictor_Glue_2
+target_dep	all	Two_Level_Branch_Predictor_Glue_2.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_2.ngc	Two_Level_Branch_Predictor_Glue_2.prj
+target_dep	Two_Level_Branch_Predictor_Glue_2.prj	Two_Level_Branch_Predictor_Glue_20_Pack.vhdl Two_Level_Branch_Predictor_Glue_20.vhdl Two_Level_Branch_Predictor_Glue_21_Pack.vhdl Two_Level_Branch_Predictor_Glue_21.vhdl Two_Level_Branch_Predictor_Glue_22_Pack.vhdl Two_Level_Branch_Predictor_Glue_22.vhdl Two_Level_Branch_Predictor_Glue_23_Pack.vhdl Two_Level_Branch_Predictor_Glue_23.vhdl Two_Level_Branch_Predictor_Glue_2_Pack.vhdl Two_Level_Branch_Predictor_Glue_2.vhdl
+
+# Two_Level_Branch_Predictor_Glue_3
+target_dep	all	Two_Level_Branch_Predictor_Glue_3.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_3.ngc	Two_Level_Branch_Predictor_Glue_3.prj
+target_dep	Two_Level_Branch_Predictor_Glue_3.prj	Two_Level_Branch_Predictor_Glue_3_Pack.vhdl Two_Level_Branch_Predictor_Glue_3.vhdl
+
+# Two_Level_Branch_Predictor_Glue_4
+target_dep	all	Two_Level_Branch_Predictor_Glue_4.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_4.ngc	Two_Level_Branch_Predictor_Glue_4.prj
+target_dep	Two_Level_Branch_Predictor_Glue_4.prj	Two_Level_Branch_Predictor_Glue_4_Pack.vhdl Two_Level_Branch_Predictor_Glue_4.vhdl
+
+# Two_Level_Branch_Predictor_Glue_5
+target_dep	all	Two_Level_Branch_Predictor_Glue_5.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_5.ngc	Two_Level_Branch_Predictor_Glue_5.prj
+target_dep	Two_Level_Branch_Predictor_Glue_5.prj	Two_Level_Branch_Predictor_Glue_5_Pack.vhdl Two_Level_Branch_Predictor_Glue_5.vhdl
+
+# Two_Level_Branch_Predictor_Glue_6
+target_dep	all	Two_Level_Branch_Predictor_Glue_6.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_6.ngc	Two_Level_Branch_Predictor_Glue_6.prj
+target_dep	Two_Level_Branch_Predictor_Glue_6.prj	Two_Level_Branch_Predictor_Glue_6_Pack.vhdl Two_Level_Branch_Predictor_Glue_6.vhdl
+
+# Two_Level_Branch_Predictor_Glue_7
+target_dep	all	Two_Level_Branch_Predictor_Glue_7.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_7.ngc	Two_Level_Branch_Predictor_Glue_7.prj
+target_dep	Two_Level_Branch_Predictor_Glue_7.prj	Two_Level_Branch_Predictor_Glue_7_Pack.vhdl Two_Level_Branch_Predictor_Glue_7.vhdl
+
+# Two_Level_Branch_Predictor_Glue_8
+target_dep	all	Two_Level_Branch_Predictor_Glue_8.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_8.ngc	Two_Level_Branch_Predictor_Glue_8.prj
+target_dep	Two_Level_Branch_Predictor_Glue_8.prj	Two_Level_Branch_Predictor_Glue_8_Pack.vhdl Two_Level_Branch_Predictor_Glue_8.vhdl
+
+# Two_Level_Branch_Predictor_Glue_9
+target_dep	all	Two_Level_Branch_Predictor_Glue_9.ngc
+target_dep	Two_Level_Branch_Predictor_Glue_9.ngc	Two_Level_Branch_Predictor_Glue_9.prj
+target_dep	Two_Level_Branch_Predictor_Glue_9.prj	Two_Level_Branch_Predictor_Glue_9_Pack.vhdl Two_Level_Branch_Predictor_Glue_9.vhdl
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,62 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h"
+
+#define NB_PARAMS 9
+
+void usage (string exec)
+{
+  cerr << "<Usage> " << exec << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - have_bht               (boolean     )" << endl
+       << " - bht_size_history       (unsigned int)" << endl
+       << " - bht_size_address       (unsigned int)" << endl
+       << " - have_pht               (boolean     )" << endl
+       << " - pht_size_address       (unsigned int)" << endl
+       << " - pht_size_address_share (unsigned int)" << endl
+       << " - size_address           (unsigned int)" << endl
+       << " - nb_prediction          (unsigned int)" << endl
+       << " - nb_branch_complete     (unsigned int)" << endl;
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc != 2+NB_PARAMS)
+    usage (argv[0]);
+
+  const string   name                     = argv[1];
+  const bool     have_bht                 = atoi(argv[ 2]);
+  const uint32_t bht_size_history         = atoi(argv[ 3]);
+  const uint32_t bht_size_address         = atoi(argv[ 4]);
+  const bool     have_pht                 = atoi(argv[ 5]);
+  const uint32_t pht_size_address         = atoi(argv[ 6]);
+  const uint32_t pht_size_address_share   = atoi(argv[ 7]);
+  const uint32_t size_address             = atoi(argv[ 8]);
+  const uint32_t nb_prediction            = atoi(argv[ 9]);
+  const uint32_t nb_branch_complete       = atoi(argv[10]);
+
+  morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters param (have_bht              ,
+																		  bht_size_history      ,
+																		  bht_size_address      ,
+																		  have_pht              ,
+																		  pht_size_address      ,
+																		  pht_size_address_share,
+																		  size_address          ,
+																		  nb_prediction         ,
+																		  nb_branch_complete    );
+
+  test (name,param);
+
+  return (EXIT_SUCCESS);
+}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/test.cpp	(revision 3)
@@ -0,0 +1,256 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#define NB_ITERATION 64
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/include/test.h"
+#include "Include/BitManipulation.h"
+#include "Include/Test.h"
+
+void test (string name,
+	   morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+  try 
+    {
+      cout << param.print(1);
+      param.test();
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      return;
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+  Two_Level_Branch_Predictor_Glue * _Two_Level_Branch_Predictor_Glue = new Two_Level_Branch_Predictor_Glue (name.c_str(),
+#ifdef STATISTICS
+					     morpheo::behavioural::Parameters_Statistics(5,50),
+#endif
+					     param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                                 CLOCK ("clock", 1.0, 0.5);
+
+  sc_signal<Tcontrol_t>                    PREDICT_BHT_ACK             [param._nb_prediction];
+  sc_signal<Tcontrol_t>                    PREDICT_PHT_ACK             [param._nb_prediction];
+  sc_signal<Tcontrol_t>                    PREDICT_ACK                 [param._nb_prediction];
+  				           
+  sc_signal<Taddress_t>                    PREDICT_ADDRESS             [param._nb_prediction];
+  sc_signal<Tbht_history_t>                PREDICT_BHT_HISTORY         [param._nb_prediction];
+  sc_signal<Taddress_t>                    PREDICT_BHT_ADDRESS         [param._nb_prediction];
+  sc_signal<Taddress_t>                    PREDICT_PHT_ADDRESS         [param._nb_prediction];
+  				           
+  sc_signal<Tcontrol_t>                    BRANCH_COMPLETE_BHT_ACK     [param._nb_branch_complete];
+  sc_signal<Tcontrol_t>                    BRANCH_COMPLETE_PHT_ACK     [param._nb_branch_complete];
+  sc_signal<Tcontrol_t>                    BRANCH_COMPLETE_ACK         [param._nb_branch_complete];
+  sc_signal<Taddress_t>                    BRANCH_COMPLETE_ADDRESS     [param._nb_branch_complete];
+  sc_signal<Tbht_history_t>                BRANCH_COMPLETE_BHT_HISTORY [param._nb_branch_complete];
+  sc_signal<Taddress_t>                    BRANCH_COMPLETE_BHT_ADDRESS [param._nb_branch_complete];
+  sc_signal<Taddress_t>                    BRANCH_COMPLETE_PHT_ADDRESS [param._nb_branch_complete];
+  
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Two_Level_Branch_Predictor_Glue" << endl;
+  
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+  (*(_Two_Level_Branch_Predictor_Glue->in_CLOCK))        (CLOCK);
+#endif
+
+  for (uint32_t i=0; i<param._nb_prediction; i++)
+    {
+      if (param._have_bht)
+	{
+      (*(_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_ACK             [i])) (PREDICT_BHT_ACK             [i]);
+      (*(_Two_Level_Branch_Predictor_Glue->out_PREDICT_BHT_ADDRESS         [i])) (PREDICT_BHT_ADDRESS         [i]);
+	}
+      if (param._have_bht and param._have_pht)
+      (*(_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_HISTORY         [i])) (PREDICT_BHT_HISTORY         [i]);
+      if (param._have_pht)
+	{
+      (*(_Two_Level_Branch_Predictor_Glue-> in_PREDICT_PHT_ACK             [i])) (PREDICT_PHT_ACK             [i]);
+      (*(_Two_Level_Branch_Predictor_Glue->out_PREDICT_PHT_ADDRESS         [i])) (PREDICT_PHT_ADDRESS         [i]);
+	}
+      (*(_Two_Level_Branch_Predictor_Glue->out_PREDICT_ACK                 [i])) (PREDICT_ACK                 [i]);
+      (*(_Two_Level_Branch_Predictor_Glue-> in_PREDICT_ADDRESS             [i])) (PREDICT_ADDRESS             [i]);
+    }
+  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+    {
+      if (param._have_bht)
+	{
+      (*(_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_ACK     [i])) (BRANCH_COMPLETE_BHT_ACK     [i]);
+      (*(_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_BHT_ADDRESS [i])) (BRANCH_COMPLETE_BHT_ADDRESS [i]);
+	}
+      if (param._have_bht and param._have_pht)
+      (*(_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (BRANCH_COMPLETE_BHT_HISTORY [i]);
+
+      if (param._have_pht)
+	{
+      (*(_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_PHT_ACK     [i])) (BRANCH_COMPLETE_PHT_ACK     [i]);
+      (*(_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (BRANCH_COMPLETE_PHT_ADDRESS [i]);
+	}
+      (*(_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_ACK         [i])) (BRANCH_COMPLETE_ACK         [i]);
+      (*(_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_ADDRESS     [i])) (BRANCH_COMPLETE_ADDRESS     [i]);
+    }
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  // Initialisation
+
+  Tcontrol_t predict_bht_ack;
+  Tcontrol_t predict_pht_ack;
+
+  Tcontrol_t branch_complete_bht_ack;
+  Tcontrol_t branch_complete_pht_ack;
+  
+  srand(0);
+  //srand(time(NULL));
+
+  sc_start(0);
+  _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Initialisation");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl;
+
+
+  _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Test ack");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Test ack" << endl;
+
+  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+    {
+      _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Iteration "+toString(iteration));
+
+      // Branch History Table
+      if (param._have_bht)
+	{
+	  predict_bht_ack         = (rand()%2)!=0;
+	  branch_complete_bht_ack = (rand()%2)!=0;
+
+	}
+      else
+	{
+	  predict_bht_ack         = 1;
+	  branch_complete_bht_ack = 1;
+	}
+
+      // Pattern History Table
+      if (param._have_pht)
+	{
+	  predict_pht_ack         = (rand()%2)!=0;
+	  branch_complete_pht_ack = (rand()%2)!=0;
+	}
+      else
+	{
+	  predict_pht_ack         = 1;
+	  branch_complete_pht_ack = 1;
+	}
+      
+      for (uint32_t i=0; i<param._nb_prediction;      i++)
+	{
+	  PREDICT_BHT_ACK         [i] .write(predict_bht_ack);
+	  PREDICT_PHT_ACK         [i] .write(predict_pht_ack);
+	}
+      
+      for (uint32_t i=0; i<param._nb_branch_complete; i++)
+	{
+	  BRANCH_COMPLETE_BHT_ACK [i] .write(branch_complete_bht_ack);
+	  BRANCH_COMPLETE_PHT_ACK [i] .write(branch_complete_pht_ack);
+	}
+      
+      sc_start(0);
+
+      // Test result
+      for (uint32_t i=0; i<param._nb_prediction;      i++)
+	TEST(Tcontrol_t,(predict_pht_ack & predict_bht_ack),PREDICT_ACK [i].read());
+
+      for (uint32_t i=0; i<param._nb_branch_complete;      i++)
+	TEST(Tcontrol_t,(branch_complete_pht_ack & branch_complete_bht_ack),BRANCH_COMPLETE_ACK [i].read());
+
+      sc_start(1);
+    }
+
+  Taddress_t     predict_address;
+  Tbht_history_t predict_bht_history;
+  Taddress_t     branch_complete_address;
+  Tbht_history_t branch_complete_bht_history;
+
+
+  _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Test address");
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Test address" << endl;
+
+  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+    {
+      _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Iteration "+toString(iteration));
+      
+      predict_address             = rand()%(1<<param._size_address    );
+      predict_bht_history         = 0;
+      branch_complete_address     = rand()%(1<<param._size_address    );
+      branch_complete_bht_history = 0;
+
+      for (uint32_t i=0; i<param._nb_prediction; i++)
+	PREDICT_ADDRESS         [i].write (predict_address);
+      for (uint32_t i=0; i<param._nb_branch_complete; i++)
+	BRANCH_COMPLETE_ADDRESS [i].write (branch_complete_address);
+
+      // Branch History Table
+      if (param._have_bht and param._have_pht)
+	{
+	  predict_bht_history         = rand()%(1<<param._bht_size_history);
+	  branch_complete_bht_history = rand()%(1<<param._bht_size_history);
+	  
+	  for (uint32_t i=0; i<param._nb_prediction; i++)
+	    PREDICT_BHT_HISTORY         [i].write(predict_bht_history);
+	  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+	    BRANCH_COMPLETE_BHT_HISTORY [i].write(branch_complete_bht_history);
+	}
+
+      sc_start(0);
+
+      // Branch History Table
+      if (param._have_bht)
+	{
+	  for (uint32_t i=0; i<param._nb_prediction; i++)
+	    TEST(Taddress_t,PREDICT_BHT_ADDRESS [i].read(),(predict_address & gen_mask<Taddress_t>(param._bht_size_address)));
+
+	  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+	    TEST(Taddress_t,BRANCH_COMPLETE_BHT_ADDRESS [i].read(),(branch_complete_address & gen_mask<Taddress_t>(param._bht_size_address)));
+	}
+
+      // Pattern History Table
+      if (param._have_pht)
+	{
+	  uint32_t shift = (param._have_bht==false)?0:(param._pht_size_address_shift);
+
+	  for (uint32_t i=0; i<param._nb_prediction; i++)
+	    TEST(Taddress_t,PREDICT_PHT_ADDRESS [i].read(),(((predict_address << shift) xor predict_bht_history) & gen_mask<Taddress_t>(param._pht_size_address)));
+	  for (uint32_t i=0; i<param._nb_branch_complete; i++)
+	    TEST(Taddress_t,BRANCH_COMPLETE_PHT_ADDRESS [i].read(), (((branch_complete_address << shift) xor branch_complete_bht_history) & gen_mask<Taddress_t>(param._pht_size_address)));
+	}
+
+      sc_start(1);	  
+    }
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+#endif
+
+  delete _Two_Level_Branch_Predictor_Glue;
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/VERSION
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/VERSION	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/VERSION	(revision 3)
@@ -0,0 +1,1 @@
+v0.3
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h	(revision 3)
@@ -0,0 +1,68 @@
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Parameters_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+    //-----[ fields ]------------------------------------------------------------
+  public : const bool     _have_bht              ;
+  public : const uint32_t _bht_size_history      ;
+  public : const uint32_t _bht_size_address      ;
+  public : const bool     _have_pht              ;
+  public : const uint32_t _pht_size_address      ;
+  public : const uint32_t _pht_size_address_share;
+  public : const uint32_t _size_address          ;
+  public : const uint32_t _nb_prediction         ;
+  public : const uint32_t _nb_branch_complete    ;
+  public : const uint32_t _pht_size_address_shift;
+
+    //-----[ methods ]-----------------------------------------------------------
+  public : Parameters  (bool     have_bht              ,
+			uint32_t bht_size_history      ,
+			uint32_t bht_size_address      ,
+			bool     have_pht              ,
+			uint32_t pht_size_address      ,
+			uint32_t pht_size_address_share,
+			uint32_t size_address          ,
+			uint32_t nb_prediction         ,
+			uint32_t nb_branch_complete    );
+
+  public : Parameters  (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters & x);
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h	(revision 3)
@@ -0,0 +1,61 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Statistics_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+//#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h"
+
+//using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                   _parameters;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics  (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  );
+//public   : Statistics  (Statistics & stat);
+  public   : ~Statistics () ;
+    
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : void     add        ();
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h	(revision 3)
@@ -0,0 +1,155 @@
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Two_Level_Branch_Predictor_Glue_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Two_Level_Branch_Predictor_Glue_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <iostream>
+#include "Include/ToString.h"
+#include "Include/Debug.h"
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h"
+#endif
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#ifdef VHDL_TESTBENCH
+#include "Behavioural/include/Vhdl_Testbench.h"
+#endif
+
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  class Two_Level_Branch_Predictor_Glue 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string     _name;
+
+  protected : const Parameters _param;
+//#ifdef STATISTICS
+//  protected : const morpheo::behavioural::Parameters_Statistics _param_statistics;
+//#endif
+
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+#endif
+
+#ifdef VHDL_TESTBENCH
+  private   : Vhdl_Testbench                 * _vhdl_testbench;
+#endif
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK                      ;
+
+  public    : SC_IN (Tcontrol_t)           **  in_PREDICT_BHT_ACK            ;
+  public    : SC_IN (Tcontrol_t)           **  in_PREDICT_PHT_ACK            ;
+  public    : SC_OUT(Tcontrol_t)           ** out_PREDICT_ACK                ;
+					   
+  public    : SC_IN (Taddress_t)           **  in_PREDICT_ADDRESS            ;
+  public    : SC_IN (Tbht_history_t)       **  in_PREDICT_BHT_HISTORY        ;
+  public    : SC_OUT(Taddress_t)           ** out_PREDICT_BHT_ADDRESS        ;
+  public    : SC_OUT(Taddress_t)           ** out_PREDICT_PHT_ADDRESS        ;
+					   
+  public    : SC_IN (Tcontrol_t)           **  in_BRANCH_COMPLETE_BHT_ACK    ;
+  public    : SC_IN (Tcontrol_t)           **  in_BRANCH_COMPLETE_PHT_ACK    ;
+  public    : SC_OUT(Tcontrol_t)           ** out_BRANCH_COMPLETE_ACK        ;
+					   
+  public    : SC_IN (Taddress_t)           **  in_BRANCH_COMPLETE_ADDRESS    ;
+  public    : SC_IN (Tbht_history_t)       **  in_BRANCH_COMPLETE_BHT_HISTORY;
+  public    : SC_OUT(Taddress_t)           ** out_BRANCH_COMPLETE_BHT_ADDRESS;
+  public    : SC_OUT(Taddress_t)           ** out_BRANCH_COMPLETE_PHT_ADDRESS;
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#endif
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (Two_Level_Branch_Predictor_Glue);
+#endif
+  public  :          Two_Level_Branch_Predictor_Glue              (
+#ifdef SYSTEMC
+								   sc_module_name                              name,
+#else					       
+								   string                                      name,
+#endif					       
+#ifdef STATISTICS
+								   morpheo::behavioural::Parameters_Statistics param_statistics,
+#endif
+								   Parameters                                  param );
+					       
+  public  :          Two_Level_Branch_Predictor_Glue              (Parameters param );
+  public  :          ~Two_Level_Branch_Predictor_Glue             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+  public  : void     transition                            (void);
+#endif						           
+  public  : void     genMealy_predict_ack                  (void);
+  public  : void     genMealy_predict_bht_address          (void);
+  public  : void     genMealy_predict_pht_address          (void);
+  public  : void     genMealy_branch_complete_ack          (void);
+  public  : void     genMealy_branch_complete_bht_address  (void);
+  public  : void     genMealy_branch_complete_pht_address  (void);
+#endif					       
+
+#ifdef STATISTICS
+  public  : string   statistics                (uint32_t depth);
+#endif
+					       
+#if VHDL				       
+  public  : void     vhdl                      (void);
+  private : void     vhdl_port                 (Vhdl & vhdl);
+  private : void     vhdl_declaration          (Vhdl & vhdl);
+  private : void     vhdl_body                 (Vhdl & vhdl);
+#endif					       
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench_port       (void);
+  private : void     vhdl_testbench_transition (void);
+#endif
+  public  : void     vhdl_testbench_label      (string label);
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef SYSTEMC
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Type_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_two_level_branch_predictor_glue_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Types.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+  typedef uint32_t Taddress_t    ;
+  typedef uint32_t Tbht_history_t;
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,73 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  Parameters::Parameters (bool     have_bht               ,
+			  uint32_t bht_size_history       ,
+			  uint32_t bht_size_address       ,
+			  bool     have_pht               ,
+			  uint32_t pht_size_address       ,
+			  uint32_t pht_size_address_share ,
+			  uint32_t size_address           ,
+			  uint32_t nb_prediction          ,
+			  uint32_t nb_branch_complete     ):
+    _have_bht                (have_bht               ),
+    _bht_size_history        (bht_size_history       ),
+    _bht_size_address        (bht_size_address       ),
+    _have_pht                (have_pht               ),
+    _pht_size_address        (pht_size_address       ),
+    _pht_size_address_share  (pht_size_address_share ),
+    _size_address            (size_address           ),
+    _nb_prediction           (nb_prediction          ),
+    _nb_branch_complete      (nb_branch_complete     ),
+    _pht_size_address_shift  (bht_size_history-pht_size_address_share)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Parameters","Begin");
+    test();
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Parameters","End");
+  };
+  
+  Parameters::Parameters (Parameters & param):
+    _have_bht                (param._have_bht               ),
+    _bht_size_history        (param._bht_size_history       ),
+    _bht_size_address        (param._bht_size_address       ),
+    _have_pht                (param._have_pht               ),
+    _pht_size_address        (param._pht_size_address       ),
+    _pht_size_address_share  (param._pht_size_address_share ),
+    _size_address            (param._size_address           ),
+    _nb_prediction           (param._nb_prediction          ),
+    _nb_branch_complete      (param._nb_branch_complete     ),
+    _pht_size_address_shift  (param._pht_size_address_shift )
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Parameters","Begin");
+    test();
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Parameters","End");
+  };
+
+  Parameters::~Parameters () 
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Parameters","Begin");
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Parameters","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_msg_error.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_msg_error.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_msg_error.cpp	(revision 3)
@@ -0,0 +1,46 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Types.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  string Parameters::msg_error(void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"msg_error","Begin");
+
+    string msg = "";
+    
+    if (_have_pht and (_pht_size_address_share >= _pht_size_address))
+      {
+	msg += "  - You can't have higher pht_size_address_share >= pht_size_address\n";
+	msg += "    * pht_size_address                : " + toString(_pht_size_address      ) + "\n";
+	msg += "    * pht_size_address_share          : " + toString(_pht_size_address_share) + "\n";
+      }
+
+    return msg;
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"msg_error","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Parameters_print.cpp	(revision 3)
@@ -0,0 +1,59 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  string Parameters::print (uint32_t depth)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print","Begin");
+
+    string tab = string(depth,'\t');
+    ostringstream msg;
+    msg << tab << "<two_level_branch_predictor_glue>" << endl
+	<< tab << "\t<have_bht               value=\"" << _have_bht               << "\" />" << endl
+	<< tab << "\t<bht_size_history       value=\"" << _bht_size_history       << "\" />" << endl
+	<< tab << "\t<bht_size_address       value=\"" << _bht_size_address       << "\" />" << endl
+	<< tab << "\t<have_pht               value=\"" << _have_pht               << "\" />" << endl
+	<< tab << "\t<pht_size_address       value=\"" << _pht_size_address       << "\" />" << endl
+	<< tab << "\t<pht_size_address_share value=\"" << _pht_size_address_share << "\" /> <!-- Need " << _pht_size_address_shift << " bits to shift -->" << endl
+	<< tab << "\t<size_address           value=\"" << _size_address           << "\" />" << endl
+	<< tab << "\t<nb_prediction          value=\"" << _nb_prediction          << "\" />" << endl
+	<< tab << "\t<nb_branch_complete     value=\"" << _nb_branch_complete     << "\" />" << endl
+      	<< tab << "</two_level_branch_predictor_glue>" << endl;
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print","End");
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,46 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Statistics","Begin");
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Statistics","End");
+  };
+  
+  Statistics::~Statistics () 
+  { 
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Statistics","Begin");
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Statistics","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,37 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Statistics::add ()
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"add","Begin");
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"add","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,55 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  string Statistics::print (uint32_t depth)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<two_level_branch_predictor_glue name=\"" << _name << "\" >" << endl
+        << print_body(depth+1) << endl
+	<< tab << "</two_level_branch_predictor_glue>" << endl;
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print","End");
+
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print_body","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "";
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"print_body","End");
+
+    return msg.str();
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue.cpp	(revision 3)
@@ -0,0 +1,220 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+#ifdef SYSTEMC
+  Two_Level_Branch_Predictor_Glue::Two_Level_Branch_Predictor_Glue (sc_module_name name,
+#else
+  Two_Level_Branch_Predictor_Glue::Two_Level_Branch_Predictor_Glue (string name,
+#endif
+#ifdef STATISTICS
+								    morpheo::behavioural::Parameters_Statistics             param_statistics,
+#endif
+								    morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters param ):
+								    _name              (name)
+								    ,_param            (param)
+// #ifdef STATISTICS
+//								    ,_param_statistics (param_statistics)
+// #endif
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Two_Level_Branch_Predictor_Glue","Begin");
+
+#ifdef STATISTICS
+    // Allocation of statistics
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // Creation of a testbench
+    //  -> port
+    //  -> clock's signals
+    _vhdl_testbench = new Vhdl_Testbench (_name);
+    vhdl_testbench_port           ();
+    _vhdl_testbench->set_clock    ("in_CLOCK",false);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    allocation ();
+
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+#endif
+
+    SC_METHOD (genMealy_predict_ack);
+    dont_initialize ();
+    sensitive_neg << *(in_CLOCK);
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	sensitive << (*(in_PREDICT_BHT_ACK     [i]));
+	if (_param._have_pht)
+	sensitive << (*(in_PREDICT_PHT_ACK     [i]));
+      }
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	  (*(out_PREDICT_ACK         [i])) (*(in_PREDICT_BHT_ACK     [i]));
+	if (_param._have_pht)
+	  (*(out_PREDICT_ACK         [i])) (*(in_PREDICT_PHT_ACK     [i]));
+      }
+#endif
+    
+    if (_param._have_bht)
+      {
+	SC_METHOD (genMealy_predict_bht_address);
+	dont_initialize ();
+	sensitive_neg << *(in_CLOCK);
+	for (uint32_t i=0; i<_param._nb_prediction; i++)
+	  sensitive << (*(in_PREDICT_ADDRESS     [i]));
+	
+#ifdef SYSTEMCASS_SPECIFIC
+	// List dependency information
+	for (uint32_t i=0; i<_param._nb_prediction; i++)
+	  (*(out_PREDICT_BHT_ADDRESS [i])) (*(in_PREDICT_ADDRESS     [i]));
+#endif
+      }
+
+    if (_param._have_pht)
+      {
+	SC_METHOD (genMealy_predict_pht_address);
+	dont_initialize ();
+	sensitive_neg << *(in_CLOCK);
+	for (uint32_t i=0; i<_param._nb_prediction; i++)
+	  {
+	    if (_param._have_bht)
+	      sensitive << (*(in_PREDICT_BHT_HISTORY [i]));
+	    sensitive << (*(in_PREDICT_ADDRESS     [i]));
+	  }
+	
+#ifdef SYSTEMCASS_SPECIFIC
+	// List dependency information
+	for (uint32_t i=0; i<_param._nb_prediction; i++)
+	  {
+	    (*(out_PREDICT_PHT_ADDRESS [i])) (*(in_PREDICT_ADDRESS     [i]));
+	    if (_param._have_bht)
+	      (*(out_PREDICT_PHT_ADDRESS [i])) (*(in_PREDICT_BHT_HISTORY [i]));
+	  }
+#endif
+      }
+
+    SC_METHOD (genMealy_branch_complete_ack);
+    dont_initialize ();
+    sensitive_neg << *(in_CLOCK);
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	sensitive << (*(in_BRANCH_COMPLETE_BHT_ACK     [i]));
+	if (_param._have_pht)
+	sensitive << (*(in_BRANCH_COMPLETE_PHT_ACK     [i]));
+      }
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	  (*(out_BRANCH_COMPLETE_ACK         [i])) (*(in_BRANCH_COMPLETE_BHT_ACK     [i]));
+	if (_param._have_pht)
+	  (*(out_BRANCH_COMPLETE_ACK         [i])) (*(in_BRANCH_COMPLETE_PHT_ACK     [i]));
+      }
+#endif
+    
+    if (_param._have_bht)
+      {
+	SC_METHOD (genMealy_branch_complete_bht_address);
+	dont_initialize ();
+	sensitive_neg << *(in_CLOCK);
+	for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	  sensitive << (*(in_BRANCH_COMPLETE_ADDRESS     [i]));
+	
+#ifdef SYSTEMCASS_SPECIFIC
+	// List dependency information
+	for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	  (*(out_BRANCH_COMPLETE_BHT_ADDRESS [i])) (*(in_BRANCH_COMPLETE_ADDRESS     [i]));
+#endif
+      }
+
+    if (_param._have_pht)
+      {
+	SC_METHOD (genMealy_branch_complete_pht_address);
+	dont_initialize ();
+	sensitive_neg << *(in_CLOCK);
+	for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	  {
+	    if (_param._have_bht)
+	      sensitive << (*(in_BRANCH_COMPLETE_BHT_HISTORY [i]));
+	    sensitive << (*(in_BRANCH_COMPLETE_ADDRESS     [i]));
+	  }
+	
+#ifdef SYSTEMCASS_SPECIFIC
+	// List dependency information
+	for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	  {
+	    (*(out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (*(in_BRANCH_COMPLETE_ADDRESS     [i]));
+	    if (_param._have_bht)
+	      (*(out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (*(in_BRANCH_COMPLETE_BHT_HISTORY [i]));
+	  }
+#endif
+      }
+
+#endif
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Two_Level_Branch_Predictor_Glue","End");
+  };
+  
+  Two_Level_Branch_Predictor_Glue::~Two_Level_Branch_Predictor_Glue (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Two_Level_Branch_Predictor_Glue","Begin");
+
+#ifdef VHDL_TESTBENCH
+    // generate the test bench
+    _vhdl_testbench->generate_file();
+    delete _vhdl_testbench;
+#endif
+
+#ifdef STATISTICS
+    _stat->generate_file(statistics(0));
+    
+    delete _stat;
+#endif
+
+#ifdef SYSTEMC
+    deallocation ();
+#endif
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Two_Level_Branch_Predictor_Glue","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_allocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_allocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_allocation.cpp	(revision 3)
@@ -0,0 +1,134 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::allocation (void)
+  {
+    string rename;
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"allocation","Begin");
+
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+    in_CLOCK  = new SC_CLOCK           ("in_CLOCK");
+#endif
+    
+    if (_param._have_bht)
+      {
+     in_PREDICT_BHT_ACK              = new SC_IN (Tcontrol_t)           * [_param._nb_prediction];
+    out_PREDICT_BHT_ADDRESS          = new SC_OUT(Taddress_t)           * [_param._nb_prediction];
+      }
+    if (_param._have_pht)
+      {
+     in_PREDICT_PHT_ACK              = new SC_IN (Tcontrol_t)           * [_param._nb_prediction];
+    out_PREDICT_PHT_ADDRESS          = new SC_OUT(Taddress_t)           * [_param._nb_prediction];
+      }
+    if (_param._have_bht and _param._have_pht)
+     in_PREDICT_BHT_HISTORY          = new SC_IN (Tbht_history_t)       * [_param._nb_prediction];
+    out_PREDICT_ACK                  = new SC_OUT(Tcontrol_t)           * [_param._nb_prediction];
+     in_PREDICT_ADDRESS              = new SC_IN (Taddress_t)           * [_param._nb_prediction];
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	  {
+	rename = " in_PREDICT_BHT_ACK_"    +toString(i);
+         in_PREDICT_BHT_ACK             [i] = new SC_IN (Tcontrol_t)     (rename.c_str());
+
+	rename = "out_PREDICT_BHT_ADDRESS_"+toString(i);
+        out_PREDICT_BHT_ADDRESS         [i] = new SC_OUT(Taddress_t)     (rename.c_str());
+	  }
+	if (_param._have_pht)
+	  {
+        rename = " in_PREDICT_PHT_ACK_"    +toString(i);
+         in_PREDICT_PHT_ACK             [i] = new SC_IN (Tcontrol_t)     (rename.c_str());
+        
+	rename = "out_PREDICT_PHT_ADDRESS_"+toString(i);
+        out_PREDICT_PHT_ADDRESS         [i] = new SC_OUT(Taddress_t)     (rename.c_str());
+	  }
+	if (_param._have_bht and _param._have_pht)
+	  {
+	rename = " in_PREDICT_BHT_HISTORY_"+toString(i);
+         in_PREDICT_BHT_HISTORY         [i] = new SC_IN (Tbht_history_t) (rename.c_str());
+	  }
+        rename = "out_PREDICT_ACK_"        +toString(i);
+        out_PREDICT_ACK                 [i] = new SC_OUT(Tcontrol_t)     (rename.c_str());
+        
+        rename = " in_PREDICT_ADDRESS_"    +toString(i);
+         in_PREDICT_ADDRESS             [i] = new SC_IN (Taddress_t)     (rename.c_str());
+      }
+
+    if (_param._have_bht)
+      {
+     in_BRANCH_COMPLETE_BHT_ACK              = new SC_IN (Tcontrol_t)           * [_param._nb_branch_complete];
+    out_BRANCH_COMPLETE_BHT_ADDRESS          = new SC_OUT(Taddress_t)           * [_param._nb_branch_complete];
+      }
+    if (_param._have_pht)
+      {
+     in_BRANCH_COMPLETE_PHT_ACK              = new SC_IN (Tcontrol_t)           * [_param._nb_branch_complete];
+    out_BRANCH_COMPLETE_PHT_ADDRESS          = new SC_OUT(Taddress_t)           * [_param._nb_branch_complete];
+      }
+    if (_param._have_bht and _param._have_pht)
+     in_BRANCH_COMPLETE_BHT_HISTORY          = new SC_IN (Tbht_history_t)       * [_param._nb_branch_complete];
+    
+    out_BRANCH_COMPLETE_ACK                  = new SC_OUT(Tcontrol_t)           * [_param._nb_branch_complete];
+     in_BRANCH_COMPLETE_ADDRESS              = new SC_IN (Taddress_t)           * [_param._nb_branch_complete];
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	  {
+	rename = " in_BRANCH_COMPLETE_BHT_ACK_"    +toString(i);
+         in_BRANCH_COMPLETE_BHT_ACK             [i] = new SC_IN (Tcontrol_t)     (rename.c_str());
+        
+        rename = "out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i);
+        out_BRANCH_COMPLETE_BHT_ADDRESS         [i] = new SC_OUT(Taddress_t)     (rename.c_str());
+	  }
+	if (_param._have_pht)
+	  {
+        rename = " in_BRANCH_COMPLETE_PHT_ACK_"    +toString(i);
+         in_BRANCH_COMPLETE_PHT_ACK             [i] = new SC_IN (Tcontrol_t)     (rename.c_str());
+
+        rename = "out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i);
+        out_BRANCH_COMPLETE_PHT_ADDRESS         [i] = new SC_OUT(Taddress_t)     (rename.c_str());
+	  }
+	if (_param._have_bht and _param._have_pht)
+	  {
+        rename = " in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i);
+         in_BRANCH_COMPLETE_BHT_HISTORY         [i] = new SC_IN (Tbht_history_t) (rename.c_str());
+	  }
+        rename = "out_BRANCH_COMPLETE_ACK_"        +toString(i);
+        out_BRANCH_COMPLETE_ACK                 [i] = new SC_OUT(Tcontrol_t)     (rename.c_str());
+        
+        rename = " in_BRANCH_COMPLETE_ADDRESS_"    +toString(i);
+         in_BRANCH_COMPLETE_ADDRESS             [i] = new SC_IN (Taddress_t)     (rename.c_str());
+      }
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"allocation","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_deallocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_deallocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_deallocation.cpp	(revision 3)
@@ -0,0 +1,104 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::deallocation (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"deallocation","Begin");
+
+    delete in_CLOCK;
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	  {
+        delete  in_PREDICT_BHT_ACK             [i];
+        delete out_PREDICT_BHT_ADDRESS         [i];
+	  }
+	if (_param._have_pht)
+	  {
+        delete  in_PREDICT_PHT_ACK             [i];
+        delete out_PREDICT_PHT_ADDRESS         [i];
+	  }
+	if (_param._have_bht and _param._have_pht)
+        delete  in_PREDICT_BHT_HISTORY         [i];
+        delete out_PREDICT_ACK                 [i];
+        delete  in_PREDICT_ADDRESS             [i];
+      }
+    if (_param._have_bht)
+      {
+    delete  in_PREDICT_BHT_ACK    ;
+    delete out_PREDICT_BHT_ADDRESS;
+      }
+    if (_param._have_pht)
+      {
+    delete  in_PREDICT_PHT_ACK    ;
+    delete out_PREDICT_PHT_ADDRESS;
+      }
+    if (_param._have_bht and _param._have_pht)
+    delete  in_PREDICT_BHT_HISTORY;
+    
+    delete out_PREDICT_ACK        ;
+    delete  in_PREDICT_ADDRESS    ;
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	  {
+        delete  in_BRANCH_COMPLETE_BHT_ACK             [i];
+        delete out_BRANCH_COMPLETE_BHT_ADDRESS         [i];
+	  }
+	if (_param._have_pht)
+	  {
+        delete  in_BRANCH_COMPLETE_PHT_ACK             [i];
+        delete out_BRANCH_COMPLETE_PHT_ADDRESS         [i];
+	  }
+	if (_param._have_bht and _param._have_pht)
+	delete  in_BRANCH_COMPLETE_BHT_HISTORY         [i];
+        delete out_BRANCH_COMPLETE_ACK                 [i];
+        delete  in_BRANCH_COMPLETE_ADDRESS             [i];
+      }
+    if (_param._have_bht)
+      {
+    delete  in_BRANCH_COMPLETE_BHT_ACK    ;
+    delete out_BRANCH_COMPLETE_BHT_ADDRESS;
+      }
+    if (_param._have_pht)
+      {
+    delete  in_BRANCH_COMPLETE_PHT_ACK    ;
+    delete out_BRANCH_COMPLETE_PHT_ADDRESS;
+      }
+    if (_param._have_bht and _param._have_pht)
+    delete  in_BRANCH_COMPLETE_BHT_HISTORY;
+    delete out_BRANCH_COMPLETE_ACK        ;
+    delete  in_BRANCH_COMPLETE_ADDRESS    ;
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"deallocation","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_ack.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_ack.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_ack.cpp	(revision 3)
@@ -0,0 +1,43 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+#include "Include/BitManipulation.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+  void Two_Level_Branch_Predictor_Glue::genMealy_branch_complete_ack (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_ack","Begin");
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	// Ackwnolegde
+	bool bht_ack = (not _param._have_bht) or PORT_READ(in_BRANCH_COMPLETE_BHT_ACK [i]);
+	bool pht_ack = (not _param._have_pht) or PORT_READ(in_BRANCH_COMPLETE_PHT_ACK [i]);		  
+
+	PORT_WRITE (out_BRANCH_COMPLETE_ACK [i], bht_ack and pht_ack);
+      }
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_ack","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_bht_address.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_bht_address.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_bht_address.cpp	(revision 3)
@@ -0,0 +1,43 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+#include "Include/BitManipulation.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+  void Two_Level_Branch_Predictor_Glue::genMealy_branch_complete_bht_address (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","Begin");
+
+    if (_param._have_bht)
+      for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	{
+	  // Address
+	  Taddress_t address = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]);
+	  
+	  PORT_WRITE (out_BRANCH_COMPLETE_BHT_ADDRESS [i], range<Taddress_t>(_param._size_address, address, _param._bht_size_address));
+	}
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_pht_address.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_pht_address.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_branch_complete_pht_address.cpp	(revision 3)
@@ -0,0 +1,54 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+#include "Include/BitManipulation.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+  void Two_Level_Branch_Predictor_Glue::genMealy_branch_complete_pht_address (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","Begin");
+
+    if (_param._have_pht)
+      for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	{
+	  // Address
+	  Taddress_t     address = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]);
+	  Tbht_history_t history = 0;
+	  
+	  if (_param._have_bht)
+	    {
+	      history = PORT_READ (in_BRANCH_COMPLETE_BHT_HISTORY [i]);
+	      address = address << _param._pht_size_address_shift;
+	    }
+
+	  Taddress_t     pht_address = (history ^ address) & gen_mask<Taddress_t>(_param._pht_size_address);
+
+	  log_printf(TRACE,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","out_BRANCH_COMPLETE_PHT_ADDRESS [%d]= %.8x xor %.8x<<%d = %.8x",i,history,PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]),_param._pht_size_address_shift, pht_address);
+	  
+	  PORT_WRITE (out_BRANCH_COMPLETE_PHT_ADDRESS [i], pht_address);
+	}
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_branch_complete_address","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_ack.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_ack.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_ack.cpp	(revision 3)
@@ -0,0 +1,43 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+#include "Include/BitManipulation.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+  void Two_Level_Branch_Predictor_Glue::genMealy_predict_ack (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_ack","Begin");
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	// Ackwnolegde
+	bool bht_ack = (not _param._have_bht) or PORT_READ(in_PREDICT_BHT_ACK [i]);
+	bool pht_ack = (not _param._have_pht) or PORT_READ(in_PREDICT_PHT_ACK [i]);		  
+
+	PORT_WRITE (out_PREDICT_ACK [i], bht_ack and pht_ack);
+      }
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_ack","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_bht_address.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_bht_address.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_bht_address.cpp	(revision 3)
@@ -0,0 +1,44 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+#include "Include/BitManipulation.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+  void Two_Level_Branch_Predictor_Glue::genMealy_predict_bht_address (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_address","Begin");
+
+    if (_param._have_bht)
+      for (uint32_t i=0; i<_param._nb_prediction; i++)
+	{
+	  // Address
+	  Taddress_t     address = PORT_READ(in_PREDICT_ADDRESS [i]);
+	  Taddress_t bht_address = range<Taddress_t>(_param._size_address, address, _param._bht_size_address);
+	  
+	  PORT_WRITE (out_PREDICT_BHT_ADDRESS [i], bht_address);
+	}
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_address","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_pht_address.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_pht_address.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_genMealy_predict_pht_address.cpp	(revision 3)
@@ -0,0 +1,50 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+#include "Include/BitManipulation.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+  void Two_Level_Branch_Predictor_Glue::genMealy_predict_pht_address (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_address","Begin");
+
+    if (_param._have_pht)
+      for (uint32_t i=0; i<_param._nb_prediction; i++)
+	{
+	  // Address
+	  Taddress_t address = PORT_READ(in_PREDICT_ADDRESS [i]);
+	  Tbht_history_t history = 0;
+	  
+	  if (_param._have_bht)
+	    {
+	      history = PORT_READ (in_PREDICT_BHT_HISTORY [i]);
+	      address = address << _param._pht_size_address_shift;
+	    }
+	  
+	  PORT_WRITE (out_PREDICT_PHT_ADDRESS [i], (history xor address) & gen_mask<Taddress_t>(_param._pht_size_address));
+	}
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"genMealy_predict_address","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_statistics.cpp	(revision 3)
@@ -0,0 +1,39 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  string Two_Level_Branch_Predictor_Glue::statistics (uint32_t depth)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"statistics","Begin");
+
+    string txt = _stat->print(depth);
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"statistics","End");
+
+    return txt;
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_transition.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef SYSTEMC
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::transition (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"transition","Begin");
+
+#ifdef STATISTICS
+    _stat->add();
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition ();
+#endif
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"transition","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::vhdl (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl","Begin");
+    Vhdl vhdl (_name);
+
+    vhdl.set_library_work (_name + "_Pack");
+
+    vhdl_port        (vhdl);
+    vhdl_declaration (vhdl);
+    vhdl_body        (vhdl);
+
+    vhdl.generate_file();
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl","End");
+
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_body.cpp	(revision 3)
@@ -0,0 +1,160 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::vhdl_body (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_body","Begin");
+
+    vhdl.set_body ("-- ack output");
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	string bht_ack, pht_ack;
+
+	if (_param._have_bht)
+	  bht_ack = "in_PREDICT_BHT_ACK_"+toString(i);
+	else
+	  bht_ack = "'1'";
+
+	if (_param._have_pht)
+	  pht_ack = "in_PREDICT_PHT_ACK_"+toString(i);
+	else
+	  pht_ack = "'1'";
+
+	vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+"         <= "+bht_ack+" and "+pht_ack+";");
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	string bht_ack, pht_ack;
+
+	if (_param._have_bht)
+	  bht_ack = "in_BRANCH_COMPLETE_BHT_ACK_"+toString(i);
+	else
+	  bht_ack = "'1'";
+
+	if (_param._have_pht)
+	  pht_ack = "in_BRANCH_COMPLETE_PHT_ACK_"+toString(i);
+	else
+	  pht_ack = "'1'";
+
+	vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= "+bht_ack+" and "+pht_ack+";");
+      }
+    
+    vhdl.set_body ("");
+    vhdl.set_body ("-- address output");
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	// The address is higher than the address size of bht
+	if (_param._have_bht)
+	  vhdl.set_body ("out_PREDICT_BHT_ADDRESS_"+toString(i)+" <= in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._bht_size_address)+";");
+
+	if (_param._have_pht)
+	  {
+	    // For pht : 2 cases
+	    if (_param._have_bht)
+	      {
+		uint32_t min = 0;
+		uint32_t max = _param._pht_size_address;
+
+		// A lot of case :
+		//
+		//      pht_size_addr
+		// addr             bht_history
+		//
+		// ---------] |
+		//            |[---------
+		//
+		// -----------|----]               share
+		//            |  [-------
+		//
+		// -----------|----]            no share
+		//            |     [-----
+		//
+		
+		// Test if address is share 
+		if (_param._pht_size_address_shift > 0)
+		  {
+		    min = _param._pht_size_address_shift;
+		    vhdl.set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+std_logic_range(min) + " <=  in_PREDICT_BHT_HISTORY_"+toString(i)+std_logic_range(min)+";");
+		  }
+
+		if (_param._bht_size_history < _param._pht_size_address)
+		  {
+		    max = _param._bht_size_history;
+		    vhdl.set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1,max) + " <=  in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";");
+		  }
+		
+		// intersection
+		if (_param._pht_size_address_share > 0)
+		  vhdl.set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+std_logic_range(max-1,min) + " <=  in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_PREDICT_BHT_HISTORY_"+toString(i)+std_logic_range(max-1,min)+";");
+	      }
+	    else
+	      vhdl.set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+" <=  in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address)+";");
+	  }
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	// The address is higher than the address size of bht
+	if (_param._have_bht)
+	  vhdl.set_body ("out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i)+" <= in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._bht_size_address)+";");
+
+	if (_param._have_pht)
+	  {
+	    // For pht : 2 cases
+	    if (_param._have_bht)
+	      {
+		uint32_t min = 0;
+		uint32_t max = _param._pht_size_address;
+
+		// Test if address is share 
+		if (_param._pht_size_address_shift > 0)
+		  {
+		    min = _param._pht_size_address_shift;
+		    vhdl.set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+std_logic_range(min) + " <=  in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+std_logic_range(min)+";");
+		  }
+
+		if (_param._bht_size_history < _param._pht_size_address)
+		  {
+		    max = _param._bht_size_history;
+		    vhdl.set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1,max) + " <=  in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";");
+		  }
+		
+		// intersection
+		if (_param._pht_size_address_share > 0)
+		  vhdl.set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+std_logic_range(max-1,min) + " <=  in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+std_logic_range(max-1,min)+";");
+	      }
+	    else
+	      vhdl.set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+" <=  in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address)+";");
+	  }
+      }
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_body","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_declaration.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_declaration.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_declaration.cpp	(revision 3)
@@ -0,0 +1,34 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::vhdl_declaration (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_declaration","Begin");
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_declaration","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_port.cpp	(revision 3)
@@ -0,0 +1,71 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::vhdl_port (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_port","Begin");
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	  {
+	vhdl.set_port (" in_PREDICT_BHT_ACK_"    +toString(i), IN, 1);
+	vhdl.set_port ("out_PREDICT_BHT_ADDRESS_"+toString(i),OUT,_param._bht_size_address);
+	  }
+	if (_param._have_bht and _param._have_pht)
+	vhdl.set_port (" in_PREDICT_BHT_HISTORY_"+toString(i), IN,_param._bht_size_history);
+	if (_param._have_pht)
+	  {
+        vhdl.set_port (" in_PREDICT_PHT_ACK_"    +toString(i), IN, 1);
+	vhdl.set_port ("out_PREDICT_PHT_ADDRESS_"+toString(i),OUT,_param._pht_size_address);
+	  }
+	
+        vhdl.set_port ("out_PREDICT_ACK_"        +toString(i),OUT, 1);
+        vhdl.set_port (" in_PREDICT_ADDRESS_"    +toString(i), IN,_param._size_address);
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	  {
+	vhdl.set_port (" in_BRANCH_COMPLETE_BHT_ACK_"    +toString(i), IN, 1);
+        vhdl.set_port ("out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i),OUT,_param._bht_size_address);
+	  }
+	if (_param._have_bht and _param._have_pht)
+	vhdl.set_port (" in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i), IN,_param._bht_size_history);
+        if (_param._have_pht)
+	  {
+        vhdl.set_port (" in_BRANCH_COMPLETE_PHT_ACK_"    +toString(i), IN, 1);
+        vhdl.set_port ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i),OUT,_param._pht_size_address);
+	  }
+        vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"        +toString(i),OUT, 1);
+        vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"    +toString(i), IN,_param._size_address);
+      }
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_port","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_label.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_label.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_label.cpp	(revision 3)
@@ -0,0 +1,33 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::vhdl_testbench_label (string label)
+  {
+#ifdef VHDL_TESTBENCH
+    _vhdl_testbench->add_label(label);
+#endif
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_port.cpp	(revision 3)
@@ -0,0 +1,71 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::vhdl_testbench_port ()
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_port","Begin");
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	  {
+	_vhdl_testbench->set_port (" in_PREDICT_BHT_ACK_"    +toString(i), IN, 1);
+	_vhdl_testbench->set_port ("out_PREDICT_BHT_ADDRESS_"+toString(i),OUT,_param._bht_size_address);
+	  }
+	if (_param._have_bht and _param._have_pht)
+	_vhdl_testbench->set_port (" in_PREDICT_BHT_HISTORY_"+toString(i), IN,_param._bht_size_history);
+	if (_param._have_pht)
+	  {
+        _vhdl_testbench->set_port (" in_PREDICT_PHT_ACK_"    +toString(i), IN, 1);
+	_vhdl_testbench->set_port ("out_PREDICT_PHT_ADDRESS_"+toString(i),OUT,_param._pht_size_address);
+	  }
+        _vhdl_testbench->set_port ("out_PREDICT_ACK_"        +toString(i),OUT, 1);
+        _vhdl_testbench->set_port (" in_PREDICT_ADDRESS_"    +toString(i), IN,_param._size_address);
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	  {
+	_vhdl_testbench->set_port (" in_BRANCH_COMPLETE_BHT_ACK_"    +toString(i), IN, 1);
+        _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i),OUT,_param._bht_size_address);
+	  }
+	if (_param._have_bht and _param._have_pht)
+	_vhdl_testbench->set_port (" in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i), IN,_param._bht_size_history);
+        if (_param._have_pht)
+	  {
+        _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_PHT_ACK_"    +toString(i), IN, 1);
+        _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i),OUT,_param._pht_size_address);
+	  }
+        _vhdl_testbench->set_port ("out_BRANCH_COMPLETE_ACK_"        +toString(i),OUT, 1);
+        _vhdl_testbench->set_port (" in_BRANCH_COMPLETE_ADDRESS_"    +toString(i), IN,_param._size_address);
+      }
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_port","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_transition.cpp	(revision 3)
@@ -0,0 +1,86 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+namespace two_level_branch_predictor_glue {
+
+
+  void Two_Level_Branch_Predictor_Glue::vhdl_testbench_transition ()
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","Begin");
+
+#ifndef SYSTEMCASS_SPECIFIC
+    sc_cycle(0);
+#endif    
+
+    // In order with file Two_Level_Branch_Predictor_Glue_vhdl_testbench_port.cpp
+    // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
+    // (because we have no control on the ordonnancer's policy)
+
+//     _vhdl_testbench->add_input (PORT_READ( in_NRESET));
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	  {
+	_vhdl_testbench->add_input  (PORT_READ( in_PREDICT_BHT_ACK      [i]));
+	_vhdl_testbench->add_output (PORT_READ(out_PREDICT_BHT_ADDRESS  [i]));
+	  }
+	if (_param._have_bht and _param._have_pht)
+	_vhdl_testbench->add_input  (PORT_READ( in_PREDICT_BHT_HISTORY  [i]));
+	if (_param._have_pht)
+	  {
+        _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_PHT_ACK      [i]));
+	_vhdl_testbench->add_output (PORT_READ(out_PREDICT_PHT_ADDRESS  [i]));
+	  }
+        _vhdl_testbench->add_output (PORT_READ(out_PREDICT_ACK          [i]));
+        _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_ADDRESS      [i]));
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	  {
+	_vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_BHT_ACK      [i]));
+        _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_BHT_ADDRESS  [i]));
+	  }
+	if (_param._have_bht and _param._have_pht)
+	_vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_BHT_HISTORY  [i]));
+        if (_param._have_pht)
+	  {
+        _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_PHT_ACK      [i]));
+        _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_PHT_ADDRESS  [i]));
+	  }
+        _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_ACK          [i]));
+        _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_ADDRESS      [i]));
+      }
+    // add_test :
+    //  - True  : the cycle must be compare with the output of systemC
+    //  - False : no test
+    _vhdl_testbench->add_test(true);
+
+    _vhdl_testbench->new_cycle (); // always at the end
+
+    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","End");
+  };
+
+}; // end namespace two_level_branch_predictor_glue
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/VERSION
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/VERSION	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/VERSION	(revision 3)
@@ -0,0 +1,1 @@
+v0.2
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h	(revision 3)
@@ -0,0 +1,77 @@
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Parameters_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+#include "Behavioural/include/Parameters.h"
+// Internal structure
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+    //-----[ fields ]------------------------------------------------------------
+  public : const bool     _have_bht              ;
+  public : const uint32_t _bht_size_shifter      ;
+  public : const uint32_t _bht_nb_shifter        ;
+  public : const bool     _have_pht              ;
+  public : const uint32_t _pht_size_counter      ;
+  public : const uint32_t _pht_nb_counter        ;
+  public : const uint32_t _pht_size_address_share;
+  public : const uint32_t _size_address          ;
+  public : const uint32_t _nb_prediction         ;
+  public : const uint32_t _nb_branch_complete    ;
+    
+  public : const uint32_t _bht_size_address  ;
+  public : const uint32_t _pht_size_address  ;
+
+  public :       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Parameters * _param_branch_history_table;
+  public :       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters * _param_pattern_history_table;
+  public :       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters * _param_two_level_branch_predictor_glue;
+
+    //-----[ methods ]-----------------------------------------------------------
+  public : Parameters  (bool     have_bht              ,
+			uint32_t bht_size_shifter      ,
+			uint32_t bht_nb_shifter        ,
+			bool     have_pht              ,
+			uint32_t pht_size_counter      ,
+			uint32_t pht_nb_counter        ,
+			uint32_t pht_size_address_share,
+			uint32_t size_address          ,
+			uint32_t nb_prediction         ,
+			uint32_t nb_branch_complete    );
+
+  public : Parameters  (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters & x);
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h	(revision 3)
@@ -0,0 +1,66 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Statistics_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Debug.h"
+// Internal structure
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Statistics.h"
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+//#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h"
+
+//using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                   _parameters;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics  (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  );
+//public   : Statistics  (Statistics & stat);
+  public   : ~Statistics () ;
+    
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : string   print      (uint32_t depth,
+				  string   component_stat
+				  );
+  public   : void     add        ();
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h	(revision 3)
@@ -0,0 +1,160 @@
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Two_Level_Branch_Predictor_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Two_Level_Branch_Predictor_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <iostream>
+#include "Include/ToString.h"
+#include "Include/Debug.h"
+
+// Internal structure
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h"
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Types.h"
+#ifdef STATISTICS
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h"
+#endif
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+#ifdef VHDL_TESTBENCH
+#include "Behavioural/include/Vhdl_Testbench.h"
+#endif
+
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  class Two_Level_Branch_Predictor 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string     _name;
+
+  protected : const Parameters _param;
+#ifdef STATISTICS
+ protected : const morpheo::behavioural::Parameters_Statistics _param_statistics;
+#endif
+
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+#endif
+
+#ifdef VHDL_TESTBENCH
+  private   : Vhdl_Testbench                 * _vhdl_testbench;
+#endif
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK                      ;
+
+    // Interface Predict
+  public    : SC_IN (Tcontrol_t)           **  in_PREDICT_VAL                ;
+  public    : SC_OUT(Tcontrol_t)           ** out_PREDICT_ACK                ;
+  public    : SC_IN (Taddress_t)           **  in_PREDICT_ADDRESS            ;
+  public    : SC_OUT(Tbht_history_t)       ** out_PREDICT_BHT_HISTORY        ;
+  public    : SC_OUT(Tpht_history_t)       ** out_PREDICT_PHT_HISTORY        ;
+			
+    // Interface Branch_complete
+  public    : SC_IN (Tcontrol_t)           **  in_BRANCH_COMPLETE_VAL        ;
+  public    : SC_OUT(Tcontrol_t)           ** out_BRANCH_COMPLETE_ACK        ;
+  public    : SC_IN (Taddress_t)           **  in_BRANCH_COMPLETE_ADDRESS    ;
+  public    : SC_IN (Tbht_history_t)       **  in_BRANCH_COMPLETE_BHT_HISTORY;
+  public    : SC_IN (Tpht_history_t)       **  in_BRANCH_COMPLETE_PHT_HISTORY;
+  public    : SC_IN (Tcontrol_t)           **  in_BRANCH_COMPLETE_DIRECTION  ;
+
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  private   : SC_SIGNAL(Tcontrol_t)        ** signal_PREDICT_BHT_ACK            ;
+  private   : SC_SIGNAL(Tcontrol_t)        ** signal_PREDICT_PHT_ACK            ;
+  private   : SC_SIGNAL(Taddress_t)        ** signal_PREDICT_BHT_ADDRESS        ;
+  private   : SC_SIGNAL(Taddress_t)        ** signal_PREDICT_PHT_ADDRESS        ;
+
+  private   : SC_SIGNAL(Tcontrol_t)        ** signal_BRANCH_COMPLETE_BHT_ACK    ;
+  private   : SC_SIGNAL(Tcontrol_t)        ** signal_BRANCH_COMPLETE_PHT_ACK    ;
+  private   : SC_SIGNAL(Taddress_t)        ** signal_BRANCH_COMPLETE_BHT_ADDRESS; 
+  private   : SC_SIGNAL(Taddress_t)        ** signal_BRANCH_COMPLETE_PHT_ADDRESS;
+#endif
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+  protected : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table  * component_Branch_History_Table;
+  protected : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Pattern_History_Table * component_Pattern_History_Table;
+  protected : morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue * component_Two_Level_Branch_Predictor_Glue;
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (Two_Level_Branch_Predictor);
+#endif					       
+  public  :          Two_Level_Branch_Predictor              (
+#ifdef SYSTEMC
+							      sc_module_name                              name,
+#else					       
+							      string                                      name,
+#endif					       
+#ifdef STATISTICS
+							      morpheo::behavioural::Parameters_Statistics param_statistics,
+#endif
+							      Parameters                                  param );
+							      
+  public  :          Two_Level_Branch_Predictor              (Parameters param );
+  public  :          ~Two_Level_Branch_Predictor             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+					       
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+  public  : void     transition                (void);
+#endif
+#endif					       
+#ifdef STATISTICS
+  public  : string   statistics                (uint32_t depth);
+#endif
+					       
+#if VHDL				       
+  public  : void     vhdl                      (void);
+  private : void     vhdl_port                 (Vhdl & vhdl);
+  private : void     vhdl_declaration          (Vhdl & vhdl);
+  private : void     vhdl_body                 (Vhdl & vhdl);
+#endif					       
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench_port       (void);
+  private : void     vhdl_testbench_transition (void);
+#endif
+  public  : void     vhdl_testbench_label      (string label);
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Types.h	(revision 3)
@@ -0,0 +1,33 @@
+#ifdef SYSTEMC
+#ifndef morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Type_h
+#define morpheo_behavioural_stage_1_ifetch_predictor_meta_predictor_two_level_branch_predictor_Type_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Include/Types.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+  typedef uint32_t Taddress_t    ;
+  typedef uint32_t Tbht_history_t;
+  typedef uint32_t Tpht_history_t;
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,129 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  Parameters::Parameters (bool     have_bht              ,
+			  uint32_t bht_size_shifter      ,
+			  uint32_t bht_nb_shifter        ,
+			  bool     have_pht              ,
+			  uint32_t pht_size_counter      ,
+			  uint32_t pht_nb_counter        ,
+			  uint32_t pht_size_address_share,
+			  uint32_t size_address          ,
+			  uint32_t nb_prediction         ,
+			  uint32_t nb_branch_complete    ) : 
+    _have_bht               (have_bht          ),
+    _bht_size_shifter       ((_have_bht == true)?bht_size_shifter:0),
+    _bht_nb_shifter         ((_have_bht == true)?bht_nb_shifter  :0),
+    _have_pht               (have_pht          ),
+    _pht_size_counter       ((_have_pht == true)?pht_size_counter:0),
+    _pht_nb_counter         ((_have_pht == true)?pht_nb_counter  :0),
+    _pht_size_address_share (((_have_bht and _have_pht) == true)?pht_size_address_share:0),
+    _size_address           (size_address      ),
+    _nb_prediction          (nb_prediction     ),
+    _nb_branch_complete     (nb_branch_complete),
+    _bht_size_address       (static_cast<uint32_t>(ceil(log2(bht_nb_shifter)))),
+    _pht_size_address       (static_cast<uint32_t>(ceil(log2(pht_nb_counter))))
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"Parameters","Begin");
+    
+    if (_have_bht)
+    _param_branch_history_table  = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Parameters (_bht_size_shifter  ,
+																				       _bht_nb_shifter    ,
+																				       _nb_prediction     ,
+																				       _nb_branch_complete);
+    if (_have_pht)
+    _param_pattern_history_table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters (_pht_size_counter  ,
+																				       _pht_nb_counter    ,
+																				       _nb_prediction     ,
+																				       _nb_branch_complete);
+    
+                                                     
+    _param_two_level_branch_predictor_glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters (_have_bht              ,
+																							   _bht_size_shifter      ,
+																							   _bht_size_address      ,
+																							   _have_pht              ,
+																							   _pht_size_address      ,
+																							   _pht_size_address_share,
+																							   _size_address          ,
+																							   _nb_prediction         ,
+																							   _nb_branch_complete    );
+
+    test();
+    log_printf(FUNC,Two_Level_Branch_Predictor,"Parameters","End");
+  };
+  
+  Parameters::Parameters (Parameters & param) :
+    _have_bht               (param._have_bht              ),
+    _bht_size_shifter       (param._bht_size_shifter      ),
+    _bht_nb_shifter         (param._bht_nb_shifter        ),
+    _have_pht               (param._have_pht              ),
+    _pht_size_counter       (param._pht_size_counter      ),
+    _pht_nb_counter         (param._pht_nb_counter        ),
+    _pht_size_address_share (param._pht_size_address_share),
+    _size_address           (param._size_address          ),
+    _nb_prediction          (param._nb_prediction         ),
+    _nb_branch_complete     (param._nb_branch_complete    ),
+    _bht_size_address       (param._bht_size_address      ),
+    _pht_size_address       (param._pht_size_address      )
+
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"Parameters","Begin");
+
+    if (_have_bht)
+    _param_branch_history_table  = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Parameters (_bht_size_shifter  ,
+																				       _bht_nb_shifter    ,
+																				       _nb_prediction     ,
+																				       _nb_branch_complete);
+    if (_have_pht)
+    _param_pattern_history_table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Parameters (_pht_size_counter  ,
+																				       _pht_nb_counter    ,
+																				       _nb_prediction     ,
+																				       _nb_branch_complete);
+
+    _param_two_level_branch_predictor_glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Parameters (_have_bht              ,
+																							   _bht_size_shifter      ,
+																							   _bht_size_address      ,
+																							   _have_pht              ,
+																							   _pht_size_address      ,
+																							   _pht_size_address_share,
+																							   _size_address          ,
+																							   _nb_prediction         ,
+																							   _nb_branch_complete    );
+
+    test();
+    log_printf(FUNC,Two_Level_Branch_Predictor,"Parameters","End");
+  };
+
+  Parameters::~Parameters () 
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"~Parameters","Begin");
+
+    if (_have_bht)
+    delete _param_branch_history_table;
+    if (_have_pht)
+    delete _param_pattern_history_table;
+    delete _param_two_level_branch_predictor_glue;
+    log_printf(FUNC,Two_Level_Branch_Predictor,"~Parameters","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters_msg_error.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters_msg_error.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters_msg_error.cpp	(revision 3)
@@ -0,0 +1,84 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h"
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Types.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+  string Parameters::msg_error(void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"msg_error","Begin");
+
+    string msg = "";
+
+    if (is_positive (_nb_prediction) == false)
+      {
+	msg += "  - nb_prediction must be > 0\n";
+	msg += "    * nb_prediction                   : " + toString(_nb_prediction) + "\n";
+      }
+
+    if (is_positive (_nb_branch_complete) == false)
+      {
+	msg += "  - nb_branch_complete must be > 0\n";
+	msg += "    * nb_branch_complete              : " + toString(_nb_branch_complete) + "\n";
+      }
+
+    if ((_have_bht or _have_pht) == false)
+      {
+	msg += "  - you have no Branch History Table and no Pattern History Table. You need a less of a BHT or a PHT\n";
+	msg += "    * have_bht                        : " + toString(_have_bht) + "\n";
+	msg += "    * have_pht                        : " + toString(_have_pht) + "\n";
+      }
+
+    if ( _have_bht and (_size_address < _bht_size_address))
+      {
+	msg += "  - the address's size must to large to the number of shifter in the Branch History Table.\n";
+	msg += "    * size_address                    : " + toString(_size_address    ) + "\n";
+	msg += "    * have_bht                        : " + toString(_have_bht        ) + "\n";
+	msg += "    * bht_size_address                : " + toString(_bht_size_address) + "\n";
+	msg += "      * bht_nb_shifter                : " + toString(_bht_nb_shifter  ) + "\n";
+      }
+
+    if (_have_pht and ( (_size_address < _pht_size_address) or
+			(_have_bht and (_pht_size_address < _bht_size_address))))
+      {
+	msg += "  - the address's size concate with shifter_out must to large to the number of counter in the Pattern History Table.\n";
+	msg += "    * size_address                    : " + toString(_size_address    ) + "\n";
+	msg += "    * have_bht                        : " + toString(_have_bht        ) + "\n";
+	msg += "    * bht_size_address                : " + toString(_bht_size_address) + "\n";
+	msg += "      * bht_nb_shifter                : " + toString(_bht_nb_shifter  ) + "\n";
+	msg += "    * have_pht                        : " + toString(_have_bht        ) + "\n";
+	msg += "    * pht_size_address                : " + toString(_pht_size_address) + "\n";
+	msg += "      * pht_nb_counter                : " + toString(_pht_nb_counter  ) + "\n";
+      }
+
+//     if ( not _have_bht and (_pht_size_address_share != 0))
+//     {
+// 	msg += "  - you have no Branch History Table but size_address_share is > 0\n";
+// 	msg += "    * have_bht                        : " + toString(_have_bht              ) + "\n";
+// 	msg += "    * pht_size_address_share          : " + toString(_pht_size_address_share) + "\n";
+//     }
+
+    return msg;
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"msg_error","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters_print.cpp	(revision 3)
@@ -0,0 +1,62 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  string Parameters::print (uint32_t depth)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"print","Begin");
+
+    string tab = string(depth,'\t');
+    ostringstream msg;
+    msg << tab << "<two_level_branch_predictor>" << endl
+	<< tab << "\t<have bht               value=\"" << _have_bht               << "\" /> <!-- size bht : " << _bht_size_shifter * _bht_nb_shifter << " bits -->" << endl
+	<< tab << "\t<bht_size_shifter       value=\"" << _bht_size_shifter       << "\" />" << endl
+	<< tab << "\t<bht_nb_shifter         value=\"" << _bht_nb_shifter         << "\" />" << endl
+	<< tab << "\t<have pht               value=\"" << _have_pht               << "\" /> <!-- size pht : " << _pht_size_counter * _pht_nb_counter << " bits -->" << endl
+	<< tab << "\t<pht_size_counter       value=\"" << _pht_size_counter       << "\" />" << endl
+	<< tab << "\t<pht_nb_counter         value=\"" << _pht_nb_counter         << "\" />" << endl
+	<< tab << "\t<pht_size_address_share value=\"" << _pht_size_address_share << "\" />" << endl
+	<< tab << "\t<size_address           value=\"" << _size_address           << "\" />" << endl
+	<< tab << "\t<nb_prediction          value=\"" << _nb_prediction          << "\" />" << endl
+	<< tab << "\t<nb_branch_complete     value=\"" << _nb_branch_complete     << "\" />" << endl;
+    if (_have_bht)
+    msg << _param_branch_history_table ->print(depth+1);
+    if (_have_pht)
+    msg << _param_pattern_history_table->print(depth+1);
+    msg << _param_two_level_branch_predictor_glue->print(depth+1);
+    msg << tab << "</two_level_branch_predictor>" << endl;
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"print","End");
+    
+    return msg.str();
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters & x)
+  {
+    output_stream << x.print(0);
+    
+    return output_stream;
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,44 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  Statistics::Statistics (string                                      name                       ,
+			  morpheo::behavioural::Parameters_Statistics parameters_statistics      ,
+			  Parameters                                  parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"Statistics","Begin");
+    log_printf(FUNC,Two_Level_Branch_Predictor,"Statistics","End");
+  };
+  
+  Statistics::~Statistics () 
+  { 
+    log_printf(FUNC,Two_Level_Branch_Predictor,"~Statistics","Begin");
+    log_printf(FUNC,Two_Level_Branch_Predictor,"~Statistics","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics_add.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics_add.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics_add.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  void Statistics::add ()
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"add","Begin");
+    log_printf(FUNC,Two_Level_Branch_Predictor,"add","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics_print.cpp	(revision 3)
@@ -0,0 +1,60 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+  string Statistics::print (uint32_t depth,
+			    string   component_stat
+			    )
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"print","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<two_level_branch_predictor name=\"" << _name << "\" >" << endl
+        << print_body(depth+1)
+	<< component_stat
+	<< tab << "</two_level_branch_predictor>" << endl;
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor,"print","End");
+
+    return msg.str();
+  };
+
+  string Statistics::print (uint32_t depth)
+  {
+    return print(depth,"");
+  };
+
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Statistics & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics_print_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics_print_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Statistics_print_body.cpp	(revision 3)
@@ -0,0 +1,43 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  string Statistics::print_body (uint32_t depth)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"print_body","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "";
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor,"print_body","End");
+
+    return msg.str();
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor.cpp	(revision 3)
@@ -0,0 +1,103 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+#ifdef SYSTEMC
+  Two_Level_Branch_Predictor::Two_Level_Branch_Predictor (sc_module_name name,
+#else
+  Two_Level_Branch_Predictor::Two_Level_Branch_Predictor (string name,
+#endif
+#ifdef STATISTICS
+			      morpheo::behavioural::Parameters_Statistics             param_statistics,
+#endif
+			      morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param ):
+			      _name              (name)
+			      ,_param            (param)
+#ifdef STATISTICS
+			      ,_param_statistics (param_statistics)
+#endif
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"Two_Level_Branch_Predictor","Begin");
+
+#ifdef STATISTICS
+    // Allocation of statistics
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL_TESTBENCH
+    // Creation of a testbench
+    //  -> port
+    //  -> clock's signals
+    _vhdl_testbench = new Vhdl_Testbench (_name);
+    vhdl_testbench_port           ();
+    _vhdl_testbench->set_clock    ("in_CLOCK",true);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    allocation ();
+
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+
+//     SC_METHOD (genMoore);
+//     dont_initialize ();
+//     sensitive_neg << *(in_CLOCK);
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+#endif    
+
+#endif
+    log_printf(FUNC,Two_Level_Branch_Predictor,"Two_Level_Branch_Predictor","End");
+  };
+  
+  Two_Level_Branch_Predictor::~Two_Level_Branch_Predictor (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"~Two_Level_Branch_Predictor","Begin");
+
+#ifdef VHDL_TESTBENCH
+    // generate the test bench
+    _vhdl_testbench->generate_file();
+    delete _vhdl_testbench;
+#endif
+
+#ifdef STATISTICS
+    _stat->generate_file(statistics(0));
+    
+    delete _stat;
+#endif
+
+#ifdef SYSTEMC
+    deallocation ();
+#endif
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"~Two_Level_Branch_Predictor","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp	(revision 3)
@@ -0,0 +1,281 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+  void Two_Level_Branch_Predictor::allocation (void)
+  {
+    string rename;
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","Begin");
+
+     in_CLOCK  = new SC_CLOCK           ("in_CLOCK");
+
+     in_PREDICT_VAL                 = new SC_IN (Tcontrol_t)     * [_param._nb_prediction     ];
+    out_PREDICT_ACK                 = new SC_OUT(Tcontrol_t)     * [_param._nb_prediction     ];
+     in_PREDICT_ADDRESS             = new SC_IN (Taddress_t)     * [_param._nb_prediction     ];
+    if (_param._have_bht)
+    out_PREDICT_BHT_HISTORY         = new SC_OUT(Tbht_history_t) * [_param._nb_prediction     ];
+    if (_param._have_pht)
+    out_PREDICT_PHT_HISTORY         = new SC_OUT(Tpht_history_t) * [_param._nb_prediction     ];
+    if (_param._have_bht)
+      {
+    signal_PREDICT_BHT_ACK          = new SC_SIGNAL(Tcontrol_t)     * [_param._nb_prediction];
+    signal_PREDICT_BHT_ADDRESS      = new SC_SIGNAL(Taddress_t)     * [_param._nb_prediction];
+      }
+    if (_param._have_pht)
+      {
+    signal_PREDICT_PHT_ACK          = new SC_SIGNAL(Tcontrol_t)     * [_param._nb_prediction];
+    signal_PREDICT_PHT_ADDRESS      = new SC_SIGNAL(Taddress_t)     * [_param._nb_prediction];
+      }
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	rename = "in_PREDICT_VAL_"         +toString(i);
+	 in_PREDICT_VAL                 [i] = new SC_IN (Tcontrol_t)     (rename.c_str());
+
+	rename = "out_PREDICT_ACK_"        +toString(i);
+	out_PREDICT_ACK                 [i] = new SC_OUT(Tcontrol_t)     (rename.c_str());
+
+	rename = "in_PREDICT_ADDRESS_"     +toString(i);
+	 in_PREDICT_ADDRESS             [i] = new SC_IN (Taddress_t)     (rename.c_str());
+
+	if (_param._have_bht)
+	  {
+	rename = "out_PREDICT_BHT_HISTORY_"+toString(i);
+	out_PREDICT_BHT_HISTORY         [i] = new SC_OUT(Tbht_history_t) (rename.c_str());
+	  }
+
+	if (_param._have_pht)
+	  {
+    	rename = "out_PREDICT_PHT_HISTORY_"+toString(i);
+	out_PREDICT_PHT_HISTORY         [i] = new SC_OUT(Tpht_history_t) (rename.c_str());
+	  }
+
+	if (_param._have_bht)
+	  {
+	rename = "signal_PREDICT_BHT_ACK_"    +toString(i);
+	signal_PREDICT_BHT_ACK          [i] = new SC_SIGNAL(Tcontrol_t)     (rename.c_str());
+
+	rename = "signal_PREDICT_BHT_ADDRESS_"+toString(i);
+	signal_PREDICT_BHT_ADDRESS      [i] = new SC_SIGNAL(Taddress_t)     (rename.c_str());
+	  }
+
+	if (_param._have_pht)
+	  {
+	rename = "signal_PREDICT_PHT_ACK_"    +toString(i);
+	signal_PREDICT_PHT_ACK          [i] = new SC_SIGNAL(Tcontrol_t)     (rename.c_str());
+
+	rename = "signal_PREDICT_PHT_ADDRESS_"+toString(i);
+	signal_PREDICT_PHT_ADDRESS      [i] = new SC_SIGNAL(Taddress_t)     (rename.c_str());
+	  }
+      }
+
+     in_BRANCH_COMPLETE_VAL         = new SC_IN (Tcontrol_t)     * [_param._nb_branch_complete];
+    out_BRANCH_COMPLETE_ACK         = new SC_OUT(Tcontrol_t)     * [_param._nb_branch_complete];
+     in_BRANCH_COMPLETE_ADDRESS     = new SC_IN (Taddress_t)     * [_param._nb_branch_complete];
+    if (_param._have_bht)
+     in_BRANCH_COMPLETE_BHT_HISTORY = new SC_IN (Tbht_history_t) * [_param._nb_branch_complete];
+    if (_param._have_pht)
+     in_BRANCH_COMPLETE_PHT_HISTORY = new SC_IN (Tpht_history_t) * [_param._nb_branch_complete];
+     in_BRANCH_COMPLETE_DIRECTION   = new SC_IN (Tcontrol_t)     * [_param._nb_branch_complete];
+    if (_param._have_bht)
+      {
+    signal_BRANCH_COMPLETE_BHT_ACK     = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete];
+    signal_BRANCH_COMPLETE_BHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete]; 
+      }
+    if (_param._have_pht)
+      {
+    signal_BRANCH_COMPLETE_PHT_ACK     = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete];
+    signal_BRANCH_COMPLETE_PHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete]; 
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	rename = "in_BRANCH_COMPLETE_VAL_"         +toString(i);
+	 in_BRANCH_COMPLETE_VAL         [i] = new SC_IN (Tcontrol_t)     (rename.c_str());
+
+	rename = "out_BRANCH_COMPLETE_ACK_"        +toString(i);
+	out_BRANCH_COMPLETE_ACK         [i] = new SC_OUT(Tcontrol_t)     (rename.c_str());
+
+	rename = "in_BRANCH_COMPLETE_ADDRESS_"     +toString(i);
+	 in_BRANCH_COMPLETE_ADDRESS     [i] = new SC_IN (Taddress_t)     (rename.c_str());
+
+	if (_param._have_bht)
+	  {
+    	rename = "in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i);
+	 in_BRANCH_COMPLETE_BHT_HISTORY [i] = new SC_IN (Tbht_history_t) (rename.c_str());
+	  }
+	if (_param._have_pht)
+	  {
+	rename = "in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i);
+	 in_BRANCH_COMPLETE_PHT_HISTORY [i] = new SC_IN (Tpht_history_t) (rename.c_str());
+	  }
+	rename = "in_BRANCH_COMPLETE_DIRECTION_"  +toString(i);
+	 in_BRANCH_COMPLETE_DIRECTION   [i] = new SC_IN (Tcontrol_t)     (rename.c_str());
+	if (_param._have_bht)
+	  {
+	rename = "signal_BRANCH_COMPLETE_BHT_ACK_"    +toString(i);
+	signal_BRANCH_COMPLETE_BHT_ACK     [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str());
+
+	rename = "signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i); 
+	signal_BRANCH_COMPLETE_BHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 
+	  }
+	if (_param._have_pht)
+	  {
+	rename = "signal_BRANCH_COMPLETE_PHT_ACK_"    +toString(i);
+	signal_BRANCH_COMPLETE_PHT_ACK     [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str());
+
+	rename = "signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i); 
+	signal_BRANCH_COMPLETE_PHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 
+	  }
+      }
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    string name_component;
+
+    // =====[ component_Branch_History_Table ]============================    
+    if (_param._have_bht)
+      {
+	name_component = _name+"_Branch_History_Table";
+
+	log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str());
+	
+	component_Branch_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table (name_component.c_str()               ,
+#ifdef STATISTICS
+																						       _param_statistics                    ,
+#endif
+																						       *(_param._param_branch_history_table));
+	
+	// Instantiation
+	(*(component_Branch_History_Table->in_CLOCK))        (*(in_CLOCK));
+
+	for (uint32_t i=0; i<_param._nb_prediction; i++)
+	  {
+	    (*(component_Branch_History_Table-> in_PREDICT_VAL             [i]))    (*(    in_PREDICT_VAL          [i]));
+	    (*(component_Branch_History_Table->out_PREDICT_ACK             [i]))    (*(signal_PREDICT_BHT_ACK      [i]));
+	    (*(component_Branch_History_Table-> in_PREDICT_ADDRESS         [i]))    (*(signal_PREDICT_BHT_ADDRESS  [i]));
+	    (*(component_Branch_History_Table->out_PREDICT_HISTORY         [i]))    (*(   out_PREDICT_BHT_HISTORY  [i]));
+	  }
+	
+	for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	  {
+	    (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_VAL       [i]))    (*(    in_BRANCH_COMPLETE_VAL         [i]));
+	    (*(component_Branch_History_Table->out_BRANCH_COMPLETE_ACK       [i]))    (*(signal_BRANCH_COMPLETE_BHT_ACK     [i]));
+	    (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_ADDRESS   [i]))    (*(signal_BRANCH_COMPLETE_BHT_ADDRESS [i]));
+	    (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_HISTORY   [i]))    (*(    in_BRANCH_COMPLETE_BHT_HISTORY [i]));
+	    (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i]))    (*(    in_BRANCH_COMPLETE_DIRECTION   [i]));
+	  }
+      }
+
+    // =====[ component_Pattern_History_Table ]===========================    
+    if (_param._have_pht)
+      {
+	name_component = _name+"_Pattern_History_Table";
+	
+	log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str());
+	
+	component_Pattern_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Pattern_History_Table (name_component.c_str()               ,
+#ifdef STATISTICS
+																							 _param_statistics                    ,
+#endif
+																							 *(_param._param_pattern_history_table));
+	
+	// Instantiation
+	(*(component_Pattern_History_Table->in_CLOCK))        (*(in_CLOCK));
+	
+	for (uint32_t i=0; i<_param._nb_prediction; i++)
+	  {
+	    (*(component_Pattern_History_Table-> in_PREDICT_VAL             [i]))    (*(    in_PREDICT_VAL          [i]));
+	    (*(component_Pattern_History_Table->out_PREDICT_ACK             [i]))    (*(signal_PREDICT_PHT_ACK      [i]));
+	    (*(component_Pattern_History_Table-> in_PREDICT_ADDRESS         [i]))    (*(signal_PREDICT_PHT_ADDRESS  [i]));
+	    (*(component_Pattern_History_Table->out_PREDICT_HISTORY         [i]))    (*(   out_PREDICT_PHT_HISTORY  [i]));
+	  }
+	
+	for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	  {
+	    (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_VAL       [i]))    (*(    in_BRANCH_COMPLETE_VAL         [i]));
+	    (*(component_Pattern_History_Table->out_BRANCH_COMPLETE_ACK       [i]))    (*(signal_BRANCH_COMPLETE_PHT_ACK     [i]));
+	    (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_ADDRESS   [i]))    (*(signal_BRANCH_COMPLETE_PHT_ADDRESS [i]));
+	    (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_HISTORY   [i]))    (*(    in_BRANCH_COMPLETE_PHT_HISTORY [i]));
+	    (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i]))    (*(    in_BRANCH_COMPLETE_DIRECTION   [i]));
+	  }
+      }
+
+    // =====[ component_Two_Level_Branch_Predictor_Glue ]===========================    
+    name_component = _name+"_Two_Level_Branch_Predictor_Glue";
+    
+    log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str());
+    
+    component_Two_Level_Branch_Predictor_Glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue (name_component.c_str()               ,
+#ifdef STATISTICS
+																										   _param_statistics                    ,
+#endif
+																										   *(_param._param_two_level_branch_predictor_glue));
+    
+    // Instantiation
+#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+    (*(component_Two_Level_Branch_Predictor_Glue->in_CLOCK))        (*(in_CLOCK));
+#endif	
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	  {
+	    (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_ACK             [i])) (*(signal_PREDICT_BHT_ACK              [i]));
+	    (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_BHT_ADDRESS         [i])) (*(signal_PREDICT_BHT_ADDRESS          [i]));
+	  }											   										  
+	if (_param._have_pht)								   							  
+	  {											   										  
+	    (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_PHT_ACK             [i])) (*(signal_PREDICT_PHT_ACK              [i]));
+	    (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_PHT_ADDRESS         [i])) (*(signal_PREDICT_PHT_ADDRESS          [i]));
+	  }											   										  
+	if (_param._have_bht and _param._have_pht)						   					  
+	  {											   										  
+	    (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_HISTORY         [i])) (*(   out_PREDICT_BHT_HISTORY          [i]));
+	  }											   										  
+	(*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_ACK                 [i])) (*(   out_PREDICT_ACK                  [i]));
+	(*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_ADDRESS             [i])) (*(    in_PREDICT_ADDRESS              [i]));
+      }
+    
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	  {
+	    (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_ACK     [i])) (*(signal_BRANCH_COMPLETE_BHT_ACK      [i]));
+	    (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_BHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_BHT_ADDRESS  [i]));
+	  }										   					       				  
+	if (_param._have_pht)							   					       	  
+	  {										   					       				  
+	    (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_PHT_ACK     [i])) (*(signal_BRANCH_COMPLETE_PHT_ACK      [i]));
+	    (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_PHT_ADDRESS  [i]));
+	  }										   					       				  
+	if (_param._have_bht and _param._have_pht)					   					  
+	  {										   					       				  
+	    (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (*(    in_BRANCH_COMPLETE_BHT_HISTORY  [i]));
+	  }										   					       				  
+	(*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_ACK         [i])) (*(   out_BRANCH_COMPLETE_ACK          [i]));
+	(*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_ADDRESS     [i])) (*(    in_BRANCH_COMPLETE_ADDRESS      [i]));
+      }
+  
+    log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","End");
+  };
+  
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp	(revision 3)
@@ -0,0 +1,123 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+  void Two_Level_Branch_Predictor::deallocation (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"deallocation","Begin");
+
+    delete in_CLOCK;
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	delete  in_PREDICT_VAL                 [i];
+	delete out_PREDICT_ACK                 [i];
+	delete  in_PREDICT_ADDRESS             [i];
+	if (_param._have_bht)
+	delete out_PREDICT_BHT_HISTORY         [i];
+	if (_param._have_pht)
+	delete out_PREDICT_PHT_HISTORY         [i];
+	if (_param._have_bht)
+	  {
+	delete signal_PREDICT_BHT_ACK          [i];
+	delete signal_PREDICT_BHT_ADDRESS      [i];
+	  }
+	if (_param._have_pht)
+	  {
+	delete signal_PREDICT_PHT_ACK          [i];
+	delete signal_PREDICT_PHT_ADDRESS      [i];
+	  }
+
+      }
+
+    delete  in_PREDICT_VAL        ;
+    delete out_PREDICT_ACK        ;
+    delete  in_PREDICT_ADDRESS    ;
+    if (_param._have_bht)
+    delete out_PREDICT_BHT_HISTORY;
+    if (_param._have_pht)
+    delete out_PREDICT_PHT_HISTORY;
+    if (_param._have_bht)
+      {
+    delete signal_PREDICT_BHT_ACK    ;
+    delete signal_PREDICT_BHT_ADDRESS;
+      }
+    if (_param._have_pht)
+      {
+    delete signal_PREDICT_PHT_ACK    ;
+    delete signal_PREDICT_PHT_ADDRESS;
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	delete  in_BRANCH_COMPLETE_VAL         [i];
+	delete out_BRANCH_COMPLETE_ACK         [i];
+	delete  in_BRANCH_COMPLETE_ADDRESS     [i];
+	if (_param._have_bht)
+	delete  in_BRANCH_COMPLETE_BHT_HISTORY [i];
+	if (_param._have_pht)
+	delete  in_BRANCH_COMPLETE_PHT_HISTORY [i];
+	delete  in_BRANCH_COMPLETE_DIRECTION   [i];
+	if (_param._have_bht)
+	  {
+	delete signal_BRANCH_COMPLETE_BHT_ACK     [i];
+	delete signal_BRANCH_COMPLETE_BHT_ADDRESS [i]; 
+	  }
+	if (_param._have_pht)
+	  {
+	delete signal_BRANCH_COMPLETE_PHT_ACK     [i];
+	delete signal_BRANCH_COMPLETE_PHT_ADDRESS [i]; 
+	  }
+      }
+
+    delete  in_BRANCH_COMPLETE_VAL        ;
+    delete out_BRANCH_COMPLETE_ACK        ;
+    delete  in_BRANCH_COMPLETE_ADDRESS    ;
+    if (_param._have_bht)
+    delete  in_BRANCH_COMPLETE_BHT_HISTORY;
+    if (_param._have_pht)
+    delete  in_BRANCH_COMPLETE_PHT_HISTORY;
+    delete  in_BRANCH_COMPLETE_DIRECTION  ;
+    if (_param._have_bht)
+      {
+    delete signal_BRANCH_COMPLETE_BHT_ACK    ;
+    delete signal_BRANCH_COMPLETE_BHT_ADDRESS; 
+      }
+    if (_param._have_pht)
+      {
+    delete signal_BRANCH_COMPLETE_PHT_ACK    ;
+    delete signal_BRANCH_COMPLETE_PHT_ADDRESS; 
+      }
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    if (_param._have_bht)
+    delete component_Branch_History_Table ;
+    if (_param._have_pht)
+    delete component_Pattern_History_Table;
+    delete component_Two_Level_Branch_Predictor_Glue;
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"deallocation","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_statistics.cpp	(revision 3)
@@ -0,0 +1,45 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  string Two_Level_Branch_Predictor::statistics (uint32_t depth)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"statistics","Begin");
+
+    string stat_component_Branch_History_Table  = (_param._have_bht==false)?"":component_Branch_History_Table  ->statistics(depth+1);
+    string stat_component_Pattern_History_Table = (_param._have_pht==false)?"":component_Pattern_History_Table ->statistics(depth+1);
+
+    string txt = _stat->print(depth,
+			      stat_component_Branch_History_Table                            +
+			      stat_component_Pattern_History_Table                           +
+			      component_Two_Level_Branch_Predictor_Glue->statistics(depth+1)
+			      );
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"statistics","End");
+
+    return txt;
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp	(revision 3)
@@ -0,0 +1,43 @@
+#ifdef SYSTEMC
+#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  void Two_Level_Branch_Predictor::transition (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"transition","Begin");
+
+#ifdef STATISTICS
+    _stat->add();
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition ();
+#endif
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"transition","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl.cpp	(revision 3)
@@ -0,0 +1,48 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  void Two_Level_Branch_Predictor::vhdl (void)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl","Begin");
+    Vhdl vhdl (_name);
+
+    vhdl.set_library_work (_name + "_Pack");
+    if (_param._have_bht)
+    vhdl.set_library_work (_name + "_Branch_History_Table_Pack");
+    if (_param._have_pht)
+    vhdl.set_library_work (_name + "_Pattern_History_Table_Pack");
+    vhdl.set_library_work (_name + "_Two_Level_Branch_Predictor_Glue_Pack");
+    
+    vhdl_port        (vhdl);
+    vhdl_declaration (vhdl);
+    vhdl_body        (vhdl);
+
+    vhdl.generate_file();
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl","End");
+
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_body.cpp	(revision 3)
@@ -0,0 +1,135 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  void Two_Level_Branch_Predictor::vhdl_body (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_body","Begin");
+
+    list<string> list_port_map;
+
+    if (_param._have_bht)
+      {
+	list_port_map.clear();
+
+	vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK");
+
+	for (uint32_t i=0; i<_param._nb_prediction; i++)
+	  {
+	    vhdl.set_body_component_port_map (list_port_map," in_PREDICT_VAL_"+toString(i)+"              ","    in_PREDICT_VAL_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_ACK_"+toString(i)+"              ","signal_PREDICT_BHT_ACK_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map," in_PREDICT_ADDRESS_"+toString(i)+"          ","signal_PREDICT_BHT_ADDRESS_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_HISTORY_"+toString(i)+"          ","signal_PREDICT_BHT_HISTORY_"+toString(i));
+	  }
+	
+	for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	  {
+	    vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_VAL_"+toString(i)+"      ","    in_BRANCH_COMPLETE_VAL_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_ACK_"+toString(i)+"      ","signal_BRANCH_COMPLETE_BHT_ACK_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+"  ","signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_HISTORY_"+toString(i)+"  ","    in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"","    in_BRANCH_COMPLETE_DIRECTION_"+toString(i));
+	  }
+	
+	vhdl.set_body_component ("component_Branch_History_Table",_name+"_Branch_History_Table",list_port_map);
+      }
+
+    if (_param._have_pht)
+      {
+	list_port_map.clear();
+
+	vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK");
+
+	for (uint32_t i=0; i<_param._nb_prediction; i++)
+	  {
+	    vhdl.set_body_component_port_map (list_port_map," in_PREDICT_VAL_"+toString(i)+"              ","    in_PREDICT_VAL_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_ACK_"+toString(i)+"              ","signal_PREDICT_PHT_ACK_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map," in_PREDICT_ADDRESS_"+toString(i)+"          ","signal_PREDICT_PHT_ADDRESS_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_HISTORY_"+toString(i)+"          ","   out_PREDICT_PHT_HISTORY_"+toString(i));
+	  }
+	
+	for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+	  {
+	    vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_VAL_"+toString(i)+"      ","    in_BRANCH_COMPLETE_VAL_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_ACK_"+toString(i)+"      ","signal_BRANCH_COMPLETE_PHT_ACK_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+"  ","signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_HISTORY_"+toString(i)+"  ","    in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i));
+	    vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"","    in_BRANCH_COMPLETE_DIRECTION_"+toString(i));
+	  }
+	
+	vhdl.set_body_component ("component_Pattern_History_Table",_name+"_Pattern_History_Table",list_port_map);
+      }
+
+    list_port_map.clear();
+    
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	  {
+	vhdl.set_body_component_port_map (list_port_map," in_PREDICT_BHT_ACK_"+toString(i)+"            ","signal_PREDICT_BHT_ACK_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_BHT_ADDRESS_"+toString(i)+"        ","signal_PREDICT_BHT_ADDRESS_"+toString(i));
+	  }											   										  
+	if (_param._have_pht)								   							  
+	  {											   										  
+	vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PHT_ACK_"+toString(i)+"            ","signal_PREDICT_PHT_ACK_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_PHT_ADDRESS_"+toString(i)+"        ","signal_PREDICT_PHT_ADDRESS_"+toString(i));
+	  }											   										  
+	if (_param._have_bht and _param._have_pht)						   					  
+	  {											   										  
+	vhdl.set_body_component_port_map (list_port_map," in_PREDICT_BHT_HISTORY_"+toString(i)+"        ","signal_PREDICT_BHT_HISTORY_"+toString(i));
+	  }											   										  
+	vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_ACK_"+toString(i)+"                ","   out_PREDICT_ACK_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map," in_PREDICT_ADDRESS_"+toString(i)+"            ","    in_PREDICT_ADDRESS_"+toString(i));
+      }
+    
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	  {
+	vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_BHT_ACK_"+toString(i)+"    ","signal_BRANCH_COMPLETE_BHT_ACK_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i)+"","signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i));
+	  }										   					       				  
+	if (_param._have_pht)
+	  {
+	vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_PHT_ACK_"+toString(i)+"    ","signal_BRANCH_COMPLETE_PHT_ACK_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+"","signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i));
+	  }										   					       				  
+	if (_param._have_bht and _param._have_pht)
+	  {
+        vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+"","    in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i));
+	  }										   					       				  
+	vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_ACK_"+toString(i)+"        ","   out_BRANCH_COMPLETE_ACK_"+toString(i));
+	vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+"    ","    in_BRANCH_COMPLETE_ADDRESS_"+toString(i));
+      }
+
+    vhdl.set_body_component ("component_Two_Level_Branch_Predictor_Glue",_name+"_Two_Level_Branch_Predictor_Glue",list_port_map);
+
+    if (_param._have_bht)
+      for (uint32_t i=0; i<_param._nb_prediction; i++)
+	vhdl.set_body("out_PREDICT_BHT_HISTORY_"+toString(i)+" <= signal_PREDICT_BHT_HISTORY_"+toString(i)+";");
+    
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_body","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_declaration.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_declaration.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_declaration.cpp	(revision 3)
@@ -0,0 +1,61 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  void Two_Level_Branch_Predictor::vhdl_declaration (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_declaration","Begin");
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	if (_param._have_bht)
+	  {
+	vhdl.set_signal  ("signal_PREDICT_BHT_ACK_"+toString(i), 1);
+	vhdl.set_signal  ("signal_PREDICT_BHT_ADDRESS_"+toString(i), _param._bht_size_address);
+	vhdl.set_signal  ("signal_PREDICT_BHT_HISTORY_"+toString(i), _param._bht_size_shifter);
+	  }
+	if (_param._have_pht)
+	  {
+	vhdl.set_signal  ("signal_PREDICT_PHT_ACK_"+toString(i), 1);
+	vhdl.set_signal  ("signal_PREDICT_PHT_ADDRESS_"+toString(i), _param._pht_size_address);
+	  }
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	if (_param._have_bht)
+	  {
+	vhdl.set_signal  ("signal_BRANCH_COMPLETE_BHT_ACK_"+toString(i), 1);
+	vhdl.set_signal  ("signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i), _param._bht_size_address);
+	  }
+	if (_param._have_pht)
+	  {
+	vhdl.set_signal  ("signal_BRANCH_COMPLETE_PHT_ACK_"+toString(i), 1);
+	vhdl.set_signal  ("signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i), _param._pht_size_address);
+	  }
+      }
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_declaration","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_port.cpp	(revision 3)
@@ -0,0 +1,56 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+  void Two_Level_Branch_Predictor::vhdl_port (Vhdl & vhdl)
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_port","Begin");
+
+    vhdl.set_port (" in_CLOCK" , IN, 1);
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	vhdl.set_port (" in_PREDICT_VAL_"+toString(i)+"                ", IN, 1);
+	vhdl.set_port ("out_PREDICT_ACK_"+toString(i)+"                ",OUT, 1);
+	vhdl.set_port (" in_PREDICT_ADDRESS_"+toString(i)+"            ", IN,_param._size_address);
+	if (_param._have_bht)
+	vhdl.set_port ("out_PREDICT_BHT_HISTORY_"+toString(i)+"        ",OUT,_param._bht_size_shifter);
+	if (_param._have_pht)
+    	vhdl.set_port ("out_PREDICT_PHT_HISTORY_"+toString(i)+"        ",OUT,_param._pht_size_counter);
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+"        ", IN, 1);
+	vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+"        ",OUT, 1);
+	vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+"    ", IN,_param._size_address);
+	if (_param._have_bht)
+    	vhdl.set_port (" in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+"", IN,_param._bht_size_shifter);
+	if (_param._have_pht)
+	vhdl.set_port (" in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i)+"", IN,_param._pht_size_counter);
+	vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"  ", IN, 1);
+      }
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_port","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_label.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_label.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_label.cpp	(revision 3)
@@ -0,0 +1,31 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  void Two_Level_Branch_Predictor::vhdl_testbench_label (string label)
+  {
+#ifdef VHDL_TESTBENCH
+    _vhdl_testbench->add_label(label);
+#endif
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_port.cpp	(revision 3)
@@ -0,0 +1,56 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  void Two_Level_Branch_Predictor::vhdl_testbench_port ()
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_port","Begin");
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	_vhdl_testbench->set_port (" in_PREDICT_VAL_"        +toString(i), IN, 1);
+	_vhdl_testbench->set_port ("out_PREDICT_ACK_"        +toString(i),OUT, 1);
+	_vhdl_testbench->set_port (" in_PREDICT_ADDRESS_"    +toString(i), IN,_param._size_address);
+	if (_param._have_bht)
+	_vhdl_testbench->set_port ("out_PREDICT_BHT_HISTORY_"+toString(i),OUT,_param._bht_size_shifter);
+	if (_param._have_pht)
+    	_vhdl_testbench->set_port ("out_PREDICT_PHT_HISTORY_"+toString(i),OUT,_param._pht_size_counter);
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	_vhdl_testbench->set_port (" in_BRANCH_COMPLETE_VAL_"        +toString(i), IN, 1);
+	_vhdl_testbench->set_port ("out_BRANCH_COMPLETE_ACK_"        +toString(i),OUT, 1);
+	_vhdl_testbench->set_port (" in_BRANCH_COMPLETE_ADDRESS_"    +toString(i), IN,_param._size_address);
+	if (_param._have_bht)
+    	_vhdl_testbench->set_port (" in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i), IN,_param._bht_size_shifter);
+	if (_param._have_pht)
+	_vhdl_testbench->set_port (" in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i), IN,_param._pht_size_counter);
+	_vhdl_testbench->set_port (" in_BRANCH_COMPLETE_DIRECTION_"  +toString(i), IN, 1);
+      }
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_port","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_transition.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_transition.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_transition.cpp	(revision 3)
@@ -0,0 +1,77 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace stage_1_ifetch {
+namespace predictor {
+namespace meta_predictor {
+namespace two_level_branch_predictor {
+
+
+  void Two_Level_Branch_Predictor::vhdl_testbench_transition ()
+  {
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_transition","Begin");
+
+#ifndef SYSTEMCASS_SPECIFIC
+    sc_cycle(0);
+#endif    
+
+    // In order with file Two_Level_Branch_Predictor_vhdl_testbench_port.cpp
+    // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
+    // (because we have no control on the ordonnancer's policy)
+
+    for (uint32_t i=0; i<_param._nb_prediction; i++)
+      {
+	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL                          [i]));
+	_vhdl_testbench->add_output(PORT_READ(component_Two_Level_Branch_Predictor_Glue->
+					      out_PREDICT_ACK                          [i]));
+	_vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS                      [i]));
+	if (_param._have_bht)
+	_vhdl_testbench->add_output(PORT_READ(component_Branch_History_Table           ->
+					      component_RegisterFile                   ->
+					      out_READ_DATA                            [i]));
+	if (_param._have_pht)
+	_vhdl_testbench->add_output(PORT_READ(component_Pattern_History_Table          ->
+					      component_RegisterFile                   ->
+					      out_READ_DATA                            [i]));
+      }
+
+    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
+      {
+	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL                  [i]));
+	_vhdl_testbench->add_output(PORT_READ(component_Two_Level_Branch_Predictor_Glue->
+					      out_BRANCH_COMPLETE_ACK                  [i]));
+	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS              [i]));
+	if (_param._have_bht)
+	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_BHT_HISTORY          [i]));
+	if (_param._have_pht)
+	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PHT_HISTORY          [i]));
+	_vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION            [i]));
+      }
+    
+    // add_test :
+    //  - True  : the cycle must be compare with the output of systemC
+    //  - False : no test
+    _vhdl_testbench->add_test(true);
+
+    _vhdl_testbench->new_cycle (); // always at the end
+
+    log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_transition","End");
+  };
+
+}; // end namespace two_level_branch_predictor
+}; // end namespace meta_predictor
+}; // end namespace predictor
+}; // end namespace stage_1_ifetch
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/configure.mkf
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/configure.mkf	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/configure.mkf	(revision 3)
@@ -0,0 +1,982 @@
+#!/usr/bin/perl
+
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+#use strict;
+
+my $mkf_file_gc = "mkf.info";
+
+######################################################
+#		temporary files
+#
+
+my @temp_files;
+my $tmp_dir = "/tmp";
+
+sub get_temp_file
+{
+    my ($ext_p) = @_;
+
+    my $fname;
+
+    do
+    {
+	my $random = int(rand(10000));
+	$fname = "$tmp_dir/configure_".$random."_".$ext_p;
+    }
+    while (-f $fname);
+
+    push (@temp_files, $fname);
+
+    return $fname;
+}
+
+sub clear_temp_files
+{
+    unlink($_) foreach (@temp_files);
+}
+
+######################################################
+#		Display functions
+#
+
+sub error
+{
+    $_ = @_[0];
+#    s/'/'\033[01;31m/g;
+#    s/`/\033[01;36m`/g;
+    print "[ Error ] $_\n";
+#    print "[ Error ] \033[01;31m$_\033[m\n";
+    clear_temp_files;
+    exit -1;
+}
+
+sub warning
+{
+    $_ = @_[0];
+#    s/'/'\033[01;93m/g;
+#    s/`/\033[01;36m`/g;
+    print "[Warning] $_\n";
+#    print "[Warning] \033[01;93m$_\033[m\n";
+}
+
+######################################################
+#		strings replace functions
+#
+
+sub replace
+{
+    my ($str_p, $value_p, $keyword_p) = @_;
+
+    $str_p =~ s/{$keyword_p}/$value_p/g;
+
+    return $str_p;
+}
+
+sub replace_vars
+{
+    my ($str_p, $vars_p, $keyword_p) = @_;
+
+    $str_p =~ s/{$keyword_p,([^\}]+)}/$$vars_p{$1}/g;
+
+    return $str_p;
+}
+
+sub replace_vars_list
+{
+    my ($str_p, $vars_p, $keyword_p) = @_;
+
+    while ($str_p =~ /{$keyword_p,([^\,]*),([^\}]+)}/)
+    {
+	my $var = $2;
+	my $pre = $1;
+	my $list;
+
+	$list = "$list $pre$_" foreach (split(/ +/, $$vars_p{$var}));
+	$str_p =~ s/{$keyword_p,$pre,$var}/$list/;
+    }
+
+    return $str_p;
+}
+
+sub replace_list
+{
+    my ($str_p, $list, $keyword_p) = @_;
+
+    return $str_p if (! $list);
+
+    while ($str_p =~ /{$keyword_p(!?),([^\},]+),?([^\}]*)}/)
+    {
+	my $val;
+	my $strip = $1;
+	my $match_p = $2;
+	my $prefix = $3;
+
+	foreach (@$list)
+	{
+	    if (/^$match_p$/)
+	    {
+		my $item = $_;
+		$item =~ s/\..*$// if ($strip);
+		$val .= " ".$prefix.$item;
+	    }
+	}
+
+	$str_p =~ s/{$keyword_p$strip,[^\}]+}/$val/;
+    }
+
+    return $str_p;
+}
+
+sub replace_temp_file
+{
+    my ($str_p, $keyword_p) = @_;
+
+    while ($str_p =~ /{$keyword_p,([^\,]+),([^\}]+)}/)
+    {
+	my $id = $1;
+	my $ext = $2;
+	my $fname = get_temp_file ($ext);
+
+	$str_p =~ s/{$keyword_p,$id,$ext}/$fname/g;
+    }
+
+    return $str_p;
+}
+
+######################################################
+#	    Mkf file commands functions
+#
+
+sub cmd_end_if
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: no parameter expected for `@$params_p[0]'"
+	if (@$params_p != 1);
+
+    my $if_depth = $$state_p{if_depth};
+    my $if_bool = $$state_p{if_bool};
+
+    error "line $line_num: no previous _if command to end" 
+	if (! $if_depth);
+
+    $$state_p{if_depth} = $if_depth - 1;
+}
+
+sub cmd_else
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: no parameter expected for `@$params_p[0]'"
+	if (@$params_p != 1);
+
+    my $if_depth = $$state_p{if_depth};
+    my $if_bool = $$state_p{if_bool};
+
+    error "line $line_num: no previous _if command" 
+	if (! $if_depth);
+
+    @{$if_bool}[$if_depth] = @{$if_bool}[$if_depth - 1] && ! @{$if_bool}[$if_depth];
+}
+
+sub cmd_if_exec_ok
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: more parameters expected for `@$params_p[0]'"
+	if (@$params_p < 2);
+
+    my $if_depth = $$state_p{if_depth};
+    my $if_bool = $$state_p{if_bool};
+    my $cmd = replace_temp_file(@$params_p[1], "TEMP");
+
+    @{$if_bool}[$if_depth + 1] = @{$if_bool}[$if_depth]
+	&& ! system($cmd . " > /dev/null 2>&1");
+
+    $$state_p{if_depth} = $if_depth + 1;
+}
+
+sub cmd_if_file_exists
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: one parameters expected for `@$params_p[0]'"
+	if (@$params_p != 2);
+
+    my $file = @$params_p[1];
+    my $if_depth = $$state_p{if_depth};
+    my $if_bool = $$state_p{if_bool};
+
+    @{$if_bool}[$if_depth + 1] = @{$if_bool}[$if_depth] && -e $file;
+
+    $$state_p{if_depth} = $if_depth + 1;
+}
+
+sub cmd_if_in_path
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: one parameters expected for `@$params_p[0]'"
+	if (@$params_p != 2);
+
+    my $exec_file = @$params_p[1];
+    my $if_depth = $$state_p{if_depth};
+    my $if_bool = $$state_p{if_bool};
+
+    @{$if_bool}[$if_depth + 1] = 0;
+
+    if (@{$if_bool}[$if_depth])
+    {
+	if ($exec_file =~ /\//)
+	{
+	    @{$if_bool}[$if_depth + 1] = -x $exec_file;
+	}
+	else
+	{
+	    foreach (split(/:/, $ENV{"PATH"}))
+	    {
+		if (-x "$_/$exec_file")
+		{
+		    @{$if_bool}[$if_depth + 1] = 1;
+		    last;
+		}
+	    }
+	}
+    }
+
+    $$state_p{if_depth} = $if_depth + 1;
+}
+
+sub cmd_if_stdout_match
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: two parameters expected for `@$params_p[0]'"
+	if (@$params_p != 3);
+
+    my $str = @$params_p[1];
+    my $exec_cmd = @$params_p[2];
+    my $if_depth = $$state_p{if_depth};
+    my $if_bool = $$state_p{if_bool};
+
+    @{$if_bool}[$if_depth + 1] = @{$if_bool}[$if_depth]
+	&& (`$exec_cmd 2>&1` =~ /$str/);
+
+    $$state_p{if_depth} = $if_depth + 1;
+}
+
+sub cmd_if_var_eq
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: two parameters expected for `@$params_p[0]'"
+	if (@$params_p < 2);
+
+    my $vars = $$state_p{vars};
+    my $var_name = @$params_p[1];
+    my $var_value = @$params_p[2];
+    my $if_depth = $$state_p{if_depth};
+    my $if_bool = $$state_p{if_bool};
+
+    @{$if_bool}[$if_depth + 1] = @{$if_bool}[$if_depth] && (${$vars}{$var_name} eq $var_value);
+
+    $$state_p{if_depth} = $if_depth + 1;
+}
+
+sub cmd_command_add
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: three parameters expected for `@$params_p[0]'"
+	if (@$params_p < 4);
+
+    my $oper = "@$params_p[1]_@$params_p[2]";
+    my $jobs = $$state_p{jobs};
+
+    $$jobs{$oper} = [] if (! exists $$jobs{$oper});
+    my $jobs_list = $$jobs{$oper};
+
+    push (@$jobs_list, join (" ", @$params_p[3..@$params_p - 1]));
+}
+
+sub cmd_clean_add
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: three parameters expected for `@$params_p[0]'"
+	if (@$params_p < 4);
+
+    my $oper = "@$params_p[1]_@$params_p[2]";
+    my $torm = $$state_p{torm};
+
+    $$torm{$oper} = [] if (! exists $$torm{$oper});
+    my $torm_list = $$torm{$oper};
+
+    foreach my $item (split(/ +/, @$params_p[3]))
+    {
+	push (@$torm_list, $item);
+    }
+}
+
+# parse C like source files to get included files
+sub auto_dep_c
+{
+    my ($dir_p, $deps_p, $c_src_p, $inc_dirs) = @_;
+
+    if (! open (C_SRC, "$dir_p/$c_src_p"))
+    {
+	warning "can't open `$c_src_p' c source file";
+	return;
+    }
+
+    foreach my $c_line (<C_SRC>)
+    {
+	# find #include "" lines
+	if ($c_line =~ /^[ \t]*\#[ \t]*include[ \t]*\"(.*)\"/)
+	{
+	    my $inc_file = $1;
+
+	    # find included file in include directories
+	    foreach my $inc_dir ((split(/ +/, $inc_dirs), "."))
+	    {
+		my $abs_path = $inc_dir =~ /^\// ? $inc_dir : "$dir_p/$inc_dir";
+
+		if (! -d $abs_path)
+		{
+		    warning "can't find `$abs_path' include directory";
+		    next;
+		}
+
+		next if (! -f "$abs_path/$inc_file");
+
+		my $dep_hdr = "$inc_dir/$inc_file";
+		$dep_hdr =~ s/^.\///;
+
+		push(@$deps_p, $dep_hdr);
+	    }
+	}
+    }
+}
+
+# dummy function, nothing to parse in file
+sub auto_dep_none
+{
+}
+
+my %auto_src_cmd = 
+(
+ "c_src" => \&auto_dep_c,
+ "none" => \&auto_dep_none,
+);
+
+sub cmd_auto_source_dep
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: three parameters expected for `@$params_p[0]'"
+	if (@$params_p != 4);
+
+    my $deps = $$state_p{deps};				# hash table for all target/deps of current Makefile
+    my $src_type = @$params_p[1];
+    my $ext = @$params_p[2];
+    my $ext_out = @$params_p[3];
+
+    foreach my $c_src (<$dir_p/*.$ext>)
+    {
+	$c_src = $1 if ($c_src =~ /.*\/(.*)/);
+
+	my $target = $c_src;
+	$target =~ s/\.$ext$/.$ext_out/g;
+
+	next if (${$deps}{$target});
+
+	${$deps}{$target} = [];
+
+	push(@{${$deps}{$target}}, $c_src);
+
+	# get pointer on function for source file parse
+	if (my $func_ptr = $auto_src_cmd{$src_type})
+	{
+	    # call command function
+	    $func_ptr -> ($dir_p, ${$deps}{$target}, $c_src, ${$$state_p{vars}}{"inc_dirs"});
+	}
+	else
+	{
+	    # error if unknow function
+	    error "line $line_num: unknown source file type `$src_type'";
+	}
+    }
+}
+
+sub cmd_auto_dep
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: two parameters expected for `@$params_p[0]'"
+	if (@$params_p != 3);
+
+    my $deps = $$state_p{deps};				# hash table for all target/deps of current Makefile
+    my $ext = @$params_p[1];
+    my $ext_out = @$params_p[2];
+
+    foreach my $dep (keys(%$deps))
+    {
+	# match file name extention in existing target
+
+	next if (not ($dep =~ /[^.]*\.(.*)$/));
+	next if ($1 ne $ext);
+
+	# change extention to $ext_out
+	my $target = $dep;
+	$target =~ s/\.$ext$/.$ext_out/g;
+
+	# skip if target already exist
+
+	${$deps}{$target} = [];
+	push(@{${$deps}{$dep}}, $target);
+    }
+}
+
+
+sub cmd_target_dep
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: two parameters expected for `@$params_p[0]'"
+	if (@$params_p != 3);
+
+    my $deps = $$state_p{deps};				# hash table for all target/deps of current Makefile
+    my $target = @$params_p[1];				# target name
+    my @target_deps = split(/ +/, @$params_p[2]);	# target dependencies name list
+
+#    error "line $line_num: redefinition of `$target' target dependencies"
+#	if (${$deps}{$target});
+
+    foreach (@target_deps)
+    {
+	${$deps}{$_} = [] if (! exists ${$deps}{$_});
+    }
+
+    push(@{${$deps}{$target}}, @target_deps);
+}
+
+sub cmd_target_dep_add
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: two parameters expected for `@$params_p[0]'"
+	if (@$params_p != 3);
+
+    my $deps = $$state_p{deps};				# hash table for all target/deps of current Makefile
+    my $target = @$params_p[1];				# target name
+    my @target_deps = split(/ +/, @$params_p[2]);	# target dependencies name list
+
+    error "line $line_num: no previous dependencies for `$target' target"
+	if (! ${$deps}{$target});
+
+    foreach (@target_deps)
+    {
+	${$deps}{$_} = "0" if (! exists ${$deps}{$_});
+    }
+
+    push (@{${$deps}{$target}}, @target_deps);
+}
+
+sub cmd_install_cmd
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: one parameters expected for `@$params_p[0]'"
+	if (@$params_p != 2);
+
+    my $jobs_list = $$state_p{install};
+
+    push (@$jobs_list, @$params_p[1]);
+}
+
+sub cmd_msg_info
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    print "[ info ] ", @$params_p[1], "\n";
+}
+
+sub cmd_msg_error
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error join (" ", @$params_p[1..@$params_p - 1]);
+}
+
+sub cmd_msg_warning
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    warning join (" ", @$params_p[1..@$params_p - 1]);
+}
+
+sub cmd_mkf_include
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: one parameters expected for `@$params_p[0]'"
+	if (@$params_p != 2);
+
+    my $filename = @$params_p[1];
+
+    local *MKF_FILE;
+    error "line $line_num: can't open `$filename' included file"
+	if (! open (MKF_FILE, "$dir_p/$filename"));
+
+    process_dir_mkffile($dir_p, $state_p, *MKF_FILE);
+}
+
+sub cmd_path_parent
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: one parameters expected for `@$params_p[0]'"
+	if (@$params_p != 2);
+
+    my $vars = $$state_p{vars};
+
+    foreach my $var_name (split(/ +/, @$params_p[1]))
+    {
+	${$vars}{$var_name} =~ s/(^| )([^\/][^ ]+)/$1..\/$2/g;
+    }
+}
+
+sub cmd_var_append
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: two parameters expected for `@$params_p[0]'"
+	if (@$params_p != 3);
+
+    my $vars = $$state_p{vars};
+    my $var_name = @$params_p[1];
+    my $var_value = @$params_p[2];
+
+#    warning "line $line_num: variable `$var_name' not defined before"
+#	if (! defined $$vars{$var_name});
+
+    ${$vars}{$var_name} .= " $var_value";
+}
+
+sub cmd_var_define
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: two parameters expected for `@$params_p[0]'"
+	if (@$params_p != 3);
+
+    my $vars = $$state_p{vars};
+    my $var_name = @$params_p[1];
+    my $var_value = @$params_p[2];
+
+    ${$vars}{$var_name} = $var_value;
+}
+
+sub cmd_var_undefine
+{
+    my ($line_num, $dir_p, $params_p, $state_p) = @_;
+
+    error "line $line_num: one parameters expected for `@$params_p[0]'"
+	if (@$params_p != 2);
+
+    my $vars = $$state_p{vars};
+    my $var_name = @$params_p[1];
+
+    ${$vars}{$var_name} = undef;
+}
+
+my %mkf_cmd = 
+(
+ "_end_if" => \&cmd_end_if,
+ "_else" => \&cmd_else,
+ "_if_exec_ok" => \&cmd_if_exec_ok,
+ "_if_file_exists" => \&cmd_if_file_exists,
+ "_if_in_path" => \&cmd_if_in_path,
+ "_if_stdout_match" => \&cmd_if_stdout_match,
+ "_if_var_eq" => \&cmd_if_var_eq,
+ "command_add" => \&cmd_command_add,
+ "clean_add" => \&cmd_clean_add,
+ "auto_source_dep" => \&cmd_auto_source_dep,
+ "auto_dep" => \&cmd_auto_dep,
+ "target_dep" => \&cmd_target_dep,
+ "target_dep_add" => \&cmd_target_dep_add,
+ "install_cmd" => \&cmd_install_cmd,
+ "msg_error" => \&cmd_msg_error,
+ "msg_info" => \&cmd_msg_info,
+ "msg_warning" => \&cmd_msg_warning,
+ "mkf_include" => \&cmd_mkf_include,
+ "path_parent" => \&cmd_path_parent,
+ "var_define" => \&cmd_var_define,
+ "var_append" => \&cmd_var_append,
+ "var_undefine" => \&cmd_var_undefine
+);
+
+######################################################
+#	    Main processing functions
+#
+
+sub process_makefile_rule
+{
+    (my $dir_p, my $target, my $state_p, local *MAKEFILE) = @_;
+
+    return if (${$$state_p{done}}{$target});
+    ${$$state_p{done}}{$target} = "1";
+
+    # get dependencies
+    my $deps = ${$$state_p{deps}}{$target};
+    my $target_name = $target;
+
+    # get jobs list
+    my $hash;
+
+    if (-d "$dir_p/$target")
+    {
+	$hash = "enter_dir";
+	$target_name = "_".$target;
+    }
+    else
+    {
+	if (($deps && (@$deps[0] =~ /[^.]*\.(.*)/)) || ($target =~ /(all)/))
+	{ $hash = $1; }
+	else
+	{ $hash = "noext"; }
+	
+	if (($target =~ /[^.]*\.(.*)/) || ($target =~ /(all)/))
+	{ $hash .= "_$1"; }
+	else
+	{ $hash .= "_noext"; }
+    }
+
+    my $job_list = ${$$state_p{jobs}}{$hash};
+    my $rm_list = ${$$state_p{torm}}{$hash};
+
+    if ((!$deps) && (!$job_list))
+    {
+	print MAKEFILE "all:\n\n" if ($target =~ /^all$/);
+	return;
+    }
+
+    # write target
+    print MAKEFILE "$target_name:";
+
+    if ($deps)
+    {
+	foreach (@$deps)
+	{
+	    if (-d "$dir_p/$_")
+	    { print MAKEFILE " _$_"; }
+	    else
+	    { print MAKEFILE " $_"; }
+	}
+    }
+    print MAKEFILE "\n";
+
+    foreach my $job (@$job_list)
+    {
+	my $job_line = $job;
+
+	$job_line = replace_vars($job_line, $$state_p{vars}, "JVAR");
+	$job_line = replace_vars_list($job_line, $$state_p{vars}, "JLIST");
+	$job_line = replace_list($job_line, $deps, "SRC");
+	$job_line = replace($job_line, $target, "OUT");
+
+	$job_line =~ s/[\t\n ]+/ /g;
+
+	print MAKEFILE "\t$job_line\n";
+    }
+    print MAKEFILE "\n";
+
+    push (@{$$state_p{outs}}, $target) if (@$job_list);	# add to out files target list
+
+    foreach my $rm (@$rm_list)
+    {
+	my $rm_line = $rm;
+
+	$rm_line = replace_vars($rm_line, $$state_p{vars}, "JVAR");
+	$rm_line = replace_list($rm_line, $deps, "SRC");
+
+	$target =~ /^([^.]*)/;
+	$rm_line = replace($rm_line, $1, "OUT!");
+
+	push (@{$$state_p{outs}}, $rm_line);
+    }
+
+    if ($deps)
+    {
+	process_makefile_rule ($dir_p, "$_", $state_p) foreach (@$deps);
+    }
+}
+
+sub process_makefile_clean
+{
+    (my $dir_p, my $target, my $state_p, local *MAKEFILE) = @_;
+
+    print MAKEFILE "clean:\n";
+
+    my @files, my @dirs;
+
+    foreach (@{$$state_p{outs}})
+    {
+	if (-d "$dir_p/$_")
+	{ push (@dirs, $_) }
+	else
+	{ push (@files, $_) }
+    }
+
+    foreach my $job (@{${$$state_p{jobs}}{"clean_file"}})
+    {
+	foreach (@files)
+	{
+	    my $job_line = $job;
+	    $job_line = replace($job_line, $_, "FILE");
+
+	    print MAKEFILE "\t$job_line\n";
+	}
+    }
+
+    foreach my $job (@{${$$state_p{jobs}}{"clean_dir"}})
+    {
+	foreach (@dirs)
+	{
+	    my $job_line = $job;
+	    $job_line = replace($job_line, $_, "DIR");
+
+	    print MAKEFILE "\t$job_line\n";
+	}
+    }
+
+    print MAKEFILE "\n";
+    print MAKEFILE "re: clean all\n\n";
+}
+
+sub process_makefile_install
+{
+    (my $dir_p, my $target, my $state_p, local *MAKEFILE) = @_;
+
+    print MAKEFILE "install:\n";
+
+    foreach my $job (@{${$$state_p{jobs}}{"install_dir"}})
+    {
+	foreach (@{$$state_p{outs}})
+	{
+	    next if (! -d "$dir_p/$_");
+
+	    my $job_line = $job;
+	    $job_line = replace($job_line, $_, "DIR");
+
+	    print MAKEFILE "\t$job_line\n";
+	}
+    }
+
+    foreach (@{$$state_p{install}})
+    {
+	    print MAKEFILE "\t$_\n";
+    }
+    print MAKEFILE "\n";
+}
+
+sub process_makefile
+{
+    my ($dir_p, $state_p) = @_;
+
+    open (MAKEFILE, ">$dir_p/Makefile.mkf");
+
+    print MAKEFILE
+	"#\n".
+	"# Makefile generated by MKF configure script\n".
+	"#\n\n";
+
+    process_makefile_rule ($dir_p, "all", $state_p, *MAKEFILE);
+    process_makefile_clean ($dir_p, "clean", $state_p, *MAKEFILE);
+    process_makefile_install ($dir_p, "install", $state_p, *MAKEFILE);
+
+    close (MAKEFILE);
+}
+
+sub process_dir_mkffile
+{
+    (my $dir_p, my $state_p, local *MKF_FILE) = @_;
+
+    # line counter for error repporting
+    my $line_num = 0;
+
+    my $enter_if_depth = $$state_p{if_depth};
+
+    # used to append lines when ended with \
+    my $last = "";
+
+    # parse mkf.info file line at once
+    foreach my $line (<MKF_FILE>)
+    {
+	$line_num++;
+
+	# keep lines and concat lines ending with \
+	if ($line =~ /^(.*)\\$/)
+	{
+	    $last .= $1;
+	    next;
+	}
+
+	# add last line ending with \ if any
+	if ($last)
+	{
+	    $line = $last.$line;
+	    $last = "";
+	}
+
+	# remove leading spaces
+	$line =~ s/^[ \t]*//g;
+
+	# skip empty lines and comment lines
+	next if ($line =~ /^[ \t]*(\#.*)?$/);
+
+	# skip if conditional state is false
+	next if ((not $line =~ /^_/) && (! @{$$state_p{if_bool}}[$$state_p{if_depth}]));
+
+	# replace variables in command line
+	$line = replace_vars($line, $$state_p{vars}, "PVAR");
+	$line = replace($line, $dir_p, "PWD");
+
+	# split fields
+	my @line_l = split(/[\n\t]+/, $line);
+
+	# get pointer on function for command
+	if (my $func_ptr = $mkf_cmd{@line_l[0]})
+	{
+	    # call command function
+	    $func_ptr -> ($line_num, $dir_p, \@line_l, $state_p);
+	}
+	else
+	{
+	    # error if unknow function
+	    error "line $line_num: unknown command `@line_l[0]'";
+	}
+    }
+
+    error "line $line_num: if not closed at end of file"
+	if ($$state_p{if_depth} != $enter_if_depth);
+}
+
+sub process_dir
+{
+    my ($dir_p, %state_p) = @_;
+
+    # add local field to state structure
+    $state_p{deps} = {};		# target/dependencies for current Makefile
+    $state_p{done} = {};		# already done targets
+
+    $state_p{if_bool} = ["1"];		# conditional state stack
+    $state_p{if_depth} = 0;		# conditional state stack index
+    $state_p{outs} = [];		# output files
+    $state_p{install} = [];		# install commands
+
+    # undefine previous local variable
+    foreach (keys(%{$state_p{vars}}))
+    {
+	${$state_p{vars}}{$_} = undef if (/^_/);
+    }
+
+    ${$state_p{vars}}{_dir} = $dir_p;
+
+    print "entering $dir_p\n";
+
+    # open mkf.info file in directory
+    local *MKF_FILE;
+    open (MKF_FILE, "$dir_p/$mkf_file_gc") || error "no $mkf_file_gc file in directory";
+
+    process_dir_mkffile($dir_p, \%state_p, *MKF_FILE);
+
+    foreach my $subdir (keys(%{$state_p{deps}}))
+    {
+	next if (! -d "$dir_p/$subdir");
+
+	my %state = 
+	    (
+	     "vars" => {%{$state_p{vars}}},
+	     "jobs" => {%{$state_p{jobs}}},
+	     "torm" => {%{$state_p{torm}}}
+	     );
+
+	process_dir ("$dir_p/$subdir", %state);
+    }
+
+    # close file
+    close (MKF_FILE);
+
+    process_makefile ("$dir_p", \%state_p);
+}
+
+sub main
+{
+    # param passed to configure script on command line
+    my %param_h;
+
+    # extract variable name and value from parameter
+    foreach my $param (@ARGV)
+    {
+	if ($param =~ /--help/)
+	{
+	    -f "mkf.help" && system("cat mkf.help");
+	    return 0;
+	}
+
+	if ($param =~ /--enable-(.*)/)
+	{
+	    $param_h{$1} = "yes";
+	    next;
+	}
+
+	if ($param =~ /--disable-(.*)/)
+	{
+	    $param_h{$1} = "no";
+	    next;
+	}
+
+	error "bad command line parameter `$param'"
+	    if (! ($param =~ /--(.*)=(.*)/));
+
+	error "command line parameter `--$1' used twice"
+	    if (defined ($param_h{$1}));
+
+	$param_h{$1} = $2;
+    }
+
+    # state structure used during configure process
+    my %state =
+    (
+     "vars" => {%param_h},
+     "jobs" => {},
+     "torm" => {}
+    );
+
+    # process current directory
+    return process_dir (".", %state);
+}
+
+main;
+clear_temp_files;
+print "Done.\n";
+exit 0;
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Configuration_Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Configuration_Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Configuration_Parameters.h	(revision 3)
@@ -0,0 +1,54 @@
+#ifndef morpheo_behavioural_Configuration_Parameters_h
+#define morpheo_behavioural_Configuration_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include <iostream>
+#include "Behavioural/include/XML.h"
+#include "Include/ErrorMorpheo.h"
+#include "Include/ToString.h"
+using namespace std;
+
+namespace morpheo     {
+namespace behavioural {
+
+  class Configuration_Parameters
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Constant
+  public   : const string    _name   ;
+  public   : const uint32_t  _value  ;
+  public   : const uint32_t  _min    ;
+  public   : const uint32_t  _max    ;
+  public   : const string    _step   ;
+  public   : const uint32_t  _default;
+  public   : const uint32_t  _level  ;
+  public   : const string    _comment;
+
+    // -----[ methods ]---------------------------------------------------
+  public   :                 Configuration_Parameters  (string   name   ,
+							uint32_t value  ,
+							uint32_t min    ,
+							uint32_t max    ,
+							string   step   ,
+							uint32_t value_default,
+							uint32_t level  ,
+							string   comment);
+  public   :                 ~Configuration_Parameters ();
+
+    // methods to print and test parameters_configuration
+  public   : string          print                      (uint32_t depth);
+  public   : friend ostream& operator<<                 (ostream& output_stream,
+							 morpheo::behavioural::Configuration_Parameters & x);
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h	(revision 3)
@@ -0,0 +1,22 @@
+#ifndef DEBUG_COMPONENT_H
+#define DEBUG_COMPONENT_H
+
+#define DEBUG_Behavioural                                 false
+
+// Behavioural/Generic/
+#define DEBUG_Counter                                     false 
+#define DEBUG_Group                                       false
+#define DEBUG_Register_File                               false 
+#define DEBUG_Shifter                                     false
+// Behavioural/Generic/Select/
+#define DEBUG_Pseudo_LRU                                  false
+// Behavioural/Stage_1_Ifetch/
+// Behavioural/Stage_1_Ifetch/Predictor/
+// Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/
+#define DEBUG_Two_Level_Branch_Predictor                  false
+// Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/
+#define DEBUG_Two_Level_Branch_Predictor_Glue             false 
+#define DEBUG_Branch_History_Table                        false
+#define DEBUG_Pattern_History_Table                       false
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Environnement.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Environnement.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Environnement.h	(revision 3)
@@ -0,0 +1,7 @@
+#if (defined(STATISTICS) and not defined(SYSTEMC))
+#  error "To have the statistics, you must set flags SYSTEMC"
+#endif
+
+#if (defined(VHDL_TESTBENCH) and not defined(SYSTEMC))
+#  error "To have the vhdl's test bench, you must set flags SYSTEMC"
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h	(revision 3)
@@ -0,0 +1,62 @@
+#ifndef morpheo_behavioural_Parameters_h
+#define morpheo_behavioural_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include <iostream>
+#include <math.h>
+#include "Behavioural/Constant/Constant_OpenRISC.h"
+#include "Behavioural/include/Environnement.h"
+#include "Include/ErrorMorpheo.h"
+#include "Include/ToString.h"
+
+using namespace morpheo::behavioural::constant;
+using namespace std;
+
+namespace morpheo     {
+namespace behavioural {
+
+  // Virtual Class - Interface of each component
+  class Parameters
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Constant
+  public   : const uint32_t _size_condition;
+  public   : const uint32_t _size_instruction;
+  public   : const uint32_t _size_instruction_log2;
+
+    // -----[ methods ]---------------------------------------------------
+  public   :                  Parameters            (void);
+  public   : virtual          ~Parameters           ();
+	
+    // methods to print and test parameters
+  public   : virtual string   print                 (uint32_t depth) = 0;
+  public   : virtual string   msg_error             (void) = 0;
+
+    // methods to generate configuration file
+
+    
+    // methods to test
+  public   :         void     test                  (void);
+  public   :         bool     is_natural            (double  val );
+  public   :         bool     is_positive           (double  val );
+  public   :         bool     is_multiple           (uint32_t val1,
+		 	    	                     uint32_t val2);
+  public   :         bool     is_between_inclusive  (uint32_t val,
+						     uint32_t min,
+						     uint32_t max);
+  public   :         bool     is_between_exclusive  (uint32_t val,
+						     uint32_t min,
+						     uint32_t max);
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters_Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters_Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters_Statistics.h	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_Parameters_Statistics_h
+#define morpheo_behavioural_Parameters_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+
+  class Parameters_Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Constant
+  public   : const uint32_t   _nb_cycle_before_begin; // nb cycle before the begining of statistics
+  public   : const uint32_t   _period_save;           // period between two save
+    
+    // -----[ methods ]---------------------------------------------------
+  public   :                  Parameters_Statistics  (uint32_t   nb_cycle_before_begin,
+						      uint32_t   period_save          );
+  public   :                  ~Parameters_Statistics ();
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Statistics.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Statistics.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Statistics.h	(revision 3)
@@ -0,0 +1,54 @@
+#ifdef STATISTICS
+
+#ifndef morpheo_behavioural_Statistics_h
+#define morpheo_behavioural_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include <iostream>
+#include "Behavioural/include/Parameters_Statistics.h"
+#include "Include/Average.h"
+#include "Include/Percent.h"
+
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+
+  class Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  protected : const string                _name;
+  protected : const Parameters_Statistics _parameters_statistics;
+
+  protected :       uint32_t _nb_statistics;         // nb period ...
+  protected :       uint32_t _period_current;        // nb cycle in current period
+
+    // -----[ methods ]---------------------------------------------------
+  public    :                  Statistics          (string                name                 ,
+						    Parameters_Statistics parameters_statistics);
+  public    : virtual          ~Statistics         ();
+
+  protected : uint32_t         compute_cycle_begin (uint32_t num_statistics);    
+  protected : uint32_t         compute_cycle_end   (uint32_t num_statistics, uint32_t nb_cycle);
+
+  public    : virtual string   print_body          (uint32_t depth) = 0;
+  public    : virtual string   print               (uint32_t depth) = 0;
+  public    : void             generate_file       (string   stat );
+  public    : void             generate_file       (void);
+
+  private   : template <class Counters, class Parameters_Counters> void save        (Counters ** &, Parameters_Counters parameters);
+  protected : template <class Counters, class Parameters_Counters> void test_if_save(Counters ** &, Parameters_Counters parameters);
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h	(revision 3)
@@ -0,0 +1,142 @@
+#ifdef VHDL
+
+#ifndef morpheo_behavioural_Vhdl_h
+#define morpheo_behavioural_Vhdl_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include <iostream>
+#include <list>
+#include "Include/ToString.h"
+#include "Include/Debug.h"
+
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+
+  typedef enum { IN, OUT, INOUT } direction_t;
+
+  string std_logic        (uint32_t size);
+  string std_logic_conv   (uint32_t size, string   value);
+  string std_logic_conv   (uint32_t size, uint32_t value);
+  string std_logic_range  (uint32_t max , uint32_t min  );
+  string std_logic_range  (uint32_t size);
+  string std_logic_others (uint32_t size, uint32_t cst  );
+
+  class Vhdl
+  {
+    // -----[ fields ]----------------------------------------------------
+  private   : const string     _name                         ;
+
+  private   : list<string>     _list_library_work            ;
+  private   : list<string>     _list_signal                  ;
+  private   : list<string>     _list_type                    ;
+  private   : list<string>     _list_alias                   ;
+  private   : list<string>     _list_port                    ;
+  private   : list<string>     _list_body                    ;
+    
+    // -----[ methods ]---------------------------------------------------
+  public    :                  Vhdl                        (string name);
+  public    : virtual          ~Vhdl                       ();
+						           
+  public    : void             generate_file               (void);
+  public    : void             generate_file               (bool generate_package,
+							    bool generate_model  );
+
+  private   : void             generate_file_package       (void);
+  private   : void             generate_file_model         (void);
+  
+  private   : string           get_package                 (uint32_t    depth                 ,
+							    string      filename              ,
+							    string      package_name          ,
+							    string      entity_name           );
+  private   : string           get_model                   (uint32_t    depth                 ,
+							    string      filename              ,
+							    string      entity_name           ,
+							    string      architecture_name     );
+  private   : string           get_header                  (uint32_t    depth                 ,
+							    string      filename              );
+  private   : string           get_entity                  (uint32_t    depth                 ,
+							    string      name                  );
+  private   : string           get_architecture            (uint32_t    depth                 , 
+							    string      name                  ,
+							    string      entity_name           );
+  private   : string           get_component               (uint32_t    depth                 ,
+							    string      name                  );
+
+  private   : string           get_port                    (uint32_t    depth                 );
+  public    : void             set_port                    (string      name                  ,
+							    direction_t direction             ,
+							    string      type                  );
+  public    : void             set_port                    (string      name                  ,
+							    direction_t direction             ,
+							    uint32_t    size                  );
+  private   : string           get_signal                  (uint32_t    depth                 );
+  public    : void             set_signal                  (string      name                  ,
+							    string      type                  );
+  public    : void             set_signal                  (string      name                  ,
+							    uint32_t    signal                );
+  public    : void             set_signal                  (string      name                  ,
+							    string      type                  ,
+							    string      init                  );
+  public    : void             set_signal                  (string      name                  ,
+							    uint32_t    size                  ,
+							    string      init                  );
+  public    : void             set_signal                  (string      name                  ,
+							    uint32_t    size                  ,
+							    uint32_t    init                  );
+  public    : void             set_constant                (string      name                  ,
+							    string      type                  ,
+							    string      init                  );
+  public    : void             set_constant                (string      name                  ,
+							    uint32_t    size                  ,
+							    string      init                  );
+  public    : void             set_constant                (string      name                  ,
+							    uint32_t    size                  ,
+							    uint32_t    init                  );
+
+  private   : string           get_type                    (uint32_t    depth                 );
+  public    : void             set_type                    (string      name                  ,
+							    string      type                  );
+  private   : string           get_alias                   (uint32_t    depth                 );
+  public    : void             set_alias                   (string      name1                 ,
+							    string      type1                 ,
+							    string      name2                 ,
+							    string      range2                );
+
+  public    : string           get_list                    (list<string> liste                ,
+							    uint32_t     depth                ,
+							    string       separator            ,
+							    bool         last_separator       );
+  public    : void             set_list                    (list<string> & liste              ,
+							    string         text               );
+
+  private   : string           get_body                    (uint32_t       depth              );
+  public    : void             set_body                    (string         text               );
+
+  public    : void             set_body_component          (string         name_instance      ,
+							    string         name_component     ,
+							    list<string>   list_port_map      );
+  public    : void             set_body_component_port_map (list<string> & list_port_map      ,
+							    string         name_port          ,
+							    string         name_signal        );
+
+  private   : string           get_library_ieee            (uint32_t    depth                 );
+  private   : string           get_library_work            (uint32_t    depth                 );
+  public    : void             set_library_work            (string      package_name          );
+
+  private   : string           direction_toString          (direction_t direction);
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl_Testbench.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl_Testbench.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl_Testbench.h	(revision 3)
@@ -0,0 +1,97 @@
+#ifdef VHDL_TESTBENCH
+
+#ifndef morpheo_behavioural_Vhdl_Testbench_h
+#define morpheo_behavioural_Vhdl_Testbench_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+#include "Include/ToString.h"
+#include "Include/ToBase2.h"
+#include <stdint.h>
+#include <iostream>
+#include <list>
+
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+
+  class Vhdl_Testbench
+  {
+    class label_t
+    {
+    public : const uint32_t _cycle;
+    public : const string   _label;
+
+      label_t (uint32_t cycle,
+	       string   label) :
+	_cycle (cycle),
+	_label (label)
+      {};
+    };
+
+    // -----[ fields ]----------------------------------------------------
+  private   : const string     _name       ;
+  private   : string           _clock_name ;
+  private   : uint32_t         _num_cycle  ;
+
+  private   : uint32_t         _size_input ;
+  private   : uint32_t         _size_output;
+
+  private   : list<string>     _list_input ;
+  private   : list<string>     _list_input_cycle;
+  private   : list<uint32_t>   _list_input_size ;
+  private   : list<string>     _list_output;
+  private   : list<string>     _list_output_cycle;
+  private   : list<uint32_t>   _list_output_size ;
+  private   : list<bool>       _list_test;
+  private   : list<string>     _list_port;
+  private   : list<label_t>    _list_label;
+
+  private   : list<uint32_t>::iterator   _num_input ;
+  private   : list<uint32_t>::iterator   _num_output;
+
+  private   : Vhdl           * _vhdl;
+    
+    // -----[ methods ]---------------------------------------------------
+  public    :                  Vhdl_Testbench              (string   name);
+  public    : virtual          ~Vhdl_Testbench             ();
+						           
+  public    : void             generate_file               (void);
+
+  public    : void             set_port                    (string      name      ,
+							    direction_t direction ,
+							    uint32_t    size      );
+  public    : void             set_clock                   (string      name      ,
+							    bool        model_have_clock);
+  public    : void             new_cycle                   (void);
+
+  private   : uint32_t         get_input                   (void);
+  private   : void             set_input                   (void);
+  public    : void             add_input                   (uint32_t    value     );
+
+  private   : uint32_t         get_output                  (void);
+  private   : void             set_output                  (void);
+  public    : void             add_output                  (uint32_t    value     );
+
+  private   : uint32_t         get_test                    (void);
+  public    : void             add_test                    (bool        must_test );
+
+  private   : void             get_label                   (void);
+  public    : void             add_label                   (string      label     );
+
+  private   : void             generate_process_clock      (uint32_t    counter   );
+  private   : void             generate_instance           (void);
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XML.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XML.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XML.h	(revision 3)
@@ -0,0 +1,60 @@
+#ifndef morpheo_behavioural_XML_h
+#define morpheo_behavioural_XML_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include <iostream>
+#include <math.h>
+#include <list>
+#include "Include/ToString.h"
+
+using namespace std;
+
+namespace morpheo     {
+namespace behavioural {
+
+  // Virtual Class - Interface of each component
+  class XML
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const string     _name            ;
+  private  : string           _body            ;
+  private  : list<string>     _list_balise_name;
+
+    // -----[ methods ]---------------------------------------------------
+  public   :                  XML                 (string name);
+  public   :                  ~XML                (void);
+	
+  public   : bool             balise_open         (string name); // no attribut
+  public   : bool             balise_open_begin   (string name);
+  public   : bool             balise_open_end     (void);      
+  public   : bool             balise_close        (void);      
+  public   : bool             singleton           (string name); // no attribut
+  public   : bool             singleton_begin     (string name);
+  public   : bool             singleton_end       (void);
+  public   : bool             attribut            (string name, string value);
+
+  public   : void             generate_file       (void);
+  public   : void             generate_file       (string encoding);
+  public   : string           get_body            (void);
+  public   : string           get_body            (uint32_t depth);
+
+  public   : bool             comment             (string text);
+  public   : bool             text                (string text);
+					          
+  private  : string           indent              (uint32_t depth );
+  private  : string           indent              (void);
+  private  : uint32_t         depth               (void);
+					          
+  private  : void             header              (string encoding);
+  };
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_as.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_as.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_as.info	(revision 3)
@@ -0,0 +1,37 @@
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+_if_var_eq		cmd_as
+ var_define		cmd_as	as
+_end_if
+
+_if_in_path		{PVAR,cmd_as}
+
+ msg_info		GNU as ({PVAR,cmd_as}) found
+ var_define		use_as	as
+
+ _if_var_eq		mkf_pretty_print	yes
+  command_add		s	o	echo "   AS               {SRC,.*\.s} -> {OUT}"
+ _end_if
+ command_add		s	o	{JVAR,cmd_as} -o {OUT} {JVAR,opt_as} {SRC,.*\.s}
+
+_else
+
+  msg_error		can't find as tool
+_end_if
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_bison.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_bison.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_bison.info	(revision 3)
@@ -0,0 +1,42 @@
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+_if_var_eq		cmd_bison
+ var_define		cmd_bison	bison
+_end_if
+
+_if_in_path		{PVAR,cmd_bison}
+
+ msg_info		GNU bison ({PVAR,cmd_bison}) found
+ var_define		use_bison	bison
+
+ _if_var_eq		mkf_pretty_print	yes
+  command_add		y	c	echo "   BISON            {SRC,.*\.y} -> {OUT}"
+ _end_if
+ command_add		y	c	{JVAR,cmd_bison} -o {OUT} -d {JVAR,opt_bison} {SRC,.*\.y}
+
+ _if_var_eq		mkf_pretty_print	yes
+  command_add		yy	cc	echo "   BISON            {SRC,.*\.yy} -> {OUT}"
+ _end_if
+ command_add		yy	cc	{JVAR,cmd_bison} -o {OUT} -d {JVAR,opt_bison} {SRC,.*\.yy}
+
+_else
+
+  msg_error		can't find bison tool
+_end_if
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_cc.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_cc.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_cc.info	(revision 3)
@@ -0,0 +1,114 @@
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+# look for available c complier if none was specified on the command line
+
+_if_var_eq		cmd_c_compiler
+ _if_in_path		gcc
+  var_define		cmd_c_compiler		gcc
+ _else
+  var_define		cmd_c_compiler		cc
+ _end_if
+_end_if
+
+_if_var_eq		use_c_compiler
+
+ _if_in_path		{PVAR,cmd_c_compiler}
+
+  _if_stdout_match	gcc		{PVAR,cmd_c_compiler} -v
+   msg_info		GNU C compiler ({PVAR,cmd_c_compiler}) found
+   var_define		use_c_compiler	gcc
+
+   var_append		opt_c_compiler	-Wall -Wshadow -Wpointer-arith -Winline -pipe
+   var_append		opt_c_compiler	-Wwrite-strings -Waggregate-return
+   var_append		opt_c_compiler	-Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations
+
+   _if_var_eq		debug		yes
+    var_append		opt_c_compiler	-g -DDEBUG -fno-inline -gstabs
+   _else
+    var_append		opt_c_compiler	-O3
+    var_append		opt_c_compiler	-fomit-frame-pointer
+    var_append		opt_c_compiler	-march=athlon -mcpu=athlon
+   _end_if
+
+  _else
+
+   _if_stdout_match	Intel		{PVAR,cmd_c_compiler} -V
+    msg_info		Intel C compiler ({PVAR,cmd_c_compiler}) found
+    var_define		use_c_compiler	intel
+
+    var_append	opt_c_compiler	-axiM -tpp6
+
+    _if_var_eq	debug		yes
+     var_append	opt_c_compiler	-g
+    _else
+     var_append	opt_c_compiler	-O3
+    _end_if
+
+   _else
+
+    _if_stdout_match	Sun|Solaris	{PVAR,cmd_c_compiler} -V
+     msg_info		Sun C compiler ({PVAR,cmd_c_compiler}) found
+     var_define		use_c_compiler	sun
+
+     _if_var_eq	debug		yes
+      var_append	opt_c_compiler	-g
+     _else
+      var_append	opt_c_compiler	-xO3
+     _end_if
+
+    _else
+
+     msg_info		native C compiler ({PVAR,cmd_c_compiler}) found
+     var_define		use_c_compiler	cc
+    _end_if
+   _end_if
+  _end_if
+
+ _else
+  msg_error		invalid or no c complier specified
+ _end_if
+_end_if
+
+_if_stdout_match	x86_64		uname -m
+ msg_info		using -fPIC for compilation
+ var_append		cmd_c_compiler	-fPIC
+_end_if
+
+_if_var_eq		mkf_pretty_print	yes
+ command_add		c	o	echo "   CC               {SRC,.*\.c} -> {OUT}"
+_end_if
+command_add		c	o	{PVAR,cmd_c_compiler} -c {JVAR,opt_c_compiler} \
+					-o {OUT} -I. {JLIST,-I,inc_dirs} {SRC,.*\.c}
+
+_if_var_eq		mkf_pretty_print	yes
+ command_add		S	o	echo "   CC (.S file)     {SRC,.*\.c} -> {OUT}"
+_end_if
+command_add		S	o	{PVAR,cmd_c_compiler} -c {JVAR,opt_c_compiler} \
+					-o {OUT} -I. {JLIST,-I,inc_dirs} {SRC,.*\.S}
+
+# check c compiler is working
+
+_if_exec_ok		echo 'int main() { return (0);}' > {TEMP,1,.c} ; {PVAR,cmd_c_compiler} \
+                        -o {TEMP,2,.bin} {TEMP,1,.c} && test -x {TEMP,2,.bin}
+
+  msg_info		C compiler is working
+_else
+  msg_warning		C compiler failed to create executable file
+_end_if
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_doc.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_doc.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_doc.info	(revision 3)
@@ -0,0 +1,72 @@
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+_if_var_eq		cmd_pdflatex
+ var_define		cmd_pdflatex	pdflatex
+_end_if
+
+_if_in_path		{PVAR,cmd_pdflatex}
+
+ msg_info		pdflatex ({PVAR,cmd_pdflatex}) found
+ var_define		use_pdflatex	pdflatex
+
+ _if_var_eq		mkf_pretty_print	yes
+  command_add		tex	pdf	echo "   LATEX (pdf)      {SRC,.*\.c} -> {OUT}"
+ _end_if
+ command_add		tex	pdf	{PVAR,cmd_pdflatex} {JVAR,opt_pdflatex} {SRC,.*\.tex}
+
+_else
+  msg_error		can't find pdflatex
+_end_if
+
+_if_var_eq		cmd_dia
+ var_define		cmd_dia		dia
+_end_if
+
+_if_in_path		{PVAR,cmd_dia}
+
+ msg_info		dia ({PVAR,cmd_dia}) found
+ var_define		use_dia		dia
+
+ _if_var_eq		mkf_pretty_print	yes
+  command_add		dia	eps	echo "   DIA (to eps)     {SRC,.*\.dia} -> {OUT}"
+ _end_if
+ command_add		dia	eps	dia -n -t eps {SRC,.*\.dia} >& /dev/null
+
+_else
+  msg_error		can't find dia
+_end_if
+
+_if_var_eq		cmd_epstopdf
+ var_define		cmd_epstopdf	epstopdf
+_end_if
+
+_if_in_path		{PVAR,cmd_epstopdf}
+
+ msg_info		epstopdf ({PVAR,cmd_epstopdf}) found
+ var_define		use_epstopdf	epstopdf
+
+ command_add		eps	pdf	epstopdf {SRC,.*\.eps} --outfile={OUT} >& /dev/null
+ _if_var_eq		mkf_pretty_print	yes
+  command_add		eps	pdf	echo "   EPSTOPDF         {SRC,.*\.eps} -> {OUT}"
+ _end_if
+
+_else
+  msg_error		can't find epstopdf
+_end_if
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_flex.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_flex.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_flex.info	(revision 3)
@@ -0,0 +1,41 @@
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+_if_var_eq		cmd_flex
+ var_define		cmd_flex	flex
+_end_if
+
+_if_in_path		{PVAR,cmd_flex}
+
+ msg_info		GNU flex ({PVAR,cmd_flex}) found
+ var_define		use_flex	flex
+
+ _if_var_eq		mkf_pretty_print	yes
+  command_add		l	c	echo "   FLEX             {SRC,.*\.l} -> {OUT}"
+ _end_if
+ command_add		l	c	{JVAR,cmd_flex} -o {OUT} --header-file={OUT}.h {JVAR,opt_flex} {SRC,.*\.l}
+
+ _if_var_eq		mkf_pretty_print	yes
+  command_add		ll	cc	echo "   FLEX             {SRC,.*\.ll} -> {OUT}"
+ _end_if
+ command_add		ll	cc	{JVAR,cmd_flex} -o {OUT} --header-file={OUT}.hh {JVAR,opt_flex} {SRC,.*\.ll}
+
+_else
+  msg_error		can't find flex tool
+_end_if
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_linker.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_linker.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_linker.info	(revision 3)
@@ -0,0 +1,89 @@
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+# static lib archiver invocation
+_if_var_eq		cmd_linker
+ var_define		cmd_linker	ld
+_end_if
+
+_if_var_eq		use_linker
+
+ _if_in_path		{PVAR,cmd_linker}
+
+  _if_stdout_match	GNU	{PVAR,cmd_linker} -V
+   msg_info		GNU linker found ({PVAR,cmd_linker})
+   var_define		use_linker	gnu
+  _else
+
+   _if_stdout_match	Solaris	{PVAR,cmd_linker} -V
+    msg_info		Solaris linker found ({PVAR,cmd_linker})
+    var_define		use_linker	solaris
+   _else
+
+    msg_info		unknown linker found ({PVAR,cmd_linker})
+    var_define		use_linker	ld
+   _end_if
+  _end_if
+
+ _else
+  msg_error		no linker found
+ _end_if
+
+_end_if
+
+# object merge link
+
+_if_var_eq		mkf_pretty_print	yes
+ command_add		o	o	@echo "   LD (partial .o)   {OUT}"
+_end_if
+command_add		o	o	{PVAR,cmd_linker} -r {JVAR,opt_o_linker} -o {OUT} {SRC,.*\.o}
+
+# dynamic lib linker invocation
+_if_var_eq		use_linker	solaris
+ msg_info		using ld -G for dynamic library generation
+ var_append		opt_so_linker	-G
+_else
+ msg_info		using ld -shared for dynamic library generation
+ var_append		opt_so_linker	-shared
+_end_if
+
+_if_var_eq		static		yes
+ var_append		opt_exe_linker	-static
+_end_if
+
+_if_var_eq		mkf_pretty_print	yes
+ command_add		o	so	@echo "   LD (shared .so)   {OUT}"
+_end_if
+command_add		o	so	{PVAR,cmd_linker} {JVAR,opt_so_linker} -o {OUT} {SRC,.*\.o} {JLIST,-l,_libs} {JLIST,-l,libs}
+
+_if_var_eq		mkf_pretty_print	yes
+ command_add		o	noext	@echo "   CC (exe linking)  {OUT}"
+_end_if
+command_add		o	noext	{JVAR,cmd_c_compiler} {JVAR,opt_exe_linker} \
+					-o {OUT} {SRC,.*\.o} {JLIST,-L,lib_dirs} {JLIST,-l,_libs} {JLIST,-l,libs}
+
+_if_var_eq		mkf_pretty_print	yes
+ command_add		o	a	@echo "   AR                {OUT}"
+_end_if
+command_add		o	a	ar -rc {OUT} {SRC,.*\.o}
+
+_if_var_eq		mkf_pretty_print	yes
+ command_add		o	a	@echo "   RANLIB            {OUT}"
+_end_if
+command_add		o	a	ranlib {OUT}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_make.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_make.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_make.info	(revision 3)
@@ -0,0 +1,73 @@
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+# make invocation
+
+_if_var_eq		cmd_make
+ _if_in_path		gmake
+  var_define		cmd_make	gmake
+ _else
+  var_define		cmd_make	make
+ _end_if
+_end_if
+
+_if_in_path		{PVAR,cmd_make}
+ _if_stdout_match	GNU		{PVAR,cmd_make} -v -f /dev/null
+
+  msg_info		GNU make ({PVAR,cmd_make}) found
+
+  _if_var_eq		mkf_pretty_print	yes
+   command_add	enter	dir	@echo " * MAKE              {PWD}/{OUT}"
+   command_add	enter	dir	@{PVAR,cmd_make} -s all -C {OUT}
+   command_add	enter	dir	@echo "   MAKE (leave)      {OUT}"
+  _else
+   command_add	enter	dir	{PVAR,cmd_make} all -C {OUT}
+  _end_if
+
+  _if_var_eq		mkf_pretty_print	yes
+   command_add	clean	dir	@echo " * MAKE (clean)      {PWD}/{DIR}"
+   command_add	clean	dir	@{PVAR,cmd_make} -s clean -C {DIR}
+   command_add	clean	dir	@echo "   MAKE (leaving)    {DIR}"
+  _else
+   command_add	clean	dir	{PVAR,cmd_make} clean -C {DIR}
+  _end_if
+
+  _if_var_eq		mkf_pretty_print	yes
+   command_add	install	dir	@echo " * MAKE (install)    {PWD}/{DIR}"
+   command_add	install	dir	@{PVAR,cmd_make} -s install -C {DIR}
+   command_add	install	dir	@echo "   MAKE (leave)      {DIR}"
+  _else
+   command_add	install	dir	{PVAR,cmd_make} install -C {DIR}
+  _end_if
+
+ _else
+
+  msg_info		native make ({PVAR,cmd_make}) found
+  command_add	enter	dir	(cd {OUT} ; {PVAR,cmd_make} all)
+  command_add	clean	dir	(cd {DIR} ; {PVAR,cmd_make} clean)
+  command_add	install	dir	(cd {DIR} ; {PVAR,cmd_make} install)
+
+ _end_if
+_else
+
+  msg_error		invalid or no make tool specified
+
+_end_if
+
+command_add	clean	file	rm -f {FILE}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_prefix.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_prefix.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_prefix.info	(revision 3)
@@ -0,0 +1,41 @@
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+_if_var_eq		prefix
+ var_define		prefix		/usr
+_else
+ var_append		opt_c_compiler		-DPREFIX=\"{PVAR,prefix}\"
+ var_append		opt_c++_compiler	-DPREFIX=\"{PVAR,prefix}\"
+_end_if
+
+_if_file_exists		{PVAR,prefix}
+ msg_info		using {PVAR,prefix} as target directory prefix
+_else
+ msg_error		can't find {PVAR,prefix} prefix directory
+_end_if
+
+_if_var_eq		install_dir
+ var_define		install_dir	{PVAR,prefix}
+_end_if
+
+_if_exec_ok		mkdir -p {PVAR,install_dir}
+ msg_info		using {PVAR,install_dir} as install directory
+_else
+ msg_error		can't create {PVAR,install_dir} install directory
+_end_if
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_xilinx_ise.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_xilinx_ise.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include_mkf/mkf_xilinx_ise.info	(revision 3)
@@ -0,0 +1,187 @@
+#    This file is part of MKF.
+#
+#    MKF is free software; you can redistribute it and/or modify
+#    it under the terms of the GNU General Public License as published by
+#    the Free Software Foundation; either version 2 of the License, or
+#    (at your option) any later version.
+#
+#    MKF is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU General Public License for more details.
+#
+#    You should have received a copy of the GNU General Public License
+#    along with MKF; if not, write to the Free Software
+#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>
+
+# used for rm -r with clean rules
+var_define		xilinx_rm_r	-r 
+
+var_define		vhdl_m4_defines	XILINX
+
+# Xilinx xst sythesis tool
+# (HDL language) .vhdl	->	(netlist) .ngc
+# (HDL language) .prj	->	(netlist) .ngc
+
+_if_var_eq		xilinx_target	
+  msg_warning		xilinx_target device not defined
+_end_if
+
+_if_var_eq		cmd_xilinx_xst
+ var_define		cmd_xilinx_xst		xst
+_end_if
+
+_if_in_path		{PVAR,cmd_xilinx_xst}
+
+ msg_info		Xilinx synthesis tool ({PVAR,cmd_xilinx_xst}) found
+ var_define		use_xilinx_xst		xst
+
+ command_add		vhdl	ngc	echo run -keep_hierarchy yes -iobuf no -ifn {SRC,.*\.vhdl} -ofn {OUT} \
+                                        -p {JVAR,xilinx_target} {JVAR,opt_xst} \
+                                        -ifmt VHDL | {JVAR,cmd_xilinx_xst}
+
+ command_add		prj	ngc	echo run -keep_hierarchy yes -iobuf no -top {SRC!,.*\.prj} \
+                                        -ifn {SRC,.*\.prj} -ofn {OUT} \
+                                        -p {JVAR,xilinx_target} {JVAR,opt_xst} \
+                                        -ifmt mixed | {JVAR,cmd_xilinx_xst}
+
+#                                        -uc {SRC!,.*\.prj}.xcf 
+
+ clean_add		prj	ngc	{OUT!}.lso {JVAR,xilinx_rm_r}xst
+
+ command_add		vhdl	prj	for i in {SRC,.*\.vhdl} ; do echo "vhdl work $$i" ; done > {OUT}
+
+ command_add		vhdl.m4	vhdl	m4 -P {JLIST,-D,vhdl_m4_defines} {JLIST,-I,inc_dirs} {SRC,.*\.vhdl.m4} > {OUT}
+
+_else
+  msg_error		can't find Xilinx xst tool
+_end_if
+
+# Xilinx ngdbuild
+# (netlist) .ngc	->	(design database) .ngd
+
+_if_var_eq		cmd_xilinx_ngdbuild
+ var_define		cmd_xilinx_ngdbuild		ngdbuild
+_end_if
+
+_if_in_path		{PVAR,cmd_xilinx_ngdbuild}
+
+ msg_info		Xilinx ngdbuild tool ({PVAR,cmd_xilinx_ngdbuild}) found
+ var_define		use_xilinx_ngdbuild		ngdbuild
+
+ command_add		ngc	ngd	{JVAR,cmd_xilinx_ngdbuild} {SRC,system.ngc} \
+                                        {SRC,.*\.ucf,-uc } {SRC,.*\.bmm,-bm } \
+                                        -p {JVAR,xilinx_target} {JVAR,opt_ngdbuild} {OUT}
+
+ clean_add		ngc	ngd	{OUT!}.bld netlist.lst
+
+_else
+  msg_error		can't find Xilinx ngdbuild tool
+_end_if
+
+# Xilinx ngcbuild
+# (netlist) .ngc	->	(netlist) .ngc
+
+_if_var_eq		cmd_xilinx_ngcbuild
+ var_define		cmd_xilinx_ngcbuild		ngcbuild
+_end_if
+
+_if_in_path		{PVAR,cmd_xilinx_ngcbuild}
+
+ msg_info		Xilinx ngcbuild tool ({PVAR,cmd_xilinx_ngcbuild}) found
+ var_define		use_xilinx_ngcbuild		ngcbuild
+
+ command_add		ngc	ngc	{JVAR,cmd_xilinx_ngcbuild} {SRC,.*\.ngc} {SRC,.*\.ucf,-uc } \
+                                        -p {JVAR,xilinx_target} {JVAR,opt_ngcbuild} {OUT}
+
+ clean_add		ngc	ngc	{OUT!}.blc
+
+_else
+  msg_error		can't find Xilinx ngcbuild tool
+_end_if
+
+# Xilinx map
+# (netlist) .ngd	->	(physical design) .ncd
+
+_if_var_eq		cmd_xilinx_map
+ var_define		cmd_xilinx_map		map
+_end_if
+
+_if_in_path		{PVAR,cmd_xilinx_map}
+
+ msg_info		Xilinx map tool ({PVAR,cmd_xilinx_map}) found
+ var_define		use_xilinx_map		map
+
+ command_add		ngd	ncd	{JVAR,cmd_xilinx_map} -u {SRC,.*\.ngd} -o {OUT} \
+                                        -p {JVAR,xilinx_target} {JVAR,opt_map}
+
+ clean_add		ngd	ncd	{SRC!,.*\.ngd}.mrp {SRC!,.*\.ngd}.ngm netlist.lst
+
+_else
+  msg_error		can't find Xilinx map tool
+_end_if
+
+# Xilinx par (place & route)
+# (physical design) .ncd	->	(physical design) .ncd
+
+_if_var_eq		cmd_xilinx_par
+ var_define		cmd_xilinx_par		par
+_end_if
+
+_if_in_path		{PVAR,cmd_xilinx_par}
+
+ msg_info		Xilinx place and route tool ({PVAR,cmd_xilinx_par}) found
+ var_define		use_xilinx_par		par
+
+ command_add		ncd	par.ncd	{JVAR,cmd_xilinx_par} -w {JVAR,opt_par} \
+                                        {SRC,.*\.ncd} {OUT} {SRC,.*\.pcf}
+
+ clean_add		ncd	par.ncd	{SRC!,.*\.ncd}.par* 
+
+_else
+  msg_error		can't find Xilinx par tool
+_end_if
+
+# Xilinx bitstream gen
+# (physical design) .ncd	->	(physical design) .bit
+
+_if_var_eq		cmd_xilinx_bitgen
+ var_define		cmd_xilinx_bitgen		bitgen
+_end_if
+
+_if_in_path		{PVAR,cmd_xilinx_bitgen}
+
+ msg_info		Xilinx bitstream generation tool ({PVAR,cmd_xilinx_bitgen}) found
+ var_define		use_xilinx_bitgen		bitgen
+
+ command_add		par.ncd	bit	{JVAR,cmd_xilinx_bitgen} -w {JVAR,opt_bitgen} \
+                                        {SRC,.*\.ncd} {OUT} {SRC,.*\.pcf}
+
+ clean_add		par.ncd	bit	{SRC!,.*\.ncd}.bgn {SRC!,.*\.ncd}.par* {SRC!,.*\.ncd}.drc
+
+_else
+  msg_error		can't find Xilinx bitgen tool
+_end_if
+
+# Xilinx data2mem
+# (physical design) .bit	->	(physical design) .bit
+
+_if_var_eq		cmd_xilinx_data2mem
+ var_define		cmd_xilinx_data2mem		data2mem
+_end_if
+
+_if_in_path		{PVAR,cmd_xilinx_data2mem}
+
+ msg_info		Xilinx memory update tool ({PVAR,cmd_xilinx_data2mem}) found
+ var_define		use_xilinx_data2mem		data2mem
+
+ command_add		bit	bit	{JVAR,cmd_xilinx_data2mem} -bm {SRC!,*\.bit}_bd.bmm \
+                                        -bt {SRC,*\.bit} -bd {SRC,*\.elf} -o b {OUT} \
+                                        {JVAR,opt_data2mem}
+
+_else
+  msg_error		can't find Xilinx data2mem tool
+_end_if
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info	(revision 3)
@@ -0,0 +1,48 @@
+#
+# Project main mkf file
+#
+
+var_define		xilinx_target	xc5vlx330t-2ff1738
+#xc5vlx330t-2ff1738
+#xc2vp30ff896-6
+
+# default include directory
+
+# use pretty printed Makefile
+_if_var_eq		mkf_pretty_print
+ var_define		mkf_pretty_print	no
+_end_if
+
+# build src directory content
+target_dep		all		Generic/Counter/SelfTest
+target_dep		all		Generic/RegisterFile/SelfTest
+target_dep		all		Generic/Shifter/SelfTest
+target_dep		all		Generic/Select/Pseudo_LRU/SelfTest
+target_dep		all		Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest
+target_dep		all		Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest
+target_dep		all		Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest
+target_dep		all		Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest
+
+# mkf include path
+var_define		_mkf_path	include_mkf
+
+# mkf included scripts
+
+#mkf_include		{PVAR,_mkf_path}/mkf_prefix.info
+mkf_include		{PVAR,_mkf_path}/mkf_make.info
+#mkf_include		{PVAR,_mkf_path}/mkf_cc.info
+#mkf_include		{PVAR,_mkf_path}/mkf_linker.info
+mkf_include		{PVAR,_mkf_path}/mkf_xilinx_ise.info
+#mkf_include		{PVAR,_mkf_path}/mkf_++.info
+#mkf_include		{PVAR,_mkf_path}/mkf_as.info
+#mkf_include		{PVAR,_mkf_path}/mkf_flex.info
+#mkf_include		{PVAR,_mkf_path}/mkf_bison.info
+
+# build documentation
+
+#_if_var_eq		doc	yes
+# mkf_include		{PVAR,_mkf_path}/mkf_doc.info
+# target_dep_add	all	doc
+#_end_if
+
+
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters.cpp	(revision 3)
@@ -0,0 +1,41 @@
+#ifdef CONFIGURATION
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Configuration_Parameters.h"
+
+namespace morpheo              {
+namespace behavioural          {
+    
+  Configuration_Parameters::Configuration_Parameters  (string   name   ,
+						       uint32_t value  ,
+						       uint32_t min    ,
+						       uint32_t max    ,
+						       string   step   ,
+						       uint32_t value_default,
+						       uint32_t level  ,
+						       string   comment):
+    _name    (name         ),
+    _value   (value        ),
+    _min     (min          ),
+    _max     (max          ),
+    _step    (step         ),
+    _default (value_default),
+    _level   (level        ),
+    _comment (comment      )
+  {
+    if ((value<min) or (value>max))
+      throw (ErrorMorpheo ("Parameters \""+name+"\" is out of bound : "+toString(value)+" not include in ["+toString(min)+":"+toString(max)+"]"));
+  };
+    
+  Configuration_Parameters::~Configuration_Parameters () 
+  {
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters_print.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters_print.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters_print.cpp	(revision 3)
@@ -0,0 +1,44 @@
+#ifdef CONFIGURATION
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Configuration_Parameters.h"
+
+
+namespace morpheo              {
+namespace behavioural          {
+
+  string Configuration_Parameters::print (uint32_t depth)
+  {
+    XML * xml = new XML (_name);
+    
+    xml->balise_open_begin("generic");
+    xml->  attribut("name"   ,         _name  );
+    xml->  attribut("value"  ,toString(_value));
+    xml->  attribut("min"    ,toString(_min  ));
+    xml->  attribut("max"    ,toString(_max  ));
+    xml->  attribut("step"   ,         _step  );
+    xml->  attribut("default",toString(_value));
+    xml->  attribut("level"  ,toString(_level));
+    xml->balise_open_end  ();
+    xml->  text  (_comment);
+    xml->balise_close();
+    
+    return xml->get_body(depth);
+  };
+  
+  ostream& operator<< (ostream& output_stream,
+		       morpheo::behavioural::Configuration_Parameters & x)
+  {
+    output_stream << x.print(0);
+
+    return output_stream;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters.cpp	(revision 3)
@@ -0,0 +1,25 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Parameters.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  Parameters::Parameters  (void) :
+    _size_condition        ( 3),
+    _size_instruction      (32) ,
+    _size_instruction_log2 (static_cast<uint32_t>(ceil(log2(_size_instruction))))
+  {
+  };
+
+  Parameters::~Parameters () 
+  {
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_Statistics.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Parameters_Statistics.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+
+  Parameters_Statistics::Parameters_Statistics  (uint32_t   nb_cycle_before_begin,
+						 uint32_t   period_save          ):
+    _nb_cycle_before_begin (nb_cycle_before_begin),
+    _period_save           (period_save          )
+  {};
+
+  Parameters_Statistics::~Parameters_Statistics () 
+  {};
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_is_xxx.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_is_xxx.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_is_xxx.cpp	(revision 3)
@@ -0,0 +1,26 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Parameters.h"
+
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool Parameters::is_natural            (double  val )  { return ( (val >= 0) && (floor(val) == ceil(val)));};
+  bool Parameters::is_positive           (double  val )  { return ( (val >= 1) && (floor(val) == ceil(val)));};
+  bool Parameters::is_multiple           (uint32_t val1,
+					  uint32_t val2) { return is_positive((1.0*val1)/(1.0*val2));};
+  bool Parameters::is_between_inclusive  (uint32_t val,
+					  uint32_t min,
+					  uint32_t max)  { return ((val >= min) && (val <= max));};
+  bool Parameters::is_between_exclusive  (uint32_t val,
+					  uint32_t min,
+					  uint32_t max)  { return ((val >  min) && (val <  max));};
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_test.cpp	(revision 3)
@@ -0,0 +1,23 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Parameters.h"
+
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void Parameters::test (void)          
+  {
+    string msg = msg_error();
+    
+    if (msg.length() != 0)
+      throw (ErrorMorpheo (msg));
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics.cpp	(revision 3)
@@ -0,0 +1,32 @@
+#ifdef STATISTICS
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Statistics.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  Statistics::Statistics  (string                name                 ,
+			   Parameters_Statistics parameters_statistics):
+    _name                  (name                 ),
+    _parameters_statistics (parameters_statistics)
+  {
+    _nb_statistics  = 0;
+    _period_current = 0;
+  };
+  
+  Statistics::~Statistics ()
+  {
+  };
+  
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_compute_cycle_xxx.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_compute_cycle_xxx.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_compute_cycle_xxx.cpp	(revision 3)
@@ -0,0 +1,31 @@
+#ifdef STATISTICS
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Statistics.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  uint32_t Statistics::compute_cycle_begin (uint32_t num_statistics)
+  {
+    return _parameters_statistics._nb_cycle_before_begin + num_statistics*_parameters_statistics._period_save;
+  };
+
+  uint32_t Statistics::compute_cycle_end   (uint32_t num_statistics, uint32_t nb_cycle)
+  {
+    if (num_statistics == (_nb_statistics-1)) // Last ?
+      return compute_cycle_begin(num_statistics  ) + nb_cycle;
+    else
+      return compute_cycle_begin(num_statistics+1) - 1;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_generate_file.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_generate_file.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_generate_file.cpp	(revision 3)
@@ -0,0 +1,53 @@
+#ifdef STATISTICS
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Statistics.h"
+#include <time.h>
+#include <sstream>
+#include <fstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void Statistics::generate_file(string stat)
+  {
+    ostringstream filename;
+    filename << _name << ".stat";
+
+    cout << "Generate file \""<< filename.str() << "\"" << endl;
+
+    ofstream file;
+    file.open(filename.str().c_str(),ios::out | ios::trunc);
+
+    time_t current_time;
+    time (&current_time);
+
+    // print header
+    file << "<!-- "                                                    << endl
+	 << "\tfile        : " << filename.str()                       << endl
+	 << "\tdate        : " << ctime (&current_time )
+	 << "\tcomment     : it's a autogenerated file : don't modify" << endl
+	 << "-->"                                                      << endl
+	 <<                                                               endl;
+	 
+    file << stat;
+    
+    file.close();
+  }
+
+  void Statistics::generate_file(void)
+  {
+    generate_file(print(0));
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_save.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_save.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_save.cpp	(revision 3)
@@ -0,0 +1,43 @@
+#ifdef STATISTICS
+
+#ifndef morpheo_behavioural_Statistics_save_cpp
+#define morpheo_behavioural_Statistics_save_cpp
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Statistics.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  template <class Counters, class Parameters_Counters>
+  void Statistics::save(Counters ** & counters, Parameters_Counters parameters)
+  {
+    // Allocation of a new slot -> take param a first count
+    Counters ** counters_tmp;
+    
+    counters_tmp = new Counters * [_nb_statistics+1];
+    
+    // Copy
+    for (uint32_t i = 0; i < _nb_statistics; i ++)
+      counters_tmp [i] = counters [i];
+    
+    // New slot !
+    counters_tmp [_nb_statistics] = new Counters (parameters);
+    
+    // update pointer
+    counters = counters_tmp;
+    _nb_statistics ++;
+  };
+
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_test_if_save.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_test_if_save.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Statistics_test_if_save.cpp	(revision 3)
@@ -0,0 +1,36 @@
+#ifdef STATISTICS
+
+#ifndef morpheo_behavioural_Statistics_test_if_save_cpp
+#define morpheo_behavioural_Statistics_test_if_save_cpp
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Statistics.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  template <class Counters, class Parameters_Counters>
+  void Statistics::test_if_save(Counters ** & counters, Parameters_Counters parameters)
+  {
+    _period_current ++;
+
+    // Test if allors a new counters ...
+    if ( ((_nb_statistics == 0) && (_period_current >= _parameters_statistics._nb_cycle_before_begin)) ||
+	 ((_nb_statistics >  0) && (_period_current >= _parameters_statistics._period_save          )) )
+      {
+	save<Counters,Parameters_Counters>(counters,parameters);
+	_period_current = 0;
+      }
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl.cpp	(revision 3)
@@ -0,0 +1,28 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  Vhdl::Vhdl  (string                name):
+    _name   (name)
+  {
+  };
+  
+  Vhdl::~Vhdl ()
+  {
+  };
+  
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench.cpp	(revision 3)
@@ -0,0 +1,34 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  Vhdl_Testbench::Vhdl_Testbench  (string   name       ):
+    _name        (name       )
+  {
+    _vhdl = new Vhdl (_name + "_Testbench");
+
+    _size_input  = 0;
+    _size_output = 0;
+
+    _num_cycle   = 0;
+  };
+  
+  Vhdl_Testbench::~Vhdl_Testbench ()
+  {
+  };
+  
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_input.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_input.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_input.cpp	(revision 3)
@@ -0,0 +1,27 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::add_input (uint32_t value)
+  {
+    _list_input_cycle.push_front(toBase2(value,*_num_input));
+    _num_input++;
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_label.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_label.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_label.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::add_label (string label)
+  {
+    _list_label.push_back(label_t(_num_cycle,label));
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_output.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_output.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_output.cpp	(revision 3)
@@ -0,0 +1,27 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::add_output (uint32_t value)
+  {
+    _list_output_cycle.push_front(toBase2(value,*_num_output));
+    _num_output ++;
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_add_test.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::add_test (bool must_test)
+  {
+    _list_test.push_back(must_test);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_generate_file.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_generate_file.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_generate_file.cpp	(revision 3)
@@ -0,0 +1,49 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+#include "Include/ErrorMorpheo.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void Vhdl_Testbench::generate_file (void)
+  {
+    _vhdl->set_library_work (_name + "_Pack");
+
+    if (_size_input == 0)
+      throw (ErrorMorpheo ("No input for the test bench."));
+    if (_size_output == 0)
+      throw (ErrorMorpheo ("No output for the test bench."));
+
+    // Only 2 signals and a variable
+    _vhdl->set_signal   ("testbench_input"       ,std_logic(_size_input ));
+    _vhdl->set_signal   ("testbench_output"      ,std_logic(_size_output));
+    _vhdl->set_signal   ("testbench_test"        ,std_logic(_size_output));
+    _vhdl->set_signal   ("testbench_must_test"   ,std_logic(1));
+    _vhdl->set_signal   ("testbench_counter"     ,"natural","0");
+
+    uint32_t counter = get_input  ();
+    get_output ();
+    get_test   ();
+    get_label  ();
+
+//     if (counter == get_output ())
+//       throw (ErrorMorpheo ("The number of input is different of number of output."));
+
+    generate_instance      ();
+    generate_process_clock (counter);
+    
+    _vhdl->generate_file(false, true);
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_generate_instance.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_generate_instance.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_generate_instance.cpp	(revision 3)
@@ -0,0 +1,38 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void Vhdl_Testbench::generate_instance (void)
+  {
+    _vhdl->set_body("");
+    _vhdl->set_body("instance_"+_name+" : "+_name);
+    _vhdl->set_body("port map (");
+    
+    list<string>::iterator i   = _list_port.begin();
+    if (i != _list_port.end())
+      {
+        _vhdl->set_body("\t "+*i+"\t=>\t"+*i);
+        ++i;
+      }
+    while (i != _list_port.end())
+      {
+        _vhdl->set_body("\t,"+*i+"\t=>\t"+*i);
+        ++i;
+      }
+    _vhdl->set_body("         );");
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_generate_process_clock.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_generate_process_clock.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_generate_process_clock.cpp	(revision 3)
@@ -0,0 +1,50 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void Vhdl_Testbench::generate_process_clock (uint32_t counter)
+  {
+    _vhdl->set_body("");
+    _vhdl->set_body(_clock_name+" <= not "+_clock_name+" after 50 ns;");
+    _vhdl->set_body("testbench_counter <= testbench_counter+1 after 100 ns;");
+    _vhdl->set_body("");
+
+    _vhdl->set_body("process ("+_clock_name+")");
+    _vhdl->set_body("begin");
+    _vhdl->set_body("\tif "+_clock_name+"'event and "+_clock_name+" = '1' then");
+    _vhdl->set_body("");
+    _vhdl->set_body("\t\tassert (not ((testbench_must_test = '1') and not (testbench_test = testbench_output)))");
+    _vhdl->set_body("\t\treport \"   Test KO - output's test is different of output's component\"");
+    _vhdl->set_body("\t\tseverity FAILURE;");
+    _vhdl->set_body("");
+    _vhdl->set_body("\t\tassert (not ((testbench_must_test = '1') and     (testbench_test = testbench_output)))");
+    _vhdl->set_body("\t\treport \"   Test OK\"");
+    _vhdl->set_body("\t\tseverity NOTE;");
+    _vhdl->set_body("");
+    _vhdl->set_body("\t\tassert (not ( testbench_must_test = '0'))");
+    _vhdl->set_body("\t\treport \"No Test\"");
+    _vhdl->set_body("\t\tseverity NOTE;");
+    _vhdl->set_body("");
+    _vhdl->set_body("\tend if;");
+    _vhdl->set_body("end process;");
+    
+    _vhdl->set_body("");
+    _vhdl->set_body("assert (not (testbench_counter = " + toString(counter)+"))");
+    _vhdl->set_body("report \"End of Simulation\"");
+    _vhdl->set_body("severity FAILURE;");
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_input.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_input.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_input.cpp	(revision 3)
@@ -0,0 +1,48 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  uint32_t Vhdl_Testbench::get_input (void)
+  {
+    list<string>::iterator i   = _list_input.begin();
+    
+    uint32_t counter = 0;
+
+    if (i != _list_input.end())
+      {
+	_vhdl->set_body ("");
+	_vhdl->set_body ("with testbench_counter select");
+	_vhdl->set_body ("\ttestbench_input <=");
+
+	while (i != _list_input.end())
+	  {
+	    list<string>::iterator j = i;
+	    ++i;
+
+	    if (i != _list_input.end())
+	      _vhdl->set_body ("\t\""+*j+"\" when "+toString(counter++)+",");
+	    else
+	      _vhdl->set_body ("\t\""+*j+"\" when others;");
+	  }
+      }
+
+    return counter;
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_label.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_label.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_label.cpp	(revision 3)
@@ -0,0 +1,32 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::get_label (void)
+  {
+    for (list<label_t>::iterator i = _list_label.begin(); i != _list_label.end(); i++)
+      {
+	_vhdl->set_body("");
+	_vhdl->set_body("assert (not (testbench_counter = " + toString(i->_cycle)+"))");
+	_vhdl->set_body("report \"***** "+i->_label+" *****\"");
+	_vhdl->set_body("severity NOTE;");  
+      }
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_output.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_output.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_output.cpp	(revision 3)
@@ -0,0 +1,48 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  uint32_t Vhdl_Testbench::get_output (void)
+  {
+    list<string>::iterator i   = _list_output.begin();
+    
+    uint32_t counter = 0;
+
+    if (i != _list_output.end())
+      {
+	_vhdl->set_body ("");
+	_vhdl->set_body ("with testbench_counter select");
+	_vhdl->set_body ("\ttestbench_test <=");
+
+	while (i != _list_output.end())
+	  {
+	    list<string>::iterator j = i;
+	    ++i;
+
+	    if (i != _list_output.end())
+	      _vhdl->set_body ("\t\""+*j+"\" when "+toString(counter++)+",");
+	    else
+	      _vhdl->set_body ("\t\""+*j+"\" when others;");
+	  }
+      }
+
+    return counter;
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_test.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_get_test.cpp	(revision 3)
@@ -0,0 +1,50 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  uint32_t Vhdl_Testbench::get_test (void)
+  {
+    list<bool>::iterator i   = _list_test.begin();
+    
+    uint32_t counter = 0;
+
+    if (i != _list_test.end())
+      {
+	_vhdl->set_body ("");
+	_vhdl->set_body ("with testbench_counter select");
+	_vhdl->set_body ("\ttestbench_must_test <=");
+
+	while (i != _list_test.end())
+	  {
+	    list<bool>::iterator j = i;
+	    ++i;
+
+	    string str = (*j==true)?"1":"0";
+
+	    if (i != _list_test.end())
+	      _vhdl->set_body ("\t'"+str+"' when "+toString(counter++)+",");
+	    else
+	      _vhdl->set_body ("\t'"+str+"' when others;");
+	  }
+      }
+
+    return counter;
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_new_cycle.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_new_cycle.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_new_cycle.cpp	(revision 3)
@@ -0,0 +1,32 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::new_cycle (void)
+  {
+    set_input();
+    set_output();
+
+    _num_input   = _list_input_size .begin();
+    _num_output  = _list_output_size.begin();
+
+    _num_cycle ++;
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_clock.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_clock.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_clock.cpp	(revision 3)
@@ -0,0 +1,34 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * must be call after all add port
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::set_clock (string name,
+				  bool   model_have_clock)
+  {
+    _clock_name = name;
+    _vhdl->set_signal (name,std_logic(1),"'0'");
+
+    if (model_have_clock == true)
+      _list_port.push_back(name);
+
+    _num_input   = _list_input_size .begin();
+    _num_output  = _list_output_size.begin();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_input.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_input.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_input.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::set_input (void)
+  {
+    string text = "";
+
+    while (_list_input_cycle.empty() == false)
+      {
+	text += _list_input_cycle.front();
+
+	_list_input_cycle.pop_front();
+      }
+
+    _list_input.push_back(text);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_output.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_output.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_output.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::set_output (void)
+  {
+    string text = "";
+
+    while (_list_output_cycle.empty() == false)
+      {
+	text += _list_output_cycle.front();
+
+	_list_output_cycle.pop_front();
+      }
+
+    _list_output.push_back(text);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_Testbench_set_port.cpp	(revision 3)
@@ -0,0 +1,53 @@
+#ifdef VHDL_TESTBENCH
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl_Testbench.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl_Testbench::set_port (string      name     ,
+				 direction_t direction,
+				 uint32_t    size     )
+  {
+    string   name2;
+    uint32_t size_old;
+    if (direction == IN)
+      {
+	_list_input_size.push_back(size);
+	size_old      = _size_input;
+	_size_input  += size;
+	name2         = "testbench_input";
+      }
+    else
+      {
+	_list_output_size.push_back(size);
+	size_old      = _size_output;
+	_size_output += size;
+	name2         = "testbench_output";
+      }
+
+    string range;
+    if (size == 1)
+      range = "("+toString(size_old)+")";
+    else
+      range = "("+toString(size_old+size-1)+" downto "+toString(size_old)+")";
+    
+    _vhdl->set_alias (name, std_logic(size), name2, range);
+
+    _list_port.push_back(name);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_direction_toString.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_direction_toString.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_direction_toString.cpp	(revision 3)
@@ -0,0 +1,32 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::direction_toString (direction_t direction)
+  {
+    switch (direction)
+      {
+      case IN    : return "in    "; break;
+      case OUT   : return "out   "; break;
+      case INOUT : return "inout "; break;
+      }
+    return "";
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file.cpp	(revision 3)
@@ -0,0 +1,38 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void Vhdl::generate_file (bool generate_package,
+			    bool generate_model  )
+  {
+    log_printf(FUNC,Behavioural,"generate_file","Begin");
+    
+    if (generate_package == true)
+      generate_file_package();
+    if (generate_model   == true)
+      generate_file_model  ();
+
+    log_printf(FUNC,Behavioural,"generate_file","End");
+  };
+
+  void Vhdl::generate_file (void)
+  {
+    log_printf(FUNC,Behavioural,"generate_file","Begin");
+    generate_file(true, true);
+    log_printf(FUNC,Behavioural,"generate_file","End");
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_model.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_model.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_model.cpp	(revision 3)
@@ -0,0 +1,44 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+#include <sstream>
+#include <fstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void Vhdl::generate_file_model(void)
+  {
+    log_printf(FUNC,Behavioural,"generate_file_model","Begin");
+
+    string filename = _name + ".vhdl";
+    
+    log_printf(TRACE,Behavioural,"generate_file_model","print %s",filename.c_str());
+
+    cout << "Generate file \""<< filename << "\"" << endl;
+
+    log_printf(TRACE,Behavioural,"generate_file_model","declaration");
+    ofstream file;
+    log_printf(TRACE,Behavioural,"generate_file_model","open file");
+    file.open(filename.c_str(),ios::out | ios::trunc);
+
+    log_printf(TRACE,Behavioural,"generate_file_model","get model");
+    file << get_model (0,filename,_name,"behavioural");
+
+    file.close();
+
+    log_printf(FUNC,Behavioural,"generate_file_model","End");
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_package.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_package.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_package.cpp	(revision 3)
@@ -0,0 +1,40 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+#include <sstream>
+#include <fstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void Vhdl::generate_file_package(void)
+  {
+    log_printf(FUNC,Behavioural,"generate_file_package","Begin");
+
+    string name     = _name + "_Pack";
+    string filename =  name + ".vhdl";
+
+    cout << "Generate file \""<< filename << "\"" << endl;
+
+    ofstream file;
+    file.open(filename.c_str(),ios::out | ios::trunc);
+
+    file << get_package (0,filename, name, _name);
+
+    file.close();
+
+    log_printf(FUNC,Behavioural,"generate_file_package","End");
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_alias.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_alias.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_alias.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_alias (uint32_t depth)
+  {
+    return get_list(_list_alias, depth, ";", true);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_architecture.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_architecture.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_architecture.cpp	(revision 3)
@@ -0,0 +1,39 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_architecture (uint32_t depth      ,
+				 string   name       ,
+				 string   entity_name)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream text;
+
+    text << tab << "architecture " << name << " of " << entity_name << " is" << endl
+	 << tab << get_type     (depth+1)                                    << endl
+	 << tab << get_signal   (depth+1)                                    << endl
+	 << tab << get_alias    (depth+1)                                    << endl
+	 << tab << "begin"                                                   << endl
+	 << tab << get_body     (depth+1)                                    << endl
+	 << tab << "end " << name << ";"                                     << endl;
+
+    return text.str();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_body.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_body (uint32_t depth)
+  {
+    return get_list(_list_body,depth,"",true);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_component.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_component.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_component.cpp	(revision 3)
@@ -0,0 +1,38 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_component(uint32_t depth,
+			     string   name)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream text;
+
+    text <<                                      endl
+	 << tab << "component " << name       << endl;
+    if (_list_port.empty() == false)
+      text << tab << "\tport ("                 << endl
+	   << tab << get_port(depth+1)          << endl
+	   << tab << "\t     );"                << endl;
+    text << tab << "end component;"           << endl;
+    
+    return text.str();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_entity.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_entity.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_entity.cpp	(revision 3)
@@ -0,0 +1,40 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_entity(uint32_t depth,
+			  string   name)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream text;
+
+    text <<                                      endl
+	 << tab << "entity " << name << " is" << endl;
+
+    if (_list_port.empty() == false)
+      text << tab << "\tport ("                 << endl
+	   << tab << get_port(depth+1)          << endl
+	   << tab << "\t     );"                << endl;
+    
+    text << tab << "end " << name << ";"      << endl;
+    
+    return text.str();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_header.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_header.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_header.cpp	(revision 3)
@@ -0,0 +1,39 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+#include <time.h>
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_header(uint32_t depth,
+			  string   filename)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream text;
+
+    time_t current_time;
+    time (&current_time);
+
+    text << tab << "-------------------------------------------------------------------------------" << endl
+	 << tab << "-- file      : " << filename                                                     << endl
+	 << tab << "-- date      : " << ctime (&current_time )
+	 << tab << "-- comment   : it's a autogenerated file : don't modify"                         << endl
+	 << tab << "-------------------------------------------------------------------------------" << endl;
+    
+    return text.str();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_library_ieee.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_library_ieee.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_library_ieee.cpp	(revision 3)
@@ -0,0 +1,40 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_library_ieee (uint32_t depth)
+  {
+    string        tab = string(depth,'\t');
+    ostringstream text;
+
+    text << tab                                       << endl
+	 << tab << "library ieee;"                    << endl
+         << tab << "use ieee.numeric_bit.all;"        << endl
+         << tab << "use ieee.numeric_std.all;"        << endl
+	 << tab << "use ieee.std_logic_1164.all;"     << endl
+         << tab << "use ieee.std_logic_arith.all;"    << endl
+         << tab << "use ieee.std_logic_misc.all;"     << endl
+         << tab << "--use ieee.std_logic_signed.all;"   << endl
+         << tab << "use ieee.std_logic_unsigned.all;" << endl
+         << tab << "--use ieee.std_logic_textio.all;"   << endl;
+      
+    return text.str();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_library_work.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_library_work.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_library_work.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_library_work (uint32_t depth)
+  {
+    list<string>::iterator i   = _list_library_work.begin();
+    string                 tab = string(depth,'\t');
+    ostringstream          text;
+
+    if (i != _list_library_work.end())
+      text << tab                    << endl
+	   << tab << "library work;" << endl
+	   << get_list(_list_library_work,depth,";",true);
+
+    return text.str();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_list.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_list.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_list.cpp	(revision 3)
@@ -0,0 +1,55 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_list (list<string> liste                ,
+			 uint32_t     depth                ,
+			 string       separator            ,
+			 bool         last_separator       )
+  {
+    list<string>::iterator i     = liste.begin();
+    bool                   empty = liste.empty();
+
+    string                 tab   = string(depth,'\t');
+    ostringstream          text;
+
+    if (not empty)
+      {
+	// First
+	if (i != liste.end())
+	  {
+	    text << tab << *i;
+	    ++i;
+	  }
+	
+	while (i != liste.end())
+	  {
+	    text << separator << endl;
+	    text << tab << *i;
+	    ++i;
+	  }
+	
+	if (last_separator)
+	  text << separator << endl;
+      }
+
+    return text.str();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_model.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_model.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_model.cpp	(revision 3)
@@ -0,0 +1,42 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_model(uint32_t depth            ,
+			 string   filename         ,
+			 string   entity_name      ,
+			 string   architecture_name)
+  {
+    log_printf(FUNC,Behavioural,"get_model","Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream text;
+
+    text << tab << get_header       (depth,filename)                      << endl
+	 << tab << get_library_ieee (depth)                               << endl
+	 << tab << get_library_work (depth)                               << endl
+	 << tab << get_entity       (depth,entity_name)                   << endl
+	 << tab << get_architecture (depth,architecture_name,entity_name) << endl;
+    
+    log_printf(FUNC,Behavioural,"get_model","End");
+
+    return text.str();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_package.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_package.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_package.cpp	(revision 3)
@@ -0,0 +1,38 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_package(uint32_t depth       ,
+			   string   filename    ,
+			   string   package_name,
+			   string   entity_name )
+  {
+    string        tab = string(depth,'\t');
+    ostringstream text;
+
+    text << tab << get_header       (depth,filename)                      << endl
+	 << tab << get_library_ieee (depth)                               << endl
+	 << tab << "package " << package_name << " is"                    << endl
+	 << tab << get_component    (depth+1,entity_name)                 << endl
+	 << tab << "end " << package_name << ";"                          << endl;
+    
+    return text.str();
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_port.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_port (uint32_t depth)
+  {
+    return get_list (_list_port, depth, ";", false);    
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_signal.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_signal.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_signal.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_signal (uint32_t depth)
+  {
+    return get_list (_list_signal, depth, ";", true);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_type.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_type.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_type.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  string Vhdl::get_type (uint32_t depth)
+  {
+    return get_list (_list_type, depth, ";", true);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_alias.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_alias.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_alias.cpp	(revision 3)
@@ -0,0 +1,29 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_alias (string      name1                 ,
+			string      type1                 ,
+			string      name2                 ,
+			string      range2                )
+  {
+    set_list(_list_alias, "alias "+ name1+"\t: "+type1+"\tis "+name2+"\t"+range2);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_body (string      text     )
+  {
+    set_list(_list_body, text);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component.cpp	(revision 3)
@@ -0,0 +1,31 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_body_component (string         name_instance      ,
+				 string         name_component     ,
+				 list<string>   list_port_map      )
+  {
+    set_body(name_instance + " : " + name_component);
+    set_body("port map (");
+    set_list(_list_body, get_list(list_port_map, 1, ",", false));
+    set_body(");");
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component_port_map.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component_port_map.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component_port_map.cpp	(revision 3)
@@ -0,0 +1,28 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_body_component_port_map (list<string> & list_port_map      ,
+					  string         name_port          ,
+					  string         name_signal        )
+  {
+    set_list(list_port_map, name_port + "\t=>" + name_signal);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_constant.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_constant.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_constant.cpp	(revision 3)
@@ -0,0 +1,42 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_constant (string      name     ,
+			   string      type     ,
+			   string      init)
+  {
+    set_list(_list_type, "constant "+ name+"\t: "+type+"\t:= "+init);
+  };
+
+  void Vhdl::set_constant (string      name     ,
+			   uint32_t    size     ,
+			   string      init)
+  {
+    set_constant(name,std_logic(size),init);
+  };
+
+  void Vhdl::set_constant (string      name     ,
+			   uint32_t    size     ,
+			   uint32_t    init)
+  {
+    set_constant(name,std_logic(size),std_logic_conv(size,init));
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_library_work.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_library_work.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_library_work.cpp	(revision 3)
@@ -0,0 +1,26 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_library_work (string      package_name)
+  {
+    set_list(_list_library_work, "use work."+ package_name + ".all");
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_list.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_list.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_list.cpp	(revision 3)
@@ -0,0 +1,27 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_list (list<string> & liste ,
+		       string         text  )
+  {
+    liste.push_back (text);
+  };
+    
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_port.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_port.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_port.cpp	(revision 3)
@@ -0,0 +1,35 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_port (string      name     ,
+		       direction_t direction,
+		       string      type     )
+  {
+    set_list (_list_port, name + "\t: " + direction_toString(direction) + " " + type);
+  };
+
+  void Vhdl::set_port (string      name     ,
+		       direction_t direction,
+		       uint32_t    size     )
+  {
+    set_port(name,direction,std_logic(size));
+  };
+    
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_signal.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_signal.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_signal.cpp	(revision 3)
@@ -0,0 +1,54 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_signal (string      name     ,
+			 string      type     )
+  {
+    set_list(_list_signal, "signal "+ name + "\t: " + type);
+  };
+
+  void Vhdl::set_signal (string      name     ,
+			 uint32_t    size     )
+  {
+    set_signal(name,std_logic(size));
+  }
+
+  void Vhdl::set_signal (string      name     ,
+			 string      type     ,
+			 string      init)
+  {
+    _list_signal.push_back ("signal "+ name+"\t: "+type+"\t:= "+init);
+  };
+
+  void Vhdl::set_signal (string      name     ,
+			 uint32_t    size     ,
+			 string      init     )
+  {
+    set_signal(name,std_logic(size),init);
+  };
+  void Vhdl::set_signal (string      name     ,
+			 uint32_t    size     ,
+			 uint32_t    init     )
+  {
+    set_signal(name,std_logic(size),std_logic_conv(size,init));
+  };
+
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_type.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_type.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_type.cpp	(revision 3)
@@ -0,0 +1,27 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Vhdl.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+  
+  void Vhdl::set_type (string      name     ,
+		       string      type     )
+  {
+    set_list(_list_type, "type "+ name + "\tis " + type);
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp	(revision 3)
@@ -0,0 +1,72 @@
+#ifdef VHDL
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <math.h>
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  string std_logic (uint32_t size)
+  {
+    string type;
+
+    if (size == 1)
+      type = "std_logic";
+    else
+      type = "std_logic_vector(" + toString(size-1) + " downto 0)";
+
+    return type;
+  };
+
+  string std_logic_conv (uint32_t size, string value)
+  {
+    string conv;
+
+    if (size == 1)
+      conv = "'"+toString(value)+"'";
+    else
+      conv = "conv_std_logic_vector("+value+","+toString(size)+")";
+
+    return conv;
+  };
+
+  string std_logic_conv (uint32_t size, uint32_t value)
+  {
+    return std_logic_conv(size,toString(value));
+  };
+
+  string std_logic_range (uint32_t max, uint32_t min)
+  {
+    string type;
+
+    if (max == min)
+      type = "("+toString(max)+")";
+    else
+      type = "("+toString(max)+" downto "+toString(min)+")";
+
+    return type;
+  };
+
+  string std_logic_range (uint32_t size)
+  {
+    return std_logic_range(size-1,0);
+  }
+
+  string std_logic_others (uint32_t size, uint32_t cst  )
+  {
+    if (size < 2)
+      return "'"+toString(cst)+"'";
+    else
+      return "(others => '"+toString(cst)+"')";
+  }
+}; // end namespace behavioural          
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML.cpp	(revision 3)
@@ -0,0 +1,23 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  XML::XML  (string name) :
+    _name (name)
+  {
+  };
+
+  XML::~XML () 
+  {
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_attribut.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_attribut.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_attribut.cpp	(revision 3)
@@ -0,0 +1,21 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::attribut (string name, string value)
+  {
+    _body += " "+name+"=\""+value+"\"";
+    
+    return true;
+  };
+  
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_close.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_close.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_close.cpp	(revision 3)
@@ -0,0 +1,25 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::balise_close ()
+  {
+    string name=*(_list_balise_name.begin());
+
+    _list_balise_name.pop_front();
+
+    _body += indent()+"</"+name+">\n";
+
+    return true;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_open.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_open.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_open.cpp	(revision 3)
@@ -0,0 +1,20 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::balise_open (string name)
+  {
+    if (not balise_open_begin(name)) return false;
+    return  balise_open_end  ();
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_open_begin.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_open_begin.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_open_begin.cpp	(revision 3)
@@ -0,0 +1,23 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::balise_open_begin (string name)
+  {
+    _body += indent() + "<"+name;
+
+    _list_balise_name.push_front(name);
+
+    return true;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_open_end.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_open_end.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_balise_open_end.cpp	(revision 3)
@@ -0,0 +1,21 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::balise_open_end (void)
+  {
+    _body += " >\n";
+
+    return true;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_comment.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_comment.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_comment.cpp	(revision 3)
@@ -0,0 +1,21 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::comment (string texte)
+  {
+    _body+=indent()+"<!-- "+texte+" -->\n";
+
+    return true;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_depth.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_depth.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_depth.cpp	(revision 3)
@@ -0,0 +1,19 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  uint32_t XML::depth (void)
+  {
+    return _list_balise_name.size();
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_generate_file.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_generate_file.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_generate_file.cpp	(revision 3)
@@ -0,0 +1,38 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+#include <fstream>
+using namespace std;
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void XML::generate_file (string encoding)
+  {
+    header (encoding);
+
+    string name     = _name;
+    string filename =  name + ".xml";
+
+    cout << "Generate file \""<< filename << "\"" << endl;
+
+    ofstream file;
+    file.open(filename.c_str(),ios::out | ios::trunc);
+
+    file << get_body();
+
+    file.close();
+  };
+
+  void XML::generate_file (void)
+  {
+    generate_file("UTF-8");
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_get_body.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_get_body.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_get_body.cpp	(revision 3)
@@ -0,0 +1,31 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  string XML::get_body (void)
+  {
+    return _body;
+  };
+
+  string XML::get_body (uint32_t depth)
+  {
+    string body       = _body;
+    string tabulation = indent(depth);
+
+    body.insert(0,tabulation);
+    for (size_t pos=body.find('\n',0); pos<body.length()-1; pos=body.find('\n',++pos))
+      body.insert(++pos,tabulation);
+
+    return body;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_header.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_header.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_header.cpp	(revision 3)
@@ -0,0 +1,19 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  void XML::header (string encoding)
+  {
+    _body = "<?xml version=\"1.0\" encoding=\""+encoding+"\" ?>\n" + _body;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_indent.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_indent.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_indent.cpp	(revision 3)
@@ -0,0 +1,24 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  string XML::indent (uint32_t depth)
+  {
+    return string(depth,'\t');
+  };
+
+  string XML::indent (void)
+  {
+    return indent(depth());
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_singleton.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_singleton.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_singleton.cpp	(revision 3)
@@ -0,0 +1,20 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::singleton (string name)
+  {
+    if (not singleton_begin(name)) return false;
+    return  singleton_end  ();
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_singleton_begin.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_singleton_begin.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_singleton_begin.cpp	(revision 3)
@@ -0,0 +1,21 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::singleton_begin (string name)
+  {
+    _body += indent() + "<"+name+" ";
+
+    return true;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_singleton_end.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_singleton_end.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_singleton_end.cpp	(revision 3)
@@ -0,0 +1,21 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::singleton_end (void)
+  {
+    _body+=" />\n";
+    
+    return true;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_text.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_text.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_text.cpp	(revision 3)
@@ -0,0 +1,21 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/XML.h"
+
+namespace morpheo              {
+namespace behavioural          {
+
+  bool XML::text (string text)
+  {
+    _body += indent()+text+"\n";
+
+    return true;
+  };
+
+}; // end namespace behavioural          
+}; // end namespace morpheo              
Index: /trunk/IPs/systemC/processor/Morpheo/Configuration/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Configuration/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Configuration/Makefile	(revision 3)
@@ -0,0 +1,51 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_SRC				= src
+DIR_INC				= include
+
+#-----[ Commands ]-----------------------------------------
+ECHO				= echo
+RM				= rm -f
+MV				= mv
+PWD				= `pwd`
+
+LEXER				= flex -v -d
+PARSER				= bison -d
+
+LEXER_FILES			= $(patsubst $(DIR_SRC)/%.l,$(DIR_SRC)/%_lexer.cpp,$(wildcard $(DIR_SRC)/*.l))
+PARSER_FILES			= $(patsubst $(DIR_SRC)/%.y,$(DIR_SRC)/%_parser.cpp,$(wildcard $(DIR_SRC)/*.y))	\
+				  $(patsubst $(DIR_SRC)/%.y,$(DIR_INC)/%_parser.h,$(wildcard $(DIR_SRC)/*.y))
+
+#-----[ Rules ]--------------------------------------------
+.PRECIOUS			: $(DIR_SRC)/%_lexer.cpp $(DIR_SRC)/%_parser.cpp $(DIR_INC)/%_parser.h
+
+all				: $(PARSER_FILES) $(LEXER_FILES) 
+
+$(DIR_SRC)/%_lexer.cpp		: $(DIR_SRC)/%.l
+				@$(ECHO) "Generate Lexical analyser   : $*"
+				@$(LEXER) -o$*_lexer.cpp $<
+				@$(MV)	$*_lexer.cpp $@
+
+$(DIR_SRC)/%_parser.cpp		: $(DIR_SRC)/%.y
+				@$(ECHO) "Generate Parser             : $*"
+				@$(PARSER) -o $*_parser.cpp $<
+				@$(MV) $*_parser.cpp $@
+
+$(DIR_INC)/%_parser.h		: $(DIR_SRC)/%_parser.cpp
+				@$(MV) $*_parser.hpp $(DIR_INC)/$*_parser.h
+#				@$(MV) $*_parser.cpp.h $(DIR_INC)/$*_parser.h
+
+clean				:
+				@$(ECHO) "Delete     temporary files in directory "$(PWD)
+				@$(RM) 	$(PARSER_FILES) 	\
+					$(LEXER_FILES) 		\
+					*~ 			\
+					$(DIR_SRC)/*~
+
Index: /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/Makefile	(revision 3)
@@ -0,0 +1,62 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_SRC				= src
+DIR_OBJ				= obj
+DIR_BIN				= bin
+DIR_DATA			= data
+
+#-----[ Commands ]-----------------------------------------
+ECHO				= echo
+MKDIR				= mkdir
+RM				= rm -fr
+PWD				= `pwd`
+
+CXX				= g++
+CXX_OPT				= -O3 -g3 -Wall -ansi $(INCLUDE) 
+
+INCLUDE				= -I. -I.. -I../include -I../../Include
+
+OBJECTS				= $(patsubst ../$(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard ../$(DIR_SRC)/*.cpp)) \
+				  $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp))
+
+EXE				= soft
+
+#-----[ Rules ]--------------------------------------------
+.PRECIOUS			: $(DIR_BIN)/%.x $(DIR_OBJ)/%.o
+
+all				: $(DIR_OBJ) $(DIR_BIN) $(DIR_BIN)/$(EXE).x
+
+test				: all
+				./$(DIR_BIN)/$(EXE).x
+
+$(DIR_BIN)/%.x			: $(OBJECTS)
+				@$(ECHO) "Compilation        : $*"
+				@$(CXX) $(CXX_OPT)     -o $@ $^
+
+$(DIR_OBJ)/%.o			: $(DIR_SRC)/%.cpp
+				@$(ECHO) "Compilation        : $*"
+				@$(CXX) $(CXX_OPT) -c -o $@ $<
+
+$(DIR_OBJ)/%.o			: ../$(DIR_SRC)/%.cpp
+				@$(ECHO) "Compilation        : $*"
+				@$(CXX) $(CXX_OPT) -c -o $@ $<
+
+$(DIR_OBJ)			:
+				@$(ECHO) "Create directory   : $@"
+				@$(MKDIR) $@
+
+$(DIR_BIN)			:
+				@$(ECHO) "Create directory   : $@"
+				@$(MKDIR) $@
+
+clean				:
+				@$(ECHO) "Delete     temporary files in directory "$(PWD)
+				@$(RM) $(DIR_OBJ) $(DIR_BIN) *~ $(DIR_SRC)/*~
+
Index: /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/data/ibm_power_5.xml
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/data/ibm_power_5.xml	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/data/ibm_power_5.xml	(revision 3)
@@ -0,0 +1,293 @@
+<?xml version="1.0" encoding="ISO-8859-1" ?>
+
+<cpu name="IBM Power 5" >
+
+  <!-- **************************** -->
+  <!-- * Définition du processeur * -->
+  <!-- **************************** -->
+
+  <type>
+    <definition id="0">
+      <allow id="0" />
+    </definition>
+
+    <definition id="1">
+      <allow id="0" />
+      <allow id="2" />
+    </definition>
+
+    <affectation name="INST_L_ADD"                   />
+    <affectation name="INST_L_SUB" type="0"          />
+    <affectation type="1"          name="INST_L_AND" />
+  </type>
+
+  <!-- defaut : delay = 1 et latence = 1 -->
+  <latence id="0">
+
+  </latence>
+
+  <latence id="1">
+    <operation name="inst1"                           />
+    <operation name="inst2" delay="8"                 />
+    <operation name="inst3" delay="1"    latence="2"  />
+    <operation name="inst4" latence="1"  delay="2"    />
+    <operation name="inst5"              latence="2"  />
+    <operation latence="1"  name="inst6" delay="2"    />
+    <operation latence="1"  delay="2"    name="inst7" />
+  </latence>
+
+  <internal>
+
+    <global>
+      <size_data     value="32"     />
+      <scheme_bypass algo ="complet"/>
+      <isa> 
+        <ORFPX  type="1"      value="1" />
+        <ORBIS  value="true"            />
+        <ORVDX  value="false" type="2"  />
+      </isa>
+    </global>
+
+    <cache>
+      <icache id="0">
+        <arbiter                              algo ="roundrobin" />
+        <nb_port                              value="2"     />
+      </icache>
+      <icache id="1">
+        <nb_port                              value="2"     />
+        <arbiter                              algo ="roundrobin" />
+      </icache>
+      <icache id="2">
+        <nb_port                              value="2"     />
+      </icache>
+      <icache id="3">
+        <arbiter                              algo ="roundrobin" />
+      </icache>
+      <icache id="4">
+      </icache>
+
+      <dcache id="0">
+         <arbiter                              algo ="roundrobin" />
+         <nb_port                              value="2"     />
+      </dcache>
+    </cache>
+
+    <!-- Etage 1 : Ifetch -->
+    <ifetch id="0">
+         <link_icache                            id="0"        />
+         <link_predictor                         id="0"        />
+         <link_decod                             id="0"        />
+    </ifetch>			                 	           
+
+    <ifetch id="1">
+         <nb_inst_fetch                          value="4"     />
+         <size_fetch_queue                       value="3"     />
+
+         <link_icache                            id="0"        />
+         <link_decod                             id="0"        />
+         <link_predictor                         id="0"        />
+    </ifetch>			                 	           
+
+    <ifetch id="2">
+
+         <link_decod                             id="0"        />
+         <link_icache                            id="0"        />
+
+         <size_fetch_queue                       value="3"     />
+
+         <link_predictor                         id="0"        />
+    </ifetch>			                 	           
+
+    <ifetch id="3">
+         <nb_inst_fetch                          value="4"     />
+
+         <link_decod                             id="0"        />
+         <link_predictor                         id="0"        />
+         <link_icache                            id="0"        />
+    </ifetch>			                 	           
+
+
+    <!-- Predicteur de branchement -->				                 	       
+    <prediction id="0">		                 	       
+
+      <arbiter                                algo ="roundrobin" />
+      <scheme_predictor                       algo ="all"   />
+      <size_return_address_stack              value="8"     />
+      <size_update_prediction                 value="4"     />
+
+      <branch_target_buffer>
+        <size_branch_target_buffer            value="32"    />
+        <associativity_branch_target_buffer   value="4"     />
+      </branch_target_buffer>
+
+      <meta_predictor>						       
+        <size_prediction                      value="32"    />
+        <nb_bit_counter                       value="2"     />
+      </meta_predictor>		
+
+      <global_predictor>				       
+        <size_prediction_history_table        value="4"     />
+        <size_prediction                      value="16"    />
+        <nb_bit_counter                       value="2"     />
+      </global_predictor>
+      
+      <local_predictor>
+        <size_prediction_history_table        value="4"     />
+        <size_prediction_l1                   value="8"     />
+        <size_prediction_l2                   value="16"    />
+        <nb_bit_counter                       value="2"     />
+        <xor                                  value="false" />
+      </local_predictor>
+
+    </prediction>					       
+
+
+
+
+
+    <branch_queue id="0">
+<!--
+      <arbiter                                algo ="roundrobin" />
+      <nb_branch_speculated                   value="4"     />
+      <nb_branch_complete                     value="1"     />
+-->
+    </branch_queue>
+
+
+
+
+	
+    <!-- Etage 2 : Décodage -->				     	       
+    <decod id="0">
+<!--
+         <arbiter                                algo ="roundrobin" />
+         <link_rename                            id="0"        />
+         <link_branch_queue                      id="0"        />
+         <nb_inst_decod                          value="3"     />
+         <nb_inst_rename                         value="3"     />
+         <size_decod_queue                       value="4"     />
+-->
+    </decod>			                 	       
+
+
+
+				                 	       
+    <!-- Etage 3 : Renommage -->
+    <rename id="0">
+<!--
+         <arbiter                                algo ="roundrobin" />
+
+         <slot>
+           <route                                id="0"        />
+         </slot>
+
+         <link_commit                            id="0"        />
+         <link_load_store_queue                  id="0"        />
+         <link_special_register_file             id="0"        />
+
+         <nb_inst_rename                         value="5"     />
+         <nb_inst_select_windows                 value="9"     />
+         <size_rename_queue                      value="15"    />
+         <nb_gpr_phy                             value="128"   />
+         <nb_gpr_free                            value="4"     />
+         <nb_spr_phy                             value="32"    />
+         <nb_spr_free                            value="2"     />
+-->
+    </rename>
+
+
+
+
+
+    <!-- Etage 4   Selection/Issue -->
+    <select_issue>
+      <!-- lien entre un slot est un cluster -->
+      <slot id="0">
+        <!-- lien entre un cluster et une waitunit -->
+        <cluster id="0">
+          <route                                 id="0"        />
+        </cluster>
+      </slot>
+    </select_issue>
+
+
+
+
+
+    <!-- Etage 5 : Execution -->
+    <execute>
+
+      <!-- Clusterisation des unités d'éxecution -->
+      <cluster id="0">
+         <!-- bypass intra cluster -->
+         <bypass_register                        value="false" />
+         <bypass_status                          value="false" />
+         
+         <!-- Wait Unit (Selection queue - Reservation Station) -->
+         <waitunit id="0">
+              <size_select_queue                 value="4"     />
+              <size_reservation_station          value="4"     />
+              <dispatch>
+                <route                           id="0"        />
+              </dispatch>
+         </waitunit>
+
+         <!-- Executive Unit (Ue (type des opérations accepté et latence des opérations) - Execute queue) -->
+         <executiveunit id="0">
+              <arbiter                           algo ="roundrobin" />
+              <size_execute_queue                value="4"     />
+              <nb_inst_execute                   value="2"     />
+              <type                              value="0"     />
+              <latence                           value="0"     />
+         </executiveunit>
+
+      </cluster>
+    </execute>
+
+
+
+
+    <!-- Etage 5bis : Memory -->
+    <memory id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+         <link_dcache                            id="0"        />
+         <link_commit                            id="0"        />
+         <nb_inst_commit                         value="4"     />
+         <nb_memory_complete                     value="5"     />
+         <size_load_store_queue                  value="32"    />
+         <bypass_memory_in                       value="false" />
+         <bypass_memory_out                      value="false" />
+         <bypass_memory_internal                 value="false" />
+    </memory>
+
+
+
+
+    <!-- Banc de registres 
+         (Autant de RegFile que d'étage 3) -->
+    <general_registerfile id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+         <nb_gpr_reader                          value="5"     />
+         <nb_gpr_writer                          value="5"     />
+         <nb_spr_reader                          value="5"     />
+         <nb_spr_writer                          value="5"     />
+    </general_registerfile>
+
+
+
+
+
+    <!-- Etage 6 : Commit -->
+    <commit id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+         <nb_inst_commit                         value="4"     />
+         <nb_inst_update                         value="5"     />
+         <nb_inst_update_windows                 value="9"     />
+         <size_re_order_buffer                   value="32"    />
+         <commit_out_of_order_thread             value="false" />
+    </commit>
+
+
+  </internal>
+
+</cpu>
Index: /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/data/test.xml
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/data/test.xml	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/data/test.xml	(revision 3)
@@ -0,0 +1,293 @@
+<?xml version="1.0" encoding="ISO-8859-1" ?>
+
+<cpu name="my_name" >
+
+  <!-- **************************** -->
+  <!-- * Définition du processeur * -->
+  <!-- **************************** -->
+
+  <type>
+    <definition id="0">
+      <allow id="0" />
+    </definition>
+
+    <definition id="1">
+      <allow id="0" />
+      <allow id="2" />
+    </definition>
+
+    <affectation name="INST_L_ADD"                   />
+    <affectation name="INST_L_SUB" type="0"          />
+    <affectation type="1"          name="INST_L_AND" />
+  </type>
+
+  <!-- defaut : delay = 1 et latence = 1 -->
+  <latence id="0">
+
+  </latence>
+
+  <latence id="1">
+    <operation name="inst1"                           />
+    <operation name="inst2" delay="8"                 />
+    <operation name="inst3" delay="1"    latence="2"  />
+    <operation name="inst4" latence="1"  delay="2"    />
+    <operation name="inst5"              latence="2"  />
+    <operation latence="1"  name="inst6" delay="2"    />
+    <operation latence="1"  delay="2"    name="inst7" />
+  </latence>
+
+  <internal>
+
+    <global>
+      <size_data     value="32"     />
+      <scheme_bypass algo ="complet"/>
+      <isa> 
+        <ORFPX  type="1"      value="1" />
+        <ORBIS  value="true"            />
+        <ORVDX  value="false" type="2"  />
+      </isa>
+    </global>
+
+    <cache>
+      <icache id="0">
+        <arbiter                              algo ="roundrobin" />
+        <nb_port                              value="2"     />
+      </icache>
+      <icache id="1">
+        <nb_port                              value="2"     />
+        <arbiter                              algo ="roundrobin" />
+      </icache>
+      <icache id="2">
+        <nb_port                              value="2"     />
+      </icache>
+      <icache id="3">
+        <arbiter                              algo ="roundrobin" />
+      </icache>
+      <icache id="4">
+      </icache>
+
+      <dcache id="0">
+         <arbiter                              algo ="roundrobin" />
+         <nb_port                              value="2"     />
+      </dcache>
+    </cache>
+
+    <!-- Etage 1 : Ifetch -->
+    <ifetch id="0">
+         <link_icache                            id="0"        />
+         <link_predictor                         id="0"        />
+         <link_decod                             id="0"        />
+    </ifetch>			                 	           
+
+    <ifetch id="1">
+         <nb_inst_fetch                          value="4"     />
+         <size_fetch_queue                       value="3"     />
+
+         <link_icache                            id="0"        />
+         <link_decod                             id="0"        />
+         <link_predictor                         id="0"        />
+    </ifetch>			                 	           
+
+    <ifetch id="2">
+
+         <link_decod                             id="0"        />
+         <link_icache                            id="0"        />
+
+         <size_fetch_queue                       value="3"     />
+
+         <link_predictor                         id="0"        />
+    </ifetch>			                 	           
+
+    <ifetch id="3">
+         <nb_inst_fetch                          value="4"     />
+
+         <link_decod                             id="0"        />
+         <link_predictor                         id="0"        />
+         <link_icache                            id="0"        />
+    </ifetch>			                 	           
+
+
+    <!-- Predicteur de branchement -->				                 	       
+    <prediction id="0">		                 	       
+
+      <arbiter                                algo ="roundrobin" />
+      <scheme_predictor                       algo ="all"   />
+      <size_return_address_stack              value="8"     />
+      <size_update_prediction                 value="4"     />
+
+      <branch_target_buffer>
+        <size_branch_target_buffer            value="32"    />
+        <associativity_branch_target_buffer   value="4"     />
+      </branch_target_buffer>
+
+      <meta_predictor>						       
+        <size_prediction                      value="32"    />
+        <nb_bit_counter                       value="2"     />
+      </meta_predictor>		
+
+      <global_predictor>				       
+        <size_prediction_history_table        value="4"     />
+        <size_prediction                      value="16"    />
+        <nb_bit_counter                       value="2"     />
+      </global_predictor>
+      
+      <local_predictor>
+        <size_prediction_history_table        value="4"     />
+        <size_prediction_l1                   value="8"     />
+        <size_prediction_l2                   value="16"    />
+        <nb_bit_counter                       value="2"     />
+        <xor                                  value="false" />
+      </local_predictor>
+
+    </prediction>					       
+
+
+
+
+
+    <branch_queue id="0">
+<!--
+      <arbiter                                algo ="roundrobin" />
+      <nb_branch_speculated                   value="4"     />
+      <nb_branch_complete                     value="1"     />
+-->
+    </branch_queue>
+
+
+
+
+	
+    <!-- Etage 2 : Décodage -->				     	       
+    <decod id="0">
+<!--
+         <arbiter                                algo ="roundrobin" />
+         <link_rename                            id="0"        />
+         <link_branch_queue                      id="0"        />
+         <nb_inst_decod                          value="3"     />
+         <nb_inst_rename                         value="3"     />
+         <size_decod_queue                       value="4"     />
+-->
+    </decod>			                 	       
+
+
+
+				                 	       
+    <!-- Etage 3 : Renommage -->
+    <rename id="0">
+<!--
+         <arbiter                                algo ="roundrobin" />
+
+         <slot>
+           <route                                id="0"        />
+         </slot>
+
+         <link_commit                            id="0"        />
+         <link_load_store_queue                  id="0"        />
+         <link_special_register_file             id="0"        />
+
+         <nb_inst_rename                         value="5"     />
+         <nb_inst_select_windows                 value="9"     />
+         <size_rename_queue                      value="15"    />
+         <nb_gpr_phy                             value="128"   />
+         <nb_gpr_free                            value="4"     />
+         <nb_spr_phy                             value="32"    />
+         <nb_spr_free                            value="2"     />
+-->
+    </rename>
+
+
+
+
+
+    <!-- Etage 4   Selection/Issue -->
+    <select_issue>
+      <!-- lien entre un slot est un cluster -->
+      <slot id="0">
+        <!-- lien entre un cluster et une waitunit -->
+        <cluster id="0">
+          <route                                 id="0"        />
+        </cluster>
+      </slot>
+    </select_issue>
+
+
+
+
+
+    <!-- Etage 5 : Execution -->
+    <execute>
+
+      <!-- Clusterisation des unités d'éxecution -->
+      <cluster id="0">
+         <!-- bypass intra cluster -->
+         <bypass_register                        value="false" />
+         <bypass_status                          value="false" />
+         
+         <!-- Wait Unit (Selection queue - Reservation Station) -->
+         <waitunit id="0">
+              <size_select_queue                 value="4"     />
+              <size_reservation_station          value="4"     />
+              <dispatch>
+                <route                           id="0"        />
+              </dispatch>
+         </waitunit>
+
+         <!-- Executive Unit (Ue (type des opérations accepté et latence des opérations) - Execute queue) -->
+         <executiveunit id="0">
+              <arbiter                           algo ="roundrobin" />
+              <size_execute_queue                value="4"     />
+              <nb_inst_execute                   value="2"     />
+              <type                              value="0"     />
+              <latence                           value="0"     />
+         </executiveunit>
+
+      </cluster>
+    </execute>
+
+
+
+
+    <!-- Etage 5bis : Memory -->
+    <memory id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+         <link_dcache                            id="0"        />
+         <link_commit                            id="0"        />
+         <nb_inst_commit                         value="4"     />
+         <nb_memory_complete                     value="5"     />
+         <size_load_store_queue                  value="32"    />
+         <bypass_memory_in                       value="false" />
+         <bypass_memory_out                      value="false" />
+         <bypass_memory_internal                 value="false" />
+    </memory>
+
+
+
+
+    <!-- Banc de registres 
+         (Autant de RegFile que d'étage 3) -->
+    <general_registerfile id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+         <nb_gpr_reader                          value="5"     />
+         <nb_gpr_writer                          value="5"     />
+         <nb_spr_reader                          value="5"     />
+         <nb_spr_writer                          value="5"     />
+    </general_registerfile>
+
+
+
+
+
+    <!-- Etage 6 : Commit -->
+    <commit id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+         <nb_inst_commit                         value="4"     />
+         <nb_inst_update                         value="5"     />
+         <nb_inst_update_windows                 value="9"     />
+         <size_re_order_buffer                   value="32"    />
+         <commit_out_of_order_thread             value="false" />
+    </commit>
+
+
+  </internal>
+
+</cpu>
Index: /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/data/test2.xml
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/data/test2.xml	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/data/test2.xml	(revision 3)
@@ -0,0 +1,241 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<cpu name="my_cpu">
+  
+  <!-- **************************** -->
+  <!-- * Définition du processeur * -->
+  <!-- **************************** -->
+
+  <definition>
+    <!-- Définition global s'applique à tous le proc -->
+    <global>
+      <size_data                                 value="32"     />        <!-- Balise Optionnel (defaut : 32 )     -->
+      <scheme_bypass                             algo ="complet"/>        <!-- Balise Optionnel (defaut : complet) -->
+      <isa> 
+        <ORBIS                                   value="true" type="2" /> <!-- Balise Obligatoire, attribut "type" optionniel (default : 1) -->
+        <ORFPX                                   value="false"  />        <!-- Balise Obligatoire, attribut "type" optionniel (default : 1) -->
+        <ORVDX                                   value="false"  />        <!-- Balise Obligatoire, attribut "type" optionniel (default : 1) -->
+      </isa>
+    </global>
+
+    <cache>
+      <icache id="0">
+         <arbiter                              algo ="roundrobin" />
+         <nb_icache_port                       value="2"     />
+      </icache>
+      <dcache id="0">
+           <arbiter                              algo ="roundrobin" />
+           <nb_dcache_port                       value="2"     />
+      </dcache>
+    </cache>
+
+    <!-- Etage 1 : Ifetch -->
+    <ifetch id="0">
+         <nb_inst_fetch                          value="4"     />
+         <size_fetch_queue                       value="3"     />
+
+         <link_icache                            id="0"        />
+         <link_decod                             id="0"        />
+         <link_predictor                         id="0"        />
+    </ifetch>			                 	           
+
+    <!-- Predicteur de branchement -->				                 	       
+    <prediction>		                 	       
+      <instance id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+
+         <scheme_predictor                       algo ="all"   />
+         <size_branch_target_buffer              value="32"    />
+         <associativity_branch_target_buffer     value="4"     />
+
+	 <meta_predictor>						       
+           <size_prediction                      value="32"    />
+           <nb_bit_counter                       value="2"     />
+	 </meta_predictor>		
+
+         <global_predictor>				       
+           <size_prediction_history_table        value="4"     />
+           <size_prediction                      value="16"    />
+           <nb_bit_counter                       value="2"     />
+	 </global_predictor>
+	
+         <local_predictor>
+           <size_prediction_history_table        value="4"     />
+           <size_prediction_l1                   value="8"     />
+           <size_prediction_l2                   value="16"    />
+           <nb_bit_counter                       value="2"     />
+           <xor                                  value="false" />
+         </local_predictor>
+
+         <size_return_address_stack              value="8"     />
+         <size_update_prediction                 value="4"     />
+
+      </instance>					       
+    </prediction>					       
+
+    <branch_queue>
+      <instance id="0">
+         <arbiter                                algo ="roundrobin" />
+         <nb_branch_speculated                   value="4"     />
+         <nb_branch_complete                     value="1"     />
+      </instance>
+    </branch_queue>
+	
+    <!-- Etage 2 : Décodage -->				         	       
+    <decod>				         	       
+      <instance id="0">			         	       
+         <arbiter                                algo ="roundrobin" />
+         <link_rename                            id="0"        />
+         <link_branch_queue                      id="0"        />
+         <nb_inst_decod                          value="3"     />
+         <nb_inst_rename                         value="3"     />
+         <size_decod_queue                       value="4"     />
+      </instance>		                 	           
+    </decod>			                 	       
+				                 	       
+    <!-- Etage 3 : Renommage -->
+    <rename>			                 	       
+      <instance id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+
+         <slot>
+           <route                                id="0"        />
+         </slot>
+
+         <link_commit                            id="0"        />
+         <link_load_store_queue                  id="0"        />
+         <link_special_register_file             id="0"        />
+         <nb_inst_rename                         value="5"     />
+         <nb_inst_select_windows                 value="9"     />
+         <size_rename_queue                      value="15"    />
+         <nb_gpr_phy                             value="128"   />
+         <nb_gpr_free                            value="4"     />
+         <nb_spr_phy                             value="32"    />
+         <nb_spr_free                            value="2"     />
+      </instance>		                 	       
+    </rename>
+
+    <!-- Etage 4   Selection/Issue -->
+    <select_issue>
+      <!-- lien entre un slot est un cluster -->
+      <slot id="0">
+        <!-- lien entre un cluster et une waitunit -->
+        <cluster id="0">
+          <route                                 id="0"        />
+        </cluster>
+      </slot>
+    </select_issue>
+
+    <!-- Etage 5 : Execution -->
+    <execute>
+
+      <!-- Clusterisation des unités d'éxecution -->
+      <cluster id="0">
+         <!-- bypass intra cluster -->
+         <bypass_register                        value="false" />
+         <bypass_status                          value="false" />
+         
+         <!-- Wait Unit (Selection queue - Reservation Station) -->
+         <waitunit>
+           <instance id="0">
+              <size_select_queue                 value="4"     />
+              <size_reservation_station          value="4"     />
+              <dispatch>
+                <route                           id="0"        />
+              </dispatch>
+           </instance>
+         </waitunit>
+
+         <!-- Executive Unit (Ue (type des opérations accepté et latence des opérations) - Execute queue) -->
+         <executiveunit>
+           <instance id="0">
+              <arbiter                           algo ="roundrobin" />
+              <size_execute_queue                value="4"     />
+              <nb_inst_execute                   value="2"     />
+              <type                              value="0"     />
+              <latence                           value="0"     />
+           </instance>
+         </executiveunit>
+
+      </cluster>
+    </execute>
+
+    <!-- Etage 5bis : Memory -->
+    <memory>
+      <instance id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+         <link_dcache                            id="0"        />
+         <link_commit                            id="0"        />
+         <nb_inst_commit                         value="4"     />
+         <nb_memory_complete                     value="5"     />
+         <size_load_store_queue                  value="32"    />
+         <bypass_memory_in                       value="false" />
+         <bypass_memory_out                      value="false" />
+         <bypass_memory_internal                 value="false" />
+      </instance>
+    </memory>
+
+    <!-- Banc de registres 
+         (Autant de RegFile que d'étage 3) -->
+    <general_registerfile>
+      <instance id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+         <nb_gpr_reader                          value="5"     />
+         <nb_gpr_writer                          value="5"     />
+         <nb_spr_reader                          value="5"     />
+         <nb_spr_writer                          value="5"     />
+      </instance>
+    </general_registerfile>
+
+    <!-- Etage 6 : Commit -->
+    <commit>
+      <instance id="0">		                 	       
+         <arbiter                                algo ="roundrobin" />
+         <nb_inst_commit                         value="4"     />
+         <nb_inst_update                         value="5"     />
+         <nb_inst_update_windows                 value="9"     />
+         <size_re_order_buffer                   value="32"    />
+         <commit_out_of_order_thread             value="false" />
+      </instance>
+    </commit>
+  </definition>
+
+  <!-- ******** -->
+  <!-- * Type * -->
+  <!-- ******** -->
+
+  <type>
+    <!-- definition : pour chaque instance, definit les types autorisé -->
+    <enumerate>
+      <instance id="0">
+        <allow id="0" />
+        <allow id="2" />
+      </instance>
+    </enumerate>
+
+    <!-- pour chaque operation, définit le type d'appartenance.
+         default : 0 -->
+    <affectation>
+        <operation name="INST_L_ADD" type="0"/>
+        <operation name="INST_L_SUB" type="0"/>
+        <operation name="INST_L_AND" type="1"/>
+        <operation name="INST_L_XOR" type="1"/>
+        <operation name="INST_L_MUL" type="2"/>
+        <operation name="INST_L_DIV" type="2"/>
+    </affectation>
+  </type>
+
+  <!-- *********** -->
+  <!-- * Latence * -->
+  <!-- *********** -->
+
+  <!-- liste pour chaque opération leur delay et latence, 
+       default : latence = 1, delay = 1 -->
+  <latence>
+    <instance id="0">
+      <operation name="INST_L_ADD" delay="1" latence="2" />
+      <operation name="INST_L_MUL" delay="8" latence="4" />
+    </instance>
+  </latence>
+
+</cpu>
Index: /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/src/main.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/src/main.cpp	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Configuration/SelfTest/src/main.cpp	(revision 3)
@@ -0,0 +1,35 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test Configuration
+ */
+
+#include <string>
+#include <iostream>
+
+#include "../SelfTest/SelfTest.h"
+#include "Configuration.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::selftest;
+using namespace morpheo::configuration;
+
+int main (void)
+{
+  cout << "<main> : SelfTest of Configuration" << endl;
+
+  /*
+  cout << "<main> : Test[0] -> Configuration without a good file" << endl;
+  Configuration config0 ("data/test0.xml");
+  */
+
+  cout << "<main> : Test[1] -> Parse the minimum file" << endl;
+  Configuration config1 ("data/test.xml");
+
+  cout << "<main> : All Test passed with Success" << endl;
+
+  return (EXIT_SUCCESS);
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Configuration/include/Configuration.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Configuration/include/Configuration.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Configuration/include/Configuration.h	(revision 3)
@@ -0,0 +1,57 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Parse a Configuration's file and generate the Tree of configuration
+ */
+
+#include <stdio.h>
+#include <iostream>
+#include "message.h"
+#include "include/Configuration_files_parser.h"
+
+using namespace std;
+
+// Déclaration de variables globales
+extern FILE * yyin;
+extern int    yyparse(void);
+
+namespace morpheo       {
+namespace configuration {
+
+  class Configuration
+  {
+
+    // -----[ fields ]----------------------------------------------------
+  private : FILE * file;
+    
+    // -----[ methods ]---------------------------------------------------
+  public  :      Configuration   (string filename)
+  {
+    // Open the file in read only
+    file = fopen(filename.c_str(), "r");
+
+    // Test if the file is open 
+    if (file == NULL)
+      {
+	cerr_msg << "The file \"" << filename << "\" can't be open" << endl;
+	exit (EXIT_FAILURE);
+      }
+    
+    // Parse the file
+    yyin = file;
+    yyparse();
+  }
+
+  public  :      ~Configuration  (void)
+  {
+    // Close the file
+    fclose(file);
+  }
+
+
+  }; // end class Configuration
+  
+}; // end namespace configuration
+}; // end namespace morpheo
Index: /trunk/IPs/systemC/processor/Morpheo/Configuration/src/Configuration_files.l
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Configuration/src/Configuration_files.l	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Configuration/src/Configuration_files.l	(revision 3)
@@ -0,0 +1,122 @@
+/* *** Paramètre de configuration */
+
+%{
+  /*  déf des tokens*/
+#include "Configuration_files_parser.h"
+#include <string.h>
+
+unsigned int lineno = 1;
+
+%}
+
+alpha   		[A-Za-z]
+chiffre 		[0-9]
+caractere		[-_.]
+nom    			({alpha}|{chiffre}|{caractere})
+
+/*----- [ Rules ]------------------------------------- */
+%s configuration commentaire
+
+%%
+%{
+	BEGIN configuration;
+%}
+<configuration>"<!--"			{ yylval.token = strdup(yytext);  BEGIN(commentaire);   } /* Balise de début de commentaires */
+<commentaire>"-->"			{ yylval.token = strdup(yytext);  BEGIN(configuration); } /* Balise de fin   de commentaires */
+
+
+" "|\t					{ yylval.token = strdup(yytext); }
+\n    					{ yylval.token = strdup(yytext);  lineno ++;       }
+
+
+<configuration>"<?xml"			{ yylval.token = strdup(yytext);  return BEGIN_XML; }
+<configuration>"?>"			{ yylval.token = strdup(yytext);  return END_XML; }
+
+<configuration>"<cpu"			{ yylval.token = strdup(yytext);  return BEGIN_CPU; }
+<configuration>"</cpu"			{ yylval.token = strdup(yytext);  return END_CPU; }
+
+<configuration>"<definition"		{ yylval.token = strdup(yytext);  return BEGIN_DEFINITION; }
+<configuration>"</definition"		{ yylval.token = strdup(yytext);  return END_DEFINITION; }
+
+<configuration>"<internal"		{ yylval.token = strdup(yytext);  return BEGIN_INTERNAL; }
+<configuration>"</internal"		{ yylval.token = strdup(yytext);  return END_INTERNAL; }
+
+<configuration>"<type"			{ yylval.token = strdup(yytext);  return BEGIN_TYPE; }
+<configuration>"</type"			{ yylval.token = strdup(yytext);  return END_TYPE; }
+
+<configuration>"<latence"		{ yylval.token = strdup(yytext);  return BEGIN_LATENCE; }
+<configuration>"</latence"		{ yylval.token = strdup(yytext);  return END_LATENCE; }
+
+<configuration>"<global"		{ yylval.token = strdup(yytext);  return BEGIN_GLOBAL; }
+<configuration>"</global"		{ yylval.token = strdup(yytext);  return END_GLOBAL; }
+
+<configuration>"<isa"			{ yylval.token = strdup(yytext);  return BEGIN_ISA; }
+<configuration>"</isa"			{ yylval.token = strdup(yytext);  return END_ISA; }
+
+<configuration>"<cache"			{ yylval.token = strdup(yytext);  return BEGIN_CACHE; }
+<configuration>"</cache"		{ yylval.token = strdup(yytext);  return END_CACHE; }
+
+<configuration>"<icache"		{ yylval.token = strdup(yytext);  return BEGIN_ICACHE; }
+<configuration>"</icache"		{ yylval.token = strdup(yytext);  return END_ICACHE; }
+
+<configuration>"<dcache"		{ yylval.token = strdup(yytext);  return BEGIN_DCACHE; }
+<configuration>"</dcache"		{ yylval.token = strdup(yytext);  return END_DCACHE; }
+
+<configuration>"<ifetch"		{ yylval.token = strdup(yytext);  return BEGIN_IFETCH; }
+<configuration>"</ifetch"		{ yylval.token = strdup(yytext);  return END_IFETCH; }
+
+<configuration>"<prediction"		{ yylval.token = strdup(yytext);  return BEGIN_PREDICTION; }
+<configuration>"</prediction"		{ yylval.token = strdup(yytext);  return END_PREDICTION; }
+
+<configuration>"<operation"		{ yylval.token = strdup(yytext);  return BEGIN_OPERATION; }
+<configuration>"<allow"		        { yylval.token = strdup(yytext);  return BEGIN_ALLOW; }
+<configuration>"<ORBIS"		        { yylval.token = strdup(yytext);  return BEGIN_ORBIS; }
+<configuration>"<ORFPX"		        { yylval.token = strdup(yytext);  return BEGIN_ORFPX; }
+<configuration>"<ORVDX"		        { yylval.token = strdup(yytext);  return BEGIN_ORVDX; }
+<configuration>"<size_data"     	{ yylval.token = strdup(yytext);  return BEGIN_SIZE_DATA       ; }
+<configuration>"<scheme_bypass" 	{ yylval.token = strdup(yytext);  return BEGIN_SCHEME_BYPASS   ; }
+<configuration>"<arbiter"       	{ yylval.token = strdup(yytext);  return BEGIN_ARBITER         ; }
+<configuration>"<nb_port"       	{ yylval.token = strdup(yytext);  return BEGIN_NB_PORT         ; }
+<configuration>"<affectation"		{ yylval.token = strdup(yytext);  return BEGIN_AFFECTATION; }
+
+<configuration>"<nb_inst_fetch" 	{ yylval.token = strdup(yytext);  return BEGIN_NB_INST_FETCH   ; }
+<configuration>"<size_fetch_queue"	{ yylval.token = strdup(yytext);  return BEGIN_SIZE_FETCH_QUEUE; }
+<configuration>"<link_icache"    	{ yylval.token = strdup(yytext);  return BEGIN_LINK_ICACHE     ; }
+<configuration>"<link_predictor"	{ yylval.token = strdup(yytext);  return BEGIN_LINK_PREDICTOR  ; }
+<configuration>"<link_decod"        	{ yylval.token = strdup(yytext);  return BEGIN_LINK_DECOD      ; }
+
+<configuration>">" 			{ yylval.token = strdup(yytext);  return END_BALISE_DUAL;}
+<configuration>"/>" 			{ yylval.token = strdup(yytext);  return END_SINGLETON;}
+
+<configuration>"="                      { yylval.token = strdup(yytext);  return EQUAL; }
+<configuration>"\""                     { yylval.token = strdup(yytext);  return QUOTE; }
+
+
+<configuration>"version"		{ yylval.token = strdup(yytext);  return VERSION         ; }
+<configuration>"encoding"		{ yylval.token = strdup(yytext);  return ENCODING        ; }
+<configuration>"name"    		{ yylval.token = strdup(yytext);  return NAME            ; }
+<configuration>"id"      		{ yylval.token = strdup(yytext);  return ID              ; }
+<configuration>"delay"      		{ yylval.token = strdup(yytext);  return DELAY           ; }
+<configuration>"latence"      		{ yylval.token = strdup(yytext);  return LATENCE         ; }
+<configuration>"type"         		{ yylval.token = strdup(yytext);  return TYPE            ; }
+<configuration>"value"        		{ yylval.token = strdup(yytext);  return VALUE           ; }
+<configuration>"algo"         		{ yylval.token = strdup(yytext);  return ALGO            ; }
+
+<configuration>"true"           	{ yylval.token = strdup(yytext);  yylval.value_int   = 1;              return INTEGER;}
+<configuration>"false"    		{ yylval.token = strdup(yytext);  yylval.value_int   = 0;              return INTEGER;}
+
+<configuration>{chiffre}+"."{chiffre}+	{ yylval.token = strdup(yytext);  yylval.value_float = atof(yytext);   return FLOAT;}
+<configuration>{chiffre}+		{ yylval.token = strdup(yytext);  yylval.value_int   = atoi(yytext);   return INTEGER;}
+<configuration>{nom}+			{ yylval.token = strdup(yytext);  yylval.name        = strdup(yytext); return STRING;}
+
+
+<commentaire>.                          { yylval.token = strdup(yytext); }
+.                                       { yylval.token = strdup(yytext);  return (*yytext); } /* Toute autre caractère */
+%%
+
+/*  *** Fonctions auxiliaire */
+
+int yywrap()
+{ 
+   return (-1);
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Configuration/src/Configuration_files.y
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Configuration/src/Configuration_files.y	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Configuration/src/Configuration_files.y	(revision 3)
@@ -0,0 +1,1267 @@
+%{
+#include <iostream>
+#include <list>
+
+  using namespace std;
+  
+  list<int> list_token;
+      
+  // define in the lexer
+  extern unsigned int lineno;
+  
+  int  yylex   ();
+  void yyerror ( const char *);
+%}
+
+// Type of yylval
+%union
+{
+  unsigned int value_int;
+  float        value_float;
+  char *       name ;
+  char *       token;
+}
+
+// Définition des Tokens
+// TOKEN
+
+// Nom de balises
+%token BEGIN_XML                END_XML
+%token BEGIN_CPU                END_CPU
+%token BEGIN_DEFINITION         END_DEFINITION
+%token BEGIN_INTERNAL           END_INTERNAL
+%token BEGIN_TYPE               END_TYPE      
+%token BEGIN_LATENCE            END_LATENCE   
+%token BEGIN_GLOBAL             END_GLOBAL
+%token BEGIN_ISA                END_ISA
+%token BEGIN_CACHE              END_CACHE
+%token BEGIN_ICACHE             END_ICACHE
+%token BEGIN_DCACHE             END_DCACHE
+%token BEGIN_IFETCH             END_IFETCH
+%token BEGIN_AFFECTATION
+%token BEGIN_OPERATION
+%token BEGIN_ALLOW
+%token BEGIN_ORBIS
+%token BEGIN_ORFPX
+%token BEGIN_ORVDX
+%token BEGIN_SIZE_DATA    
+%token BEGIN_SCHEME_BYPASS
+%token BEGIN_ARBITER
+%token BEGIN_NB_PORT
+%token BEGIN_NB_INST_FETCH   
+%token BEGIN_SIZE_FETCH_QUEUE
+%token BEGIN_LINK_ICACHE     
+%token BEGIN_LINK_PREDICTOR  
+%token BEGIN_LINK_DECOD      
+%token                          END_SINGLETON
+%token                          END_BALISE_DUAL
+
+// Nom d'attribut
+%token VERSION ENCODING NAME ID DELAY LATENCE TYPE VALUE ALGO
+
+// Symbole
+%token EQUAL QUOTE
+// Type
+%token INTEGER FLOAT STRING;
+
+%type  <value_float> FLOAT   attribut_float;
+%type  <value_int>   INTEGER attribut_integer;
+%type  <name>        STRING  attribut_string;
+
+%type  <value_int>   attribut_id attribut_delay attribut_latence attribut_type attribut_value
+%type  <name>        attribut_name attribut_algo
+
+%start file
+
+// Rule to the grammar
+%%
+
+// *****{ Fichier }*****
+file                             : file_header file_body 
+                                 {
+		                   cout << "file" << endl;
+		                 }
+                                 ;
+		                 
+file_header                      : balise_xml
+                                 ;                     
+		                 
+file_body                        : balise_cpu
+                                 ;
+
+// ====={ Balise "xml" }=====
+balise_xml                       : begin_xml liste_attributs_xml end_xml
+                                 ;
+		                 
+begin_xml                        : _begin_xml
+                                 ;
+		                 
+_begin_xml                       : BEGIN_XML
+                                 {
+				   list_token.push_back(BEGIN_XML);
+				 }
+                                 ;
+
+liste_attributs_xml              : VERSION attribut_float ENCODING attribut_string 
+                                 {
+		                   // Test
+		                   if ($2 != 1.0)
+		                     yyerror ("balise \"xml\" - attribut \"version\" - value is always equal at \"1.0\"");
+		                   
+		                   if (strcmp($4,"ISO-8859-1") != 0)
+		                     yyerror ("balise \"xml\" - attribut \"version\" - value is always equal at \"ISO-8859-1\"");
+		                 }
+                                 ;
+		                 
+end_xml                          : _end_xml
+                                 ;
+
+// ====={ Balise "cpu" }=====
+// <cpu>
+balise_cpu                       : begin_cpu body_cpu end_cpu
+                                 ;
+		                 
+begin_cpu                        : _begin_cpu liste_attributs_cpu END_BALISE_DUAL
+                                 ;
+		                 
+_begin_cpu                       : BEGIN_CPU
+                                 {
+				   list_token.push_back(BEGIN_CPU);
+				 }
+                                 ;
+
+liste_attributs_cpu              : attribut_optionnel_name
+                                 ;
+		                 
+body_cpu                         : empty
+                                 | balise_internal body_cpu
+                                 | balise_type     body_cpu
+                                 | balises_latence body_cpu
+                                 ;
+		                 
+end_cpu                          : END_CPU _end_balise_dual
+                                 ;
+	                 
+// ====={ Balise "type" }=====
+// <cpu>
+// +- <type>
+
+balise_type                      : begin_type body_type end_type
+                                 ;
+	                         	     
+begin_type                       : _begin_type liste_attributs_type END_BALISE_DUAL
+                                 ;
+	                         	     
+_begin_type                      : BEGIN_TYPE
+                                 {
+				   list_token.push_back(BEGIN_TYPE);
+				 }
+                                 ;
+
+liste_attributs_type             : empty
+                                 ;
+	                         	     
+body_type                        : empty
+                                 | balises_definition           body_type
+                                 | balise_optionnel_affectation body_type
+                                 ;
+
+end_type                         : END_TYPE _end_balise_dual
+                                 ;
+
+// ====={ Balise "definition" }=====
+// <cpu> 
+// +- <type>
+//    +- <definition>
+
+balises_definition               : balise_definition
+                                 | balise_definition balises_definition
+                                 ;
+		                 
+balise_definition                : begin_definition body_definition end_definition
+                                 ;
+		                   
+begin_definition                 : _begin_definition liste_attributs_definition END_BALISE_DUAL
+                                 ;
+		                   
+_begin_definition                : BEGIN_DEFINITION
+                                 {
+				   list_token.push_back(BEGIN_DEFINITION);
+				 }
+                                 ;
+
+liste_attributs_definition       : attribut_id
+                                 ;
+
+body_definition                  : balises_allow
+                                 ;
+
+end_definition                   : END_DEFINITION _end_balise_dual
+                                 ;
+
+// ====={ Balise "allow" }=====
+// <cpu> 
+// +- <type>
+//    +- <definition>
+//       +- <allow>
+
+balises_allow                    : balise_allow
+                                 | balise_allow balises_allow
+                                 ;
+		                 
+balise_allow                     : _begin_allow liste_attributs_allow _end_singleton
+                                 ;
+		                   
+_begin_allow                     : BEGIN_ALLOW
+                                 {
+				   list_token.push_back(BEGIN_ALLOW);
+				 }
+                                 ;
+
+liste_attributs_allow            : attribut_id
+                                 ;
+
+// ====={ Balise "affectation" }=====
+// <cpu> 
+// +- <type>
+//    +- <affectation>
+
+balise_optionnel_affectation     : empty
+                                 | balise_affectation balise_optionnel_affectation
+                                 ;
+		                    
+balise_affectation               : _begin_affectation liste_attributs_affectation _end_singleton
+                                 ;
+		                    
+_begin_affectation               : BEGIN_AFFECTATION
+                                 {
+				   list_token.push_back(BEGIN_AFFECTATION);
+				 }
+                                 ;
+
+liste_attributs_affectation      : attribut_name           attribut_optionnel_type    
+                                 | attribut_optionnel_type attribut_name
+                                 ;
+
+// ====={ Balise "latence" }=====
+// <cpu> 
+// +- <latence>
+
+balises_latence                  : balise_latence
+                                 | balise_latence balises_latence
+                                 ;
+
+balise_latence                   : begin_latence body_latence end_latence
+                                 ;
+		                    
+begin_latence                    : _begin_latence liste_attributs_latence END_BALISE_DUAL
+                                 ;
+		                    
+_begin_latence                   : BEGIN_LATENCE
+                                 {
+				   list_token.push_back(BEGIN_LATENCE);
+				 }
+                                 ;
+
+liste_attributs_latence          : attribut_id
+                                 ;
+		                    
+body_latence                     : balises_operation
+                                 ;
+		                    
+end_latence                      : END_LATENCE _end_balise_dual
+                                 ;
+
+// ====={ Balise "operation" }=====
+// <cpu> 
+// +- <latence>
+//    +- <operation>
+
+balises_operation                : empty
+                                 | balise_operation balises_operation
+                                 ;
+		                 
+balise_operation                 : _begin_operation liste_attributs_operation _end_singleton
+                                 ;
+
+_begin_operation                 : BEGIN_OPERATION
+                                 {
+				   list_token.push_back(BEGIN_OPERATION);
+				 }
+                                 ;
+		                   
+liste_attributs_operation        : attribut_name              attribut_optionnel_delay   attribut_optionnel_latence
+                                 | attribut_name              attribut_optionnel_latence attribut_optionnel_delay
+                                 | attribut_optionnel_delay   attribut_optionnel_latence attribut_name
+                                 | attribut_optionnel_delay   attribut_name              attribut_optionnel_latence 
+                                 | attribut_optionnel_latence attribut_optionnel_delay   attribut_name
+                                 | attribut_optionnel_latence attribut_name              attribut_optionnel_delay   
+                                 ;
+
+// ====={ Balise "internal" }=====
+// <cpu> 
+// +- <internal>
+
+balise_internal                  : begin_internal body_internal end_internal
+                                 ;
+
+begin_internal                   : _begin_internal liste_attributs_internal END_BALISE_DUAL
+                                 ;
+
+_begin_internal                  : BEGIN_INTERNAL
+                                 {
+				   list_token.push_back(BEGIN_INTERNAL);
+				 }
+                                 ;
+		                    
+liste_attributs_internal         : empty
+                                 ;
+		                    
+body_internal                    : empty
+                                 | balise_global  body_internal
+                                 | balise_cache   body_internal
+                                 | balises_ifetch body_internal
+                                 ;
+
+end_internal                     : END_INTERNAL _end_balise_dual
+                                 ;
+
+// ====={ Balise "global" }=====
+// <cpu> 
+// +- <internal>
+//    +- <global>
+
+balise_global                    : begin_global body_global end_global
+                                 ;
+		                    
+begin_global                     : _begin_global liste_attributs_global END_BALISE_DUAL
+                                 ;
+
+_begin_global                    : BEGIN_GLOBAL
+                                 {
+				   list_token.push_back(BEGIN_GLOBAL);
+				 }
+                                 ;
+		                    
+liste_attributs_global           : empty
+                                 ;
+		                    
+body_global                      : empty
+                                 | balise_optionnel_isa body_global
+                                 | balise_size_data     body_global
+                                 | balise_scheme_bypass body_global
+                                 ;
+		                    
+end_global                       : END_GLOBAL _end_balise_dual
+                                 ;
+
+// ====={ Balise "isa" }=====
+// <cpu> 
+// +- <internal>
+//    +- <global>
+//       +- <isa>
+
+balise_optionnel_isa             : empty
+                                 | balise_isa  
+                                 ;
+
+balise_isa                       : begin_isa body_isa end_isa
+                                 ;
+		                    
+begin_isa                        : _begin_isa liste_attributs_isa END_BALISE_DUAL
+                                 ;
+		                    
+_begin_isa                       : BEGIN_ISA  
+                                 {
+				   list_token.push_back(BEGIN_ISA);
+				 }
+                                 ;
+
+liste_attributs_isa              : empty
+                                 ;
+		                    
+body_isa                         : empty
+                                 | balise_optionnel_orbis body_isa
+                                 | balise_optionnel_orfpx body_isa
+                                 | balise_optionnel_orvdx body_isa
+                                 ;
+		                    
+end_isa                          : END_ISA _end_balise_dual
+                                 ;
+
+// ====={ Balise "orbis" }=====
+// <cpu> 
+// +- <internal>
+//    +- <global>
+//       +- <isa>
+//          +- <orbis>
+
+balise_optionnel_orbis           : empty
+                                 | balise_orbis
+                                 ;
+		                 
+balise_orbis                     : _begin_orbis liste_attributs_orbis _end_singleton
+                                 ;
+
+_begin_orbis                     : BEGIN_ORBIS
+                                 {
+				   list_token.push_back(BEGIN_ORBIS);
+				 }
+                                 ;
+		                   
+liste_attributs_orbis            : attribut_value          attribut_optionnel_type 
+                                 | attribut_optionnel_type attribut_value
+                                 ;
+
+// ====={ Balise "orfpx" }=====
+// <cpu> 
+// +- <internal>
+//    +- <global>
+//       +- <isa>
+//          +- <orfpx>
+
+balise_optionnel_orfpx           : empty
+                                 | balise_orfpx
+                                 ;
+		                 
+balise_orfpx                     : _begin_orfpx liste_attributs_orfpx _end_singleton
+                                 ;
+		                   
+_begin_orfpx                     : BEGIN_ORFPX
+                                 {
+				   list_token.push_back(BEGIN_ORFPX);
+				 }
+                                 ;
+
+liste_attributs_orfpx            : attribut_value          attribut_optionnel_type 
+                                 | attribut_optionnel_type attribut_value
+                                 ;
+
+// ====={ Balise "orvdx" }=====
+// <cpu> 
+// +- <internal>
+//    +- <global>
+//       +- <isa>
+//          +- <orvdx>
+
+balise_optionnel_orvdx           : empty
+                                 | balise_orvdx
+                                 ;
+		                 
+balise_orvdx                     : _begin_orvdx liste_attributs_orvdx _end_singleton
+                                 ;
+
+_begin_orvdx                     : BEGIN_ORVDX
+                                 {
+				   list_token.push_back(BEGIN_ORVDX);
+				 }
+                                 ;
+		                   
+liste_attributs_orvdx            : attribut_value          attribut_optionnel_type 
+                                 | attribut_optionnel_type attribut_value
+                                 ;
+
+// ====={ Balise "size_data" }=====
+// <cpu> 
+// +- <internal>
+//    +- <global>
+//       +- <size_data>
+
+balise_size_data                 : _begin_size_data liste_attributs_size_data _end_singleton
+                                 ;
+
+_begin_size_data                 : BEGIN_SIZE_DATA
+                                 {
+				   list_token.push_back(BEGIN_SIZE_DATA);
+				 }
+                                 ;
+		                   
+liste_attributs_size_data        : attribut_value
+                                 ;
+
+// ====={ Balise "scheme_bypass" }=====
+// <cpu> 
+// +- <internal>
+//    +- <global>
+//       +- <scheme_bypass>
+
+balise_scheme_bypass             : _begin_scheme_bypass liste_attributs_scheme_bypass _end_singleton
+                                 ;
+
+_begin_scheme_bypass             : BEGIN_SCHEME_BYPASS
+                                 {
+				   list_token.push_back(BEGIN_SCHEME_BYPASS);
+				 }
+                                 ;
+		                   
+liste_attributs_scheme_bypass    : attribut_algo
+                                 ;
+
+// ====={ Balise "cache" }=====
+// <cpu> 
+// +- <internal>
+//    +- <cache>
+
+balise_cache                     : begin_cache body_cache end_cache
+                                 ;
+		                    
+begin_cache                      : _begin_cache liste_attributs_cache END_BALISE_DUAL
+                                 ;
+		                    
+_begin_cache                     : BEGIN_CACHE
+                                 {
+				   list_token.push_back(BEGIN_CACHE);
+				 }
+                                 ;
+
+liste_attributs_cache            : empty
+                                 ;
+		                    
+body_cache                       : empty
+                                 | balises_icache body_cache
+                                 | balises_dcache body_cache
+                                 ;
+		                    
+end_cache                        : END_CACHE _end_balise_dual
+                                 ;
+
+// ====={ Balise "icache" }=====
+// <cpu> 
+// +- <internal>
+//    +- <cache>
+//       +- <icache>
+
+balises_icache                   : balise_icache
+                                 | balise_icache balises_icache
+                                 ;
+
+balise_icache                    : begin_icache body_icache end_icache
+                                 ;
+		                    
+begin_icache                     : _begin_icache liste_attributs_icache END_BALISE_DUAL
+                                 ;
+
+_begin_icache                    : BEGIN_ICACHE
+                                 {
+				   list_token.push_back(BEGIN_ICACHE);
+				 }
+                                 ;
+		                    
+liste_attributs_icache           : attribut_id
+                                 ;
+		                    
+body_icache                      : empty
+                                 | balise_optionnel_arbiter body_icache
+                                 | balise_optionnel_nb_port body_icache
+                                 ;
+		                    
+end_icache                       : END_ICACHE _end_balise_dual
+                                 ;
+
+// ====={ Balise "dcache" }=====
+// <cpu> 
+// +- <internal>
+//    +- <cache>
+//       +- <dcache>
+
+balises_dcache                   : balise_dcache
+                                 | balise_dcache balises_dcache
+                                 ;
+
+balise_dcache                    : begin_dcache body_dcache end_dcache
+                                 ;
+		                    
+begin_dcache                     : _begin_dcache liste_attributs_dcache END_BALISE_DUAL
+                                 ;
+		                    
+_begin_dcache                    : BEGIN_DCACHE
+                                 {
+				   list_token.push_back(BEGIN_DCACHE);
+				 }
+                                 ;
+
+liste_attributs_dcache           : attribut_id
+                                 ;
+		                    
+body_dcache                      : body_icache
+                                 ;
+		                    
+end_dcache                       : END_DCACHE _end_balise_dual
+                                 ;
+
+// ====={ Balise "arbiter" }=====
+// <cpu> 
+// +- <internal>
+//    +- <cache>
+//       +- <icache>
+//       |  +- <arbiter>
+//       +- <dcache>
+//          +- <arbiter>
+
+balise_optionnel_arbiter         : empty
+                                 | balise_arbiter
+                                 ;
+		                 
+balise_arbiter                   : _begin_arbiter liste_attributs_arbiter _end_singleton
+                                 ;
+		                   
+_begin_arbiter                   : BEGIN_ARBITER
+                                 {
+				   list_token.push_back(BEGIN_ARBITER);
+				 }
+                                 ;
+
+liste_attributs_arbiter          : attribut_algo
+                                 ;
+
+// ====={ Balise "nb_port" }=====
+// <cpu> 
+// +- <internal>
+//    +- <cache>
+//       +- <icache>
+//       |  +- <arbiter>
+//       +- <dcache>
+//          +- <arbiter>
+
+balise_optionnel_nb_port         : empty
+                                 | balise_nb_port
+                                 ;
+		                 
+balise_nb_port                   : _begin_nb_port liste_attributs_nb_port _end_singleton
+                                 ;
+
+_begin_nb_port                   : BEGIN_NB_PORT
+                                 {
+				   list_token.push_back(BEGIN_NB_PORT);
+				 }
+                                 ;
+		                   
+liste_attributs_nb_port          : attribut_value
+                                 ;
+
+// ====={ Balise "ifetch" }=====
+// <cpu> 
+// +- <internal>
+//     +- <ifetch>
+
+balises_ifetch                   : balise_ifetch
+                                 | balise_ifetch balises_ifetch
+                                 ;
+
+balise_ifetch                    : begin_ifetch body_ifetch end_ifetch
+                                 ;
+		                    
+begin_ifetch                     : _begin_ifetch liste_attributs_ifetch END_BALISE_DUAL
+                                 ;
+
+_begin_ifetch                    : BEGIN_IFETCH
+                                 {
+				   list_token.push_back(BEGIN_IFETCH);
+				 }
+                                 ;
+		                    
+liste_attributs_ifetch           : attribut_id
+                                 ;
+		                    
+body_ifetch                      : empty
+                                 | balise_optionnel_nb_inst_fetch    body_ifetch 
+                                 | balise_optionnel_size_fetch_queue body_ifetch 
+                                 | balise_link_icache                body_ifetch 
+                                 | balise_link_predictor             body_ifetch 
+                                 | balise_link_decod                 body_ifetch 
+                                 ;
+		                    
+end_ifetch                       : END_IFETCH _end_balise_dual
+                                 ;
+
+// ====={ Balise "nb_inst_fetch" }=====
+// <cpu> 
+// +- <internal>
+//     +- <ifetch>
+//        +- <nb_inst_fetch>
+
+balise_optionnel_nb_inst_fetch   : empty
+                                 | balise_nb_inst_fetch
+                                 ;
+		                 
+balise_nb_inst_fetch             : _begin_nb_inst_fetch liste_attributs_nb_inst_fetch _end_singleton
+                                 ;
+
+_begin_nb_inst_fetch             : BEGIN_NB_INST_FETCH
+                                 {
+				   list_token.push_back(BEGIN_NB_INST_FETCH);
+				 }
+                                 ;
+		                   
+liste_attributs_nb_inst_fetch    : attribut_value
+                                 ;
+
+// ====={ Balise "size_fetch_queue" }=====
+// <cpu> 
+// +- <internal>
+//     +- <ifetch>
+//        +- <size_fetch_queue>
+
+balise_optionnel_size_fetch_queue: empty
+                                 | balise_size_fetch_queue
+                                 ;
+		                 
+balise_size_fetch_queue          : _begin_size_fetch_queue liste_attributs_size_fetch_queue _end_singleton
+                                 ;
+
+_begin_size_fetch_queue          : BEGIN_SIZE_FETCH_QUEUE
+                                 {
+				   list_token.push_back(BEGIN_SIZE_FETCH_QUEUE);
+				 }
+                                 ;
+		                   
+liste_attributs_size_fetch_queue : attribut_value
+                                 ;
+// ====={ Balise "link_icache" }=====
+// <cpu> 
+// +- <internal>
+//     +- <ifetch>
+//        +- <link_icache>
+		                 
+balise_link_icache               : _begin_link_icache liste_attributs_link_icache _end_singleton
+                                 ;
+
+_begin_link_icache               : BEGIN_LINK_ICACHE
+                                 {
+				   list_token.push_back(BEGIN_LINK_ICACHE);
+				 }
+                                 ;
+		                   
+liste_attributs_link_icache      : attribut_id
+                                 ;
+
+// ====={ Balise "link_predictor" }=====
+// <cpu> 
+// +- <internal>
+//     +- <ifetch>
+//        +- <link_predictor>
+		                 
+balise_link_predictor            : _begin_link_predictor liste_attributs_link_predictor _end_singleton
+                                 ;
+
+_begin_link_predictor            : BEGIN_LINK_PREDICTOR
+                                 {
+				   list_token.push_back(BEGIN_LINK_PREDICTOR);
+				 }
+                                 ;
+		                   
+liste_attributs_link_predictor   : attribut_id
+                                 ;
+
+// ====={ Balise "link_decod" }=====
+// <cpu> 
+// +- <internal>
+//     +- <ifetch>
+//        +- <link_decod>
+		                 
+balise_link_decod                : _begin_link_decod liste_attributs_link_decod _end_singleton
+                                 ;
+
+_begin_link_decod                : BEGIN_LINK_DECOD
+                                 {
+				   list_token.push_back(BEGIN_LINK_DECOD);
+				 }
+                                 ;
+		                   
+liste_attributs_link_decod       : attribut_id
+                                 ;
+
+// *****{ balise "_end_xml" }*****		       
+
+_end_xml                         : END_XML       
+                                 {
+				   list_token.pop_back();
+				 }
+
+// *****{ balise "_end_balise_dual" }*****		       
+
+_end_balise_dual                 : END_BALISE_DUAL
+                                 {
+				   list_token.pop_back();
+				 }
+
+// *****{ balise "_end_singleton" }*****		       
+
+_end_singleton                   : END_SINGLETON
+                                 {
+				   list_token.pop_back();
+				 }
+
+// *****{ Attribut_Optionnel }*****		       
+attribut_optionnel_name          : empty
+                                 | attribut_name   
+                                 ;
+
+attribut_optionnel_delay         : empty
+                                 | attribut_delay
+                                 ;
+
+attribut_optionnel_latence       : empty
+                                 | attribut_latence
+                                 ;
+
+attribut_optionnel_type          : empty
+                                 | attribut_type
+                                 ;
+
+// *****{ Type Attribut - Top level }*****
+attribut_name                    : NAME    attribut_string
+                                 {
+		                   $$ = $2;
+		                 }
+                                 ;
+
+attribut_algo                    : ALGO    attribut_string
+                                 {
+		                   $$ = $2;
+		                 }
+                                 ;
+
+attribut_value                   : VALUE   attribut_integer
+                                 {
+		                   $$ = $2;
+		                 }
+                                 ;
+
+attribut_type                    : TYPE    attribut_integer
+                                 {
+		                   $$ = $2;
+		                 }
+                                 ;
+		                 
+attribut_id                      : ID      attribut_integer
+                                 {
+		                   $$ = $2;
+		                 }
+                                 ;
+		                 
+attribut_delay                   : DELAY   attribut_integer
+                                 {
+		                   $$ = $2;
+		                 }
+                                 ;
+		                 
+attribut_latence                 : LATENCE attribut_integer
+                                 {
+		                   $$ = $2;
+		                 }
+                                 ;
+
+// *****{ Type Attribut - Bottom Level }*****
+attribut_string                  : EQUAL QUOTE STRING QUOTE
+                                 {
+		                   $$ = $3;
+		                 }
+                                 ;
+		                 
+attribut_integer                 : EQUAL QUOTE INTEGER QUOTE
+                                 {
+		                   $$ = $3;
+		                 }
+                                 ;
+		                 
+attribut_float                   : EQUAL QUOTE FLOAT QUOTE
+                                 {
+		                   $$ = $3;
+		                 }
+                                 ;
+
+empty                            : /* vide */
+%%
+
+// *** Fct auxilaire
+
+void yyerror (const char * message) 
+{
+  cerr << "Line " << lineno << " : " << message << endl;
+  cerr << "Near of token \"" << yylval.token << "\"" << endl;
+  cerr << endl;
+  
+  if (list_token.empty() == true)
+    {
+      cerr << "Invalid file, the format is :" << endl;
+      cerr << endl;
+      cerr << "  <?xml _attributs_xml ?>" << endl;
+      cerr << "  <cpu  _attributs_cpu  > _body_cpu </cpu>" << endl;
+
+      exit(-1);
+    }
+  
+  int token = list_token.back();
+  
+  switch (token)
+    {
+    case BEGIN_XML           :
+      {
+	cerr << "In balise <xml>, the format is :" << endl;
+	cerr << endl;
+	cerr << "  <?xml _attribut ?>" << endl;
+	cerr << endl;
+	cerr << "  _attribut ::= _value _encoding" << endl;
+	cerr << "  _value    ::= value=\"_float\"" << endl;
+	cerr << "  _encoding ::= encoding=\"_string\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_CPU           :
+      {
+	cerr << "In balise <cpu>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <cpu _attribut_cpu > _body_cpu </cpu>"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_cpu ::= _name"                << endl;
+	cerr << "  _name         ::= name=\"_string\""     << endl;
+	cerr << endl;
+	cerr << "  _body_cpu     ::= _type"                << endl;
+	cerr << "                  | _latence"              << endl;
+	cerr << "                  | _internal"             << endl;
+	cerr << "  _type         ::= <type     _attribut_type >     _body_type     </type>"     << endl;
+	cerr << "  _latence      ::= <latence  _attribut_latence >  _body_latence  </latence>"  << endl;
+	cerr << "  _internal     ::= <internal _attribut_internal > _body_internal </internal>" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_TYPE          :
+      {
+	cerr << "In balise <type>, the format is :"    << endl;
+	cerr << endl;
+	cerr << "  <type> _body_type </type>"          << endl;
+	cerr << endl;
+	cerr << "  _body_type    ::= [_definition]+"   << endl;
+	cerr << "                  | [_affectation]*"  << endl;
+	cerr << "  _definition   ::= <definition  _attribut_definition >  _body_definition  </definition>"  << endl;
+	cerr << "  _affectation  ::= <affectation _attribut_affectation />"                                 << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_DEFINITION    :
+      {
+	cerr << "In balise <definition>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <definition _attribut_definition > _body_definition </definition>"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_definition ::= _id"                                           << endl;
+	cerr << "  _id                  ::= id=\"_integer\""                               << endl;
+	cerr << endl;
+	cerr << "  _body_definition     ::= [_allow]+"                                     << endl;
+	cerr << "  _allow               ::= <allow _attribut_allow />"                     << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_ALLOW         :
+      {
+	cerr << "In balise <allow>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <allow _attribut_allow />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_allow ::= _id"               << endl;
+	cerr << "  _id             ::= type=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_AFFECTATION   :
+      {
+	cerr << "In balise <affectation>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <affectation _attribut_affectation />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_affectation ::= [_name]"           << endl;
+	cerr << "                          | [_type]"           << endl;
+	cerr << "  _name                 ::= name=\"_string\""  << endl;
+	cerr << "  _type                 ::= type=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_LATENCE       :
+      {
+	cerr << "In balise <latence>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <latence _attribut_latence > _body_latence </latence>"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_latence ::= _id"                               << endl;
+	cerr << "  _id               ::= id=\"_integer\""                   << endl;
+	cerr << endl;
+	cerr << "  _body_latence     ::= [_operation]*"                     << endl;
+	cerr << "  _operation        ::= <operation _attribut_operation />" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_OPERATION     :
+      {
+	cerr << "In balise <operation>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <operation _attribut_operation />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_operation ::= [_name]"              << endl;
+	cerr << "                        | [_delay]"             << endl;
+	cerr << "                        | [_latence]"           << endl;
+	cerr << "  _name               ::= name=\"_string\""     << endl;
+	cerr << "  _delay              ::= delay=\"_integer\""   << endl;
+	cerr << "  _latence            ::= latence=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_INTERNAL      :
+      {
+	cerr << "In balise <internal>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <internal> _body_internal </internal>"  << endl;
+	cerr << endl;
+	cerr << "  _body_internal    ::= _global"                           << endl;
+	cerr << "                      | _cache"                            << endl;
+	cerr << "                      | _ifetch"                           << endl;
+	cerr << "                      | ..."                               << endl;
+	cerr << "  _global           ::= <global _attribut_global> _body_global </global>" << endl;
+	cerr << "  _cache            ::= <cache _attribut_cache>   _body_cache  </cache>" << endl;
+	cerr << "  _ifetch           ::= <ifetch _attribut_ifetch> _body_ifetch </ifetch>" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_GLOBAL        :
+      {
+	cerr << "In balise <global>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <global> _body_global </global>"  << endl;
+	cerr << endl;
+	cerr << "  _body_global    ::= _size_data"                       << endl;
+	cerr << "                    | _scheme_bypass"                   << endl;
+	cerr << "                    | [_isa]*"                          << endl;
+	cerr << "  _size_data        ::= <size_data     _attribut_size_data />" << endl;
+	cerr << "  _scheme_bypass    ::= <scheme_bypass _attribut_scheme_bypass />" << endl;
+	cerr << "  _isa              ::= <isa           _attribut_isa> _body_isa </isa>" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_SIZE_DATA     :
+      {
+	cerr << "In balise <size_data>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <size_data _attribut_size_data />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_size_data ::= _value"             << endl;
+	cerr << "  _value              ::= value=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_SCHEME_BYPASS :
+      {
+	cerr << "In balise <scheme_bypass>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <scheme_bypass _attribut_scheme_bypass />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_scheme_bypass ::= _algo"             << endl;
+	cerr << "  _algo                   ::= algo =\"_string\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_ISA           :
+      {
+	cerr << "In balise <isa>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <isa> _body_isa </isa>"  << endl;
+	cerr << endl;
+	cerr << "  _body_isa    ::= [_orbis]"                  << endl;
+	cerr << "                 | [_orfpx]"                  << endl;
+	cerr << "                 | [_orvdx]"                  << endl;
+	cerr << "  _orbis       ::= <ORBIS _attribut_orbis />" << endl;
+	cerr << "  _orfpx       ::= <ORFPX _attribut_orfpx />" << endl;
+	cerr << "  _orvdx       ::= <ORVDX _attribut_orvdx />" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_ORBIS         :
+      {
+	cerr << "In balise <ORBIS>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <ORBIS _attribut_orbis />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_orbis ::= _value"             << endl;
+	cerr << "                    | [_type]"            << endl;
+	cerr << "  _type           ::= type=\"_integer\""  << endl;
+	cerr << "  _value          ::= value=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_ORFPX         :
+      {
+	cerr << "In balise <ORFPX>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <ORFPX _attribut_orfpx />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_orfpx ::= [_type]"            << endl;
+	cerr << "                    | [_value]"           << endl;
+	cerr << "  _type           ::= type=\"_integer\""  << endl;
+	cerr << "  _value          ::= value=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_ORVDX         :
+      {
+	cerr << "In balise <ORVDX>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <ORVDX _attribut_orvdx />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_orvdx ::= [_type]"            << endl;
+	cerr << "                    | [_value]"           << endl;
+	cerr << "  _type           ::= type=\"_integer\""  << endl;
+	cerr << "  _value          ::= value=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_CACHE         :
+      {
+	cerr << "In balise <cache>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <cache> _body_cache </cache>"  << endl;
+	cerr << endl;
+	cerr << "  _body_cache    ::= [_icache]+"                  << endl;
+	cerr << "                   | [_dcache]+"                  << endl;
+	cerr << "  _icache        ::= <icache _attribut_icache /> _body_icache </icache>" << endl;
+	cerr << "  _dcache        ::= <dcache _attribut_dcache /> _body_dcache </dcache>" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_ICACHE        :
+      {
+	cerr << "In balise <icache>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <icache _attribut_icache > _body_icache </icache>"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_icache ::= _id"                           << endl;
+	cerr << "  _id              ::= id=\"_integer\""               << endl;
+	cerr << endl;
+	cerr << "  _body_icache     ::= [_arbiter]"                    << endl;
+	cerr << "                     | [_nb_port]"                    << endl;
+	cerr << "  _arbiter         ::= <arbiter _attribut_arbiter />" << endl;
+	cerr << "  _nb_port         ::= <nb_port _attribut_nb_port />" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_DCACHE        :
+      {
+	cerr << "In balise <dcache>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <dcache _attribut_dcache > _body_dcache </dcache>"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_dcache ::= _id"                           << endl;
+	cerr << "  _id              ::= id=\"_integer\""               << endl;
+	cerr << endl;
+	cerr << "  _body_dcache     ::= [_arbiter]"                    << endl;
+	cerr << "                     | [_nb_port]"                    << endl;
+	cerr << "  _arbiter         ::= <arbiter _attribut_arbiter />" << endl;
+	cerr << "  _nb_port         ::= <nb_port _attribut_nb_port />" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_ARBITER	     :
+      {
+	cerr << "In balise <arbiter>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <arbiter _attribut_arbiter />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_arbiter ::= _algo"            << endl;
+	cerr << "  _algo             ::= algo=\"_string\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_NB_PORT       :
+      {
+	cerr << "In balise <nb_port>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <nb_port _attribut_nb_port />"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_nb_port ::= _value"             << endl;
+	cerr << "  _value            ::= value=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_IFETCH        :
+      {
+	cerr << "In balise <ifetch>, the format is :"         << endl;
+	cerr << endl;
+	cerr << "  <ifetch _attribut_ifetch > _body_ifetch </ifetch>"  << endl;
+	cerr << endl;
+	cerr << "  _attribut_ifetch  ::= _id"                           << endl;
+	cerr << "  _id               ::= id=\"_integer\""               << endl;
+	cerr << endl;
+	cerr << "  _body_ifetch      ::= [_nb_inst_fetch]"              << endl;
+	cerr << "                      | [_size_fetch_queue]"           << endl;
+	cerr << "                      | _link_icache"                  << endl;
+	cerr << "                      | _link_predictor"               << endl;
+	cerr << "                      | _link_decod"                   << endl;
+	cerr << "  _nb_inst_fetch    ::= <nb_inst_fetch    _attribut_nb_inst_fetch    />" << endl;
+	cerr << "  _size_fetch_queue ::= <size_fetch_queue _attribut_size_fetch_queue />" << endl;
+	cerr << "  _link_icache      ::= <link_icache      _attribut_link_icache      />" << endl;
+	cerr << "  _link_predictor   ::= <link_predictor   _attribut_link_predictor   />" << endl;
+	cerr << "  _link_decod       ::= <link_decod       _attribut_link_decod       />" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_NB_INST_FETCH :
+      {
+	cerr << "In balise <nb_inst_fetch>, the format is :"       << endl;
+	cerr << endl;
+	cerr << "  <nb_inst_fetch _attribut_nb_inst_fetch />"      << endl;
+	cerr << endl;
+	cerr << "  _attribut_nb_inst_fetch ::= _value"             << endl;
+	cerr << "  _value                  ::= value=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_SIZE_FETCH_QUEUE :
+      {
+	cerr << "In balise <size_fetch_queue>, the format is :"       << endl;
+	cerr << endl;
+	cerr << "  <size_fetch_queue _attribut_size_fetch_queue />"   << endl;
+	cerr << endl;
+	cerr << "  _attribut_size_fetch_queue ::= _value"             << endl;
+	cerr << "  _value                     ::= value=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_LINK_ICACHE         :
+      {
+	cerr << "In balise <link_icache>, the format is :"      << endl;
+	cerr << endl;
+	cerr << "  <link_icache _attribut_link_icache />"       << endl;
+	cerr << endl;
+	cerr << "  _attribut_link_icache ::= _id"               << endl;
+	cerr << "  _id                   ::= type=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_LINK_PREDICTOR         :
+      {
+	cerr << "In balise <link_predictor>, the format is :"      << endl;
+	cerr << endl;
+	cerr << "  <link_predictor _attribut_link_predictor />"    << endl;
+	cerr << endl;
+	cerr << "  _attribut_link_predictor ::= _id"               << endl;
+	cerr << "  _id                      ::= type=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    case BEGIN_LINK_DECOD         :
+      {
+	cerr << "In balise <link_decod>, the format is :"      << endl;
+	cerr << endl;
+	cerr << "  <link_decod _attribut_link_decod />"        << endl;
+	cerr << endl;
+	cerr << "  _attribut_link_decod ::= _id"               << endl;
+	cerr << "  _id                  ::= type=\"_integer\"" << endl;
+	cerr << endl;
+	break;
+      }
+    default                  :
+      {
+	cerr << "Internal error : Unknow token (" << token << "). Please contact the Tools maintener" << endl;
+      }
+    }// end switch
+  
+  exit (1);
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/common/bibliographie.bib
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/common/bibliographie.bib	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/common/bibliographie.bib	(revision 3)
@@ -0,0 +1,1979 @@
+@book{1983_Lee,
+  title={{Analysis of Branch Prediction Strategies and Branch Target Buffer Design}},
+  author={Lee, J.K.F. and Smith, A.J.},
+  year={1983},
+  publisher={Computer Science Division (EECS), University of California}
+}
+@article{1991_kaeli,
+  title={{Branch history table prediction of moving target branches due to subroutine returns}},
+  author={Kaeli, D.R. and Emma, P.G.},
+  journal={Proceedings of the 18th annual international symposium on Computer architecture},
+  pages={34--42},
+  year={1991},
+  publisher={ACM Press New York, NY, USA}
+}
+@article{scherson1991ogc,
+  title={{Orthogonal graphs for the construction of a class ofinterconnection networks}},
+  author={Scherson, ID},
+  journal={Parallel and Distributed Systems, IEEE Transactions on},
+  volume={2},
+  number={1},
+  pages={3--19},
+  year={1991}
+}
+@article{1991_wall,
+  title={{Wall, Limits of instruction-level parallelism}},
+  author={David, W.},
+  journal={Proceedings of the fourth international conference on Architectural support for programming languages and operating systems},
+  pages={176--188},
+  year={1991}
+}
+
+01/12/2004
+
+Etude sur le niveau de parallélisme d'un programme => l'ILP ne dépasse pas 5-7 instructions
+Ceci déterminera la viabilité d'ajout de mécanismes pour traiter en parralléle un maximum d'instructions (superscalaire, renommage de registre etc..)
+               #instruction
+Parrallelism = -------------
+               #cycle requit
+
+Le parallélisme est en moyenne de 3-4 inst. Peut être plus haut (ex. Programme numérique). Le profit d'une crête de parrallélisme est bas si la moyenne est basse.
+
+Augmenter l'ILP : 2 variétés de techniques :
+ a) Parrallélisme dans un bloc de base
+ b) Parrallélisme entre plusieurs blocs de base
+
+a) limité par les dépendances entre paire d'instructions
+    -> Renommage de registres (Hardware ou Software). Les compilos préfére utilisé le moins de registres possibles.
+    -> Pur les dépendances d'adresse mémoire => analyse d'alias
+b) Nombre d'instructions entre 2 branchements est en moyenne moins de 6 instructions
+    -> Prédiction de branchement pour exécuter de manière spéculatives les blocs de bases
+    -> Déroullement de boucles => augmentation de la taille des blocs de base
+    -> Pipeline logiciel => augmente le parallélisme au sein d'un bloc
+    -> Ordonnanceur de trace => trace : séquence de blocs souvent éxecuté
+
+CADRE DE TRAVAIL:
+
+* Execution du programme pour produire une trace d'execution
+* Algorithme va "paquetiser" ses instructions en groupe d'instruction non suspendu => on tente d'avoir 64 inst en //
+* Pas de limites d'unité fonctionnelle ni de limite d'accès au banc de registres. Chaque instruction à une latence d'un cycle, de même pour les opérations mémoires
+* L'execution se faire par groupe de paquet, si la suspension à également lieu dans le modèle, alors le paquet suivant sera exécuter le cycle suivant. Sinon, nous pouvons l'exécuter le même cycle.
+
+Le parrallélisme sera donc le nombre d'instruction par le nombre de cycles
+
+Paramètres :
+Register renamings : Parfait(nombre infinie de registres)
+                     finit (allocation dynamique => LRU, 256 registres entier, 256 flottant)
+                     aucun
+Prédiction de branchement : Prédiction parfaite (tjs correctement prédit)
+                            finit (dynamique) (prédiction d'un schéma à 2 bits , avec une table à 2048 entrées)
+                            finit (statique)  (tjs la même prédiction (dépendant de la prédiction parfaite))      
+                            aucun -> prédiciton tjs faux
+Idem pour le jump prediction
+analyse d'alias : Parfait (Il y a un conflit d'adresse que si l'adresse d'une écriture est la même qu'une autre écriture ou lecture)
+                  Aucune analyse (Une écritures sont en conflits avec chaque autre écriture et lecture)
+                  inspection d'instruction => pas de conflits si même registre de base mais dpt différent
+                                                              si registre de base différent (Mais explecitement différent ex utilisation de sp et gp qui sont deux pointeurs différents)
+                  analyse par le compilateur => analyse parfaite de la pile et des références globales
+Taille de la fenêtre : Nombre maximum d'instructions pouvant apparaître dans un cycle de traitement
+                     => Gestion de la fenêtre de manière discrète (Chercher une fênetre entière)
+                                                         continue (Chercher autant d'instruction qui viennent de ce terminer)
+
+Définitions de 5 modèles :
+
+          +----------------+--------------+--------------+----------------+
+          | branch Perfect | Jump predict | Reg renaming | Alias analysis |
++---------+----------------+--------------+--------------+----------------+
+| Stupid  | none           | none         | none         | none           |
+| Fair    | infinite       | infinite     | 256          | inspection     |
+| Good    | infinite       | infinite     | 256          | perfect        |
+| Great   | infinite       | infinite     | perfect      | perfect        |
+| Perfect | perfect        | perfect      | perfect      | perfect        |
++---------+----------------+--------------+--------------+----------------+
+
+Pour une taille de fenêtre de 2048 instructions ( continue)
+
+Sur les jeux de tests, on notera que le parrallélisme du modèle :
+ - stupide ne dépasse pas 2 
+ - pauvre  ne dépasse pas 4
+ - Great   ne dépasse pas 8 sauf pour quelque modèle numérique qui exploite l'analyse des alias 
+ - Parfait 
+
+Le déroullage de boucles à un effet significatif pour les modèles ambitieux. Sinon, ceci est limite par les load de début de boucle et les stores de fin de boucles (càd réduite par les technique d'alias analysis)
+
+Taille de la fenêtre
+
+La modification de la taille de la fenêtre n'influe que sur les modèles ambitieux grâce à leur technique de prediction améliorer. La plupart des benchmarks ont besoin que d'une fenêtre de 32 inst
+Avec une gestion de fenêtre demanière discrete, cela exploite moins de parrallélisme (- d'inst prete)
+
+Effet des predictions de branchements :
+
+Réduire le niveau de la prédiction de branchment à un impact significatif sur le parrallélisme (Beaucoup moins d'instructions prête à être executer). Mais réduire le niveau de la prédiction de saut n'a d'effet que si la prédiction de branchement est parfaite.
+De plus sur le modèle parfait, l'augmentation de la latence d'un miss à un effet significatif sur le parrallélisme (Car les instructions feteched ne sont plus executé en parralléle car les instructions précédentes sont déjà terminées)
+
+Effet du rennommage de registres et de l'analyse des alias
+
+L'analyse d'alias par inspection n'est pas très performantes (augmente l'ILP de 0.5). L'analyse par compilation n'est performante que pour des programmes utilisant la pile .
+Le nombre de registre pour le renomage de registres n'influe que très peu sur le parallélisme dans un modèle où les prédictions ne sont pas parfaite (à l'exception faite des programmes ayant beaucoup de dépendance)
+
+CONCLUSION
+
+Une bonne prédiction (hard ou soft) est un facteur déterminant pour l'augmentation de l'ILP. Le renommage de registres est important si le compilateur l'exploite.
+Le parrallelism moyen tourne autour de 5 d'après cette étude. (Dans un contexte très favorable => latence des inst = 1, etc...)
+@article{1992_pan,
+  title={{Improving the accuracy of dynamic branch prediction using branch correlation}},
+  author={Pan, S.T. and So, K. and Rahmeh, J.T.},
+  journal={Proceedings of the fifth international conference on Architectural support for programming languages and operating systems},
+  pages={76--84},
+  year={1992},
+  publisher={ACM Press New York, NY, USA}
+}
+@article{1992_yeh,
+  title={{Alternative Implementations of Two-Level Adaptive Branch Prediction}},
+  author={Yeh, T.Y. and Patt, YN},
+  journal={Computer Architecture, 1992. Proceedings., The 19th Annual International Symposium on},
+  pages={124--134},
+  year={1992}
+}
+@techreport{1993_mcfarling,
+  title={{Combining Branch Predictors}},
+  author={McFarling, S.},
+  institution={Technical Report WRL Technical Note TN-36, Digital Equipment Corporation, June 1993}
+}
+@article{1993_Perleberg,
+  title={{Branch target buffer design and optimization}},
+  author={Perleberg, CH and Smith, AJ},
+  journal={Computers, IEEE Transactions on},
+  volume={42},
+  number={4},
+  pages={396--412},
+  year={1993}
+}
+@article{1993_yeh,
+  title={{A comparison of dynamic branch predictors that use two levels of branch history}},
+  author={Yeh, T.Y. and Patt, Y.N.},
+  journal={Proceedings of the 20th annual international symposium on Computer architecture},
+  pages={257--266},
+  year={1993},
+  publisher={ACM Press New York, NY, USA}
+}
+@InProceedings{1995_sohi,
+  author = 	 {Sohi, G.S.     and
+                  Breach, S.E.   and
+                  Vijaykumar, T.N. },
+  title = 	 {Multiscalar processors},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Computer Architecture, 1995. Proceedings. 22nd Annual International Symposium on},
+  OPTpages = 	 {414-425},
+  OPTyear = 	 {1995},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Santa Margherita Ligure  ,   Italy},
+  OPTmonth = 	 {22-24 Jun},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+22/02/2005
+
+Paradigme de base : fetch-execute - pointé par un program counter
+                    -> sous entend que les instructions vont être executer dans le même ordre que le programme.
+
+processeur ILP et les compilos désordonne le programme en respectant toutefois les dépendances sur les données et les controles.
+Les dépendances de contrôles peuvent être représenté par un "control flow graph" -> bloc de bases sont représenté par des noeuds et les arcs représentent les flots de contrôles
+
+Overview
+--------
+Objectif : A partir du "control flow graph" (CFG), on peut établir une fenêtre dynamique d'instruction pouvant être extré et lancé.
+
+le CFG peut être vut : - instruction / instruction
+                       - bloc / bloc
+                       - tâche / tâche (thread)
+
+Assignation d'une tâche à une unité d'execution.
+Le multiscalar à une collection d'unité d'execution et un séquenceur s'occupant de distribuer les tâches au UE.
+
+=> Obligation de maintenir l'ordre séquentielle de consommation et de production de données (registre ou accès mémoire)
+ Synchronisation  des accès mémoires 
+ - approche conservatrice : Attendre que les accès mémoires des tâches moins spéculatives soit terminer
+ - approche aggréssive    : Réaliser des chargements spéculatifs (vérif dynamique si une tâche moins spéculatifs écrit dans un zone chargé spéculativement.)
+
+Le contrôle et les accès aux données peuvent être spéculative. -> Mécanisme de "Retour en arrière" et de commit
+Gestion circulaire des tâches : La tâche en tête n'est jamais spéculative. On retire les tâches de manière circulaire.
+
+Software
+~~~~~~~~
+ - Le séquenceur a besoin des informations sur le CFG.
+ - Il faut caractériser une tâche par les données consommés et les données produites.
+   |-> Analyse statique par la compilation et création d'un "create mask" indiquant quel registres sont produits par la tâche.
+   |-> Noté quel est la dernière instructions produisant le registre pour pouvoir ensuite le forwarder.
+
+Hardware
+~~~~~~~~
+Hardware -> lancement des tâches vers une unités d'execution
+         -> Maintient d'une execution séquentielle apparente
+
+Le séquenceur détermine l'ordre des tâches. (Charge le descripteur de tâche et à partir de la va charger la tâche, creer les différent masqie et déterminer (ou prédit) la prochaine tâche à executer)
+
+Les accès à la mémoire donnée sont réalisées par le Address résolution buffer (ARB) qui gére la spéculation, dépendance ...
+
+Distribution des cycles pour l'execution
+----------------------------------------
+Relacement d'un calcul si :
+ - utilisation d'une valeur incorrect
+ - prediction incorrect
+
+Pour cela :
+ a) Synchronisation des communications de données
+
+ b) Détermination de la prediction :
+  - Registre pas de problèmes
+  - Accès mémoires : synchronisé explicitement
+Pour les prédictions -> Valider la prédiction au plus tôt : 
+  * intruction explicite de validation de prediction
+  * changer la structure de la bcl afin de tester la condition au + tôt
+
+
+Cycle idle          : aucune unité de calculs n'a de tâches à executer
+Cycle de non calcul : les unités ont des tâches mais ne peux pas les executer
+ - Dépendances intra-tâche : dépendance entre instructions d'une même tâche (désordonnancement, cache non bloquant etc ...)
+ - Dépendances inter-tâche : dépendance entre tâches (calculs de la condition de la boucle à la fin du corps de bcl etc ...)
+
+Conclusion
+----------
+Exploite l'ILP. Pour cela utilisation d'une combinaison hardware/software afin d'extraire l'ILP
+ -> division le CFG en tâche 
+ -> traverser le CFG de manière spéculative
+ -> Les tâches sont distribués à une collection d'unité d'execution.
+ -> Chaque unité d'execution fetche et execute les instructions de la tâche associées
+ -> Processeurs utilise plusieurs PCs  afin de pouvoir séquencer plusieurs parties différente du CFG.
+@InBook{         1996_mudge,
+  ALTauthor = 	 {trevor mudge},
+  ALTeditor = 	 {},
+  title = 	 {ACM Computing Surveys (CSUR)},
+  chapter = 	 { Special ACM 50th-anniversary issue: strategic directions in computing research},
+  publisher = 	 {ACM Press   New York, NY, USA },
+  year = 	 {1996},
+  OPTkey = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTtype = 	 {},
+  OPTaddress = 	 {},
+  OPTedition = 	 {},
+  OPTmonth = 	 {december},
+  OPTpages = 	 {671 - 678},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+01/12/2004
+
+Architecture des ordinateurs est un degré significatif sur les activités de l'ingénieurs pour trouver une solution à un problem avec une contrainte de coûts.
+
+Tendance -> a) resulte d'un apport de la technologie (ex. techno micronique et submicronique)
+         -> b) resulte d'un contexte d'application (ex. Multi processings => ajout de mécanisme de tâches)
+a) Défi : Consommation (Au premier ordre conso est proportionnel à la fréquence, loi de moore : Double la fréquence tous les Deux ans donc double la conso)
+          Latence : La fréquence d'horloge croit plus vite que la technologie des Rams : f(CPU) +50\%/an , vitesse(DRAM) +10\%/an
+b) application guide les architectures : Les processeurs deviennent de + en + grand public  (jeux 3D, multimédia etc..). Avant ils étaient surtout utilisé par des militaires. 
+
+L'auteur voit 3 challenges pour la prochaine décade (càd jusqu'en 2006)
+-> Puissance et taille
+-> Performance
+-> Complexité
+
+Axes de recherches
+-> locality
+-> Paralélisme
+-> Prédictabilité
+
+Paralélisme au niveau instructions (ILP) -> Approche VLIW et superscalaire
+            au niveau application  -> Simultaneous multithreadings (SMT)
+
+l'idée de ce SMT viens du processeur HEP devellopper par denelcor vers la fin des années 70
+
+Hierarchie mémoire => nécessité de masquer la latence des accès mémoires (technique de prefetching => utilisation de la bande passante innoccupé en vue d'aller chercher des instructions potentiellement utiles)
+
+Evolution des benchmarks pour prendre en compte des évolutions de marché pour le processeurs (c'est à dire bench "multimédia")
+@InProceedings{,
+  author = 	 { Kunle Olukotun  and
+                   Basem A. Nayfeh and
+                   Lance Hammond   and
+                   Ken Wilson      and
+                   Kunyung Chang 	
+                 },
+  title = 	 {the case for a single-chip multiprocessor},
+  OPTcrossref =  {ISBN:0-89791-767-7},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the seventh international conference on Architectural support for programming languages and operating systems},
+  OPTpages = 	 {2-11},
+  OPTyear = 	 {1996},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Cambridge, Massachusetts, United States},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = {ACM Press},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+24/01/2005
+
+Opposition entre un mono-processeur compléxe et des multi-processeurs simple.
+
+Comparaison entre un processeur super scalaire 6 voies à ordonnancement dynamique et 4 processeurs superscalaire 2 voies. 
+Un superscalaire est décomposé en 3 phases :
+
+                     |----| <-> E
+           |----| -> |    | <-> E
+ICache <-> | IF | -> | IR | <-> E
+           |----| -> |    | <-> E
+                     |----| <-> E
+
+- Instructions fetch => fournir le maximum d'instruction prête.
+  Limitation : 
+   * Branchement mal prédit (degré de spéculation)
+   * Instruction mal aligné
+   * Miss de caches
+- Issue and retirement 
+  Rennommage : 
+   * Table de mappage (nb_opérande * nb_voie_scalaire   ports de lecture)
+   * Reorder buffer   (nb_bit_codage_registre * Taille_file_instruction_issue * nb_opérande * nb_voie_scalaire
+- Execution
+  Augmentation du temps de cycle lors de l'écriture si beaucoup de voie scalaire
+  Compléxité du by-pass (augmentation quadratique en fonction du nombre d'unité d'execution)
+
+Single-Chip Multiprocessor
+--------------------------
+1) -> Les OS actuelles sont multi processus => fort parrallélisme
+2) -> Les processus sont également multi thread
+3) -> Les appli mono thread peuvent être découper en thread de manière hard. assez contraignant.
+
+Architecture pour comparaison
+-----------------------------
+
+* Super Scalaire => R10000 de degré 4 à 6. (Augmentation des caractéristiques pour arriver à 430 mm2)
+* Multi proc     => 4 * R10000 de degré 2  (Diminution   des caractéristiques pour arriver à 430 mm2)
+
+=> Même surface de silicium pour les deux architectures.
+
+Performance
+-----------
+Gel d'un proceeseur dut au miss de cache. 
+Superscalaire -> execution désordonné, spéculative, cache non bloquant. Masquage des couts de Miss.
+
+Mesure de performance : Gain par rapport à la version MP - 1 proc.
+- Sur les applications avec peu de parallélismes, le superscalaire est plus performant car exploite mieux l'ILP.
+- Sur les applications avec un grain fin de parallélisme et beaucoup de communication, l'approche SS et MP est équivalente (Les deux approches exploite le parrallélisme grain fin)
+- Sur les applications avec un large degré de parallélisme, le multi proc prend l'avantage. Car le parrallélisme dépasse la fenêtre du supersclaire.
+
+
+=> l'approche SS est limité par l'ILP du programme, et le matériel nécessaire (lancement dynamique et banc de registres) augmente de manière quadratique le matériel et donc le temps de cycle.
+
+@article{1996_tullsen,
+  title={{Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor}},
+  author={Tullsen, D.M. and Eggers, S.J. and Emer, J.S. and Levy, H.M. and Lo, J.L. and Stamm, R.L.},
+  journal={Proceedings of the 23rd annual international symposium on Computer architecture},
+  pages={191--202},
+  year={1996},
+  publisher={ACM Press New York, NY, USA}
+}
+
+16/03/2005
+
+Préentation d'un architecture SMT suivant 3 contraintes :
+ - Minimiser l'impact par rapport à une architecture Superscalaire
+ - Minimiser la perte de performance lors de l'execution de programme monothread
+ - Avoir un gain de performance lors de l'execution de programme multithread
+
+Architecture SMT
+----------------
+L'article dérive un Supersclaire classique 
+(Fetch unit, Decode, Register renaming, wait\_queue, lecture des registres, unités d'executions, commit).
+Les instructions sont lancées dans le désordre, retiré dans l'ordre
+
+Changement minimum à apporter :
+ - un pc/thread et un thread séquenceur
+ - une pile de retour séparé (pour la prédiction de retours)
+ - Par thread : mécanisme pour retirer les instructions, file d'instructions à retirer et mécanisme de trape
+ - un thread id pour le BTB
+ - un large banc de registres
+
+Note : les instructions présente dans la file d'executions sont partagé par plusieurs threads donc grâce au mécanisme de renommage, on ne sélectionne que les instructions indépendante
+
+Conséquence :
+
+* Un pc est prioritaire (choisit de manière round robin)
+* Taille du banc de registres conséquents impose l'augmentation de la profondeur du pipeline.
+
+Performance
+~~~~~~~~~~~
+L'architecture gère 8 threads.
+
+Remarque : Si un seul thread est utilisé, il y a une perte de 2\% sur l'IPC par rapport au superscalaire de référence dut à l'augmentation du pipeline.
+
+Goulot d'étranglement :
+- Taille des files d'instructions : à cause de l'augmentation de l'IPC, elle deviennent souvent pleines
+- l'étage ifetch n'a pas la connaissance que les files sont pleines donc continue à fétché des instructions.
+- manque de parrallélisme : à cause des fausses instructions.
+
+Fetch Unit
+----------
+Il y à un partage de la bande passante de fetch avec tous les threads.
+ -> le fetch unit peut choisir parmit plusieurs source, donc incrémenter l'utilisation de la bande passante (car si un thread est bloqué, les autres ne le sont pas forcément)
+ -> le fetch unit peut choisir pour quels threads travailler (si un thread n'est pas bloqué mais qu'il réalise beaucoup de miss de spéculation, alors il est peut profitable de lui chargé des instructions qui auront de fortes chances d'être fausse)
+
+Définition de plusieurs stratégie de fetchs, classement suivant 3 critères :
+
+ 1) Partionnement du l'unité d'ifetch parmis les threads
+ 2) Efficacité de l'unité de fetch (Qualité des instructions chargés)
+ 3) Disponiblitité de l'unité de fetch (Elimination des conditions de blockage de l'unité)
+
+1) Partitionnement
+~~~~~~~~~~~~~~~~~~
+L'unité fetch charge jusqu'a 8 instructions par cycle.
+Mais comme les blocs de bases sont plutôt petit, il est difficille d'exploiter complétement la bande passante utilement pour un thread.
+ -> Partage des 8 instructions parmit plusieurs threads. Le cache reste identique mais est découpé en plusieurs banc, deux threads peuvent intérrogé deux bancs différents
+
+1.8 (1 threads ayant 8 instructions) -> blocs trop petits 
+2.4 - 4.2                            -> idéal
+8.1                                  -> Il n'y a pas assez de threads non bloqué
+
+Ajout de matériel : Mutipléxeur d'adresse, plusieurs buses d'adresse; logique de sélection des tristates de sorties, logique de conflit de bancs, duplication de la logique de calcul des hit/miss
+=> Augmente la latence du cache mais réduit la latence du bloc decode et rename (car moins de dépendance à calculer)
+
+autre vision : 
+2.8 -> le premier thread est prioritaire et peut charger jusqu'a 8 instructions, s'il n'y arrive pas un autre thread oeut tenter de combler le manque.
+c'est la méthode la plus performante car elle permet de gère la bande passante parmit plusieurs threads et d'avoir un partitionnement flexible.
+
+2) Algorithme
+~~~~~~~~~~~~~
+Algorithme de décision sur le thread prioritaire : Déterminer le meilleur "thread"
+ a) probabilité de ne pas charger un faux chemin
+ b) temps prit par l'instructions pour être executable
+
+* Round-robin
+* BRCOUNT     -> Favorise le thread qui à le moins de branchement non résolue (améliore a)
+* MISSCOUNT   -> Favorise le thread qui à le moins de miss de donnée (améliore b)
+* ICOUNT      -> Favorise le thread qui à le moins d'instructions dans les étages D R IQ (IQ = Instruction queue) (améliore b)
+* IQPOSN      -> Donne la plus basse priorité au thread la plus proche de la tête des files d'attente (améliore b) (la plus vieille instruction) (Ne requiert pas de compteur)
+
+ICOUNT et IQPOSN sont les deux algos les plus performants.
+
+3) Disponibilité
+~~~~~~~~~~~~~~~~
+Condition de blocage du fetch unit : IQ full, Icache miss.
+
+* BIGQ -> Augmentation de la taille du IQ sans augmenter la taille de la zone de recherche
+* ITAG -> Scrute le cache un cycle plutôt est on sélectionne que les threads qui ne vont pas faire de miss
+
+Choix de l'instruction à lancé
+------------------------------
+
+Superscalaire : le degré de spéculation est croissant avec sa position dans l'IQ
+Dans un SMT, ceci n'est pas vrai. 
+
+* OLDEST
+* OPT\_LAST     -> Optimiste
+* SPEC\_LAST    -> Spéculatif en dernier (les instructions sont spéculatifs sont prioritaires)
+* BRANCH\_FIRST -> Branchement sont prioritaires (afin de connaître si un branchement est spéculatif)
+ 
+Les performances n'influe pas énormément -> la bande passante du lancement n'influe pas sur les performances.
+
+Goulot d'étranglement
+---------------------
+Bande passante du lancement      -> non
+Taille de la file d'instructions -> non
+Bande passante du fetch          -> oui : la fréquence des sauts et les problèmes d'alignements du pc ne permet pas d'utiliser entièrement la bande passante.
+Prédiction de branchement        -> non : Le SMT est plus tolérant au mauvaise prédiction qu'un superscalaire classique. plus il y a de threads, plus ils seront entrelacés donc moins d'instructions seront chargé après un branchement.
+Execution spéculative            -> non, mais un SMT bénéficie beaucoup moins de l'apport de l'execution spéculative.
+Sortance de la mémoire           -> non
+Taille du banc de registres      -> oui : Temps d'accès devient limitant
+
+
+
+
+
+@InProceedings{1996_wallace,
+  author = 	 {Wallace, S.     and
+                  Bagherzadeh, N.    },
+  title = 	 {A scalable register file architecture for dynamically scheduled processors},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Parallel Architectures and Compilation Techniques, 1996., Proceedings of the 1996 Conference on},
+  OPTpages = 	 {179-184},
+  OPTyear = 	 {1996},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Boston, MA, USA},
+  OPTmonth = 	 {Oct},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+01/04/2005
+
+Abstract
+--------
+
+A major obstacle in designing dynamically scheduled processors is the size and port requirement of the register file. By using a multiple banked register file and performing dynamic result renaming, a scalable register file architecture can be implemented without performance degradation. In addition, a new hybrid register renaming technique to efficiently map the logical to physical registers and reduce the branch misprediction penalty is introduced. The performance was simulated using the SPEC95 benchmark suite
+
+@article{1996_yeager,
+  title={{The Mips R10000 superscalar microprocessor}},
+  author={Yeager, KC},
+  journal={Micro, IEEE},
+  volume={16},
+  number={2},
+  pages={28--41},
+  year={1996}
+}
+@article{burger1997sts,
+  title={{The SimpleScalar tool set, version 2.0}},
+  author={Burger, D. and Austin, T.M.},
+  journal={ACM SIGARCH Computer Architecture News},
+  volume={25},
+  number={3},
+  pages={13--25},
+  year={1997},
+  publisher={ACM Press New York, NY, USA}
+}
+@InProceedings{1997_palacharla,
+  author = 	 {Palacharla, S.  and
+                  Jouppi, N.P.    and
+                  Smith, J.E.   },
+  title = 	 {Complexity-Effective Superscalar Processors},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Computer Architecture, 1997. Conference Proceedings. The 24th Annual International Symposium on},
+  OPTpages = 	 {206 - 218},
+  OPTyear = 	 {1997},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {},
+  OPTmonth = 	 {Jun},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+07/02/2005
+
+=> Perte de performances du au matériel très couteux.
+
+2 directives pour fabriquer un mono processeurs :
+ - Le compléxifier le matériel afin d'extraire encore plus le nombre d'instructions lancée
+ - Le rendre plus simple afin d'avoir une plus grande fréquence d'horloge
+
+Source de compléxité
+--------------------
+
+Modèle de pipeline typique :
+
+1) FETCH             Lecture de plusieurs instructions, prediction de branchement
+2) DECODE            Décodage d'instruction
+3) RENAME            renommage de registre, dispatchement dans la fenêtre d'isntructions
+4) SELECT/ISSUE      Une fois qu'une instruction à ces opérandes => prête à être lancé -> Envoie vers l'UF approprié
+5) REG READ          Prise des opérandes / bypass
+6) EXECUTE/BY PASS   Execution
+7) DCACHE ACCESS     Accès mémoire
+8) REG WRITE/COMMIT  Accès dans les registres et valdiation (instruction non spéculatif et non érroné)
+
+Dépendance de complexité :
+- Largeur/profondeur de la fenêtre de lancement
+- Structure "Dispatch et issue"
+- Longeur des fils dans ces structures qui se mettent à jour par broadcasting
+
+-> Logique de renommage
+-> Logique de wake up (détermine quel instructions est prête ou non)
+-> Logique de selection
+-> Logique des by-pass
+
+Détails
+-------
+
+Logique de renommage
+~~~~~~~~~~~~~~~~~~~~
+Accès à une table de mappage pour diriger le numéro de registres logique vers le numéro de registres physique
+Accès multiple (plusieurs instructions)
+-> Logique de vérification de dépendances
+
+2 schémas : - schéma RAM : Une table de NB\_REG\_LOG pointant sur les registres physiques
+            - schéma CAM : Une table de NB\_REG\_PHY pointant vers les registres logiques
+Trename   = Tdecode + Twordline + Tbitline + Tsenseamp
+          = cst0 + cst1*IW + cst2*IW²
+
+Twordline (proportionnel à la taille de l'adresse du registre physique (environ 8) )
+Tbitline  (proportionnel au # de registre logique (souvent 32) )
+Tsenseamp fonction de bitline delay
+cst sont donnée par la technologie
+
+=> croit linéairement avec la taille de la fenêtre
+
+Logique de wakeup
+~~~~~~~~~~~~~~~~~
+A chaque résultat produit, a tag associé au résultat est diffusé à toutes les instructions contenus dans la fenête de lancement (IW).
+Chaque instructions compare le tag avec ses opérandes sources
+Si la comparaison est positive => mise à jour du bit ready de(s) l'opérande(s) (Quand tous les bit sont positionnés => instructions prête au lancement)
+
+Il y a IW tag soit NB\_OPERANDE x IW comparaions
+
+Twakeup = Ttagdrive + Ttagmatch + Tmatch\_or
+        = c0 + (c1 + c2 * IW)*WINSIZE + (c3 + c4*IW + c5*IW²)*WINSIZE²        
+
+(IW => nombre d'instruction en attente d'être executer)
+(WINSIZE => nombre d'instruction allant être executé)
+
+Incrémenter le nombre de ligne va incrémenter le nombre de comparaisone et la puissance nécessaire pour atteindre ces comparaisons.
+Seul le Ttagdrive dépend de la taille de fenêtre de lancement (fan-out + élevé car + de comparateur)
+
+Logique de selection
+~~~~~~~~~~~~~~~~~~~~
+Choix des instructions à executer parmit la IW
+ -> Plusieurs types d'instructions
+ -> Plusieurs types d'unités fonctionnelles pouvant acceptés une instructions de plusieurs types d'instructions.
+
+Un signal REQ par instruction contenant dans la IW (actif si instruction prête)
+Un signal GRANT est émit par le bloc de sélection (1 par signal de requête) => indique que l'instructions est lancé dans une unité fonctionnelle.
+Politique de selection -> en général FIFO, ou la plus vieille (C'est à dire la plus en bas de la fenêtre d'instruction)
+
+=> Arbre d'arbitrage.
+ 2 phases : 1) Propagation de la requête jusqu'à la l'unité fonctionnelle
+            2) Propagation de la réponse (GRANT) jusqu'a toute les req d'instructions
+
+Tselection = c0 + c1 * log4(WINSIZE)
+
+log4 car les noeuds de l'arbre d'arbitre accepte 4 requêtes.
+
+Logique des bypass
+~~~~~~~~~~~~~~~~~~
+Si complétement bypassé, il faut : 2*IW²*S (S est le nombre d'étage)
+-> Un fils par unité fonctionnelle
+-> Tous les unité fonctionnelle (ainsi que le banc de registres) doivent avoir un bloc mux
+-> banc de registres à autant 2*UF ports de lecture et UF ports d'écriture
+-> Bloc mux à UF ports d'entrée et en sorties ce sont des bus attaqués pas UF signaux.
+-> Sans oublier les compateurs dans chaque alu
+
+Tbypass = 0.5*R*C*L²   => Dépend principalement de la longueur des fils.
+
+Analyse des résultats
+---------------------
+
+IW  Window-size Trename Tselection Tbypass
+
+(0.18)
+4   32          351.0   578.0      184.9
+8   64          427.9   724.0      1056.4
+
+-> La selection (logique de fenêtrage) et les bypass posent des problèmes de scalabilités.
+=> Toutes les autres structures ne posent pas de pbl d'horloge, où s'il y en a, alors ils peuvent être pipeliné.
+
+Si on découpe l'étage Wakeup (Chercher les opérances) et selection (Chercher une ALU disponible), alors il y aura au meilleur des cas au moins un cycle de gels entre deux instructions dépendante consécutive.
+
+... | WUP | SEL | EXE | ...                add r3,r2,r1
+                   | (Bypass)
+......... | WUP | WUP | SEL | EXE | ...    add r5,r4,r3
+
+Proposition d'architecture
+--------------------------
+Remplacement de la fenêtre de lancement par une architecture "dependance-based"
+Clusterisation des by-pass.
+
+=> architecture "dependance-based"
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Exploitation des dépendances instraséques entre instructions.
+Fenêtre de lancement découpé en plusieurs fifos. Les instructions dépendantes sont routés vers la même fifos.
+Execution In-order des instructions dépendante entre elles. Execution désordonné des autres flots d'instructions.
+Il n'y que les instructions de têtes à aller verifier le banc de registres.
+
+Besoin d'une table(SRC\_FIFO)  où les dépendances des instructions sont maintenus à jour
+SRC\_FIFO(num reg log) -> numéro fifo
+
+=> Clusterisation des by-pass
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Décomposé les unités fonctionnelles en cluster. 
+Il y a 2 types de bypass 
+ - intra cluster (dans le même cycle) 
+ - inter cluster (peut nécessité plusieurs cycles)
+=> N copies du banc de registres : 1 pour chaque cluster
+
+Conclusion
+----------
+Les techniques diminues faiblement (au max 12\%) le CPI mais augmente sensiblement la fréquence d'horloge. Au total, la performance global est meilleur.
+
+Autre technique :
+
+1 cluster - 1 window (Superscalar basique)
+
+-> Window -> Cluster0
+
+
+2 cluster - Fifo dispatch
+
+     -> Cluster0
+   /
+-> 
+   \ 
+     -> Cluster1
+
+2 cluster - windows - Choix du cluster : exec
+
+Instruction stocké dans une fenêtre global puis assigne à un cluster
+
+             -> Cluster0
+           /
+-> Windows 
+           \ 
+             -> Cluster1
+
+2 cluster - windows - Choix du cluster : dispacth
+
+
+     -> Windows -> Cluster0
+   /
+-> 
+   \ 
+     -> Windows -> Cluster1
+
+2 cluster - windows - Choix du cluster : random
+
+Choix des clusters aléatoire
+     -> Windows -> Cluster0
+   /
+-> 
+   \ 
+     -> Windows -> Cluster1
+
+@InProceedings{ 1998_hammond,
+  author = 	 {Lance Hammond and
+                  Mark Willey   and
+                  Kunle Olukotun},
+  title = 	 {},
+  OPTcrossref =  {SSN:0163-5980},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the eighth international conference on Architectural support for programming languages and operating systems},
+  OPTpages = 	 {58-69},
+  OPTyear = 	 {1998},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 { San Jose, California, United States},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = {ACM Press},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+27/01/2005
+
+Thread level speculation
+------------------------
+Technique autorisant l'execution paralléle d'une application séquentiel (donc à pour but de tourner sur un multi processeur).
+=> Mécanisme fonctionnant bien pour des applications avec un grain moyen de parallélisme de boucle. Mais quand la granularité de parallélisme devient trop petite, l'overhead devient trop couteux.
+
+DATA Spéculatation
+~~~~~~~~~~~~~~~~~~
+
+Processeur superscalaire avec execution désordonné :
+ -> réordonne les instructions ALU (renommage de registre , ordonnancement dynamique).
+Pas de réordonnancement des accès mémoires si les adresses ne sont pas connut on sont connus et dépendante.
+
+Data spéculation : On execute des loads qui ce situe après des stores dont l'adresse n'est pas encore connus.
+ -> S'il y a une vrai dépendance => le store est prioritaire et le load (et chaque execution en dépendant) sont ré-executés.
+
+Le programmeurs / Compilateur peut diviser un programme séquentiel en plusieurs threads. Or les dépendances de registres et de mémoires imposent beaucoup de contraintes.
+=>Si les dépendance ne peut pas être connus lors de la compilation (exemple des pointeurs en C) alors impossibilité  de diviser le code ou alors placer des routine de synchronisation logicielle.
+
+Avec le thread level data speculation (TLDS)
+=> le compilo divise seulement le programme en threads. 
+=> Chaque thread à un numéro, celui-ci indique le numéro correspondant à l'ordre dans lequel il devrait être s'il été executer en séquence.
+=> La spéculation hardware d'occupe des vrais dépendances entre les accès mémoires
+
+Les écritures deviennent des points de synchronisations.
+
+Chaque processeur execute un thread :
+On classe les procs par rapport au numéro que le thread possède.
+Celui avec le numéro le plus faible (executer sur le processeur de tête) est donc non spéculatif. Les autres sont de + en + spéculatif.
+
+Temps 0 : CPU i   -> R
+Temps 1 : CPU i+1 -> R
+Action  : -
+
+Temps 0 : CPU i   -> R
+Temps 1 : CPU i+1 -> W
+Action  : renomage dans i+1
+
+Temps 0 : CPU i   -> W
+Temps 1 : CPU i+1 -> R
+Action  : envoie de la donnée écrite par i vers i+1
+
+Temps 0 : CPU i   -> W
+Temps 1 : CPU i+1 -> W
+Action  : Ecriture de i puis renommage de i+1 et écrasage de la donnée
+
+Temps 0 : CPU i+1 -> R
+Temps 1 : CPU i   -> R
+Action  : -
+
+Temps 0 : CPU i+1 -> R
+Temps 1 : CPU i   -> W
+Action  : Renommage de i+1
+
+Temps 0 : CPU i+1 -> W
+Temps 1 : CPU i   -> R
+Action  : RAW : i+1 redemarré
+
+Temps 0 : CPU i+1 -> W
+Temps 1 : CPU i   -> W
+Action  : Renommage de i+1, + tard le forward de i sera ignoré
+
+Le matériel de spéculation des donnés doit fournir :
+ - Détection des vrai dépendances mémoire dans l'ordre.
+ - Possibilité de retour en arrière et ré-execution du threads
+ - Bufferisation des écritures jusqu'a ce qu'elle ne sont plus spéculative (Ou supprimé)
+
+Décomposition en thread spéculatif
+----------------------------------
+
+2 architectures différentes :
+ - The Multiscalar architecture => découpage en tâche arbitraire, allocation des tâche dans l'ordre sur un anneau de processeur
+ - The TLDS architecture => support minimum pour la spéculation, principalement controlé par logiciel.
+
+Solution apportée ici :
+Combinaison de l'approche hard/Soft (~TLDS)
+-> Utilisation du support du hardware pour diviser le programme en thread et les distribuer sur les différents processeurs.
+  |-> Coprocesseur de spéculation
+
+Comment diviser un prcess en threads?
+ -> utilisation d'appel de sous fonction
+   -> Un autre processeur va executer de manière spéculatif la suite du programme principal
+ -> Boucle (Ceux indiqué par le compilateur)
+   -> Les différentes itérations sont distribuées sur les différents processeurs
+
+Subroutine Thread
+~~~~~~~~~~~~~~~~~
+
+Spéculation de fonction géré par une list chainé de threads actifs ordonnée du moins au + spéculatif
+Lors d'un appel de fonction, envoie d'un message au autre processeur.
+
+1) Le processeur alloue un register passing buffer (RPB) pour le thread nouvellement crée. 
+2) Sauvegarde des registres (devant être sauvegarder lors d'un appel systems) puis prédition de la valeur retourné 
+  alogo repeat least return value (car en C -> beaucoup de void fonction ou de retour d'erreur, ou imprédictible)
+3) Insertion du buffer dans la list des buffer actif juste après le process courent (pour garder l'ordre par spéculation)
+4) Attribution d'un processeur à ce nouveau thread (soit un libre, soit un executant le plus spéculatif des threads)
+
+Ceci est réaliser dans l'exception handler (Donc chaque appel à une sous fonction génére une exception)
+Si l'appel de fonction à une valeur de type imprédictible, alors on ne considère pas la spéculation.
+
+Au retour d'un appel de fonction :
+1) Le processeur attend jusqu'a ce qu'il soit le processeur de tête (donc sont code devient non spéculatif et deplus il n'est pas en conflit avec les autres thread)
+2) La valeur retourné est comparé avec la une valeur prédite. Si miss => Toute les threads sont relancés
+3) Le RPB est remis dans la free-list, le thread suivant devient celui de tête
+4) L'ancien processeur de tête va executer un thread (donc devient le plus spéculatif)
+
+Loop itération Thread
+~~~~~~~~~~~~~~~~~~~~~
+
+Un boucle spéculatice est préceder d'une verification pour savoir s'il est avantageux ou non de l'exécuter de manière spéculative.
+Une itération de boucle est donnée a chaque proc disponible.
+
+A la fin d'une itération -> validation, l'itération suivante devient le CPU de tête.
+Ceci jusqu'à ce que la condition de terminaison soit trouvée (dans ce cas invalidation de tous les autres threads) 
+
+2 manières de traiter les boucles :
+ - Si la boucle est longue : rebouclage des RPB
+ - sinon Schéma habituel : insertion de 4 RPB (1 pour chaque proc) => Overhead moins couteux mais méthode peu fléxible
+
+Taille des Threads
+~~~~~~~~~~~~~~~~~~
+
+Facteur de Limitations :
+1) Taille limité des buffers : Il n'y a que le CPU de tête qui réalise des mise à jour de la mémoire. Les CPU spéculative ne peuvent commiter leur buffer que s'il deviennent buffers de têtes.
+2) Vrai dépendance : Les grands threads augmente la probabilité de vrai dépendance
+3) Longueur des redémarrages : Un redémmarrage sur un grand thread augmente la charge de travail (données à défaire etc..)
+4) Overhead : Les très petits threads ont un coût d'overhead trop élevé.
+
+=> Violation counters : élimine les threads avec trop de dépendances
+=> Thread timers : élimine les threads trop long
+=> Stall timers : élimine les threads trop souvent bloqués (voir plus bas)
+
+Exception
+~~~~~~~~~
+Si un thread réalise une exception, ou un appel système, alors celui-ci est bloqué.
+
+Speculation Control Coprocessor
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+=> Implémenter dans le Coprocesseur2 du mips
+-> Fonction accèder par software
+-> Contient la table des vecteurs d'exceptions
+
+Hardware Support
+----------------
+
+Sur le multiscalar processor => ARB (Dcache partagé) associé avec un traceur de reférence mémoire spéculative.
+Sur le TDLS processor        => Protocole plus simple
+
+Ici : 
+ - Modification dans le Dcache : Sur chaque tag d'une ligne de cache, ajout de qq bits (modified bit, pre-invalidate bit) (Read, Write bits => pour détecter les vrai dépendance, un bit par mots contenu dans la ligne)
+ - Buffers dans le cache L2    : Bufferisation des écritures encore spéculative. Une fois qu'il ne sont plus spéculative, ordre venant du processeur pour rentre permannent les changement. Le buffer est dépiller par ordre d'arriver et écrit dans le L2. Le buffer full est détecter par chaque proc qui possède une copie local des Tags du buffer couramment utilisé.
+Lors d'un load  spéculatif , On va lire le DCACHE, puis on va lire dans le buffer courrant au proc, puis on remonte tous les buffer appartement a des process moins spéculative (jusqu'a la tête) et enfin on va lire dans le L2 cache. (Tous est vérifier en parralléle)
+Lors d'un sotre spéculatif , il peut se produire : écriture dans le DCACHE (demander par le proc courant), une invalidation par un cpu moins spéculatif (vrai dépendance), une pré invalidation venant des cpu plus spéculatif (vérification). Si proc devient la tête : Drainage du buffer.
+@TechReport{1998_olukotun,
+  author = 	 {Lance Hammond and
+                  Kunle Olukotun},
+  title = 	 {Considerations in the design of hydra : a multiprocessor-on-a-chip microarchitecture},
+  institution =  {Stanford University},
+  year = 	 {1998},
+  OPTkey = 	 {CSL-TR-98-749},
+  OPTtype = 	 {},
+  OPTnumber = 	 {},
+  OPTaddress = 	 {},
+  OPTmonth = 	 {February},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+24/01/2005
+
+Décrit de manière détaillée :
+- Hiérarchie mémoire
+- Bus internes
+- Contrôle et arbitrage
+
+Hierarchie Mémoire
+~~~~~~~~~~~~~~~~~~
+L1 - On chip - I D séparé , et 1 couple pour chaque proc
+L2 - On chip - Partagé avec les 4 processeurs
+L3 - Off chip
+Mémoire principale - Off chip
+
+L1 unifié pour les 4 procs :
+ - Trop de ports R/W
+ - Cache L1 devient "plus gros" pour rendre les même services
+ - Logique entre le cache et le L1 (en cas d'accès à la même case)
+ - Trop de logique => Ne réponds pas en 1 cycle
+
+L1 séparé
+ - Obligation d'un mécanisme de snoop
+
+Limitation d'avoir un L3 off chip :
+ - RAM rapide sont onéreuse
+ - Demande beaucoup de plots
+ - Electriquement non triviale
+
+Communication
+~~~~~~~~~~~~~
+2 bus internes :
+ - Bus Read/Replace
+ - Bus Write-through 
+
+Gérer de manière pipeliné, demande 1 cycle pour l'arbitrage afin d'avoir un débit d'un accès par cycle
+
+Bus Read/Replace  : 256b de large (1 ligne de cache L1 / L2). Liaison entre le L2, et le L3 ainsi que tous les L1 (en lecture uniquement). Bus avec un faible traffic (dans leur exemple : occupation inférieur à 50\% pour les tests les plus gourmand en accès mémoires)
+
+Bus Write-through : 64b de large, de tous les caches L1 vers le L2. Cohérence du cache L1 sur snoop de ce bus (pas le read/replace bus) , Invalidation sur écriture (Un seul cache est propriétaire d'un bloc). Les écritures de tous les procs se retrouvent séquencer.
+
+L'utilisation du write-bus n'est pas scalable :
+ * write-bus multiple (Ou 1 seul rapide) => Ports supplémentaires pour le L1 Tags, snoop et invalidation multiple par cycle. Dans le L2 => plusieurs données peuvent être écrite par cycle.
+ * Une ligne de bus avec un mode rafale
+ * Protocole conventionnel de cohérence MESI, et elimination du write bus pour un bus partagé entre les lecture et les écritures
+
+Contrôleur mémoire
+~~~~~~~~~~~~~~~~~~
+Chaque ctrl mémoire est divisé en 2 pipelines indépendants. 
+ - un pour manager les accès en lecture (Instruction fetch et load)
+ - l'autre pour manager les accès en écriture
+
+Lecture  : en général prévisible et donc absorbé par le cache
+Ecriture : A cause du write throught : répercuter à chaque fois sur le bus. De plus les codes ont tendance à faire des burst de store. En général absorbé par le store buffer.
+
+pipeline de Lecture et celui d'ecriture sont similaire :
+3 étages :
+ - accès L2 (~5  cycles)
+ - accès L3 (~15 cycles)
+ - Initiation de l'accès à la mémoire principal ( 5-10 cycles)
+L'avancement dans le pipeline se fait sur un miss de l'accès courant.
+
+Degré de pipeline :
+Accès L2, Accès L3 pipeliné
+Accès mémoire non pipeliné (1 seul requêtes dans cet étage)
+
+De plus il y a deux autres ctrl dans la mémoire principale et l'interface I/O
+-> Retourne les données venant de l'extérieur vers le cache approprié.
+-> ~ au ctrl des caches
+
+Arbitre
+~~~~~~~
+Les demandes d'accès les plus anciennes sont servies en premier
+
+Ce n'est pas une allocation cycle par cycle ou ressource par ressource. Mais par unité de cycle (de 5 à 20 cycles).
+
+Chaque CPU pipeline (ctrl mémoire) envoie une requete de ressource au début de chaque étage de pipeline.
+Priorité fixe :
+ - vers Accès mémoire et I/O
+ - vers L3
+ - vers L2
+(Les plus courants sont les moins prioritaire, évite la famine)
+
+Read pipeline est prioritaire sur le write pipeline. Possibilité au L1 d'inverser la priorité si le write buffer est (proche d'être) plein.
+
+Arbitrage sur la même adresse
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+2 accès se réalise en parrallèle (L1 / L2 / L3 / Mémoire) sur le même adresses
+Problèmes :
+ - Copie multiple d'une ligne de cache => Plus de proporité d'exclusivité des lignes de caches.
+ 
+@article{1998_kessler,
+  title={{The Alpha 21264 microprocessor architecture}},
+  author={Kessler, RE and McLellan, EJ and Webb, DA},
+  journal={Computer Design: VLSI in Computers and Processors, 1998. ICCD'98. Proceedings., International Conference on},
+  pages={90--95},
+  year={1998}
+}
+@InProceedings{1998_krishnan,
+  author = 	 {Krishnan, V.   and
+                  Torrellas, J.  },
+  title = 	 {A clustered approach to multithreaded processors},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Parallel Processing Symposium, 1998. 1998 IPPS/SPDP. Proceedings of the First Merged International...and Symposium on Parallel and Distributed Processing 1998},
+  OPTpages = 	 {627-634},
+  OPTyear = 	 {1998},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Orlando, FL  ,   USA},
+  OPTmonth = 	 {30 Mar - 3 Apr},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+25/02/2005
+
+SMT                    -> Flexible (TLP et ILP) 
+Fixed assignement (FA) -> Sous utilisation des ressources
+
+CMT -> un thread à tous les ressources à un instant donné
+Pbl SMT -> Conséquence sur le temps de cycle !!!
+
+SMT clusterisé : Unité de calculs sont multisthreadé, l'unité de dispatch va envoyé les instructions d'un thread vers les unités de calculs qui lui sont associés.
+
+Model de parallélisme
+---------------------
+
+Architecture fixe : N threads ayant M unités d'execution. Une unité d'execution n'apaprtient qu'a un thread => jusqu'a M IPC
+Si X nb d'Unité d'execution total fixe -> M = X/M 
+  - Si N trop grand -> exploite peu l'ILP
+  - Si N trop petit -> exploite peu le TLP
+
+Architectures
+-------------
+
+Centralisé et clusterisé SMT:
+
+Fetch unit partagé par ts les threads, (géré round robin ou autre), les instructions sont ensuite placé dans une fênetre d'instructions commune. Les instructions sont commité par thread.
+ -> limite : large interconnections entre les unités fonctionnelles et le banc de registres (en particulier les by-pass)
+
+FA :
+
+Réduction de la centralisation des ressources : partionnement du SMT classique en clusters (SMT d'ordre X*Y devient X clusters étant des SMT d'ordre Y).
+Chaque cluster à sont unités de FETCH
+
+Evaluation
+----------
+Un gaspillage d'un slot d'instructions peut être classé en :
+- struc : Manque d'unités fonctionnelle
+- mem   : Accès mémoire
+- data  : Dépendance de donnnées
+- ctrl  : Miss predictions de branchements
+- sync  : Barrières de synchro
+- fetch : Pas d'instructons pour un thread dans la fenêtre
+- autre
+
+Comparaison d'un FA8  (8 clusters qui sont des superscalaire d'ordre 1)
+                 FA4  (4 clusters qui sont des superscalaire d'ordre 2)
+                 FA2  (2 clusters qui sont des superscalaire d'ordre 4)
+                 FA1  (1 clusters qui sont des superscalaire d'ordre 8)
+                 SMT8 (8 clusters qui sont des SMT supportant 1 threads lancant 1 inst/cycles) 
+                 SMT4 (4 clusters qui sont des SMT supportant 2 threads lancant 2 inst/cycles) 
+                 SMT2 (2 clusters qui sont des SMT supportant 4 threads lancant 4 inst/cycles) 
+                 SMT1 (1 clusters qui sont des SMT supportant 8 threads lancant 8 inst/cycles) 
+En terme de complexité SMTx = FAx
+SMT8 est identique à FA8
+SMT1 est une architectures SMT centralisés
+
+de FA8 à FA1 : sync décroit mais les data et mem croit. (logique :P)
+
+@article{1998_tullsen,
+  title={{Simultaneous multithreading: maximizing on-chip parallelism}},
+  author={Tullsen, D.M. and Eggers, S.J. and Levy, H.M.},
+  journal={International Conference on Computer Architecture},
+  pages={533--544},
+  year={1998},
+  publisher={ACM Press New York, NY, USA}
+}
+
+15/02/2005
+
+Présentation du multi-threading.
+-> lancement de plusieurs flots de plusieurs threads dans les unités fonctionnelles du processeurs.
+-> but : augmenter l'utilisation du processeur face au long latence de la mémoire et de ILP limité dans un seul thread
+
+plan :
+ - modèle de SMT
+ - evaluation des perfs (par rapport à un superscalaire et un fine grain multi threading)
+ - hierarchie mémoire dans un SMT
+ - SMT vs CMP
+
+Modification d'un alpha 21164 :
+
+- 10 unités d'execution (4 integer, 2 flottant, 3 load/store et 1 branchement) => complétement pipeliné
+- Issue : 8 inst/cy
+- execution dynamique
+  |-> gestion des dépendance in-order
+  |-> lancement out-order
+- Prediction de bcht
+
+Limitations du super-scalaire
+-----------------------------
+en moyenne, le processeur lance 1.5 inst/cy sur une machine pouvant en lancer 8.
+différente cause :
+ - conflits mémoire, dépendance de donnée (flottant, ou entiere), délai de chargement, bulle de contrôle, mauvaise prédiction, miss de cache et de TLB.
+
+Toutes les cas peuvent être classé suivant deux types d'incidences sur le pipeline
+ - gaspillage verticale   : à un cycle donnée, aucune unité d'exécution ne sera utilisé
+ - gaspillage horizontale : à un cycle donnée, non utilisation d'un créneau de lancement (issue slot)
+
+un corse grain / Fine grain multithreading limite le gaspillage verticale.
+
+Modèles de processeurs
+----------------------
+Chaque modèles à 10 unités fonctionnelles et peut lancer 8 inst/cycles (Donc au max 8 threads)
+
+- Fine-grain multithreading : 1 thread peut lancer des instructions pendant 1 cycle (cycle suivant commutation)
+- SMT : full issue : les 8 threads sont en compétitions sur chaque issue slots à chaque cycle
+- SMT : N issue : chaque threads peut lancer un maximum de N inst/cycle (full issue = 8)
+- SMT : Connection limité : Chaque thread hardware est directement connecter à une unité fonctionnelle de chaque type (si il y a 8 threads et 4 unités fonctionnelles d'un type, alors chaque unité fonctionnelle est connecté à 2 threads)
+
+3 facteurs :
+ 1- # de threads en compétition
+ 2- # d'instructions lancé/thread
+ 3- # d'UF visible/thread
+
+augmente   Port registre | dépendance interinst | logique forward | ordonnancement inst
+1                                                 + complexe        + complexe          -> les ufs ont plus destination possible pour les résultats
+                                                                                        -> plus d'instructions devant être routé
+2          + complexe      + complexe                                                   -> plus d'instruction à lancer (donc chercher les opérandes)
+                                                                                        -> plus d'instruction à analyser (augmentation de la fenêtre de chaque thread)
+3          + complexe      + complexe             + complexe        + complexe          -> l'ordonnancement devient de + en + dépendant d'autre FU
+                                                                                        -> une UF qui est privé à moins de destination possible
+
+Caches
+------
+Le partage des caches et des TLB est néfastes sur les performances.
+Lors du partage des caches entre threads :
+ - Il y a virtuellement moins d'espace par threads
+ - Il faut des caches non bloquants
+
+-> Cache privé afin d'avoir des caches dédié à un thread (le cache est partionné en NB\_THREAD parties) Bon pour les Icaches (Pas d'évincement d'une ligne d'instruction par un autre thread)
+-> Cache partagé : Tous les threads ont accès au même cache => peu de contrôle, bon pour les Dcaches car 1 seules mécanisme de cohérence mémoires à implémenter.
+
+SMT vs CMP
+----------
+Ressemblance :
+Duplication des registres, multiple unité fonctionnelle, grand nombre d'instruction lancé par cycle
+Différence :
+les ressources ne sont pas partitionné et ordonnancé. Ils ont alloué de manière statique à un thread (ou un groupe de threads)
+
+Le SMT surpasse le CMP à complexité égal :
+ -> Un SMT 8 threads - 8 issues avec 10 FU surpasse de 24\% 8 proc 1 issue avec 4 UFs
+
+ * performance avec peu de thread (car partage des ufs)
+ * granularité et flexibilité
+
+
+@article{2000_barroso,
+  title={{Piranha: a scalable architecture based on single-chip multiprocessing}},
+  author={Barroso, L.A. and Gharachorloo, K. and McNamara, R. and Nowatzyk, A. and Qadeer, S. and Sano, B. and Smith, S. and Stets, R. and Verghese, B.},
+  journal={Proceedings of the 27th annual international symposium on Computer architecture},
+  pages={282--293},
+  year={2000},
+  publisher={ACM Press New York, NY, USA}
+}
+
+02/12/2004
+
+systeme Piranha : Exploite le multiprocesseur à l'aide de 8 alpha (simple) avec 2 niveaux de caches, le tout sur un seul chip.
+
+Les processeurs hautes performances vise l'exploitation au maximum de l'ILP. Réalisant des architectures de + en + complexe, afin d'améliorer les benchmarks de types SPEC.
+Or Les domaines d'applications demandant vraiment de la haute performance se situe au niveau des serveurs. (Application internet) => Comportement n'est pas comme les bench SPEC
+
+Pourquoi cette architecture : Le coût d'un SMT (simultaneous multithrading) étant plus cher qu'un CMP (chip multiprocessing), car plus complexe (le SMT contient du matériel pour gérer les changement de thread, + de banc mémoire etc ...). Alors que l'approche CMP peut être réaliser avec des processeurs plus simple.
+
+Idée dans le piranha :
+ -> Mémoire secondaire partagée (non inclusive avec un niveau L1)
+ -> Cohérence des caches
+ -> architecture I/O
+
+Architecture générale :
+-----------------------
+
+ * CPU alpha possèdant un I et DCACHE dédié
+ * Tous ces couple Proc+Cache sont relié autours d'un Interconnect
+ * Sur cette interconnect, il y a également les caches L2 (donc partagés avec n'importe lequel des CPU)
+ * Sur chacun des caches L2 est connecté un controleur mémoire.
+ * Ce dernier à une liaison directer avec des RDRAM.
+ * Connecté sur le Bus, pour la communication avec le monde extérieur
+    - Home engine
+    - Remote engine
+ * Les 2 moteurs de protocoles sont connecté au routeur de paquet qui distribue les paquets entre les moteurs internes et file d'entrée et de sortie. 
+ * Le bus étant piloté par un module : system control
+
+Structure hiérarchique forte.
+
+Réseau de noeud Piranha :
+ - Les P-chip   => en interne possède 8 CPU alpha
+ - Les I/O-chip => Permet de faire la liaison avec le monde extérieur (Au lieu des 8 CPU, il n'y en a qu'un + un bloc I/O)
+
+D'après les concepteurs, un réseau peut aller jusqu'a 1024 noeuds avec un nombre quelconque de noeud I/O.
+Un des principes fondamental, est qu'un noeud I/O est traité de la même manière qu'un noeud de traitements.
+
+Architecture détaillée :
+------------------------
+
+CPU + L1 cache
+~~~~~~~~~~~~~~
+Processeur alpha de 500Mhz, 8 étages de pipeline classique (Ifetch, Decode, Execute (*5), Writeback).
+ -> Unité flottante, BTB, logic de prédécodage.
+2 caches séparé :
+ -> 64 ko, ass 2voies. Cache bloquant avec adresse Virt et Tag phy. 
+ -> TLB de 256, ass 4voies
+ -> Protocole de cohérence MESI
+ -> Non inclusif avec le niveau L2
+
+Intra-Chips Switch (ICS)
+~~~~~~~~~~~~~~~~~~~~~~~~
+Conceptuellement, c'est un crossbar.
+-> Uni-directionnel, interface Push-only
+-> ECC , bits de parités
+-> pré-allocation (spéculation)
+-> 2 priorités (low & high), un chip peut choisir la priorité désiré.
+
+Cache L2
+~~~~~~~~
+Cache unifié d'1Mo, découpé en 8 bancs qui sont ass 8voies (Remplacement round robin)
+-> Maintient de la cohérence intra-chip
+-> Non inclusif avec le niveau 1 de caches (Non dédoublement des instructions)
+-> write no allocate
+-> Duplication du registre de TAG du cache L1 associé au cache L2
+
+L1 envoie une requete mémoire à son banc L2. Celui-ci peut :
+ -> Servir directement la requête
+ -> La renvoie à un autre Cache L1
+ -> La renvoie à un autre protocle de cohérence
+ -> Obtient la donnée à par le contrôleur mémoire
+
+Contrôlleur Mémoire
+~~~~~~~~~~~~~~~~~~~
+Un Contrôlleur mémoire par cache L2.
+A une liaison rapide avec les RAMs,
+N'a pas de liaison direct avec l'ICS
+
+Protocole Engine
+~~~~~~~~~~~~~~~~
+Assure le support pour la mémoire partagé, 2 blocs spérarés :
+ -> "home engine"   responsable d'exporter la mémoire local a ce noeud
+ -> "remote engine" importe la mémoire qui se trouve dans un noeud distant
+
+Chaque bloc est a peu de chose près conçu de la même manière :
+* Input controller
+* microcode controlled execution unit
+* Ouput controller
+
+Une execution micoprogrammé assure la gestion entre les deux interfaces.
+
+Cohérence des caches : Read, Read-exclusive, Exclusive, Exclusive-without-data
+
+Interconnecte système
+~~~~~~~~~~~~~~~~~~~~~
+3 partie distinct :
+-> Output Queue
+-> Input  Queue
+-> Routeur
+
+Topologie indépendante, adaptatif, Buffer avec différents niveau de priorités, canaux virtuels
+
+Mise en place de dispositifs pour assurer la fiabilité, disponibilité et l'utilité des données :
+ - redondance sur les dispositifs mémorisants
+ - procetection CRC sur les chemins de donn"s
+ - protocle de recouvrement d'erreur
+ - enregistrement d'erreur
+ - Liens permuttable à chaud
+
+METHODOLOGIE D'EVALUATION
+-------------------------
+
+Utilisation d'un bench simulant des accès de clients sur des bases de données.
+ -> Oracle (logiciel)
+ -> SimOS-Alpha (Os pour processeur alpha assez fournit (gère le multi processeur, la mémoire virtuel ...)
+
+Comparaison de l'archi piranha avec :
+ - Un alpha21364 : un superscalaire Out of order, à 1Ghz, 2 niveaux de caches etc...
+ - un système piranha avec 8 procs (P8)
+ - un système piranha avec 1 proc  (P1)
+ - un proc superscalaire In order
+
+Constatation :
+ - le piranha 8 est relativement performant
+ - Le traffic dans l'interconnect local est d'autant plus grand qu'il y a de processeurs, surtout a cause des mécanisme de cohérence de cache (Forwarding vers d'autre cache L2)
+
+Remarque de fin :
+Les auteurs finissent par cette perspective :
+ => La question clé pour les designers des processeurs futures ne va pas être de savoir si on va employés des multi procs, mais de déterminer la bonne compensation entre le nombre de coeurs et la puissance de chaque coeurs. Et quel sera la meilleur hierarchie mémoire.
+@article{2000_hammond,
+  title={{The Stanford Hydra CMP}},
+  author={Hammond, L. and Hubbert, B.A. and Siu, M. and Prabhu, M.K. and Chen, M. and Olukotun, K.},
+  journal = 	 {Micro, IEEE},
+  year = 	 {2000}
+}
+
+07/12/2004
+
+MOTIVATION
+----------
+
+Les processeurs sont plus petits et rapide. Donc pour une même surface, nous avons une augmentation du "budget" de processeur.
+ -> Soit on augmente la complexité d'un mono-processeur
+ -> Soit on augment le nombre de mono-processeur simple sur un chip
+
+Parrallélisme:
+2 types de parrallélisme : ILP (Instruction level parrallelism) et TLP (Thread level parrallelism)
+Souvent la logique utilisé pour augmenter l'ILP fait augmenter le cycle d'horloge de manière quadratique.
+De plus il est limite à 4-6 instructions (cf 1991\_wall)
+
+Contrainte technologique :
+Délai causé par l'interconnection des portes (délai des nets) devient significatif => zone localement synchrone et globalement asynchrone. Un CMP peut faire en sorte de placer des processeurs simples dans les zones localement synchrones
+
+Temps de design:
+La conception d'un CMP s'appuie plus sur l'utilisation d'IP.
+
+Pourquoi les CMP ne sont pas utilisé?
+ -> Difficulté à convertir un programme pour mono-proc en multi-proc (Problème de consitence mémoire, synchronisation entre proc etc ...)
+ -> Les compilateurs parralléles sont encore très assistés par le programmeur
+
+DESIGN
+------
+
+Le chip Hydra est un chip multiprocessor (CMP) intégrant 4 processeurs MIPS possédant chacun un Icache et un Dcache L1, mais un niveau L2 partagé.
+Tous les controleurs des Caches L1 et le cache L2 sont sur le même bus. (Appellé bus d'écriture)
+Un autre bus prévut pour les échanges entre l'extérieur et le cache L2 mais avec possibilités de lecture des contrôleurs L1
+
+Protocole d'invalidation simple sur le bus d'écriture
+
+Il existe beaucoup d'application pour mono-processeur. Pour l'executer sur un système multi-proc, soit on sous utilise notre architecture, soit on ajoute de la thread-level speculation.
+L'hydra va utiliser la deuxième technique.
+
+thread-level speculation
+~~~~~~~~~~~~~~~~~~~~~~~~
+Prends une séquence d'instructions, la découpe de manière arbitraire en thread. Le hardware doit suivre ces threads. Si un thread réalise une lecture trop tôt (Donc un autre thread n'a pas encore fournit de résultat), le hard doit s'arranger pour que ce thread ce réexecute avec la bonne lecture.
+Grande complexité car on doit déterminer toute les possibilités de "vrai dépendances"
+
+Outre le cas normal, il y a 5 types de problèmes de cohérences :
+- Cas normal : début de boucle load X , fin de boucle write X
+- Renvoie de la donnée entre thread parralléle
+- Détection si les lectures sont "proche" (Dépendance RAW) : Au moment de faire un write sur X à l'itération i, alors le distribuer au load de l'itération i+1 (Forward data entre deux thread paralléle). 
+ => Mécanisme pour ce souvenir des traces d'execution (S'il y a eu précedement une lecture sur X dans l'itération i+1 lros de l'execution de l'instuction write sur X de l'itération i, alors il y a une erreur).
+- Annulation saine de l'exec spéculatif après violation 
+- Retirer les écritures spéculatives dans le bonne ordres (Dépendance WAW) (tjs l'itération la plus ancienne en premier) => Les écritures ne deviennent plus spéculative.
+- Fournir le rennomage mémoire (Dépendance WAR)
+
+Le système doit avoir un mécanisme pour décomposer en thread, et pouvoir les arreter les threads spéculatifs.
+
+Où découper les threads : En pratique : que lorsque l'on peut avoir plusieurs voie, càd boucle et appel de fonctions (Si la fonction ne retourne pas de résultats ou le résultat est facilement prédictible)
+Le speculation runtime system va choisir les 4 threads les moins spéculatifs et les executer (car il y a 4 procs).
+
+Le mécanisme de spéculation demande des médiums de communication rapide inter processor, sinon le processus mono thread risque de couter moins cher que sont équivalents découpés en plusieurs threads (spéculatif).
+
+Sur l'hydra, le matériel additionnel pour utiliser cette technique est placé dans 2 blocs matériels :
+- Ram de flags pour les caches L1 (est ce que la donnée contenu dans la ligne à été spéculativement lut ou écrite?)
+- Write buffers dans le cache L2 (Buffer d'écriture permettant de sauvegarder "sainement" les données dans le cache L2. (Garantie de donnée non spéculative)
+
+Comment cela fonctionne?
+~~~~~~~~~~~~~~~~~~~~~~~~
+- Un buffer est alloué à chaque thread en train d'être éxecuté sur ce système. Dès qu'un thread ne devient plus spéculative, alors les buffers écrivent dans la mémoire.
+- Pour contrôler le séquencement des threads, il y a un petit composant utilisant l'interface coprocesseur du mips.
+  |-> "speculation coprocessors"
+
+Classement de threads par degré de spécultation, quand un thread spéculatif d'ordre i envoie un message sur le writebus, seul les ctrls rattaché à des procs éxecutant un thread plus spéculatif (donc d'ordre > i) snoop le bus (rappel => utilisation de l'invalidation sur snoop)
+
+=> Lors d'un accès mémoire => Lecture en L1, si miss (surement invalidé) alors regarde dans son write buffer  puis dans les write buffer des threads de - en - spéculatif, et enfin dans le cache L2.
+
+COUT ET PERFORMANCE
+-------------------
+Cout        : augmente la surface de quelques pourcents.
+Performance : Programme difficille ou impossible à parralléser, cependant ce sont des applications hautements parralléles.
+@article{2000_sharangpani,
+  title={{Itanium processor microarchitecture}},
+  author={Sharangpani, H. and Arora, H.},
+  journal={Micro, IEEE},
+  volume={20},
+  number={5},
+  pages={24--43},
+  year={2000}
+}
+@article{2001_hinton,
+  title={{The microarchitecture of the Pentium 4 processor}},
+  author={Hinton, G. and Sager, D. and Upton, M. and Boggs, D. and Carmean, D. and Kyker, A. and Roussel, P.},
+  journal={Intel Technology Journal},
+  volume={1},
+  pages={2001},
+  year={2001}
+}
+@InProceedings{2001_nagarajan,
+  author = 	 { Ramadass Nagarajan   	  and
+                   Karthikeyan Sankaralingam 	 and
+                   Doug Burger 	 and
+                   Stephen W. Keckler},
+  title = 	 {A design space evaluation of grid processor architectures},
+  OPTcrossref =  {SBN ~ ISSN:1072-4451 , 0-7695-1369-7},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture },
+  OPTpages = 	 {40-51},
+  OPTyear = 	 {2001},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 { Austin, Texas},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = { IEEE Computer Society },
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+02/02/2005
+
+En quoi consiste un Grid processors architecture?
+ -> tableau d'ALU avec un contrôle limité.
+ -> Les alu sont connecté par un réseau ou circule leur opérande
+ -> Les programmes sont éxécutés en mappant les blocs de manière statique et a executé les isntructions de manières dynamiques
+ -> Executions possible via une chaine d'alu (sorte de pipeline)
+
+Le GPA est conçut en vut d'avoir une grande fréquence d'horloge et une grande exploitation de l'ILP
+Le coeur de calcul d'un GPA consiste en une matrice 2D de noeuds. Chaque noeud contient un buffer d'instruction et une unité d'execution.
+-> noeud peuvent donc réaliser des calculs à grain fins
+-> les noeuds sont interconnecter avec un réseau dédié à la communication de données et d'opérande.
+-> Contrôle assuré par un mécanisme mappant les instructions sur les noeuds
+
+=> Equivalent à une approche VLIW : Ressources alloués statiquement par le compilo mais le lancement est dynamique
+
+MODELE D'EXECUTION
+------------------
+
+Modèle d'execution : traite des groupes d'instructions comme une unité atomique pour le fetch, mappage de ressources des unités d'execution et le commit.
+Dans ce modèle, les groupes d'instructions sont définit par le compileur.
+ -> Un groupe n'a pas de transfert interne de ctrl (c'est à dire un saut prit sera la dernière instruction d'un groupe) (Un bloc peut être un bloc de base ou une trace d'execution ...)
+ -> Données utilisé sont de 3 types : (Modèle Producteur - consommateur)
+    * entrée : valeur produite par un autre groupe et consommé par ce groupe
+    * sortie : valeur produite par le groupe et consommé par un autre groupe -> écriture des données dans un mémoire tampon jusqu'au commit
+    * temporaire : valeur produite et consommé par le groupe -> transimition des données en internes
+
+Compilateur assigne statiquement chaque instruction à un groupe d'alu. Un groupe ne peut être allouer à plus d'une instruction
+
+1) Un groupe est fétché et mapped sur les ALUs
+2) Chaque instruction dans le groupe est écrite dans les buffers d'instructions ( ~ station de réservations)
+3) Lecture des opérandes dans le banc de registres et placement des opérandes dans les alus.
+4) Execution de l'instruction
+5) Une fois que l'execution est terminé, le résultat est renvoyé vers l'alu consomatrice. (Ou vers le banc de registres)
+
+Destination encodé explicitement dans l'instruction
+
+6) Lorsque tte les instructions d'un groupe sont finis => commit : update de la mémoire
+7) Le groupe est libéré des ALUs
+8) Mappage du prochain groupe ...
+
+Il existe un branch register pour les résultats des branchements.
+
+Avantage
+--------
+-> Peu de structures larges impliqué dans l'execution (càd non centralisé, pas de fenêtre de lancement associative, pas de table de renommage de registres, peu d'accès en lecture et écriture simultané)
+-> Execution désordonnée (sans vérification de dépendance large, diffusion des bypass, réseau dédié au forward)
+
+Implémentation
+--------------
+
+ICACHEM -- REG --- REG --- REG --- REG
+            |  \ /  |  \ /  |  \ /  |
+            |  / \  |  / \  |  / \  |
+ICACHE --- ALU --- ALU --- ALU --- ALU --- DCACHE
+            |  \ /  |  \ /  |  \ /  |
+            |  / \  |  / \  |  / \  |
+ICACHE --- ALU --- ALU --- ALU --- ALU --- DCACHE
+            |  \ /  |  \ /  |  \ /  |
+            |  / \  |  / \  |  / \  |
+ICACHE --- ALU --- ALU --- ALU --- ALU --- DCACHE
+            |  \ /  |  \ /  |  \ /  |
+            |  / \  |  / \  |  / \  |
+ICACHE --- ALU --- ALU --- ALU --- ALU --- DCACHE
+
+          BLOC TERMINAISON ET TERMINAISON
+
+
+ALU rangé en matrice de n*m cases.
+Le bloc de terminaison détermine quel groupe d'instructions est mappé et quand celui-ci à terminé (dc commit)
+Chaque alu contient 
+ * des ports d'entrée pour les opérandes
+ * des buffers d'instructions et d'opérandes
+ * un routeur pour délivrer les résultats vers les ports de sorties
+Un prédicteur de branchement va prédire le succès de ce blocs et va fetché et mappé sur la grille le bloc suivant.
+
+Caractéristique influencant les performances :
+- Organisation des ALUs (nombre et position)
+- la latence du réseau d'unterconnection d'un noeud
+- le nombre d'I/O de chaque noeud
+
+Alternatives
+------------
+* Changer le design du réseaux de grille : Préreservations du flow, découpage du message, 
+* Chgt du système mémoire : Format d'instruction compressé, envoyant ce code compréssé au L1. Dcache ~ fifo pour maintenir la cohérence => Utilisation de technique de spéculation.
+* Spéculation de grille
+* Management des frames : Execution de multi thread, thread spéculatif 
+
+
+@article{2002_mukherjee,
+  title={{The Alpha 21364 network architecture}},
+  author={Mukherjee, SS and Bannon, P. and Lang, S. and Spink, A. and Webb, D.},
+  journal={Micro, IEEE},
+  volume={22},
+  number={1},
+  pages={26--35},
+  year={2002}
+}
+@article{2002_tendler,
+  title={{POWER4 system microarchitecture}},
+  author={Tendler, J.M. and Dodson, J.S. and Fields Jr, J.S. and Le, H. and Sinharoy, B.},
+  journal={IBM Journal of Research and Development},
+  volume={46},
+  number={1},
+  pages={5--25},
+  year={2002}
+}
+@Article{2002_ungerer,
+  author = 	 {T. Ungerer and 
+                  B. Robic   and
+                  J. Silc },
+  title = 	 {Multithreaded processors},
+  journal = 	 {The Computer Journal},
+  year = 	 {2002},
+  OPTkey = 	 {},
+  OPTvolume = 	 {45},
+  OPTnumber = 	 {3},
+  OPTpages = 	 {320-348},
+  OPTmonth = 	 {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+17/02/2005
+
+Contrainte de la conception d'un proc multi thread :
+ - Différente logique pour le calcul d'adresse
+ - Les threads doivent avoir une espaces d'adressage commun
+ - Extraction de thread de manière hardware ou software (compilo)
+
+-> implicite multi threading : Chaque architecture va executer de manière concurrentiel différent thread d'un même programme séquentiel (predication de branchement etc...)
+-> explicite multi threading : Execution d'un flots multi programmé
+
+But principal -> recouvrir la latence d'un thread par l'execution d'un autre.
+
+
+Mécanisme minimal :
+- Plusieurs PC
+- Mécanisme pour commuter les threads
+  |-> Potentiellement avoir plusieurs banc de registres permet d'augmenter la commutation
+
+3 approches :
+- multithreading imbriqué  (FMT) : Changement de thread à chaque cycle
+- multithreading bloqué    (VMT) : Changement de thread à chaque évenement (evt induiant une latence => ex div, miss etc ...)
+- multithreading simultané (SMT) : Plusieurs threads actifs en même temps
+
+Fine graine MT
+~~~~~~~~~~~~~~
+L'imbrication de plusieurs threads va limiter la perf de chaque thread
+ -> technique "dependance lookahead" : ajout de bits à chaque inst dans l'isa pour déterminer combien d'inst suivant n'a pas de dépendance avec celle-ci
+ -> technique d'imbrication : chgt de thread à chaque cycle
+
+Diverses "astuces" : Cray-MTA à au moins 128 contextes afin de masquer la latence de la mémoire étant de 128 cycles (Changement de contexte à chaque cycle)
+
+Coarse graine MT
+~~~~~~~~~~~~~~~~
+
+=> Execution d'un thread jusqu'a ce qu'une condition de changement de contexte est atteinte :
+
+ -> Modèle statique
+     -> Chgt explicite (Par instr "switch" ou une instruction "taggé")
+     -> Chgt implicite (Sur load, store, branch etc ...)
+ -> Modèle dynamique
+     -> Chgt sur miss de cache
+     -> Chgt sur evenement (interruption, trap ...)
+     -> Chgt sur profil d'utilisation (trop de chargemement (ou pas accès) etc ...)
+     -> Chgt conditionnel (instruction de switch conditionnelle)
+
+Un plus petit nombre de threads est nécessaire pour atteindre de bonne performance.
+-> Pénalisation d'un thread remplicant souvent la condition de changement de contexte
+
+Avantage de Modèle statique -> le changement de contexte peut être détecter tôt dans le pipeline (Voir tjs dans le même étage).
+
+Simultaneous MT
+~~~~~~~~~~~~~~~
+FMT et CMT sont très performant pour des processeurs scalaire ou VLIW (un flut d'instruction)
+
+L'unité d'IFETCH peut être partagé par plusieurs threads, (Dans ce cas on augmente la probabilité d'aller chercher des instructions non spéculative). 
+De plus l'unité IFECTH peut choisir quel thread privilégié pour aller chercher ces instructions.
+
+ -> Partage de ressources : tous les thread partage un maximum de ressources (ifetch buffer, décodeur, banc de registres, fenêtre d'instruction etc ...)
+ -> Duplication de ressources : Chaque buffer interne appartient à un thread spécifique. Les étages internes peuvent être multiplexé ou dupliqué entre les threads.
+
+Priorité :
+ RR        : Round-Robin
+ ICOUNT    : La priorité est donné au thread ayant le moins d'instructions dans les étages decodes, rename et queue
+ BRCOUNT   : La priorité est donné au thread ayant le moins de branchement (donc le - spéculatif)
+ MISSCOUNT : La priorité est donné au thread ayant le moins de DCACHE miss
+ IQPOSN    : La priorité est donné au thread ayant les plus vieille instructions
+
+SMT peut aussi executer les deux chemins d'un branchement. 
+
+Diverses technique :
+~~~~~~~~~~~~~~~~~~~~
+
+- Division d'un thread en collection de tâches qui sont distribués dans les unités d'executions.
+  -> processeur de trace
+- Processeur "super-threadé" un pipeline d'execution/thread,  peut être alloué par le compilateur
+- dynamic multi threading processor : Création de threads de manière dynamique (sur appel de procédure et déroulement de boucle ...)
+- microthread -> Création d'un microthread de manière explicite => préfetech une donner, calculer en avance la condition de saut ...
+              -> Utilisation des threads "idle"
+- Execution des 2 branches d'un saut -> utilisation des threads "idle"
+                                     -> utilisation de la prédication
+
+Multi-threading et le temps réel
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-> Le chgt de contexte "rapide" est un avantage clé pour les systèmes temps réel.
+-> Le multi threading permet d'avoir la routine d'intérruption et le programme principale dans 2 threads du processeurs
+
+Chip multi processors
+---------------------
+Symetric multiprocessors (SMP) et le Distribued shared Memory multiprocessors (DSM) -> espace mémoire uniforme (UMA)
+un DSM peut également ne pas maintenir la propriété d'espace mémoire uniforme => Communication par passage de message
+
+Cohérence des caches par snooping (SMP) ou directory based (DSM).
+
+3 alternatives de CMP :
+ - mémoire partagé (SMP typique)
+ - L2 partagé
+ - L1 partagé
+partagé les niveaux de caches diminue le délai de communication iter-processeur. Plus d'espaces pour les threads
+
+@article{2003_koufaty,
+  title={{Hyperthreading technology in the netburst microarchitecture}},
+  author={Koufaty, D. and Marr, DT},
+  journal={Micro, IEEE},
+  volume={23},
+  number={2},
+  pages={56--65},
+  year={2003}
+}
+@article{2003_mcnairy,
+  title={{Itanium 2 processor microarchitecture}},
+  author={McNairy, C. and Soltis, D.},
+  journal={Micro, IEEE},
+  volume={23},
+  number={2},
+  pages={44--55},
+  year={2003}
+}
+@InProceedings{2003_sankaralingam,
+  author = 	 { Karthikeyan Sankaralingam   	  and
+                   Ramadass Nagarajan 	 and
+                   Haiming Liu 	 and
+                   Changkyu Kim 	 and
+                   Jaehyuk Huh 	 and
+                   Doug Burger 	 and
+                   Stephen W. Keckler 	 and
+                   Charles R. Moore},
+  title = 	 {Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture},
+  OPTcrossref =  { ISBN:0-7695-1945-8},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the 30th annual international symposium on Computer architecture},
+  OPTpages = 	 {422-433},
+  OPTyear = 	 {2003},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {Volume 31 Issue 2},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {San Diego, California},
+  OPTmonth = 	 {May},
+  OPTorganization = {},
+  OPTpublisher = {ACM Press},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+01/02/2005
+
+Architecture polymorphe : TRIPS
+Peut être configuré pour différente granularité et types de parallélisme => Instruction level paralelism, Thread LP Data LP.
+
+Processeur : Soit on a un général-purpose microprocesseur qui sait tout ou alors on spécialise le processeur :
+ -> Bureautique, network, serveur, scientifique, graphique ou signaux digitaux.
+
+La spécialisation à un défaut :
+ -> Le processeur devient peut performant dans un domaine qui n'est pas sa spécialisation.
+
+Les CMP peuvent être vut de 2 manières :
+ -> Homogène   : Ensemble de processeurs identiques
+ -> Hétérogène : Regroupement de processeurs spécialisé -> mappage d'une application sur cet architecture ...
+    |-> Défauts : * Augmentation de la compléxité
+                  * Sous utilisation des ressources si un thread n'a pas besoin de la spécialité
+
+Une architecture polymorphique est capable de configurer le hard pour exécuter de manière efficace un large spectre d'applications.
+-> Approche synthétique : Utilisation de CMP à grain fin -> synthése de plusieurs éléments de calcul en une large entité logique.
+-> Approche partitionné : Utilisation de CMP à grain grossier => Partitionnement de l'entité la plus large pour exploiter le parrallélisme à grain fin.
+
+Une architecture polymorphe ne va pas surpasser une architecture dédié, mais devrait bien se comporter avec un large spectre d'application.
+
+TRIPS -> Architecture polymorphique, approche partitionné combiné avec un coeur de processeur en grille à grain grossier et avec un système  mémoire on chip adaptatif.
+Objectif -> Avoir un coeur d'architecture qui peut aussi bien être très large que minuscule (scalable)
+
+Architecture TRIPS
+------------------
+Architecture orienté blocs.
+Un programme compilé pour le TRIPS est partitionné en bloc large d'instruction avec un seul point d'entrée, sans boucle et plusieurs point de sorties
+Les blocs valide de manière atomique et les intérruptions sont "blocs précis". (Plus de décision au point de vue instruction mais au point de vue bloc)
+
+Compilateur est résponsable de l'allocation statique de chaque bloc d'instruction dans le le système (Dépendance explicite).
+
+Une opération de flot usuel du proc : Chgt d'un boc depuis la mémoire, chgt dans le moteur de calcul, execution,  reporter les resultats dans la mémoire, chgt d'un autre bloc ...
+
+-> TRIPS est constitué de 4 blocs de 16 coeurs polymorphe. Une grille de 32Ko de mémoire connecter en quadrillage, des ctrl mémoires distribué pour connecter de la mémoire externe.
+-> Chaque blocs est constitué de d'un tableau de noeud d'execution, Il y a un ICACHE L1 par ligne dans la matrice , et une partie du banc de registre par colonne. Sur chaque ligne (droite) il y a également un DCACHE L1. En dessous de la matrice il y a le block de logique de ctrl qui s'occupe du séquencement de ce bloc et de la sélection du prochain bloc. Les caches L1 sont connecté au cache L2 a l'aide d'un interconnect.
+
+-> Chaque noeud d'execution contient une IU, FPU, des stations de réservations, un routeur de connections I/O, un noeud est directement connecter avec ses plus proches voisins, mais peut communiquer avec n'importe quel noeud dans la matrice
+-> Chaque stations de réservations stocke des isntructions et 2 opérandes sources.
+
+3 types principaux de ressources :
+ * hardcoded (ressources utilisées dans tous les mode et non modfiable) ex : interconnect, unité d'execution, cache L1
+ * ressources utilisé dans tous les modes et modifiable
+ * ressources non nécessaires dans tous les modes et pouvant être désactivés.
+
+Gestion du ILP : D-morph
+------------------------
+-> La configuration D-morph traite les buffers d'instructions comme un large, distribué fenêtre de lancement d'instructions. Possibilé d'avoir de l'execution our-of-order
+Le buffer d'instruction doit fournir une large bande passante de chargement d'instruction, un contrôle aggréssif et une spéculation sur les données, une mémoire à faible latence et qui préserve les accès mémoires de manière séquentiels
+
+Vue des buffers comme en trois dimension (x,y sont les coordonées physique dans un bloc et z correspond au nombre de place d'instructions dans chaque noeuds d'ALU.
+Le compilateur va découper le code en hyperblock (morceau de code communicant dans un graphe en 3D et dont il n'y à qu'un net de sortie.) Mappage de ces blocs dans des frames. (Différents slots de buffers sur le même noeuds d'alu). Les A-frame est la zone contenant tous les frame mappant un hyperblock.
+
+Spéculation de Multiblock : Les A-frames vide vont spéculativement chargé et executé un hyperblock. Les A-frames sont traités de manière circulaire : Le buffer de tête étant le moins spéculatif
+
+Instruction fetching -> pc pointe sur les têtes d'hyperblocks. Prédiction sur le prochain hyperblock (et non sur la prochaine instruction). Hyperblock sont codés du style VLIW.
+Interface mémoire : Entrelacement des bancs mémoires -> accès simultané a des adresses non conflictuelles.
+Mémoire secondaire configure le réseau de bank comme un cache à accès non uniform.
+
+Résumé : Prédiction  de fin assuré, grande bande passante pour l'ifecth, Dcache partitioné, execution concourente d'hyperblock (avec le réenvoie des valeur d'interbloc), le Dmorph est capable d'utiliser le buffer d'instrcution comme une fenêtre de lancement out of order
+
+Gestion du TLP : T-morph
+------------------------
+-> fournit un mappage un contrôle pour les multi thread.
+SMT -> cache et unité d'execution sont partagé.
+
+2 stratégies : 
+ - processeurs de lignes -> Partage la matrice d'ALU, en alloue une ou plusieurs lignes par threads. -> chaque thread à un nombre de  ICACHE et un DCACHE proportionnel au nombre de lignes alloué. Attention : La distance du banc de registre n'est pas uniforme (pénalise les lignes inférieurs)
+ - processeurs de frames -> Partage le processeur par un ensemble de frames
+
+|-> Les frames sont partagé entre thread. Un l'intérieur d'un thread, les frmae peuvent être spéculatif (cf D-morph)
+|-> T-morph maintient n PC et n historique de banc de registres
+
+Gestion du DLP : S-morph
+------------------------
+TRIPs est principalement prévut pour les flots multimédia et les calculs scientifiques => contient beaucoup de parrallélisme a niveau donnée
+
+-> fusion des Aframe pour un Super Aframe => Les boucles sont déroullées
+-> mapping reuse : un bloc est gardé dans les stations de réservations pour être utilisé plusieurs fois
+-> Dans les caches, ajout d'une fonctionnalité DMA
+@InProceedings{2004_chaudhuri,
+  author = 	 {Mainak Chaudhuri   and
+                  Mark Heinrich},
+  title = 	 {SMTp: An Architecture for Next-generation Scalable Multi-threading},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the 31st annual international symposium on Computer architecture},
+  OPTpages = 	 {124-136},
+  OPTyear = 	 {2004},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {0},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {München, Germany},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = {IEEE Computer Society},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+17/03/2005
+
+Modification d'uns SMT pour intégré un protocol de cohérence des threads afin de le placer dans un système à mémoire distribué (DSM).
+
+DSM sont scalable, mais s'ils n'utilisent pas de protocoles de snoop. Le directory based impose des structations de tableaux.
+
+Architecture
+------------
+
+Le processeur à une architecture classique :
+ 9 étages : fetch, decode, issue, lecture1, lecture2, exec, cache accès, commit
+fetch suit la politique ICOUNT (cf 1996\_tullsen)
+=> Il y a 2 threads. Tous est partagé sauf pile des adresses de retours, table de mappage, prédicteur dynamqiue
+
+Un noeud est séparé en deux parties :
+ - le coeur du proc
+ - le contrôlleur mémoire
+
+Le protocole de cohérence est lié à un thread. Celui-ci n'execute que cela (programme dédié donc n'est pas visible de l'extérieur). Il n'est pas aborder de solution dynamique (dès que la cohérence est nécessaire, un thread doit executer ce dernier)
+
+Afin d'éviter les deadlocks (applications tournants sur les threads et le threads gérant le protocole partagent les même ressources (file d'execution etc ...)), il y a des ressources dédié au threads executant le protocles des threads.
+
+Performance
+-----------
+3 limitations :
+- Le protocole de thread souffre de la latence du pipeline
+- Le nombre de registre entiers
+- Le DCACHE-L1 et les CACHE-L2 sont partagés entre les applications tounants sur les threads et le protocole de cohérences des threads
+
+@article{2004_dolbeau,
+  title={{CASH: Revisiting hardware sharing in single-chip parallel processor}},
+  author={Dolbeau, R. and Seznec, A.},
+  journal={Journal of Instruction-Level Parallelism},
+  volume={6},
+  pages={1--16},
+  year={2004}
+}
+@article{2004_kalla,
+  title={{IBM Power5 chip: a dual-core multithreaded processor}},
+  author={Kalla, R. and Sinharoy, B. and Tendler, JM},
+  journal={Micro, IEEE},
+  volume={24},
+  number={2},
+  pages={40--47},
+  year={2004}
+}
+@article{2004_kumar,
+  title={{Conjoined-Core Chip Multiprocessing}},
+  author={Kumar, R. and Jouppi, N.P. and Tullsen, D.M.},
+  journal={Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture},
+  pages={195--206},
+  year={2004},
+  publisher={IEEE Computer Society Washington, DC, USA}
+}
+
+@InProceedings{  2004_wang,
+  author = 	 {Nicholas J. Wang and
+		  Justin Quek      and
+                  Todd M. Rafacz   and 
+                  Sanjay J. Pate},
+  title = 	 {Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline},
+  OPTcrossref =  {In the Proceedings of the 2004 International Conference on Dependable Systems and Networks},
+  OPTkey = 	 {},
+  OPTbooktitle = {},
+  OPTpages = 	 {},
+  OPTyear = 	 {2004},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Florence , ITALY},
+  OPTmonth = 	 {june},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+30/11/2004
+
+Moins de 15 \% des corruptions binaires sont visibles du logiciel, des techniques simples d'overhead diminues de 75\% des fautes.
+
+D'ou viennent les fautes :
+ - Sources externe (pulsation electro magnétique)
+ - Sources interne (fuite, bruit da'alimentation ...)
+
+Pour caractériser ses fautes, ils ont définit un modèle de processeur :
+ - ISA alpha
+ - Superscalaire, ordonnacement dynamique (à 32 entrées)
+ - execution spéculative
+ - prédiction des dépendances mémoires
+ - 12 étages de pipelines
+ - 6 inst lancées/cycle
+
+4 types d'erreurs :
+ - Correspondances à un état de la micro architecture
+ - Arret prématuré de la tâche
+ - Corruption d'une donnée
+ - Rien sur le comportement
+
+85\% des fautes sont masqués
+ 3\% sont invisibles
+12\% réalise une execution erronée
+
+=> Les registres visibles sont les plus vulnérables
+
+Types d'erreurs dut à une execution erronnée :
+ - Inconsistence du banc de registres
+ - Inconsistence mémoire
+ - deadlock ou livelock
+ - Accès à une page virtuel invalide (Inst ou data)
+ - Part en exception
+ - Réalise une instruction non demandé
+ 
+Mécanisme de protection :
+ - Timeout => Evite les lock
+ - Code correcteur d'erreur => sur le banc de registres et sur le pointeur de ce banc (register renaming)
+ - Bit de parité => sur le registre IP (il traverse tous le pipeline)
+@article{2005_kongetira,
+  title={{Niagara: a 32-way multithreaded Sparc processor}},
+  author={Kongetira, P. and Aingaran, K. and Olukotun, K.},
+  journal={IEEE Micro},
+  volume={25},
+  number={2},
+  pages={21--29},
+  year={2005}
+}
+@article{2005_mcnairy,
+  title={{Montecito: a dual-core, dual-thread Itanium processor}},
+  author={McNairy, C. and Bhatia, R.},
+  journal={Micro, IEEE},
+  volume={25},
+  number={2},
+  pages={10--20},
+  year={2005}
+}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/01_abstract.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/01_abstract.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/01_abstract.tex	(revision 3)
@@ -0,0 +1,2 @@
+\section{Résumé}
+Dans ce document nous allons aborder l'incidence du partage des caches de niveau 1, de la partie opérative et de la partie exécutive d'un processeur. Ceci n'est qu'une étude de performance en terme d'exécution, mais nous pouvons en déduire que le partage des caches fait perdre 10\% de performances, le partage de la partie exécutif n'influe que légerement, à l'oposé de la partie opérative qui fait chuter les performances de 2,7 entre un CMP de degré 4 et un SMT de même degré.
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/02_introduction.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/02_introduction.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/02_introduction.tex	(revision 3)
@@ -0,0 +1,9 @@
+\section{Introduction}
+
+De nos jours, la capacité d'intégration augmente. Un concepteur possède un ``tas'' de transistors toujours plus grand à sa disposition. L'objectif des vingt dernières années étaient d'avoir un processeur monolithique pouvant extraire le plus d'ILP (Instruction Level Parallelism) possible. Les études de David W. Wall \cite{1991_wall} montre que le parallélisme moyen est de 3-5 instructions. Les mono processeurs de la fin du XXème siècles comme le MipsR10000 \cite{1996_yeager}, l'alpha 21264 \cite{1998_kessler}, le pentium 4 \cite{2001_hinton} ou encore l'Itanium et l'Itanium 2 d'Intel \cite{2000_sharangpani}, \cite{2003_mcnairy} exploitent tous fortement l'ILP. Dans le même laps de temps des systèmes CMP (Chip Multi Processors) émergaient. Ils consitents en plusieurs processeurs exploitant faiblement l'ILP. Mais le système d'exploitation peut alors éxecuter plusieurs tâches simultanéments. Ces CMP exploitent le TLP (Thread Level Paralelism). Dans cette catégorie nous pouvons citer le piranha de Compaq \cite{2000_barroso}, l'Hydra de Stanford \cite{2000_hammond}. On peut également citer le Power4 \cite{2002_tendler} ou l'alpha 21364 \cite{2002_mukherjee} qui sont des processeurs monolithiques mais étant conçut pour être intégrer dans un environnement multi-processeur.
+
+En prenant en compte la sous exploitation des ressources internes des processeurs mono-core, une autre voie pour exploiter le TLP à émerger. Elle consiste à intégrer non pas un mais plusieurs contextes par core. Ceci est la technique du Multi-threading et de sa variante le SMT (Simultaneous multi threading). C'est principalement les travaux de recherches de l'équipe de Tullsen \cite{1995_tullsen}, \cite{1996_tullsen}. Pour un ajout minime en surface (une duplication de quelques registres d'état, des multiplexeurs ...), nous pouvons avoir des processeurs mono-core multi-threadé. Ceci à vut l'apparition du Pentium 4 Hyperthreading d'Intel \cite{2003_koufaty} (ajoutant de 5\% en surface pour un gain de performance de 30\%). 
+
+Il y a deux grandes lignes de conduites : Les ressources sont soit totalement dédiés à une tâches (cas des CMP classique), soit totalement partagés entre plusieurs tâches (cas des SMT). Entre ces deux voies, nous pouvons faire varier le degré de partage des ressources entre les tâches. C'est à dire que les ressources internes d'un core ne sont partagées de manière uniformes entre tous les threads. Ils y a alors l'émergence de CMP de SMT. Le POWER 5 \cite{2004_kalla} est un dual-core où chaque core est SMT de degré 2. De même pour le montecito d'Intel \cite{2005_mcnairy}. Alors que le Niagara de Sun intégre 8 cores de CMT (Corse Grain Multi Threanding) de degré 4 \cite{2005_kongetira}.
+
+L'objectif de ce papier est d'analyser en terme de performance le partage des ressources d'un processeur. Pour cela, nous allons voir dans la section \ref{experimentations} les éxperimentations que nous allons réaliser, ainsi que celles qui ont déjà été réalisé. Dans la section \ref{methodologie} nous allons montrer nos hypothèse de travail. Suivit d'une section interprétant les résultats.
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/03_experimentation.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/03_experimentation.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/03_experimentation.tex	(revision 3)
@@ -0,0 +1,79 @@
+\section{Experimentations}\label{experimentations}
+Le SMT est une solution Bas coût d'obtenir une SMT. Elle à aussi l'avantage de tirer profit des systèmes Single Thread. Car Comme les ressources sont intégralement partagé, s'il n'y a qu'un seul thread à éxecuter, il pourra utiliser l'intégralité des ressources du processeur. Avoir plusieurs thread éxecutable en parralléle permet de mieux exploiter les ressources du processeur.
+
+Malheuresement cette solution à deux problèmes importants. Le premier est que comme les threads sont en compétition pour obtenir les ressources, la rapidité d'execution d'un thread dépend des autres thread en compétition. Par exemple si tous les threads font des accès mémoires fréquents, l'unité mémoire va rapidement saturée. Le deuxième problème étant la polution des ressources partagées. Les meilleurs exemples sont les caches et la BTB (Branch Target Buffer). Suivant les activités des autres threads, des lignes de caches peuvent être désalloué à un thread en faveur à un autre même s'il elle lui était utile. De plus les actions comme le prefetch ou la prediciton de branchement risque de privé des threads de lignes utiles contre une hypothétique ligne utile pour le thread bénéficiaire.
+
+Pour ces raisons, nous allons faire varier le degré de partage des ressources. Des travaux équivalent ont été réalisé. Dans \cite{2004_dolbeau}, ils étudient l'influence du partage des des unités à latence longue (multiplication, division ...), du prédicteur de branchement, ainsi que des caches Instructions et Données. Pour ce faire, ils ont implémentés l'architecture {\bf CASH} (CMP And SMP Hybrid) qui consiste en 4 cores. Dans un autre article, \cite{2004_kumar}, il y a une étude en terme de performance d'éxecution mais également en terme de surface du partage des unités flottantes, des ports du crossbar reliant les Caches à la mémoire et des caches instructions et données. Ici l'équipe de Tullsen à valider leur hypothèses sur un système à 8 cores. Le partage des ressources ce fait entre deux cores voisins.
+
+Notre approche consiste à tester l'incidence du partage des caches, des Unités d'éxecutions et du Front End et Back end (Que les threads se partage tous les ressources qui ne sont pas les unités d'excutions).
+
+Nous démominons les partage comme suit :
+\begin{description}
+\item[Cluster :] Les clusters ce partage les caches de niveaux 2 et les unités d'executions.
+\item[Unité de lancement :] Les unités d'éxecutions ce partage les ports des caches de niveaux 1 et les unités d'éxecutions.
+\item[Contexte :] Les contextes ce partages l'accès au décodeur, au icache et au prédicteur de branchement.
+\end{description}
+
+L'expérimentation ce fait avec le générateur de processeur MORPHEO (acronyme de ``Multi ORganisation for a Processor HEterogeneous and Open''). Une vue d'ensemble de l'architecture résultante peut être vue dans la figure \ref{MORPHEO_overview}. 
+
+\printgraph{MORPHEO_overview}{0.45}{MORPHEO - Vue d'ensemble}
+
+Notre allons analyser l'incidence du partage des ressources au niveau Cluster, UL et Contexte dans un système à 4 Threads, pouvant lancer à chaque cycle 8 instructions. Trois tableaux rémusent les caractérisques communes de chaque instance ainsi que les paramètres spécifiques pour les configurations avec 1,2 et 4 cores (nous définisions un core une UL ou un cluster). Le troisème résument le systèmes mémoires
+
+\begin{center}
+\begin{tabular}{|l|c|}
+  \hline
+  \multicolumn{2}{|c|}{Caractéristiques communes}               \\
+  \hline
+  Unité d'éxecutions                           & 8              \\
+  Profondeur des Stations de Réservations      & 4		\\
+  Nombre de branchements spéculés              & 8 		\\
+  Return Address Stack                         & 16		\\
+  Réseau de bypass                             & Complet        \\
+  Nombre de port de lecture                    & 12		\\
+  Nombre de port d'écriture                    & 8		\\
+  \hline
+\end{tabular}
+\end{center}
+
+\begin{center}
+\begin{tabular}{|l|ccc|}
+  \hline
+  \multicolumn{4}{|c|}{Caractéristiques spécifiques}            \\
+  \hline
+                                               & 1 core		& 2 cores	& 4 cores	\\
+  \hline
+  Largeur du pipeline                          & 8 		& 4 		& 2 		\\
+  Taille - Ifetch\_queue                       & 8 		& 4 		& 2 		\\
+  Taille - Issue queue                         & 32		& 16 		& 8 		\\
+  Taille - Re Order Buffer                     & 128		& 64 		& 32  		\\
+  Taille - autres                              & 16		& 8 		& 4  		\\
+  Largeur des fenêtres                         & 16		& 8 		& 4 		\\
+  Branch Target Buffer                         & 256	        & 128 	        & 64 	        \\
+  Méta prédicteur                              & 16k		& 8k		& 4k		\\
+  Banc de Registres                            & 256        	& 128      	& 64      	\\
+  \hline
+\end{tabular}
+\end{center}
+   
+\begin{center}
+\begin{tabular}{|l|cc|}
+  \hline
+  \multicolumn{3}{|c|}{Caractéristiques du système mémoire}\\
+  \hline
+	                     & L1          & L2             \\
+	                     & I/D séparé  & unifié         \\
+	\hline
+	Taille               & 8 ko        & 2 Mo           \\
+	Nombre de lignes     & 128*        & 16k            \\
+	Nombre de mots/ligne & 16          & 32             \\
+	Associativité        & 4 voies     & 4 voies        \\
+	Latence - Hit        & 2 cycles    & 6 cycles       \\
+	Pénalités - Miss     & 4 cycles    & 100 cycles     \\
+  \hline
+\end{tabular}
+\end{center}
+
+(Le nombre de lignes du premier niveau de cache est divisé par le nombre de cluster).
+
+Nous allons maintenant voir la méthodologie de test.
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/04_methodologie.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/04_methodologie.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/04_methodologie.tex	(revision 3)
@@ -0,0 +1,38 @@
+\section{Méthodologie}\label{methodologie}
+
+\subsection{Charge de travails}
+
+Dans un premier temps, nous avons sélectionné 6 benchmarks parmit les SPECINT2000 (164.gzip, 175.vpr, 181.mcf, 255.vortex, 256.bzip2, 300.twolf). Nous ne les avons pas tous sélectionnée afin de ne pas avoir trop de simulations à effectuer et car tous les benchmarks ne fonctionnes pas (problème de compatibilité avec gcc 4 et avec notre modèle).
+
+
+Le nombre de software soumit au architecture est décrite par la combinaison $C_{nb\_benchmarks}^{nb\_threads}$. Comme le nombre de benchmark est de 6 pour 4 threads possible, nous obtenons une charge de travails composée de 15 simulations.
+
+Pour les libraries standard (libc et libm) ainsi que les fonctions bas niveaux (read, write, open, close ...) qu'un système d'exploitation ce doit d'offrit, nous utilisons la librairie {\it Newlib}.
+
+\subsection{Simulation}
+
+Pour les simulations, nous avons prit 14 instances de notre modèle. Elle sont déterminer par le nombre de cluster (A), le nombre d'UL de chaque cluster (B) et le nombre de contexte de chaque UL (C). De plus chaque UL n'a accès qu'a un sous ensemble distinct d'ALU. Le nombre d'ALU accèssible par un core est définit par la taille du groupe (D).
+
+Si E=A*B*C, nous nommerons une instance x$E$\_$A$\_$B$\_$C$-$D$. Le tableau suivant récapitules toutes les instances que nous avons sélectionnés.
+
+\begin{tabular}{ccccc}
+Nom          & Cluster & UL & Contexte & Taille groupe d'ALUs\\
+x4-1\_1\_4-8 & 1       & 1  & 4        & 8\\
+x4-1\_2\_2-8 & 1       & 2  & 2        & 8\\
+x4-1\_2\_2-4 & 1       & 2  & 2        & 4\\
+x4-1\_4\_1-8 & 1       & 4  & 1        & 8\\
+x4-1\_4\_1-2 & 1       & 4  & 1        & 2\\
+x4-2\_1\_2-8 & 2       & 1  & 2        & 8\\
+x4-2\_1\_2-4 & 2       & 1  & 2        & 4\\
+x4-2\_2\_1-8 & 2       & 2  & 1        & 8\\
+x4-2\_2\_1-4 & 2       & 2  & 1        & 4\\
+x4-2\_2\_1-2 & 2       & 2  & 1        & 2\\
+x4-4\_1\_1-8 & 4       & 1  & 1        & 8\\
+x4-4\_1\_1-4 & 4       & 1  & 1        & 4\\
+x4-4\_1\_1-2 & 4       & 1  & 1        & 2\\
+\end{tabular}
+
+Nous simulerons 110 millions de cycles. Les 10 premiers millions seront ignorés afin de ne pas dégrader les résultats avec des miss à froid des caches et des unités de spéculations. Pour chaque instance, nous prenons le nombre d'instructions éxecutée des 15 simulations. Ce résultat est comparer à la moyenne des 6 benchmarks éxecuter dans la version Single Thread du processeur (execution séquentiels des 6 benchmarks avec la même instance).
+
+Nous pouvons remarque que les instances ne vont pas être comparé entre eux par une instance de référence, mais serons comparer avec le speedup de la version MT par rapport à la version ST. Ceci à la bonne propriété d'avoir une borne maximal au speed up qui est le nombre de thread (ici 4). 
+
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/05_resultat.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/05_resultat.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/05_resultat.tex	(revision 3)
@@ -0,0 +1,51 @@
+\section{Résultat}\label{resultat}
+
+La simulation nous fournit le graph \ref{simulation_all}
+
+\printgraphonly{simulation_all}{0.6}
+
+Première constation simple : plus on dédicace les ressources, plus nous approchons du speed up maximal. La version du x4\_4\_1\_1-2 ne partage que les caches de niveau L2, et est donc une version CMP pure, atteind un speed up de 3,92. Alors que la version x4-1\_1\_4-8 qui est un SMT pur à un speed up de 1.46. 
+
+Attention dans l'interprétation des résultats, car ici nous ne comparons qu'en terme de performances l'incidence du partage des ressources matériels. Pour que l'études soit complètes, nous devons aussi ajouté l'augmentation de la surface entre la version MT et la version ST et comparé alors le rapport entre l'augmentation de la performance sur le coût matériel.
+
+En terme de performance, il y a une speedup de 2,7 entre la version CMP et la version SMT. Si nous faisons une étude abstraite du coût en surface, le rapport de surface entre la version MT et ST de l'instance x4-4\_1\_1-2 est de 4. Si nous réutilisons les estimations d'intel pour le Pentium 4 HT \cite{2003_koufaty} indiquant que l'ajout d'un Contexte est de 5\%, trois contextes de plus nous amène à 15\% soit un rapport de surface entre la version MT et ST de l'instance x4\_1\_1\_4-8 est de 1,15. Le rapport performance/surface pour la version CMP de degré 4 nous donnes 0,98 alors que la version SMT de degré 4 nous donnes 1,27.
+
+Pour le partage du cache, nous pouvons tirer enseignement des 3 instances suivantes :
+\begin{itemize}
+\item x4-4\_1\_1-2 avec 4 Icaches et Dcaches L1 de 2k chacun et accessible par un seul thread . Le speed-up de 3,92.
+\item x4-2\_2\_1-2 avec 2 Icaches et Dcaches L1 de 4k chacun et accessible par deux    threads. Le speed-up de 3,63.
+\item x4-1\_4\_1-2 avec 1 Icache  et Dcache  L1 de 8k chacun et accessible par quatre  threads. Le speed-up de 3,27.
+\end{itemize}
+
+Le partage du cache induit des conflits d'accès au port : dans le premier cas, il y a 4 ports d'accés au icache de largeur de deux instructions. Alors que dans le troisième cas, il n'y a qu'un port de largeur de 8 instructions. Les paquets de 8 instructions permettent de mieux exploiter l'ILP mais moins le TLP : chaque contexte doit attendre 4 cycles avant de prendre un nouveau paquet. De plus, le partage du cache entraîne un effet de bord : le pourrissement du contenus du caches par les autres threads, et un allongements du temps de réponces des miss dut au plus grand nombre de miss et à la plus grande longueur des lignes. Le cache, optimisé pour être tirer partie de la localité spatiale et temporelles des instructions et des données ce retrouve confrontés à plusieurs flots.
+
+Enfin pour le partage de la partie éxecutive, nous pouvons observé les instances suivantes :
+\begin{itemize}
+\item x4-2\_2\_1-2 où il y a 4 groupes de 2 ALUs et chacune est accéssible par 1 Threads. Le speed-up est de 3.63.
+\item x4-2\_2\_1-4 où il y a 2 groupes de 4 ALUs et chacune est accéssible par 2 Threads. Le speed-up est de 3.41.
+\item x4-2\_2\_1-8 où il y a 1 groupe  de 8 ALUs et         est accéssible par 4 Threads. Le speed-up est de 3.38.
+\end{itemize}
+
+Le partage des unités d'éxecutions n'influe que légèrement sur les performances. Les ressources sont plus utilisés, mais implique un effet de bord : elle augmente la sensibilité du aux erreux de routages (envoye vers une ALUs surchargés alors que d'autres ALUs sont en famine). Ceci est également du à notre politique actuel qui est un round robin classique.
+
+Notons que dans le cas où il y a plus d'un contexte par core (x4-1\_2\_2-8 et x4-1\_2\_2-4 qui ont eu deux un speed-up de 2.37 alors que les instances x4-2\_1\_2-8 et x4-2\_1\_2-4 on un speed-up respectif de 2.51 et 2.4) le partage des unités d'executions est favorable. Ceci peut être expliquer par une bonne exploitation du TLP : la fenêtre de lancement est mieux exploiter et le réseau de routage à plus d'instruction à sa disposition. 
+
+% Il y a aussi une hétérogéneité des instructions longues.
+
+Pour le partage opérative, voyons les instances suivantes :
+\begin{itemize}
+\item x4-1\_1\_4-8, 1 cluster  possèdant chacun 1 UL  avec 4 contextes chacun. Le speed-up est de 1.46.
+\item x4-1\_2\_2-8, 1 cluster  possèdant chacun 2 ULs avec 2 contextes chacun. Le speed-up est de 2.37.
+\item x4-1\_4\_1-8, 1 cluster  possèdant chacun 4 ULs avec 1 contexte  chacun. Le speed-up est de 2.94.
+\item x4-2\_1\_2-8, 2 clusters possèdant chacun 1 UL  avec 2 contextes chacun. Le speed-up est de 2.51.
+\item x4-2\_2\_1-8, 2 clusters possèdant chacun 2 ULs avec 1 contexte  chacun. Le speed-up est de 3.38.
+\item x4-4\_1\_1-8, 4 clusters possèdant chacun 1 UL  avec 1 contexte  chacun. Le speed-up est de 3.94.
+\end{itemize}
+
+Le partage de la partie opérative donne des résultats très disparates et demande une analyse plus poussés des resultats. Nous pouvons noté qu'il y a une augmentation de la sensiblité des instructions de synchronisation et des instructions d'accès au registres spéciaux (car nous imposons qu'avant d'éxecuter une instruction d'accès au registres spéciaux que le pipeline soit vide.)
+
+Tous comme une augmentation des miss de spéculations dut au partage du prédicteur de branchement. Ceci implique qu'il y a une augmentation de nombres des instructions inutiles dans le pipeline (dans x4-1\_1\_4-8 représente 6,12\% des instructions, alors qu'il ne représente que 2,17\% dans l'instance x4-4\_1\_1-8). Ceci est aussi dut à la largeur du pipeline et donc à la sous exploitation de L'ILP. Lors du decodage, nous choissisons de manière round robin la fetch queue contenant un paquet. Dans l'instance x4-4\_1\_1-8, 4 decodeurs décode chacun en moyenne 1,63 instruction sur des paquets de 2 instruction alors que dans l'instance x4-1\_1\_4-8, 1 décodeur prend un paquet de 8 instructions et en décodent en moyenne 3,7. Ceci est dut qu'un paquet d'instruction est aligné et à la présence de branchements.
+
+
+
+
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/06_conclusion.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/06_conclusion.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/06_conclusion.tex	(revision 3)
@@ -0,0 +1,5 @@
+\section{Conclusion}
+
+Cette étude à démontrer un fait déjà acquis, que le speedup entre la version MT et la version ST d'un processeur diminue avec l'augmentation du partage du ressource. 
+
+Notre modèle de processeur étant encore en cours de dévellopement, nous nous destinons à fournir un modèle VHDL synthétisable. Ainsi la prochaine étude porteras sur le coût surfacique du partage des ressources matériels et ainsi déterminer quel degré de partage apporte le meilleur ratio performance/surface.
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/root.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/root.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr.old/root.tex	(revision 3)
@@ -0,0 +1,7 @@
+\input{\dirroot/01_abstract}
+\input{\dirroot/02_introduction}
+\input{\dirroot/03_experimentation.tex}
+\input{\dirroot/04_methodologie.tex}
+\input{\dirroot/05_resultat.tex}
+\input{\dirroot/06_conclusion.tex}
+\bibliography{\dircommon/bibliographie}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/01_abstract.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/01_abstract.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/01_abstract.tex	(revision 3)
@@ -0,0 +1,2 @@
+\section{Résumé}
+Dans ce document nous allons aborder l'incidence du partage des caches de niveau 1, de la partie opérative et de la partie exécutive d'un processeur. Ceci n'est qu'une étude de performance en terme d'exécution, mais nous pouvons en déduire que le partage des caches fait perdre 10\% de performances, le partage de la partie exécutif n'influe que légèrement, à l'opposé de la partie opérative qui fait chuter les performances de 2,7 entre un CMP de degré 4 et un SMT de même degré.
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/02_introduction.tex
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--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/02_introduction.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/02_introduction.tex	(revision 3)
@@ -0,0 +1,9 @@
+\section{Introduction}
+
+De nos jours, la capacité d'intégration augmente. Un concepteur possède un ``tas'' de transistors toujours plus grand à sa disposition. L'objectif des vingt dernières années étaient d'avoir un processeur monolithique pouvant extraire le plus d'ILP (Instruction Level Parallelism) possible. Les études de David W. Wall \cite{1991_wall} montre que le parallélisme moyen est de 3-5 instructions. Les mono processeurs de la fin du XX ème siècles comme le MipsR10000 \cite{1996_yeager}, l'alpha 21264 \cite{1998_kessler}, le pentium 4 \cite{2001_hinton} ou encore l'Itanium et l'Itanium 2 d'Intel \cite{2000_sharangpani}, \cite{2003_mcnairy} exploitent tous fortement l'ILP. Dans le même laps de temps des systèmes CMP (Chip Multi Processors) émergeaient. Ils consistent en plusieurs processeurs exploitant faiblement l'ILP. Mais le système d'exploitation peut alors exécuter plusieurs tâches simultanément. Ces CMP exploitent le TLP (Thread Level Parallelism). Dans cette catégorie nous pouvons citer le piranha de Compaq \cite{2000_barroso}, l'Hydra de Stanford \cite{2000_hammond}. On peut également citer le Power4 \cite{2002_tendler} ou l'alpha 21364 \cite{2002_mukherjee} qui sont des processeurs monolithiques mais étant conçut pour être intégrer dans un environnement multi-processeur.
+
+En prenant en compte la sous exploitation des ressources internes des processeurs mono-core, une autre voie pour exploiter le TLP à émerger. Elle consiste à intégrer non pas un mais plusieurs contextes par core. Ceci est la technique du Multi-threading et de sa variante le SMT (Simultaneous multi threading). C'est principalement les travaux de recherches de l'équipe de Tullsen \cite{1998_tullsen}, \cite{1996_tullsen}. Pour un ajout minime en surface (une duplication de quelques registres d'état, des multiplexeurs ...), nous pouvons avoir des processeurs mono-core multi-thread. Ceci à vu l'apparition du Pentium 4 Hyper-Threading d'inter \cite{2003_koufaty} (ajoutant de 5\% en surface pour un gain de performance de 30\%). 
+
+Il y a deux grandes lignes de conduites : Les ressources sont soit totalement dédiés à une tâches (cas des CMP classique), soit totalement partagés entre plusieurs tâches (cas des SMT). Entre ces deux voies, nous pouvons faire varier le degré de partage des ressources entre les tâches. C'est à dire que les ressources internes d'un core ne sont partagées de manière uniformes entre tous les threads. Ils y a alors l'émergence de CMP de SMT. Le POWER 5 \cite{2004_kalla} est un dual-core où chaque core est SMT de degré 2. De même pour le montecito d'Intel \cite{2005_mcnairy}. Alors que le Niagara de Sun intègre 8 cores de CMT (Corse Grain Multi Threading) de degré 4 \cite{2005_kongetira}.
+
+L'objectif de ce papier est d'analyser en terme de performance le partage des ressources d'un processeur. Pour cela, nous allons voir dans la section \ref{experimentations} les expérimentations que nous allons réaliser, ainsi que celles qui ont déjà été réalisé. Dans la section \ref{methodologie} nous allons montrer nos hypothèse de travail. Suivit d'une section interprétant les résultats.
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/03_experimentation.tex
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--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/03_experimentation.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/03_experimentation.tex	(revision 3)
@@ -0,0 +1,79 @@
+\section{Experimentations}\label{experimentations}
+Le SMT est une solution Bas coût d'obtenir une SMT. Elle à aussi l'avantage de tirer profit des systèmes Single Thread. Car Comme les ressources sont intégralement partagé, s'il n'y a qu'un seul thread à exécuter, il pourra utiliser l'intégralité des ressources du processeur. Avoir plusieurs threads exécutable parallèlement permet de mieux exploiter les ressources du processeur.
+
+Malheureusement cette solution à deux problèmes importants. Le premier est que comme les threads sont en compétition pour obtenir les ressources, la rapidité d'exécution d'un thread dépend des autres thread en compétition. Par exemple si tous les threads font des accès mémoires fréquents, l'unité mémoire va rapidement saturée. Le deuxième problème étant la pollution des ressources partagées. Les meilleurs exemples sont les caches et la BTB (Branch Target Buffer). Suivant les activités des autres threads, des lignes de caches peuvent être désallouées à un thread en faveur à un autre même s'il elle lui était utile. De plus les actions comme le prefetch ou la prédiction de branchement risque de privé des threads de lignes utiles contre une hypothétique ligne utile pour le thread bénéficiaire.
+
+Pour ces raisons, nous allons faire varier le degré de partage des ressources. Des travaux équivalent ont été réalisé. Dans \cite{2004_dolbeau}, ils étudient l'influence du partage des des unités à latence longue (multiplication, division ...), du prédicteur de branchement, ainsi que des caches Instructions et Données. Pour ce faire, ils ont implémentés l'architecture {\bf CASH} (CMP And SMT Hybrid) qui consiste en 4 cores. Dans un autre article, \cite{2004_kumar}, il y a une étude en terme de performance d'exécution mais également en terme de surface du partage des unités flottantes, des ports du crossbar reliant les Caches à la mémoire et des caches instructions et données. Ici l'équipe de Tullsen à valider leur hypothèses sur un système à 8 cores. Le partage des ressources ce fait entre deux cores voisins.
+
+Notre approche consiste à tester l'incidence du partage des caches, des Unités d'exécutions et du Front End et Back end (Que les threads se partage tous les ressources qui ne sont pas les unités d'exécutions).
+
+Nous nommons les partages comme suit :
+\begin{description}
+\item[Cluster :] Les clusters ce partage les caches de niveaux 2 et les unités d'exécutions.
+\item[Unité de lancement :] Les unités d'exécutions ce partage les ports des caches de niveaux 1 et les unités d'exécutions.
+\item[Contexte :] Les contextes ce partages l'accès au décodeur, au Icache et au prédicteur de branchement.
+\end{description}
+
+L'expérimentation ce fait avec le générateur de processeur MORPHEO (acronyme de ``Multi ORganisation for a Processor HEterogeneous and Open''). Une vue d'ensemble de l'architecture résultante peut être vue dans la figure \ref{MORPHEO_overview}. 
+
+\printgraph{MORPHEO_overview}{0.45}{MORPHEO - Vue d'ensemble}
+
+Notre allons analyser l'incidence du partage des ressources au niveau Cluster, UL et Contexte dans un système à 4 Threads, pouvant lancer à chaque cycle 8 instructions. Trois tableaux résument les caractéristiques communes de chaque instance ainsi que les paramètres spécifiques pour les configurations avec 1,2 et 4 cores (nous définissons un core une UL ou un cluster). Le troisième résument le systèmes mémoires
+
+\begin{center}
+\begin{tabular}{|l|c|}
+  \hline
+  \multicolumn{2}{|c|}{Caractéristiques communes}               \\
+  \hline
+  Unité d'exécutions                           & 8              \\
+  Profondeur des Stations de Réservations      & 4		\\
+  Nombre de branchements spéculés              & 8 		\\
+  Return Address Stack                         & 16		\\
+  Réseau de bypass                             & Complet        \\
+  Nombre de port de lecture                    & 12		\\
+  Nombre de port d'écriture                    & 8		\\
+  \hline
+\end{tabular}
+\end{center}
+
+\begin{center}
+\begin{tabular}{|l|ccc|}
+  \hline
+  \multicolumn{4}{|c|}{Caractéristiques spécifiques}            \\
+  \hline
+                                               & 1 core		& 2 cores	& 4 cores	\\
+  \hline
+  Largeur du pipeline                          & 8 		& 4 		& 2 		\\
+  Taille - Ifetch\_queue                       & 8 		& 4 		& 2 		\\
+  Taille - Issue queue                         & 32		& 16 		& 8 		\\
+  Taille - Re Order Buffer                     & 128		& 64 		& 32  		\\
+  Taille - autres                              & 16		& 8 		& 4  		\\
+  Largeur des fenêtres                         & 16		& 8 		& 4 		\\
+  Branch Target Buffer                         & 256	        & 128 	        & 64 	        \\
+  Méta prédicteur                              & 16k		& 8k		& 4k		\\
+  Banc de Registres                            & 256        	& 128      	& 64      	\\
+  \hline
+\end{tabular}
+\end{center}
+   
+\begin{center}
+\begin{tabular}{|l|cc|}
+  \hline
+  \multicolumn{3}{|c|}{Caractéristiques du système mémoire}\\
+  \hline
+	                     & L1          & L2             \\
+	                     & I/D séparé  & unifié         \\
+	\hline
+	Taille               & 8 ko        & 2 Mo           \\
+	Nombre de lignes     & 128*        & 16k            \\
+	Nombre de mots/ligne & 16          & 32             \\
+	Associativité        & 4 voies     & 4 voies        \\
+	Latence - Hit        & 2 cycles    & 6 cycles       \\
+	Pénalités - Miss     & 4 cycles    & 100 cycles     \\
+  \hline
+\end{tabular}
+\end{center}
+
+(Le nombre de lignes du premier niveau de cache est divisé par le nombre de cluster).
+
+Nous allons maintenant voir la méthodologie de test.
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/04_methodologie.tex
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--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/04_methodologie.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/04_methodologie.tex	(revision 3)
@@ -0,0 +1,38 @@
+\section{Méthodologie}\label{methodologie}
+
+\subsection{Charge de travails}
+
+Dans un premier temps, nous avons sélectionné 6 benchmarks parmi les SPECINT2000 (164.gzip, 175.vpr, 181.mcf, 255.vortex, 256.bzip2, 300.twolf). Nous ne les avons pas tous sélectionnée afin de ne pas avoir trop de simulations à effectuer et car tous les benchmarks ne fonctionnes pas (problème de compatibilité avec gcc 4 et avec notre modèle).
+
+
+Le nombre de software soumit au architecture est décrite par la combinaison $C_{nb\_benchmarks}^{nb\_threads}$. Comme le nombre de benchmark est de 6 pour 4 threads possible, nous obtenons une charge de travails composée de 15 simulations.
+
+Pour les libraries standard (libc et libm) ainsi que les fonctions bas niveaux (read, write, open, close ...) qu'un système d'exploitation ce doit d'offrir, nous utilisons la librairie {\it Newlib}.
+
+\subsection{Simulation}
+
+Pour les simulations, nous avons prit 14 instances de notre modèle. Elle sont déterminer par le nombre de cluster (A), le nombre d'ULs de chaque cluster (B) et le nombre de contexte de chaque UL (C). De plus chaque UL n'a accès qu'a un sous ensemble distinct d'ALUs. Le nombre d'ALUs accessible par un core est définit par la taille du groupe (D).
+
+Si E=A*B*C, nous nommerons une instance x$E$\_$A$\_$B$\_$C$-$D$. Le tableau suivant récapitules toutes les instances que nous avons sélectionnés.
+
+\begin{tabular}{ccccc}
+Nom          & Cluster & UL & Contexte & Taille groupe d'ALUs\\
+x4-1\_1\_4-8 & 1       & 1  & 4        & 8\\
+x4-1\_2\_2-8 & 1       & 2  & 2        & 8\\
+x4-1\_2\_2-4 & 1       & 2  & 2        & 4\\
+x4-1\_4\_1-8 & 1       & 4  & 1        & 8\\
+x4-1\_4\_1-2 & 1       & 4  & 1        & 2\\
+x4-2\_1\_2-8 & 2       & 1  & 2        & 8\\
+x4-2\_1\_2-4 & 2       & 1  & 2        & 4\\
+x4-2\_2\_1-8 & 2       & 2  & 1        & 8\\
+x4-2\_2\_1-4 & 2       & 2  & 1        & 4\\
+x4-2\_2\_1-2 & 2       & 2  & 1        & 2\\
+x4-4\_1\_1-8 & 4       & 1  & 1        & 8\\
+x4-4\_1\_1-4 & 4       & 1  & 1        & 4\\
+x4-4\_1\_1-2 & 4       & 1  & 1        & 2\\
+\end{tabular}
+
+Nous simulerons 110 millions de cycles. Les 10 premiers millions seront ignorés afin de ne pas dégrader les résultats avec des miss à froid des caches et des unités de spéculations. Pour chaque instance, nous prenons le nombre d'instructions exécutée des 15 simulations. Ce résultat est comparé à la moyenne des 6 benchmarks exécutés dans la version Single Thread du processeur (execution séquentiels des 6 benchmarks avec la même instance).
+
+Nous pouvons remarque que les instances ne vont pas être comparé entre eux par une instance de référence, mais serons comparer avec le speedup de la version MT par rapport à la version ST. Ceci à la bonne propriété d'avoir une borne maximal au speed up qui est le nombre de thread (ici 4). 
+
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/05_resultat.tex
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--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/05_resultat.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/05_resultat.tex	(revision 3)
@@ -0,0 +1,51 @@
+\section{Résultat}\label{resultat}
+
+La simulation nous fournit le graph \ref{simulation_all}
+
+\printgraphonly{simulation_all}{0.6}
+
+Première constatation simple : plus on dédicace les ressources, plus nous approchons du speed up maximal. La version du x4\_4\_1\_1-2 ne partage que les caches de niveau L2, et est donc une version CMP pure, atteint un speed up de 3,92. Alors que la version x4-1\_1\_4-8 qui est un SMT pur à un speed up de 1.46. 
+
+Attention dans l'interprétation des résultats, car ici nous ne comparons qu'en terme de performances l'incidence du partage des ressources matériels. Pour que l'étude soit complètes, nous devons aussi ajouté l'augmentation de la surface entre la version MT et la version ST et comparé alors le rapport entre l'augmentation de la performance sur le coût matériel.
+
+En terme de performance, il y a une speedup de 2,7 entre la version CMP et la version SMT. Si nous faisons une étude abstraite du coût en surface, le rapport de surface entre la version MT et ST de l'instance x4-4\_1\_1-2 est de 4. Si nous réutilisons les estimations d'Intel pour le Pentium 4 HT \cite{2003_koufaty} indiquant que l'ajout d'un Contexte est de 5\%, trois contextes de plus nous amène à 15\% soit un rapport de surface entre la version MT et ST de l'instance x4\_1\_1\_4-8 est de 1,15. Le rapport performance/surface pour la version CMP de degré 4 nous donnes 0,98 alors que la version SMT de degré 4 nous donnes 1,27.
+
+Pour le partage du cache, nous pouvons tirer enseignement des 3 instances suivantes :
+\begin{itemize}
+\item x4-4\_1\_1-2 avec 4 Icaches et Dcaches L1 de 2k chacun et accessible par un seul thread . Le speed-up de 3,92.
+\item x4-2\_2\_1-2 avec 2 Icaches et Dcaches L1 de 4k chacun et accessible par deux    threads. Le speed-up de 3,63.
+\item x4-1\_4\_1-2 avec 1 Icache  et Dcache  L1 de 8k chacun et accessible par quatre  threads. Le speed-up de 3,27.
+\end{itemize}
+
+Le partage du cache induit des conflits d'accès au port : dans le premier cas, il y a 4 ports d'accès au Icache de largeur de deux instructions. Alors que dans le troisième cas, il n'y a qu'un port de largeur de 8 instructions. Les paquets de 8 instructions permettent de mieux exploiter l'ILP mais moins le TLP : chaque contexte doit attendre 4 cycles avant de prendre un nouveau paquet. De plus, le partage du cache entraîne un effet de bord : le pourrissement du contenus du caches par les autres threads, et un allongements du temps de réponses des miss dut au plus grand nombre de miss et à la plus grande longueur des lignes. Le cache, optimisé pour être tirer partie de la localité spatiale et temporelles des instructions et des données ce retrouve confrontés à plusieurs flots.
+
+Enfin pour le partage de la partie exécutive, nous pouvons observé les instances suivantes :
+\begin{itemize}
+\item x4-2\_2\_1-2 où il y a 4 groupes de 2 ALUs et chacune est accessible par 1 Threads. Le speed-up est de 3.63.
+\item x4-2\_2\_1-4 où il y a 2 groupes de 4 ALUs et chacune est accessible par 2 Threads. Le speed-up est de 3.41.
+\item x4-2\_2\_1-8 où il y a 1 groupe  de 8 ALUs et         est accessible par 4 Threads. Le speed-up est de 3.38.
+\end{itemize}
+
+Le partage des unités d'exécutions n'influe que légèrement sur les performances. Les ressources sont plus utilisés, mais implique un effet de bord : elle augmente la sensibilité du aux erreurs de routages (envoie vers une ALUs surchargés alors que d'autres ALUs sont en famine). Ceci est également du à notre politique actuel qui est un round robin classique.
+
+Notons que dans le cas où il y a plus d'un contexte par core (x4-1\_2\_2-8 et x4-1\_2\_2-4 qui ont eu deux un speed-up de 2.37 alors que les instances x4-2\_1\_2-8 et x4-2\_1\_2-4 on un speed-up respectif de 2.51 et 2.4) le partage des unités d'exécutions est favorable. Ceci peut être expliquer par une bonne exploitation du TLP : la fenêtre de lancement est mieux exploiter et le réseau de routage à plus d'instruction à sa disposition. 
+
+% Il y a aussi une hétérogénéité des instructions longues.
+
+Pour le partage opérative, voyons les instances suivantes :
+\begin{itemize}
+\item x4-1\_1\_4-8, 1 cluster  possédant chacun 1 UL  avec 4 contextes chacun. Le speed-up est de 1.46.
+\item x4-1\_2\_2-8, 1 cluster  possédant chacun 2 ULs avec 2 contextes chacun. Le speed-up est de 2.37.
+\item x4-1\_4\_1-8, 1 cluster  possédant chacun 4 ULs avec 1 contexte  chacun. Le speed-up est de 2.94.
+\item x4-2\_1\_2-8, 2 clusters possédant chacun 1 UL  avec 2 contextes chacun. Le speed-up est de 2.51.
+\item x4-2\_2\_1-8, 2 clusters possédant chacun 2 ULs avec 1 contexte  chacun. Le speed-up est de 3.38.
+\item x4-4\_1\_1-8, 4 clusters possédant chacun 1 UL  avec 1 contexte  chacun. Le speed-up est de 3.94.
+\end{itemize}
+
+Le partage de la partie opérative donne des résultats très disparates et demande une analyse plus poussés des résultats. Nous pouvons noté qu'il y a une augmentation de la sensibilité des instructions de synchronisation et des instructions d'accès au registres spéciaux (car nous imposons qu'avant d'exécuter une instruction d'accès au registres spéciaux que le pipeline soit vide.)
+
+Tous comme une augmentation des miss de spéculations dut au partage du prédicteur de branchement. Ceci implique qu'il y a une augmentation de nombres des instructions inutiles dans le pipeline (dans x4-1\_1\_4-8 représente 6,12\% des instructions, alors qu'il ne représente que 2,17\% dans l'instance x4-4\_1\_1-8). Ceci est aussi dut à la largeur du pipeline et donc à la sous exploitation de L'ILP. Lors du décodage, nous choisissons de manière round robin la fetch queue contenant un paquet. Dans l'instance x4-4\_1\_1-8, 4 décodeurs décode chacun en moyenne 1,63 instruction sur des paquets de 2 instruction alors que dans l'instance x4-1\_1\_4-8, 1 décodeur prend un paquet de 8 instructions et en décodent en moyenne 3,7. Ceci est dut qu'un paquet d'instruction est aligné et à la présence de branchements.
+
+
+
+
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/06_conclusion.tex
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--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/06_conclusion.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/06_conclusion.tex	(revision 3)
@@ -0,0 +1,5 @@
+\section{Conclusion}
+
+Cette étude à démontrer un fait déjà acquis, que le speedup entre la version MT et la version ST d'un processeur diminue avec l'augmentation du partage du ressource. 
+
+Notre modèle de processeur étant encore en cours de dévellopement, nous nous destinons à fournir un modèle VHDL synthétisable. Ainsi la prochaine étude porteras sur le coût surfacique du partage des ressources matériels et ainsi déterminer quel degré de partage apporte le meilleur ratio performance/surface.
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/root.tex
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--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/root.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-morpheo-share_architectural_ressources_between_hardware_context/fr/root.tex	(revision 3)
@@ -0,0 +1,7 @@
+\input{\dirroot/01_abstract}
+\input{\dirroot/02_introduction}
+\input{\dirroot/03_experimentation.tex}
+\input{\dirroot/04_methodologie.tex}
+\input{\dirroot/05_resultat.tex}
+\input{\dirroot/06_conclusion.tex}
+\bibliography{\dircommon/bibliographie}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-configuration_file_syntax/fr/root.tex
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--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-configuration_file_syntax/fr/root.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-configuration_file_syntax/fr/root.tex	(revision 3)
@@ -0,0 +1,45 @@
+\section{Introduction}
+
+\section{Comment lire ce document}
+\begin{itemize}
+\item les noms de balises sont en italique
+\item leur attribut sont en gras
+\end{itemize}
+
+\section{Fichiers de configurations}
+
+Pour une structure rigoureuse est une facilité aussi bien d'écriture que de lecture, le fichier de configurations suit une description au format XML.
+
+Le fichier de configuration doit donc avoir comme entête la balise {\bf xml} :
+\begin{verbatim}
+<?xml version="1.0" encoding="ISO-8859-1"?> 
+\end{verbatim}
+
+Nous imposons la présence de l'attribut {\it encoding} et de la valeur ISO-8859-1. Mais aucun test sur l'encodage des caractère sera effectué.
+
+La balise englobante est {\bf cpu}
+
+
+\section{Liste des balises}
+
+\subsection{cpu}
+
+\subsubsection{Description}
+
+\subsubsection{Attributs}
+~\newline
+\begin{tabular}{lll}
+{\it name       } & chaîne & \\
+\end{tabular}
+
+\subsubsection{Parents}
+~\newline
+Aucun
+
+\subsubsection{Fils}
+~\newline
+\begin{tabular}{ll}
+{\bf definition } & *\\
+{\bf type       } & *\\
+{\bf latence    } & *\\
+\end{tabular}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-methodology/fr/root.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-methodology/fr/root.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-methodology/fr/root.tex	(revision 3)
@@ -0,0 +1,25 @@
+\section{Méthodologie}
+Dans cette section, nous allons voir la méthodologie générale de dévelloppement du modèle Morpheo.
+
+Pour la conception du modèle de processeur nous avons suivit trois grandes étapes. Comme le processeur à pour vocation d'être un modèle de processeur généraliste, nous avons réalisé l'état de l'art sur les processeurs commerciaux superscalaire et/ou multi-core / multi-threaded. Pour cela, nous nous sommes principalement inspirés du Mips R10000, de l'intel Pentium 4, et de l'IBM Power 5.
+De cette étude préliminaire, nous avons réalisé un découpage grossier du processeur en 7 étages logiques. Les communications entres étages sont définit cette étape, mais la composition exact de ces interface ne sont pas déterminer aux signals près.
+
+La deuxième étape consiste à réaliser un découpage structurelle en macro bloc. C'est à dire que chaque étage logique est sous divisé en macro bloc réalisant une fonction. Un exemple significatif étant l'étage de renommage où nous pouvons identifier 4 macro blocs : la table de RAT (Register Address Translation), la Free-list (contenant les registres pouvant être utilisé dans le processus de renommage), un bloc combinatoire détectant les dépendances RAW (Read-after-Write) proche et enfin l'Issue Queue (file d'attente des instructions).
+
+Lors de cette deuxième étapes, nous avons dévellopés un modèle haut niveau (écrit pour le simulateur SystemC) CABA (Cycle accurate bit Accurate). Cependant certaines fonctionnalités reste encore non précis au cycle comme par exemple l'étape d'initialisation du processeur lors de l'activation de l'entrée de Reset.
+
+Les Macro-bloc offrent la possibilité d'être relativement simple à transformé en VHDL synthétisable. C'est l'objectif de la troisème phase. Chacun de ces Macro-blocs sont décomposés en micro-blocs. Les premiers étant précis à l'interface, l'interconnection des macro-blocs traduit en micro bloc ne poseras que peut de problème.
+Or nous pouvons remarquer que notre modèle haut niveau CABA s'éloigneras de la représentation en VHDL synthétisable. Dans un souçit de cohérence forte entre ces deux niveaux de représentation, nous avons décidé de décrire un modèle systemC au niveau micro bloc. Celui-ci deviendra notre modèle final.
+
+
+Qu'offre un modèle d'un micro bloc?
+
+Chaque modèle écrit en systemC (donc en C++) offre divers services : 
+\begin{itemize}
+\item Une classe pour paramétrer le micro-bloc et vérifier ainsi la cohérence des paramètre. La vérification de fait en 3 points : la vérification fonctionnel (interaction des paramètres entre eux. Par exemple toujours dans le Rat, il est inutiles de renommer plus d'instruction que de case dans l'Issue Queue ou que de Registre Physique supplémentaire). La seconde est une vérification de cohérence (entier soit positif, soit naturel. Voir même obligation d'être une puissance de 2 (comme par exemple toute les tailles de files.)
+\item Le modèle systemC/CABA du composant.
+\item Avec le modèle systemC, nous fournissons un petit jeux de test afin de vérifier le bon fonctionnement du modèle dans des conditions d'utilisations courantes.
+\item La possibilité de générer un modèle VHDL synthétisable à partir des paramètres du modèles.
+\item Lors de la simulation, nous pouvons générer un fichier de statistiques afin de vérifier l'influence des paramètres actuelles sur ce bloc.
+\item Et enfin, à l'instar d'un test du modèle systemC, nous pouvons générer un fichier de bench pour le modèle vhdl en sauvegardant les transactions au interface du modèle systemC en cours de simulations. Ceci nous permettra alors de garantir la stricte compatibilité entre le modèle systemC CABA et le modèle Vhdl Synthétisable.
+\end{itemize}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-new_component/fr/root.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-new_component/fr/root.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-new_component/fr/root.tex	(revision 3)
@@ -0,0 +1,92 @@
+Nous allons détailler les étapes qui doivent être suivit afin de créer un Component du nom de XXX localiser dans le répertoire YYY. Ce dernier étant un sous répertoire de Morpheo/Behavioural. A la fin de chaque étape, il est conseillé de faire des tests.
+
+Tous les tests sont contenus dans le répertoire ./SelfTest. Les fichiers contenus dans ./SelfTest/main sont des jeux de paramètres. Ils sont le points d'entrées de la fonction test contenus dans ./SelfTest/src/test.cpp
+
+\begin{enumerate}
+\item 
+{\bf Initialisation}
+\begin{enumerate}
+\item {\it Morpheo/Behavioural}, éxècutez la commande ./New\_component.sh YYY XXX, puis aller dans le répertoire YYY.
+\end{enumerate}
+\item 
+{\bf Paramètres}
+\begin{enumerate}
+\item {\it ./include/Parameters.h}, définition des constantes définissant les paramètres. (Ne pas oublier les paramètres du constructeur)
+\item {\it ./src/Parameters.cpp}, constructeur et constructeur par copie.
+\item {\it ./src/Parameters\_msg\_error.cpp}, énumérer les conditions d'erreurs.
+\end{enumerate}
+\item 
+{\bf Interfaces}
+\begin{enumerate}
+\item {\it ./include/XXX.h}, Ajout de l'interface.
+\item {\it ./include/Types.h}, Ajout des types composants l'interface.
+\item {\it ./src/Parameters\_msg\_error.cpp}, Ajouter si non effectuer dans l'étape précedente, les erreurs pouvant survenir pour une erreur d'encodage des types.
+\item {\it ./src/XXX\_allocation.cpp}, Allocation des ports d'interface (en fonction des paramètres).
+\item {\it ./src/XXX\_desallocation.cpp}, Désallocation des ports d'interface.
+\item {\it ./SelfTest/src/test.h}, Ajout des signaux interne et instanciation avec l'instance du modèle.
+\end{enumerate}
+\item 
+{\bf SystemC}
+\begin{enumerate}
+\item {\it ./SelfTest/src/test.h}, Ecriture du test en lui même pour les tests combinatoires, ne pas oublier de faire avancer le delta cycle en utilisant sc\_start(0). L'écriture des tests est plus difficle à faire avant l'écriture du code, mais cela ne supposeras alors aucun apriori et permet se baser uniquement sur l'interface vut dans l'étape précedente.
+\item {\it ./include/XXX.h}, Ajout des prototypes des fonctions de Mealy et de Moore. (Prenez comme exemple la fonction ``transition'')
+\item {\it ./include/XXX.cpp}, Ajout de la liste de sensibilité des fonctions de Mealy et de Moore. (Prenez comme exemple la fonction ``transition'')
+\item {\it ./include/transition.cpp}, Ajouter le corps de la fonction de transition. Créez un fichier par fonctions de Mealy et Moore contenus dans le modèle (Prenez comme exemple la fonction ``transition''). Note pour la compatibilité systemCass : un signal ne doit être affecté qu'un seul fois.
+\end{enumerate}
+\item 
+{\bf Statistics}
+\begin{enumerate}
+\item {\it ./include/Statistics.h}, Ajouter les variables qui vont servir de sondes, et pour la fonction ``add'' ajouter également autant de paramètres que de sondes. Si vous devez sonder un ensemble d'élément (port, file, banc de registres), et déterminer l'utilisation moyenne, nous vous proposer la classe Statistics contenus dans {\it Behavioural/Generic/Group/include/Statistics.h}
+\item {\it ./src/Statistics.cpp}, Remplir le corps du constructeur et du destructeur de la classe Statistics.
+\item {\it ./src/Statistics\_print.cpp}, Ajouter le corps de la fonction print contenus dans ce fichier. Son but étant d'imprimer au format XML.
+\item {\it ./src/Statistics\_add.cpp}, Implémentation de la fonction add de la classe Statistics. (Son but étant d'incrémenter les variables de la classe)
+\item {\it ./src/XXX\_transition.cpp}, Dernière étape pour l'ajout des statistics : à la fin de la fonction de transition, faire un appel à la méthode add de la classe statistics. Il peut être utile d'ajouter des variables local à la classe XXX dans ./include/XXX.h, mais n'oubliez pas de les protéger par un \#ifdef STATISTICS
+\end{enumerate}
+\item 
+{\bf Vhdl}
+\begin{enumerate}
+\item {\it ./src/XXX\_vhdl.cpp} Normalement vous n'avez pas à modifier ce fichier. Mais si bloc est structurelle et ne contient pas des sous bloc définit par d'autre composant, alors fonction vhdl de la classe XXX doit s'occuper d'appeler les bonnes fonctions pour les généreés. (prenez exemple sur {\it ./Behavioural/Predictor/Branch\_Target\_Buffer/Sort/src/Sort\_vhdl.cpp}
+\item {\it ./src/XXX\_vhdl\_declaration.cpp} Enumeration des types nécessaires pour le corps du code VHDL.
+\item {\it ./src/XXX\_vhdl\_port.cpp} Listes des ports du composants. Attention, les types des ports doivent être des types simples. (De préférence pas les types définitions dans le fichier {\it ./src/XXX\_vhdl\_type.cpp}).
+\item {\it ./src/XXX\_vhdl\_declaration.cpp} Définitions des signaux internes aux composants.
+\item {\it ./src/XXX\_vhdl\_body.cpp} Corps du composant... Amusez vous bien :)
+\end{enumerate}
+\item 
+{\bf Vhdl - TestBench}
+\begin{enumerate}
+\item {\it ./src/XXX.cpp} Dans le constructeur, on définit l'horloge interne du testBench. A la ligne {\bf \_vhdl\_testbench->set\_clock("in\_CLOCK",true);} le premier argument de {\it set\_clock} est le nom du port de l'horloge. Le deuxième argument est un booléen qui indique si le modèle à tester possède une horloge ou pas. Modifier cette ligne pour être en adéquation avec votre composant.
+\item {\it ./src/XXX\_vhdl\_testbench\_port.cpp} Enumaration des ports du modèle. Il s'agit en générale d'une bête recopie du fichier {\it ./src/XXX\_vhdl\_port.cpp} avec quelques petites retouches.
+\item {\it ./src/XXX\_vhdl\_testbench\_transition.cpp} Ajout dans le testbench des valeurs des entrées et des sorties du modèles. Les ports doivent être listé dans le même ordre que celui du fichier {\it ./src/XXX\_vhdl\_testbench\_port.cpp}.
+\end{enumerate}
+\end{enumerate}
+
+	
+%%+-------------------------------+---------------------------------------------------------------+
+%%|	List of flags		|	exemple ( component : RegisterFile )			|
+%%+-------------------------------+---------------------------------------------------------------+
+%%|				|								|
+%%|	@DIR_MORPHEO		|	../..							|
+%%|				|								|
+%%|	@COMPONENT		|	RegisterFile						|
+%%|				|								|
+%%|	Behavioural/@DIRECTORY		|	Behavioural/Generic/RegisterFile			|
+%%|				|								|
+%%|	behavioural_@DEFINE			|	behavioural_generic_registerfile			|
+%%|				|								|
+%%|	namespace behavioural {
+%%@NAMESPACE_BEGIN	|	namespace behavioural                {			|
+%%|				|	namespace generic                    {			|
+%%|				|	namespace registerfile               {			|
+%%|				|								|
+%%|	@NAMESPACE_END
+%%}; // end namespace behavioural		|	}; // end namespace registerfile 			|
+%%|				|	}; // end namespace generic				|
+%%|				|	}; // end namespace behavioural          		|
+%%|				|								|
+%%|	behavioural::@NAMESPACE_USE		|	behavioural::generic::registerfile			|
+%%|				|								|
+%%|	using namespace morpheo::behavioural;
+%%@NAMESPACE_USING	|	using namespace morpheo::behavioural;			|
+%%|				|	using namespace morpheo::behavioural::generic;		|
+%%|				|								|
+%%+-------------------------------+---------------------------------------------------------------+
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/common/biblio.bib
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/common/biblio.bib	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/common/biblio.bib	(revision 3)
@@ -0,0 +1,1922 @@
+@book{1983_Lee,
+  title={{Analysis of Branch Prediction Strategies and Branch Target Buffer Design}},
+  author={Lee, J.K.F. and Smith, A.J.},
+  year={1983},
+  publisher={Computer Science Division (EECS), University of California}
+}
+@article{1991_kaeli,
+  title={{Branch history table prediction of moving target branches due to subroutine returns}},
+  author={Kaeli, D.R. and Emma, P.G.},
+  journal={Proceedings of the 18th annual international symposium on Computer architecture},
+  pages={34--42},
+  year={1991},
+  publisher={ACM Press New York, NY, USA}
+}
+
+@InProceedings{  1991_wall,
+  author = 	 {David W. Wall},
+  title = 	 {Architectural Support for Programming Languages and Operating Systems},
+  OPTcrossref =  { ISBN:0-89791-380-9},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the fourth international conference on Architectural support for programming languages and operating systems},
+  OPTpages = 	 {176-188},
+  OPTyear = 	 {1991},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Santa Clara, California, United States},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = {ACM Press},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+01/12/2004
+
+Etude sur le niveau de parallélisme d'un programme => l'ILP ne dépasse pas 5-7 instructions
+Ceci déterminera la viabilité d'ajout de mécanismes pour traiter en parralléle un maximum d'instructions (superscalaire, renommage de registre etc..)
+               #instruction
+Parrallelism = -------------
+               #cycle requit
+
+Le parallélisme est en moyenne de 3-4 inst. Peut être plus haut (ex. Programme numérique). Le profit d'une crête de parrallélisme est bas si la moyenne est basse.
+
+Augmenter l'ILP : 2 variétés de techniques :
+ a) Parrallélisme dans un bloc de base
+ b) Parrallélisme entre plusieurs blocs de base
+
+a) limité par les dépendances entre paire d'instructions
+    -> Renommage de registres (Hardware ou Software). Les compilos préfére utilisé le moins de registres possibles.
+    -> Pur les dépendances d'adresse mémoire => analyse d'alias
+b) Nombre d'instructions entre 2 branchements est en moyenne moins de 6 instructions
+    -> Prédiction de branchement pour exécuter de manière spéculatives les blocs de bases
+    -> Déroullement de boucles => augmentation de la taille des blocs de base
+    -> Pipeline logiciel => augmente le parallélisme au sein d'un bloc
+    -> Ordonnanceur de trace => trace : séquence de blocs souvent éxecuté
+
+CADRE DE TRAVAIL:
+
+* Execution du programme pour produire une trace d'execution
+* Algorithme va "paquetiser" ses instructions en groupe d'instruction non suspendu => on tente d'avoir 64 inst en //
+* Pas de limites d'unité fonctionnelle ni de limite d'accès au banc de registres. Chaque instruction à une latence d'un cycle, de même pour les opérations mémoires
+* L'execution se faire par groupe de paquet, si la suspension à également lieu dans le modèle, alors le paquet suivant sera exécuter le cycle suivant. Sinon, nous pouvons l'exécuter le même cycle.
+
+Le parrallélisme sera donc le nombre d'instruction par le nombre de cycles
+
+Paramètres :
+Register renamings : Parfait(nombre infinie de registres)
+                     finit (allocation dynamique => LRU, 256 registres entier, 256 flottant)
+                     aucun
+Prédiction de branchement : Prédiction parfaite (tjs correctement prédit)
+                            finit (dynamique) (prédiction d'un schéma à 2 bits , avec une table à 2048 entrées)
+                            finit (statique)  (tjs la même prédiction (dépendant de la prédiction parfaite))      
+                            aucun -> prédiciton tjs faux
+Idem pour le jump prediction
+analyse d'alias : Parfait (Il y a un conflit d'adresse que si l'adresse d'une écriture est la même qu'une autre écriture ou lecture)
+                  Aucune analyse (Une écritures sont en conflits avec chaque autre écriture et lecture)
+                  inspection d'instruction => pas de conflits si même registre de base mais dpt différent
+                                                              si registre de base différent (Mais explecitement différent ex utilisation de sp et gp qui sont deux pointeurs différents)
+                  analyse par le compilateur => analyse parfaite de la pile et des références globales
+Taille de la fenêtre : Nombre maximum d'instructions pouvant apparaître dans un cycle de traitement
+                     => Gestion de la fenêtre de manière discrète (Chercher une fênetre entière)
+                                                         continue (Chercher autant d'instruction qui viennent de ce terminer)
+
+Définitions de 5 modèles :
+
+          +----------------+--------------+--------------+----------------+
+          | branch Perfect | Jump predict | Reg renaming | Alias analysis |
++---------+----------------+--------------+--------------+----------------+
+| Stupid  | none           | none         | none         | none           |
+| Fair    | infinite       | infinite     | 256          | inspection     |
+| Good    | infinite       | infinite     | 256          | perfect        |
+| Great   | infinite       | infinite     | perfect      | perfect        |
+| Perfect | perfect        | perfect      | perfect      | perfect        |
++---------+----------------+--------------+--------------+----------------+
+
+Pour une taille de fenêtre de 2048 instructions ( continue)
+
+Sur les jeux de tests, on notera que le parrallélisme du modèle :
+ - stupide ne dépasse pas 2 
+ - pauvre  ne dépasse pas 4
+ - Great   ne dépasse pas 8 sauf pour quelque modèle numérique qui exploite l'analyse des alias 
+ - Parfait 
+
+Le déroullage de boucles à un effet significatif pour les modèles ambitieux. Sinon, ceci est limite par les load de début de boucle et les stores de fin de boucles (càd réduite par les technique d'alias analysis)
+
+Taille de la fenêtre
+
+La modification de la taille de la fenêtre n'influe que sur les modèles ambitieux grâce à leur technique de prediction améliorer. La plupart des benchmarks ont besoin que d'une fenêtre de 32 inst
+Avec une gestion de fenêtre demanière discrete, cela exploite moins de parrallélisme (- d'inst prete)
+
+Effet des predictions de branchements :
+
+Réduire le niveau de la prédiction de branchment à un impact significatif sur le parrallélisme (Beaucoup moins d'instructions prête à être executer). Mais réduire le niveau de la prédiction de saut n'a d'effet que si la prédiction de branchement est parfaite.
+De plus sur le modèle parfait, l'augmentation de la latence d'un miss à un effet significatif sur le parrallélisme (Car les instructions feteched ne sont plus executé en parralléle car les instructions précédentes sont déjà terminées)
+
+Effet du rennommage de registres et de l'analyse des alias
+
+L'analyse d'alias par inspection n'est pas très performantes (augmente l'ILP de 0.5). L'analyse par compilation n'est performante que pour des programmes utilisant la pile .
+Le nombre de registre pour le renomage de registres n'influe que très peu sur le parallélisme dans un modèle où les prédictions ne sont pas parfaite (à l'exception faite des programmes ayant beaucoup de dépendance)
+
+CONCLUSION
+
+Une bonne prédiction (hard ou soft) est un facteur déterminant pour l'augmentation de l'ILP. Le renommage de registres est important si le compilateur l'exploite.
+Le parrallelism moyen tourne autour de 5 d'après cette étude. (Dans un contexte très favorable => latence des inst = 1, etc...)
+@article{1992_pan,
+  title={{Improving the accuracy of dynamic branch prediction using branch correlation}},
+  author={Pan, S.T. and So, K. and Rahmeh, J.T.},
+  journal={Proceedings of the fifth international conference on Architectural support for programming languages and operating systems},
+  pages={76--84},
+  year={1992},
+  publisher={ACM Press New York, NY, USA}
+}
+@article{1992_yeh,
+  title={{Alternative Implementations of Two-Level Adaptive Branch Prediction}},
+  author={Yeh, T.Y. and Patt, YN},
+  journal={Computer Architecture, 1992. Proceedings., The 19th Annual International Symposium on},
+  pages={124--134},
+  year={1992}
+}
+@techreport{1993_mcfarling,
+  title={{Combining Branch Predictors}},
+  author={McFarling, S.},
+  institution={Technical Report WRL Technical Note TN-36, Digital Equipment Corporation, June 1993}
+}
+@article{1993_yeh,
+  title={{A comparison of dynamic branch predictors that use two levels of branch history}},
+  author={Yeh, T.Y. and Patt, Y.N.},
+  journal={Proceedings of the 20th annual international symposium on Computer architecture},
+  pages={257--266},
+  year={1993},
+  publisher={ACM Press New York, NY, USA}
+}
+@InProceedings{1995_sohi,
+  author = 	 {Sohi, G.S.     and
+                  Breach, S.E.   and
+                  Vijaykumar, T.N. },
+  title = 	 {Multiscalar processors},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Computer Architecture, 1995. Proceedings. 22nd Annual International Symposium on},
+  OPTpages = 	 {414-425},
+  OPTyear = 	 {1995},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Santa Margherita Ligure  ,   Italy},
+  OPTmonth = 	 {22-24 Jun},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+22/02/2005
+
+Paradigme de base : fetch-execute - pointé par un program counter
+                    -> sous entend que les instructions vont être executer dans le même ordre que le programme.
+
+processeur ILP et les compilos désordonne le programme en respectant toutefois les dépendances sur les données et les controles.
+Les dépendances de contrôles peuvent être représenté par un "control flow graph" -> bloc de bases sont représenté par des noeuds et les arcs représentent les flots de contrôles
+
+Overview
+--------
+Objectif : A partir du "control flow graph" (CFG), on peut établir une fenêtre dynamique d'instruction pouvant être extré et lancé.
+
+le CFG peut être vut : - instruction / instruction
+                       - bloc / bloc
+                       - tâche / tâche (thread)
+
+Assignation d'une tâche à une unité d'execution.
+Le multiscalar à une collection d'unité d'execution et un séquenceur s'occupant de distribuer les tâches au UE.
+
+=> Obligation de maintenir l'ordre séquentielle de consommation et de production de données (registre ou accès mémoire)
+ Synchronisation  des accès mémoires 
+ - approche conservatrice : Attendre que les accès mémoires des tâches moins spéculatives soit terminer
+ - approche aggréssive    : Réaliser des chargements spéculatifs (vérif dynamique si une tâche moins spéculatifs écrit dans un zone chargé spéculativement.)
+
+Le contrôle et les accès aux données peuvent être spéculative. -> Mécanisme de "Retour en arrière" et de commit
+Gestion circulaire des tâches : La tâche en tête n'est jamais spéculative. On retire les tâches de manière circulaire.
+
+Software
+~~~~~~~~
+ - Le séquenceur a besoin des informations sur le CFG.
+ - Il faut caractériser une tâche par les données consommés et les données produites.
+   |-> Analyse statique par la compilation et création d'un "create mask" indiquant quel registres sont produits par la tâche.
+   |-> Noté quel est la dernière instructions produisant le registre pour pouvoir ensuite le forwarder.
+
+Hardware
+~~~~~~~~
+Hardware -> lancement des tâches vers une unités d'execution
+         -> Maintient d'une execution séquentielle apparente
+
+Le séquenceur détermine l'ordre des tâches. (Charge le descripteur de tâche et à partir de la va charger la tâche, creer les différent masqie et déterminer (ou prédit) la prochaine tâche à executer)
+
+Les accès à la mémoire donnée sont réalisées par le Address résolution buffer (ARB) qui gére la spéculation, dépendance ...
+
+Distribution des cycles pour l'execution
+----------------------------------------
+Relacement d'un calcul si :
+ - utilisation d'une valeur incorrect
+ - prediction incorrect
+
+Pour cela :
+ a) Synchronisation des communications de données
+
+ b) Détermination de la prediction :
+  - Registre pas de problèmes
+  - Accès mémoires : synchronisé explicitement
+Pour les prédictions -> Valider la prédiction au plus tôt : 
+  * intruction explicite de validation de prediction
+  * changer la structure de la bcl afin de tester la condition au + tôt
+
+
+Cycle idle          : aucune unité de calculs n'a de tâches à executer
+Cycle de non calcul : les unités ont des tâches mais ne peux pas les executer
+ - Dépendances intra-tâche : dépendance entre instructions d'une même tâche (désordonnancement, cache non bloquant etc ...)
+ - Dépendances inter-tâche : dépendance entre tâches (calculs de la condition de la boucle à la fin du corps de bcl etc ...)
+
+Conclusion
+----------
+Exploite l'ILP. Pour cela utilisation d'une combinaison hardware/software afin d'extraire l'ILP
+ -> division le CFG en tâche 
+ -> traverser le CFG de manière spéculative
+ -> Les tâches sont distribués à une collection d'unité d'execution.
+ -> Chaque unité d'execution fetche et execute les instructions de la tâche associées
+ -> Processeurs utilise plusieurs PCs  afin de pouvoir séquencer plusieurs parties différente du CFG.
+@InProceedings{1995_tullsen,
+  author = 	 {Tullsen, D.M.  and
+                  Eggers, S.J.   and
+                  Levy, H.M.  },
+  title = 	 {Simultaneous multithreading: Maximizing on-chip parallelism},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Computer Architecture, 1995. Proceedings. 22nd Annual International Symposium on},
+  OPTpages = 	 {392-403},
+  OPTyear = 	 {1995},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Santa Margherita Ligure  ,   Italy},
+  OPTmonth = 	 {22-24 jun},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+15/02/2005
+
+Présentation du multi-threading.
+-> lancement de plusieurs flots de plusieurs threads dans les unités fonctionnelles du processeurs.
+-> but : augmenter l'utilisation du processeur face au long latence de la mémoire et de ILP limité dans un seul thread
+
+plan :
+ - modèle de SMT
+ - evaluation des perfs (par rapport à un superscalaire et un fine grain multi threading)
+ - hierarchie mémoire dans un SMT
+ - SMT vs CMP
+
+Modification d'un alpha 21164 :
+
+- 10 unités d'execution (4 integer, 2 flottant, 3 load/store et 1 branchement) => complétement pipeliné
+- Issue : 8 inst/cy
+- execution dynamique
+  |-> gestion des dépendance in-order
+  |-> lancement out-order
+- Prediction de bcht
+
+Limitations du super-scalaire
+-----------------------------
+en moyenne, le processeur lance 1.5 inst/cy sur une machine pouvant en lancer 8.
+différente cause :
+ - conflits mémoire, dépendance de donnée (flottant, ou entiere), délai de chargement, bulle de contrôle, mauvaise prédiction, miss de cache et de TLB.
+
+Toutes les cas peuvent être classé suivant deux types d'incidences sur le pipeline
+ - gaspillage verticale   : à un cycle donnée, aucune unité d'exécution ne sera utilisé
+ - gaspillage horizontale : à un cycle donnée, non utilisation d'un créneau de lancement (issue slot)
+
+un corse grain / Fine grain multithreading limite le gaspillage verticale.
+
+Modèles de processeurs
+----------------------
+Chaque modèles à 10 unités fonctionnelles et peut lancer 8 inst/cycles (Donc au max 8 threads)
+
+- Fine-grain multithreading : 1 thread peut lancer des instructions pendant 1 cycle (cycle suivant commutation)
+- SMT : full issue : les 8 threads sont en compétitions sur chaque issue slots à chaque cycle
+- SMT : N issue : chaque threads peut lancer un maximum de N inst/cycle (full issue = 8)
+- SMT : Connection limité : Chaque thread hardware est directement connecter à une unité fonctionnelle de chaque type (si il y a 8 threads et 4 unités fonctionnelles d'un type, alors chaque unité fonctionnelle est connecté à 2 threads)
+
+3 facteurs :
+ 1- # de threads en compétition
+ 2- # d'instructions lancé/thread
+ 3- # d'UF visible/thread
+
+augmente   Port registre | dépendance interinst | logique forward | ordonnancement inst
+1                                                 + complexe        + complexe          -> les ufs ont plus destination possible pour les résultats
+                                                                                        -> plus d'instructions devant être routé
+2          + complexe      + complexe                                                   -> plus d'instruction à lancer (donc chercher les opérandes)
+                                                                                        -> plus d'instruction à analyser (augmentation de la fenêtre de chaque thread)
+3          + complexe      + complexe             + complexe        + complexe          -> l'ordonnancement devient de + en + dépendant d'autre FU
+                                                                                        -> une UF qui est privé à moins de destination possible
+
+Caches
+------
+Le partage des caches et des TLB est néfastes sur les performances.
+Lors du partage des caches entre threads :
+ - Il y a virtuellement moins d'espace par threads
+ - Il faut des caches non bloquants
+
+-> Cache privé afin d'avoir des caches dédié à un thread (le cache est partionné en NB\_THREAD parties) Bon pour les Icaches (Pas d'évincement d'une ligne d'instruction par un autre thread)
+-> Cache partagé : Tous les threads ont accès au même cache => peu de contrôle, bon pour les Dcaches car 1 seules mécanisme de cohérence mémoires à implémenter.
+
+SMT vs CMP
+----------
+Ressemblance :
+Duplication des registres, multiple unité fonctionnelle, grand nombre d'instruction lancé par cycle
+Différence :
+les ressources ne sont pas partitionné et ordonnancé. Ils ont alloué de manière statique à un thread (ou un groupe de threads)
+
+Le SMT surpasse le CMP à complexité égal :
+ -> Un SMT 8 threads - 8 issues avec 10 FU surpasse de 24\% 8 proc 1 issue avec 4 UFs
+
+ * performance avec peu de thread (car partage des ufs)
+ * granularité et flexibilité
+
+@InBook{         1996_mudge,
+  ALTauthor = 	 {trevor mudge},
+  ALTeditor = 	 {},
+  title = 	 {ACM Computing Surveys (CSUR)},
+  chapter = 	 { Special ACM 50th-anniversary issue: strategic directions in computing research},
+  publisher = 	 {ACM Press   New York, NY, USA },
+  year = 	 {1996},
+  OPTkey = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTtype = 	 {},
+  OPTaddress = 	 {},
+  OPTedition = 	 {},
+  OPTmonth = 	 {december},
+  OPTpages = 	 {671 - 678},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+01/12/2004
+
+Architecture des ordinateurs est un degré significatif sur les activités de l'ingénieurs pour trouver une solution à un problem avec une contrainte de coûts.
+
+Tendance -> a) resulte d'un apport de la technologie (ex. techno micronique et submicronique)
+         -> b) resulte d'un contexte d'application (ex. Multi processings => ajout de mécanisme de tâches)
+a) Défi : Consommation (Au premier ordre conso est proportionnel à la fréquence, loi de moore : Double la fréquence tous les Deux ans donc double la conso)
+          Latence : La fréquence d'horloge croit plus vite que la technologie des Rams : f(CPU) +50\%/an , vitesse(DRAM) +10\%/an
+b) application guide les architectures : Les processeurs deviennent de + en + grand public  (jeux 3D, multimédia etc..). Avant ils étaient surtout utilisé par des militaires. 
+
+L'auteur voit 3 challenges pour la prochaine décade (càd jusqu'en 2006)
+-> Puissance et taille
+-> Performance
+-> Complexité
+
+Axes de recherches
+-> locality
+-> Paralélisme
+-> Prédictabilité
+
+Paralélisme au niveau instructions (ILP) -> Approche VLIW et superscalaire
+            au niveau application  -> Simultaneous multithreadings (SMT)
+
+l'idée de ce SMT viens du processeur HEP devellopper par denelcor vers la fin des années 70
+
+Hierarchie mémoire => nécessité de masquer la latence des accès mémoires (technique de prefetching => utilisation de la bande passante innoccupé en vue d'aller chercher des instructions potentiellement utiles)
+
+Evolution des benchmarks pour prendre en compte des évolutions de marché pour le processeurs (c'est à dire bench "multimédia")
+@InProceedings{,
+  author = 	 { Kunle Olukotun  and
+                   Basem A. Nayfeh and
+                   Lance Hammond   and
+                   Ken Wilson      and
+                   Kunyung Chang 	
+                 },
+  title = 	 {the case for a single-chip multiprocessor},
+  OPTcrossref =  {ISBN:0-89791-767-7},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the seventh international conference on Architectural support for programming languages and operating systems},
+  OPTpages = 	 {2-11},
+  OPTyear = 	 {1996},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Cambridge, Massachusetts, United States},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = {ACM Press},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+24/01/2005
+
+Opposition entre un mono-processeur compléxe et des multi-processeurs simple.
+
+Comparaison entre un processeur super scalaire 6 voies à ordonnancement dynamique et 4 processeurs superscalaire 2 voies. 
+Un superscalaire est décomposé en 3 phases :
+
+                     |----| <-> E
+           |----| -> |    | <-> E
+ICache <-> | IF | -> | IR | <-> E
+           |----| -> |    | <-> E
+                     |----| <-> E
+
+- Instructions fetch => fournir le maximum d'instruction prête.
+  Limitation : 
+   * Branchement mal prédit (degré de spéculation)
+   * Instruction mal aligné
+   * Miss de caches
+- Issue and retirement 
+  Rennommage : 
+   * Table de mappage (nb_opérande * nb_voie_scalaire   ports de lecture)
+   * Reorder buffer   (nb_bit_codage_registre * Taille_file_instruction_issue * nb_opérande * nb_voie_scalaire
+- Execution
+  Augmentation du temps de cycle lors de l'écriture si beaucoup de voie scalaire
+  Compléxité du by-pass (augmentation quadratique en fonction du nombre d'unité d'execution)
+
+Single-Chip Multiprocessor
+--------------------------
+1) -> Les OS actuelles sont multi processus => fort parrallélisme
+2) -> Les processus sont également multi thread
+3) -> Les appli mono thread peuvent être découper en thread de manière hard. assez contraignant.
+
+Architecture pour comparaison
+-----------------------------
+
+* Super Scalaire => R10000 de degré 4 à 6. (Augmentation des caractéristiques pour arriver à 430 mm2)
+* Multi proc     => 4 * R10000 de degré 2  (Diminution   des caractéristiques pour arriver à 430 mm2)
+
+=> Même surface de silicium pour les deux architectures.
+
+Performance
+-----------
+Gel d'un proceeseur dut au miss de cache. 
+Superscalaire -> execution désordonné, spéculative, cache non bloquant. Masquage des couts de Miss.
+
+Mesure de performance : Gain par rapport à la version MP - 1 proc.
+- Sur les applications avec peu de parallélismes, le superscalaire est plus performant car exploite mieux l'ILP.
+- Sur les applications avec un grain fin de parallélisme et beaucoup de communication, l'approche SS et MP est équivalente (Les deux approches exploite le parrallélisme grain fin)
+- Sur les applications avec un large degré de parallélisme, le multi proc prend l'avantage. Car le parrallélisme dépasse la fenêtre du supersclaire.
+
+
+=> l'approche SS est limité par l'ILP du programme, et le matériel nécessaire (lancement dynamique et banc de registres) augmente de manière quadratique le matériel et donc le temps de cycle.
+
+@InProceedings{ 1996_tullsen,
+  author = 	 {Dean M. Tullsen   and
+                  Susan J. Eggers   and
+                  Joel S. Emer      and
+                  Henry M. Levy     and
+                  Jack L. Lo        and
+                  Rebecca L. Stamm},
+  title = 	 {Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the 23rd annual international symposium on Computer architecture},
+  OPTpages = 	 {191-202},
+  OPTyear = 	 {1996},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 { Philadelphia, Pennsylvania, United States},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = {ACM Press},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+16/03/2005
+
+Préentation d'un architecture SMT suivant 3 contraintes :
+ - Minimiser l'impact par rapport à une architecture Superscalaire
+ - Minimiser la perte de performance lors de l'execution de programme monothread
+ - Avoir un gain de performance lors de l'execution de programme multithread
+
+Architecture SMT
+----------------
+L'article dérive un Supersclaire classique 
+(Fetch unit, Decode, Register renaming, wait\_queue, lecture des registres, unités d'executions, commit).
+Les instructions sont lancées dans le désordre, retiré dans l'ordre
+
+Changement minimum à apporter :
+ - un pc/thread et un thread séquenceur
+ - une pile de retour séparé (pour la prédiction de retours)
+ - Par thread : mécanisme pour retirer les instructions, file d'instructions à retirer et mécanisme de trape
+ - un thread id pour le BTB
+ - un large banc de registres
+
+Note : les instructions présente dans la file d'executions sont partagé par plusieurs threads donc grâce au mécanisme de renommage, on ne sélectionne que les instructions indépendante
+
+Conséquence :
+
+* Un pc est prioritaire (choisit de manière round robin)
+* Taille du banc de registres conséquents impose l'augmentation de la profondeur du pipeline.
+
+Performance
+~~~~~~~~~~~
+L'architecture gère 8 threads.
+
+Remarque : Si un seul thread est utilisé, il y a une perte de 2\% sur l'IPC par rapport au superscalaire de référence dut à l'augmentation du pipeline.
+
+Goulot d'étranglement :
+- Taille des files d'instructions : à cause de l'augmentation de l'IPC, elle deviennent souvent pleines
+- l'étage ifetch n'a pas la connaissance que les files sont pleines donc continue à fétché des instructions.
+- manque de parrallélisme : à cause des fausses instructions.
+
+Fetch Unit
+----------
+Il y à un partage de la bande passante de fetch avec tous les threads.
+ -> le fetch unit peut choisir parmit plusieurs source, donc incrémenter l'utilisation de la bande passante (car si un thread est bloqué, les autres ne le sont pas forcément)
+ -> le fetch unit peut choisir pour quels threads travailler (si un thread n'est pas bloqué mais qu'il réalise beaucoup de miss de spéculation, alors il est peut profitable de lui chargé des instructions qui auront de fortes chances d'être fausse)
+
+Définition de plusieurs stratégie de fetchs, classement suivant 3 critères :
+
+ 1) Partionnement du l'unité d'ifetch parmis les threads
+ 2) Efficacité de l'unité de fetch (Qualité des instructions chargés)
+ 3) Disponiblitité de l'unité de fetch (Elimination des conditions de blockage de l'unité)
+
+1) Partitionnement
+~~~~~~~~~~~~~~~~~~
+L'unité fetch charge jusqu'a 8 instructions par cycle.
+Mais comme les blocs de bases sont plutôt petit, il est difficille d'exploiter complétement la bande passante utilement pour un thread.
+ -> Partage des 8 instructions parmit plusieurs threads. Le cache reste identique mais est découpé en plusieurs banc, deux threads peuvent intérrogé deux bancs différents
+
+1.8 (1 threads ayant 8 instructions) -> blocs trop petits 
+2.4 - 4.2                            -> idéal
+8.1                                  -> Il n'y a pas assez de threads non bloqué
+
+Ajout de matériel : Mutipléxeur d'adresse, plusieurs buses d'adresse; logique de sélection des tristates de sorties, logique de conflit de bancs, duplication de la logique de calcul des hit/miss
+=> Augmente la latence du cache mais réduit la latence du bloc decode et rename (car moins de dépendance à calculer)
+
+autre vision : 
+2.8 -> le premier thread est prioritaire et peut charger jusqu'a 8 instructions, s'il n'y arrive pas un autre thread oeut tenter de combler le manque.
+c'est la méthode la plus performante car elle permet de gère la bande passante parmit plusieurs threads et d'avoir un partitionnement flexible.
+
+2) Algorithme
+~~~~~~~~~~~~~
+Algorithme de décision sur le thread prioritaire : Déterminer le meilleur "thread"
+ a) probabilité de ne pas charger un faux chemin
+ b) temps prit par l'instructions pour être executable
+
+* Round-robin
+* BRCOUNT     -> Favorise le thread qui à le moins de branchement non résolue (améliore a)
+* MISSCOUNT   -> Favorise le thread qui à le moins de miss de donnée (améliore b)
+* ICOUNT      -> Favorise le thread qui à le moins d'instructions dans les étages D R IQ (IQ = Instruction queue) (améliore b)
+* IQPOSN      -> Donne la plus basse priorité au thread la plus proche de la tête des files d'attente (améliore b) (la plus vieille instruction) (Ne requiert pas de compteur)
+
+ICOUNT et IQPOSN sont les deux algos les plus performants.
+
+3) Disponibilité
+~~~~~~~~~~~~~~~~
+Condition de blocage du fetch unit : IQ full, Icache miss.
+
+* BIGQ -> Augmentation de la taille du IQ sans augmenter la taille de la zone de recherche
+* ITAG -> Scrute le cache un cycle plutôt est on sélectionne que les threads qui ne vont pas faire de miss
+
+Choix de l'instruction à lancé
+------------------------------
+
+Superscalaire : le degré de spéculation est croissant avec sa position dans l'IQ
+Dans un SMT, ceci n'est pas vrai. 
+
+* OLDEST
+* OPT\_LAST     -> Optimiste
+* SPEC\_LAST    -> Spéculatif en dernier (les instructions sont spéculatifs sont prioritaires)
+* BRANCH\_FIRST -> Branchement sont prioritaires (afin de connaître si un branchement est spéculatif)
+ 
+Les performances n'influe pas énormément -> la bande passante du lancement n'influe pas sur les performances.
+
+Goulot d'étranglement
+---------------------
+Bande passante du lancement      -> non
+Taille de la file d'instructions -> non
+Bande passante du fetch          -> oui : la fréquence des sauts et les problèmes d'alignements du pc ne permet pas d'utiliser entièrement la bande passante.
+Prédiction de branchement        -> non : Le SMT est plus tolérant au mauvaise prédiction qu'un superscalaire classique. plus il y a de threads, plus ils seront entrelacés donc moins d'instructions seront chargé après un branchement.
+Execution spéculative            -> non, mais un SMT bénéficie beaucoup moins de l'apport de l'execution spéculative.
+Sortance de la mémoire           -> non
+Taille du banc de registres      -> oui : Temps d'accès devient limitant
+
+
+
+
+
+@InProceedings{1996_wallace,
+  author = 	 {Wallace, S.     and
+                  Bagherzadeh, N.    },
+  title = 	 {A scalable register file architecture for dynamically scheduled processors},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Parallel Architectures and Compilation Techniques, 1996., Proceedings of the 1996 Conference on},
+  OPTpages = 	 {179-184},
+  OPTyear = 	 {1996},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Boston, MA, USA},
+  OPTmonth = 	 {Oct},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+01/04/2005
+
+Abstract
+--------
+
+A major obstacle in designing dynamically scheduled processors is the size and port requirement of the register file. By using a multiple banked register file and performing dynamic result renaming, a scalable register file architecture can be implemented without performance degradation. In addition, a new hybrid register renaming technique to efficiently map the logical to physical registers and reduce the branch misprediction penalty is introduced. The performance was simulated using the SPEC95 benchmark suite
+
+@article{burger1997sts,
+  title={{The SimpleScalar tool set, version 2.0}},
+  author={Burger, D. and Austin, T.M.},
+  journal={ACM SIGARCH Computer Architecture News},
+  volume={25},
+  number={3},
+  pages={13--25},
+  year={1997},
+  publisher={ACM Press New York, NY, USA}
+}
+@InProceedings{1997_palacharla,
+  author = 	 {Palacharla, S.  and
+                  Jouppi, N.P.    and
+                  Smith, J.E.   },
+  title = 	 {Complexity-Effective Superscalar Processors},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Computer Architecture, 1997. Conference Proceedings. The 24th Annual International Symposium on},
+  OPTpages = 	 {206 - 218},
+  OPTyear = 	 {1997},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {},
+  OPTmonth = 	 {Jun},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+07/02/2005
+
+=> Perte de performances du au matériel très couteux.
+
+2 directives pour fabriquer un mono processeurs :
+ - Le compléxifier le matériel afin d'extraire encore plus le nombre d'instructions lancée
+ - Le rendre plus simple afin d'avoir une plus grande fréquence d'horloge
+
+Source de compléxité
+--------------------
+
+Modèle de pipeline typique :
+
+1) FETCH             Lecture de plusieurs instructions, prediction de branchement
+2) DECODE            Décodage d'instruction
+3) RENAME            renommage de registre, dispatchement dans la fenêtre d'isntructions
+4) SELECT/ISSUE      Une fois qu'une instruction à ces opérandes => prête à être lancé -> Envoie vers l'UF approprié
+5) REG READ          Prise des opérandes / bypass
+6) EXECUTE/BY PASS   Execution
+7) DCACHE ACCESS     Accès mémoire
+8) REG WRITE/COMMIT  Accès dans les registres et valdiation (instruction non spéculatif et non érroné)
+
+Dépendance de complexité :
+- Largeur/profondeur de la fenêtre de lancement
+- Structure "Dispatch et issue"
+- Longeur des fils dans ces structures qui se mettent à jour par broadcasting
+
+-> Logique de renommage
+-> Logique de wake up (détermine quel instructions est prête ou non)
+-> Logique de selection
+-> Logique des by-pass
+
+Détails
+-------
+
+Logique de renommage
+~~~~~~~~~~~~~~~~~~~~
+Accès à une table de mappage pour diriger le numéro de registres logique vers le numéro de registres physique
+Accès multiple (plusieurs instructions)
+-> Logique de vérification de dépendances
+
+2 schémas : - schéma RAM : Une table de NB\_REG\_LOG pointant sur les registres physiques
+            - schéma CAM : Une table de NB\_REG\_PHY pointant vers les registres logiques
+Trename   = Tdecode + Twordline + Tbitline + Tsenseamp
+          = cst0 + cst1*IW + cst2*IW²
+
+Twordline (proportionnel à la taille de l'adresse du registre physique (environ 8) )
+Tbitline  (proportionnel au # de registre logique (souvent 32) )
+Tsenseamp fonction de bitline delay
+cst sont donnée par la technologie
+
+=> croit linéairement avec la taille de la fenêtre
+
+Logique de wakeup
+~~~~~~~~~~~~~~~~~
+A chaque résultat produit, a tag associé au résultat est diffusé à toutes les instructions contenus dans la fenête de lancement (IW).
+Chaque instructions compare le tag avec ses opérandes sources
+Si la comparaison est positive => mise à jour du bit ready de(s) l'opérande(s) (Quand tous les bit sont positionnés => instructions prête au lancement)
+
+Il y a IW tag soit NB\_OPERANDE x IW comparaions
+
+Twakeup = Ttagdrive + Ttagmatch + Tmatch\_or
+        = c0 + (c1 + c2 * IW)*WINSIZE + (c3 + c4*IW + c5*IW²)*WINSIZE²        
+
+(IW => nombre d'instruction en attente d'être executer)
+(WINSIZE => nombre d'instruction allant être executé)
+
+Incrémenter le nombre de ligne va incrémenter le nombre de comparaisone et la puissance nécessaire pour atteindre ces comparaisons.
+Seul le Ttagdrive dépend de la taille de fenêtre de lancement (fan-out + élevé car + de comparateur)
+
+Logique de selection
+~~~~~~~~~~~~~~~~~~~~
+Choix des instructions à executer parmit la IW
+ -> Plusieurs types d'instructions
+ -> Plusieurs types d'unités fonctionnelles pouvant acceptés une instructions de plusieurs types d'instructions.
+
+Un signal REQ par instruction contenant dans la IW (actif si instruction prête)
+Un signal GRANT est émit par le bloc de sélection (1 par signal de requête) => indique que l'instructions est lancé dans une unité fonctionnelle.
+Politique de selection -> en général FIFO, ou la plus vieille (C'est à dire la plus en bas de la fenêtre d'instruction)
+
+=> Arbre d'arbitrage.
+ 2 phases : 1) Propagation de la requête jusqu'à la l'unité fonctionnelle
+            2) Propagation de la réponse (GRANT) jusqu'a toute les req d'instructions
+
+Tselection = c0 + c1 * log4(WINSIZE)
+
+log4 car les noeuds de l'arbre d'arbitre accepte 4 requêtes.
+
+Logique des bypass
+~~~~~~~~~~~~~~~~~~
+Si complétement bypassé, il faut : 2*IW²*S (S est le nombre d'étage)
+-> Un fils par unité fonctionnelle
+-> Tous les unité fonctionnelle (ainsi que le banc de registres) doivent avoir un bloc mux
+-> banc de registres à autant 2*UF ports de lecture et UF ports d'écriture
+-> Bloc mux à UF ports d'entrée et en sorties ce sont des bus attaqués pas UF signaux.
+-> Sans oublier les compateurs dans chaque alu
+
+Tbypass = 0.5*R*C*L²   => Dépend principalement de la longueur des fils.
+
+Analyse des résultats
+---------------------
+
+IW  Window-size Trename Tselection Tbypass
+
+(0.18)
+4   32          351.0   578.0      184.9
+8   64          427.9   724.0      1056.4
+
+-> La selection (logique de fenêtrage) et les bypass posent des problèmes de scalabilités.
+=> Toutes les autres structures ne posent pas de pbl d'horloge, où s'il y en a, alors ils peuvent être pipeliné.
+
+Si on découpe l'étage Wakeup (Chercher les opérances) et selection (Chercher une ALU disponible), alors il y aura au meilleur des cas au moins un cycle de gels entre deux instructions dépendante consécutive.
+
+... | WUP | SEL | EXE | ...                add r3,r2,r1
+                   | (Bypass)
+......... | WUP | WUP | SEL | EXE | ...    add r5,r4,r3
+
+Proposition d'architecture
+--------------------------
+Remplacement de la fenêtre de lancement par une architecture "dependance-based"
+Clusterisation des by-pass.
+
+=> architecture "dependance-based"
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Exploitation des dépendances instraséques entre instructions.
+Fenêtre de lancement découpé en plusieurs fifos. Les instructions dépendantes sont routés vers la même fifos.
+Execution In-order des instructions dépendante entre elles. Execution désordonné des autres flots d'instructions.
+Il n'y que les instructions de têtes à aller verifier le banc de registres.
+
+Besoin d'une table(SRC\_FIFO)  où les dépendances des instructions sont maintenus à jour
+SRC\_FIFO(num reg log) -> numéro fifo
+
+=> Clusterisation des by-pass
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Décomposé les unités fonctionnelles en cluster. 
+Il y a 2 types de bypass 
+ - intra cluster (dans le même cycle) 
+ - inter cluster (peut nécessité plusieurs cycles)
+=> N copies du banc de registres : 1 pour chaque cluster
+
+Conclusion
+----------
+Les techniques diminues faiblement (au max 12\%) le CPI mais augmente sensiblement la fréquence d'horloge. Au total, la performance global est meilleur.
+
+Autre technique :
+
+1 cluster - 1 window (Superscalar basique)
+
+-> Window -> Cluster0
+
+
+2 cluster - Fifo dispatch
+
+     -> Cluster0
+   /
+-> 
+   \ 
+     -> Cluster1
+
+2 cluster - windows - Choix du cluster : exec
+
+Instruction stocké dans une fenêtre global puis assigne à un cluster
+
+             -> Cluster0
+           /
+-> Windows 
+           \ 
+             -> Cluster1
+
+2 cluster - windows - Choix du cluster : dispacth
+
+
+     -> Windows -> Cluster0
+   /
+-> 
+   \ 
+     -> Windows -> Cluster1
+
+2 cluster - windows - Choix du cluster : random
+
+Choix des clusters aléatoire
+     -> Windows -> Cluster0
+   /
+-> 
+   \ 
+     -> Windows -> Cluster1
+
+@InProceedings{ 1998_hammond,
+  author = 	 {Lance Hammond and
+                  Mark Willey   and
+                  Kunle Olukotun},
+  title = 	 {},
+  OPTcrossref =  {SSN:0163-5980},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the eighth international conference on Architectural support for programming languages and operating systems},
+  OPTpages = 	 {58-69},
+  OPTyear = 	 {1998},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 { San Jose, California, United States},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = {ACM Press},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+27/01/2005
+
+Thread level speculation
+------------------------
+Technique autorisant l'execution paralléle d'une application séquentiel (donc à pour but de tourner sur un multi processeur).
+=> Mécanisme fonctionnant bien pour des applications avec un grain moyen de parallélisme de boucle. Mais quand la granularité de parallélisme devient trop petite, l'overhead devient trop couteux.
+
+DATA Spéculatation
+~~~~~~~~~~~~~~~~~~
+
+Processeur superscalaire avec execution désordonné :
+ -> réordonne les instructions ALU (renommage de registre , ordonnancement dynamique).
+Pas de réordonnancement des accès mémoires si les adresses ne sont pas connut on sont connus et dépendante.
+
+Data spéculation : On execute des loads qui ce situe après des stores dont l'adresse n'est pas encore connus.
+ -> S'il y a une vrai dépendance => le store est prioritaire et le load (et chaque execution en dépendant) sont ré-executés.
+
+Le programmeurs / Compilateur peut diviser un programme séquentiel en plusieurs threads. Or les dépendances de registres et de mémoires imposent beaucoup de contraintes.
+=>Si les dépendance ne peut pas être connus lors de la compilation (exemple des pointeurs en C) alors impossibilité  de diviser le code ou alors placer des routine de synchronisation logicielle.
+
+Avec le thread level data speculation (TLDS)
+=> le compilo divise seulement le programme en threads. 
+=> Chaque thread à un numéro, celui-ci indique le numéro correspondant à l'ordre dans lequel il devrait être s'il été executer en séquence.
+=> La spéculation hardware d'occupe des vrais dépendances entre les accès mémoires
+
+Les écritures deviennent des points de synchronisations.
+
+Chaque processeur execute un thread :
+On classe les procs par rapport au numéro que le thread possède.
+Celui avec le numéro le plus faible (executer sur le processeur de tête) est donc non spéculatif. Les autres sont de + en + spéculatif.
+
+Temps 0 : CPU i   -> R
+Temps 1 : CPU i+1 -> R
+Action  : -
+
+Temps 0 : CPU i   -> R
+Temps 1 : CPU i+1 -> W
+Action  : renomage dans i+1
+
+Temps 0 : CPU i   -> W
+Temps 1 : CPU i+1 -> R
+Action  : envoie de la donnée écrite par i vers i+1
+
+Temps 0 : CPU i   -> W
+Temps 1 : CPU i+1 -> W
+Action  : Ecriture de i puis renommage de i+1 et écrasage de la donnée
+
+Temps 0 : CPU i+1 -> R
+Temps 1 : CPU i   -> R
+Action  : -
+
+Temps 0 : CPU i+1 -> R
+Temps 1 : CPU i   -> W
+Action  : Renommage de i+1
+
+Temps 0 : CPU i+1 -> W
+Temps 1 : CPU i   -> R
+Action  : RAW : i+1 redemarré
+
+Temps 0 : CPU i+1 -> W
+Temps 1 : CPU i   -> W
+Action  : Renommage de i+1, + tard le forward de i sera ignoré
+
+Le matériel de spéculation des donnés doit fournir :
+ - Détection des vrai dépendances mémoire dans l'ordre.
+ - Possibilité de retour en arrière et ré-execution du threads
+ - Bufferisation des écritures jusqu'a ce qu'elle ne sont plus spéculative (Ou supprimé)
+
+Décomposition en thread spéculatif
+----------------------------------
+
+2 architectures différentes :
+ - The Multiscalar architecture => découpage en tâche arbitraire, allocation des tâche dans l'ordre sur un anneau de processeur
+ - The TLDS architecture => support minimum pour la spéculation, principalement controlé par logiciel.
+
+Solution apportée ici :
+Combinaison de l'approche hard/Soft (~TLDS)
+-> Utilisation du support du hardware pour diviser le programme en thread et les distribuer sur les différents processeurs.
+  |-> Coprocesseur de spéculation
+
+Comment diviser un prcess en threads?
+ -> utilisation d'appel de sous fonction
+   -> Un autre processeur va executer de manière spéculatif la suite du programme principal
+ -> Boucle (Ceux indiqué par le compilateur)
+   -> Les différentes itérations sont distribuées sur les différents processeurs
+
+Subroutine Thread
+~~~~~~~~~~~~~~~~~
+
+Spéculation de fonction géré par une list chainé de threads actifs ordonnée du moins au + spéculatif
+Lors d'un appel de fonction, envoie d'un message au autre processeur.
+
+1) Le processeur alloue un register passing buffer (RPB) pour le thread nouvellement crée. 
+2) Sauvegarde des registres (devant être sauvegarder lors d'un appel systems) puis prédition de la valeur retourné 
+  alogo repeat least return value (car en C -> beaucoup de void fonction ou de retour d'erreur, ou imprédictible)
+3) Insertion du buffer dans la list des buffer actif juste après le process courent (pour garder l'ordre par spéculation)
+4) Attribution d'un processeur à ce nouveau thread (soit un libre, soit un executant le plus spéculatif des threads)
+
+Ceci est réaliser dans l'exception handler (Donc chaque appel à une sous fonction génére une exception)
+Si l'appel de fonction à une valeur de type imprédictible, alors on ne considère pas la spéculation.
+
+Au retour d'un appel de fonction :
+1) Le processeur attend jusqu'a ce qu'il soit le processeur de tête (donc sont code devient non spéculatif et deplus il n'est pas en conflit avec les autres thread)
+2) La valeur retourné est comparé avec la une valeur prédite. Si miss => Toute les threads sont relancés
+3) Le RPB est remis dans la free-list, le thread suivant devient celui de tête
+4) L'ancien processeur de tête va executer un thread (donc devient le plus spéculatif)
+
+Loop itération Thread
+~~~~~~~~~~~~~~~~~~~~~
+
+Un boucle spéculatice est préceder d'une verification pour savoir s'il est avantageux ou non de l'exécuter de manière spéculative.
+Une itération de boucle est donnée a chaque proc disponible.
+
+A la fin d'une itération -> validation, l'itération suivante devient le CPU de tête.
+Ceci jusqu'à ce que la condition de terminaison soit trouvée (dans ce cas invalidation de tous les autres threads) 
+
+2 manières de traiter les boucles :
+ - Si la boucle est longue : rebouclage des RPB
+ - sinon Schéma habituel : insertion de 4 RPB (1 pour chaque proc) => Overhead moins couteux mais méthode peu fléxible
+
+Taille des Threads
+~~~~~~~~~~~~~~~~~~
+
+Facteur de Limitations :
+1) Taille limité des buffers : Il n'y a que le CPU de tête qui réalise des mise à jour de la mémoire. Les CPU spéculative ne peuvent commiter leur buffer que s'il deviennent buffers de têtes.
+2) Vrai dépendance : Les grands threads augmente la probabilité de vrai dépendance
+3) Longueur des redémarrages : Un redémmarrage sur un grand thread augmente la charge de travail (données à défaire etc..)
+4) Overhead : Les très petits threads ont un coût d'overhead trop élevé.
+
+=> Violation counters : élimine les threads avec trop de dépendances
+=> Thread timers : élimine les threads trop long
+=> Stall timers : élimine les threads trop souvent bloqués (voir plus bas)
+
+Exception
+~~~~~~~~~
+Si un thread réalise une exception, ou un appel système, alors celui-ci est bloqué.
+
+Speculation Control Coprocessor
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+=> Implémenter dans le Coprocesseur2 du mips
+-> Fonction accèder par software
+-> Contient la table des vecteurs d'exceptions
+
+Hardware Support
+----------------
+
+Sur le multiscalar processor => ARB (Dcache partagé) associé avec un traceur de reférence mémoire spéculative.
+Sur le TDLS processor        => Protocole plus simple
+
+Ici : 
+ - Modification dans le Dcache : Sur chaque tag d'une ligne de cache, ajout de qq bits (modified bit, pre-invalidate bit) (Read, Write bits => pour détecter les vrai dépendance, un bit par mots contenu dans la ligne)
+ - Buffers dans le cache L2    : Bufferisation des écritures encore spéculative. Une fois qu'il ne sont plus spéculative, ordre venant du processeur pour rentre permannent les changement. Le buffer est dépiller par ordre d'arriver et écrit dans le L2. Le buffer full est détecter par chaque proc qui possède une copie local des Tags du buffer couramment utilisé.
+Lors d'un load  spéculatif , On va lire le DCACHE, puis on va lire dans le buffer courrant au proc, puis on remonte tous les buffer appartement a des process moins spéculative (jusqu'a la tête) et enfin on va lire dans le L2 cache. (Tous est vérifier en parralléle)
+Lors d'un sotre spéculatif , il peut se produire : écriture dans le DCACHE (demander par le proc courant), une invalidation par un cpu moins spéculatif (vrai dépendance), une pré invalidation venant des cpu plus spéculatif (vérification). Si proc devient la tête : Drainage du buffer.
+@TechReport{1998_olukotun,
+  author = 	 {Lance Hammond and
+                  Kunle Olukotun},
+  title = 	 {Considerations in the design of hydra : a multiprocessor-on-a-chip microarchitecture},
+  institution =  {Stanford University},
+  year = 	 {1998},
+  OPTkey = 	 {CSL-TR-98-749},
+  OPTtype = 	 {},
+  OPTnumber = 	 {},
+  OPTaddress = 	 {},
+  OPTmonth = 	 {February},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+24/01/2005
+
+Décrit de manière détaillée :
+- Hiérarchie mémoire
+- Bus internes
+- Contrôle et arbitrage
+
+Hierarchie Mémoire
+~~~~~~~~~~~~~~~~~~
+L1 - On chip - I D séparé , et 1 couple pour chaque proc
+L2 - On chip - Partagé avec les 4 processeurs
+L3 - Off chip
+Mémoire principale - Off chip
+
+L1 unifié pour les 4 procs :
+ - Trop de ports R/W
+ - Cache L1 devient "plus gros" pour rendre les même services
+ - Logique entre le cache et le L1 (en cas d'accès à la même case)
+ - Trop de logique => Ne réponds pas en 1 cycle
+
+L1 séparé
+ - Obligation d'un mécanisme de snoop
+
+Limitation d'avoir un L3 off chip :
+ - RAM rapide sont onéreuse
+ - Demande beaucoup de plots
+ - Electriquement non triviale
+
+Communication
+~~~~~~~~~~~~~
+2 bus internes :
+ - Bus Read/Replace
+ - Bus Write-through 
+
+Gérer de manière pipeliné, demande 1 cycle pour l'arbitrage afin d'avoir un débit d'un accès par cycle
+
+Bus Read/Replace  : 256b de large (1 ligne de cache L1 / L2). Liaison entre le L2, et le L3 ainsi que tous les L1 (en lecture uniquement). Bus avec un faible traffic (dans leur exemple : occupation inférieur à 50\% pour les tests les plus gourmand en accès mémoires)
+
+Bus Write-through : 64b de large, de tous les caches L1 vers le L2. Cohérence du cache L1 sur snoop de ce bus (pas le read/replace bus) , Invalidation sur écriture (Un seul cache est propriétaire d'un bloc). Les écritures de tous les procs se retrouvent séquencer.
+
+L'utilisation du write-bus n'est pas scalable :
+ * write-bus multiple (Ou 1 seul rapide) => Ports supplémentaires pour le L1 Tags, snoop et invalidation multiple par cycle. Dans le L2 => plusieurs données peuvent être écrite par cycle.
+ * Une ligne de bus avec un mode rafale
+ * Protocole conventionnel de cohérence MESI, et elimination du write bus pour un bus partagé entre les lecture et les écritures
+
+Contrôleur mémoire
+~~~~~~~~~~~~~~~~~~
+Chaque ctrl mémoire est divisé en 2 pipelines indépendants. 
+ - un pour manager les accès en lecture (Instruction fetch et load)
+ - l'autre pour manager les accès en écriture
+
+Lecture  : en général prévisible et donc absorbé par le cache
+Ecriture : A cause du write throught : répercuter à chaque fois sur le bus. De plus les codes ont tendance à faire des burst de store. En général absorbé par le store buffer.
+
+pipeline de Lecture et celui d'ecriture sont similaire :
+3 étages :
+ - accès L2 (~5  cycles)
+ - accès L3 (~15 cycles)
+ - Initiation de l'accès à la mémoire principal ( 5-10 cycles)
+L'avancement dans le pipeline se fait sur un miss de l'accès courant.
+
+Degré de pipeline :
+Accès L2, Accès L3 pipeliné
+Accès mémoire non pipeliné (1 seul requêtes dans cet étage)
+
+De plus il y a deux autres ctrl dans la mémoire principale et l'interface I/O
+-> Retourne les données venant de l'extérieur vers le cache approprié.
+-> ~ au ctrl des caches
+
+Arbitre
+~~~~~~~
+Les demandes d'accès les plus anciennes sont servies en premier
+
+Ce n'est pas une allocation cycle par cycle ou ressource par ressource. Mais par unité de cycle (de 5 à 20 cycles).
+
+Chaque CPU pipeline (ctrl mémoire) envoie une requete de ressource au début de chaque étage de pipeline.
+Priorité fixe :
+ - vers Accès mémoire et I/O
+ - vers L3
+ - vers L2
+(Les plus courants sont les moins prioritaire, évite la famine)
+
+Read pipeline est prioritaire sur le write pipeline. Possibilité au L1 d'inverser la priorité si le write buffer est (proche d'être) plein.
+
+Arbitrage sur la même adresse
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+2 accès se réalise en parrallèle (L1 / L2 / L3 / Mémoire) sur le même adresses
+Problèmes :
+ - Copie multiple d'une ligne de cache => Plus de proporité d'exclusivité des lignes de caches.
+ 
+@InProceedings{1998_krishnan,
+  author = 	 {Krishnan, V.   and
+                  Torrellas, J.  },
+  title = 	 {A clustered approach to multithreaded processors},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Parallel Processing Symposium, 1998. 1998 IPPS/SPDP. Proceedings of the First Merged International...and Symposium on Parallel and Distributed Processing 1998},
+  OPTpages = 	 {627-634},
+  OPTyear = 	 {1998},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Orlando, FL  ,   USA},
+  OPTmonth = 	 {30 Mar - 3 Apr},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+25/02/2005
+
+SMT                    -> Flexible (TLP et ILP) 
+Fixed assignement (FA) -> Sous utilisation des ressources
+
+CMT -> un thread à tous les ressources à un instant donné
+Pbl SMT -> Conséquence sur le temps de cycle !!!
+
+SMT clusterisé : Unité de calculs sont multisthreadé, l'unité de dispatch va envoyé les instructions d'un thread vers les unités de calculs qui lui sont associés.
+
+Model de parallélisme
+---------------------
+
+Architecture fixe : N threads ayant M unités d'execution. Une unité d'execution n'apaprtient qu'a un thread => jusqu'a M IPC
+Si X nb d'Unité d'execution total fixe -> M = X/M 
+  - Si N trop grand -> exploite peu l'ILP
+  - Si N trop petit -> exploite peu le TLP
+
+Architectures
+-------------
+
+Centralisé et clusterisé SMT:
+
+Fetch unit partagé par ts les threads, (géré round robin ou autre), les instructions sont ensuite placé dans une fênetre d'instructions commune. Les instructions sont commité par thread.
+ -> limite : large interconnections entre les unités fonctionnelles et le banc de registres (en particulier les by-pass)
+
+FA :
+
+Réduction de la centralisation des ressources : partionnement du SMT classique en clusters (SMT d'ordre X*Y devient X clusters étant des SMT d'ordre Y).
+Chaque cluster à sont unités de FETCH
+
+Evaluation
+----------
+Un gaspillage d'un slot d'instructions peut être classé en :
+- struc : Manque d'unités fonctionnelle
+- mem   : Accès mémoire
+- data  : Dépendance de donnnées
+- ctrl  : Miss predictions de branchements
+- sync  : Barrières de synchro
+- fetch : Pas d'instructons pour un thread dans la fenêtre
+- autre
+
+Comparaison d'un FA8  (8 clusters qui sont des superscalaire d'ordre 1)
+                 FA4  (4 clusters qui sont des superscalaire d'ordre 2)
+                 FA2  (2 clusters qui sont des superscalaire d'ordre 4)
+                 FA1  (1 clusters qui sont des superscalaire d'ordre 8)
+                 SMT8 (8 clusters qui sont des SMT supportant 1 threads lancant 1 inst/cycles) 
+                 SMT4 (4 clusters qui sont des SMT supportant 2 threads lancant 2 inst/cycles) 
+                 SMT2 (2 clusters qui sont des SMT supportant 4 threads lancant 4 inst/cycles) 
+                 SMT1 (1 clusters qui sont des SMT supportant 8 threads lancant 8 inst/cycles) 
+En terme de complexité SMTx = FAx
+SMT8 est identique à FA8
+SMT1 est une architectures SMT centralisés
+
+de FA8 à FA1 : sync décroit mais les data et mem croit. (logique :P)
+
+
+@InProceedings{  2000_barroso,
+  author = 	 {Luiz André Barroso   and
+                  Kourosh Gharachorloo and
+                  Robert McNamara      and
+                  Andreas Nowatzyk     and
+                  Shaz Qadeer          and
+                  Barton Sano          and
+                  Scott Smith          and
+                  Robert Stets         and
+                  Ben Verghese},
+  title = 	 {International Conference on Computer Architecture},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the 27th annual international symposium on Computer architecture},
+  OPTpages = 	 {282 - 293},
+  OPTyear = 	 {2000},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Vancouver, British Columbia, Canada},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = {ACM Press},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+02/12/2004
+
+systeme Piranha : Exploite le multiprocesseur à l'aide de 8 alpha (simple) avec 2 niveaux de caches, le tout sur un seul chip.
+
+Les processeurs hautes performances vise l'exploitation au maximum de l'ILP. Réalisant des architectures de + en + complexe, afin d'améliorer les benchmarks de types SPEC.
+Or Les domaines d'applications demandant vraiment de la haute performance se situe au niveau des serveurs. (Application internet) => Comportement n'est pas comme les bench SPEC
+
+Pourquoi cette architecture : Le coût d'un SMT (simultaneous multithrading) étant plus cher qu'un CMP (chip multiprocessing), car plus complexe (le SMT contient du matériel pour gérer les changement de thread, + de banc mémoire etc ...). Alors que l'approche CMP peut être réaliser avec des processeurs plus simple.
+
+Idée dans le piranha :
+ -> Mémoire secondaire partagée (non inclusive avec un niveau L1)
+ -> Cohérence des caches
+ -> architecture I/O
+
+Architecture générale :
+-----------------------
+
+ * CPU alpha possèdant un I et DCACHE dédié
+ * Tous ces couple Proc+Cache sont relié autours d'un Interconnect
+ * Sur cette interconnect, il y a également les caches L2 (donc partagés avec n'importe lequel des CPU)
+ * Sur chacun des caches L2 est connecté un controleur mémoire.
+ * Ce dernier à une liaison directer avec des RDRAM.
+ * Connecté sur le Bus, pour la communication avec le monde extérieur
+    - Home engine
+    - Remote engine
+ * Les 2 moteurs de protocoles sont connecté au routeur de paquet qui distribue les paquets entre les moteurs internes et file d'entrée et de sortie. 
+ * Le bus étant piloté par un module : system control
+
+Structure hiérarchique forte.
+
+Réseau de noeud Piranha :
+ - Les P-chip   => en interne possède 8 CPU alpha
+ - Les I/O-chip => Permet de faire la liaison avec le monde extérieur (Au lieu des 8 CPU, il n'y en a qu'un + un bloc I/O)
+
+D'après les concepteurs, un réseau peut aller jusqu'a 1024 noeuds avec un nombre quelconque de noeud I/O.
+Un des principes fondamental, est qu'un noeud I/O est traité de la même manière qu'un noeud de traitements.
+
+Architecture détaillée :
+------------------------
+
+CPU + L1 cache
+~~~~~~~~~~~~~~
+Processeur alpha de 500Mhz, 8 étages de pipeline classique (Ifetch, Decode, Execute (*5), Writeback).
+ -> Unité flottante, BTB, logic de prédécodage.
+2 caches séparé :
+ -> 64 ko, ass 2voies. Cache bloquant avec adresse Virt et Tag phy. 
+ -> TLB de 256, ass 4voies
+ -> Protocole de cohérence MESI
+ -> Non inclusif avec le niveau L2
+
+Intra-Chips Switch (ICS)
+~~~~~~~~~~~~~~~~~~~~~~~~
+Conceptuellement, c'est un crossbar.
+-> Uni-directionnel, interface Push-only
+-> ECC , bits de parités
+-> pré-allocation (spéculation)
+-> 2 priorités (low & high), un chip peut choisir la priorité désiré.
+
+Cache L2
+~~~~~~~~
+Cache unifié d'1Mo, découpé en 8 bancs qui sont ass 8voies (Remplacement round robin)
+-> Maintient de la cohérence intra-chip
+-> Non inclusif avec le niveau 1 de caches (Non dédoublement des instructions)
+-> write no allocate
+-> Duplication du registre de TAG du cache L1 associé au cache L2
+
+L1 envoie une requete mémoire à son banc L2. Celui-ci peut :
+ -> Servir directement la requête
+ -> La renvoie à un autre Cache L1
+ -> La renvoie à un autre protocle de cohérence
+ -> Obtient la donnée à par le contrôleur mémoire
+
+Contrôlleur Mémoire
+~~~~~~~~~~~~~~~~~~~
+Un Contrôlleur mémoire par cache L2.
+A une liaison rapide avec les RAMs,
+N'a pas de liaison direct avec l'ICS
+
+Protocole Engine
+~~~~~~~~~~~~~~~~
+Assure le support pour la mémoire partagé, 2 blocs spérarés :
+ -> "home engine"   responsable d'exporter la mémoire local a ce noeud
+ -> "remote engine" importe la mémoire qui se trouve dans un noeud distant
+
+Chaque bloc est a peu de chose près conçu de la même manière :
+* Input controller
+* microcode controlled execution unit
+* Ouput controller
+
+Une execution micoprogrammé assure la gestion entre les deux interfaces.
+
+Cohérence des caches : Read, Read-exclusive, Exclusive, Exclusive-without-data
+
+Interconnecte système
+~~~~~~~~~~~~~~~~~~~~~
+3 partie distinct :
+-> Output Queue
+-> Input  Queue
+-> Routeur
+
+Topologie indépendante, adaptatif, Buffer avec différents niveau de priorités, canaux virtuels
+
+Mise en place de dispositifs pour assurer la fiabilité, disponibilité et l'utilité des données :
+ - redondance sur les dispositifs mémorisants
+ - procetection CRC sur les chemins de donn"s
+ - protocle de recouvrement d'erreur
+ - enregistrement d'erreur
+ - Liens permuttable à chaud
+
+METHODOLOGIE D'EVALUATION
+-------------------------
+
+Utilisation d'un bench simulant des accès de clients sur des bases de données.
+ -> Oracle (logiciel)
+ -> SimOS-Alpha (Os pour processeur alpha assez fournit (gère le multi processeur, la mémoire virtuel ...)
+
+Comparaison de l'archi piranha avec :
+ - Un alpha21364 : un superscalaire Out of order, à 1Ghz, 2 niveaux de caches etc...
+ - un système piranha avec 8 procs (P8)
+ - un système piranha avec 1 proc  (P1)
+ - un proc superscalaire In order
+
+Constatation :
+ - le piranha 8 est relativement performant
+ - Le traffic dans l'interconnect local est d'autant plus grand qu'il y a de processeurs, surtout a cause des mécanisme de cohérence de cache (Forwarding vers d'autre cache L2)
+
+Remarque de fin :
+Les auteurs finissent par cette perspective :
+ => La question clé pour les designers des processeurs futures ne va pas être de savoir si on va employés des multi procs, mais de déterminer la bonne compensation entre le nombre de coeurs et la puissance de chaque coeurs. Et quel sera la meilleur hierarchie mémoire.
+@Article{         2000_hammond,
+  author = 	 {Hammond, L.   and
+                  Hubbert, B.A. and
+                  Siu, M.       and
+                  Prabhu, M.K.  and
+                  Chen, M.      and
+                  Olukolun, K.   },
+  title = 	 {The Stanford Hydra CMP},
+  journal = 	 {Micro, IEEE},
+  year = 	 {2000},
+  OPTkey = 	 {},
+  OPTvolume = 	 {Volume 20, Issue 2},
+  OPTnumber = 	 {},
+  OPTpages = 	 {71-84},
+  OPTmonth = 	 {Mars/April},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+07/12/2004
+
+MOTIVATION
+----------
+
+Les processeurs sont plus petits et rapide. Donc pour une même surface, nous avons une augmentation du "budget" de processeur.
+ -> Soit on augmente la complexité d'un mono-processeur
+ -> Soit on augment le nombre de mono-processeur simple sur un chip
+
+Parrallélisme:
+2 types de parrallélisme : ILP (Instruction level parrallelism) et TLP (Thread level parrallelism)
+Souvent la logique utilisé pour augmenter l'ILP fait augmenter le cycle d'horloge de manière quadratique.
+De plus il est limite à 4-6 instructions (cf 1991\_wall)
+
+Contrainte technologique :
+Délai causé par l'interconnection des portes (délai des nets) devient significatif => zone localement synchrone et globalement asynchrone. Un CMP peut faire en sorte de placer des processeurs simples dans les zones localement synchrones
+
+Temps de design:
+La conception d'un CMP s'appuie plus sur l'utilisation d'IP.
+
+Pourquoi les CMP ne sont pas utilisé?
+ -> Difficulté à convertir un programme pour mono-proc en multi-proc (Problème de consitence mémoire, synchronisation entre proc etc ...)
+ -> Les compilateurs parralléles sont encore très assistés par le programmeur
+
+DESIGN
+------
+
+Le chip Hydra est un chip multiprocessor (CMP) intégrant 4 processeurs MIPS possédant chacun un Icache et un Dcache L1, mais un niveau L2 partagé.
+Tous les controleurs des Caches L1 et le cache L2 sont sur le même bus. (Appellé bus d'écriture)
+Un autre bus prévut pour les échanges entre l'extérieur et le cache L2 mais avec possibilités de lecture des contrôleurs L1
+
+Protocole d'invalidation simple sur le bus d'écriture
+
+Il existe beaucoup d'application pour mono-processeur. Pour l'executer sur un système multi-proc, soit on sous utilise notre architecture, soit on ajoute de la thread-level speculation.
+L'hydra va utiliser la deuxième technique.
+
+thread-level speculation
+~~~~~~~~~~~~~~~~~~~~~~~~
+Prends une séquence d'instructions, la découpe de manière arbitraire en thread. Le hardware doit suivre ces threads. Si un thread réalise une lecture trop tôt (Donc un autre thread n'a pas encore fournit de résultat), le hard doit s'arranger pour que ce thread ce réexecute avec la bonne lecture.
+Grande complexité car on doit déterminer toute les possibilités de "vrai dépendances"
+
+Outre le cas normal, il y a 5 types de problèmes de cohérences :
+- Cas normal : début de boucle load X , fin de boucle write X
+- Renvoie de la donnée entre thread parralléle
+- Détection si les lectures sont "proche" (Dépendance RAW) : Au moment de faire un write sur X à l'itération i, alors le distribuer au load de l'itération i+1 (Forward data entre deux thread paralléle). 
+ => Mécanisme pour ce souvenir des traces d'execution (S'il y a eu précedement une lecture sur X dans l'itération i+1 lros de l'execution de l'instuction write sur X de l'itération i, alors il y a une erreur).
+- Annulation saine de l'exec spéculatif après violation 
+- Retirer les écritures spéculatives dans le bonne ordres (Dépendance WAW) (tjs l'itération la plus ancienne en premier) => Les écritures ne deviennent plus spéculative.
+- Fournir le rennomage mémoire (Dépendance WAR)
+
+Le système doit avoir un mécanisme pour décomposer en thread, et pouvoir les arreter les threads spéculatifs.
+
+Où découper les threads : En pratique : que lorsque l'on peut avoir plusieurs voie, càd boucle et appel de fonctions (Si la fonction ne retourne pas de résultats ou le résultat est facilement prédictible)
+Le speculation runtime system va choisir les 4 threads les moins spéculatifs et les executer (car il y a 4 procs).
+
+Le mécanisme de spéculation demande des médiums de communication rapide inter processor, sinon le processus mono thread risque de couter moins cher que sont équivalents découpés en plusieurs threads (spéculatif).
+
+Sur l'hydra, le matériel additionnel pour utiliser cette technique est placé dans 2 blocs matériels :
+- Ram de flags pour les caches L1 (est ce que la donnée contenu dans la ligne à été spéculativement lut ou écrite?)
+- Write buffers dans le cache L2 (Buffer d'écriture permettant de sauvegarder "sainement" les données dans le cache L2. (Garantie de donnée non spéculative)
+
+Comment cela fonctionne?
+~~~~~~~~~~~~~~~~~~~~~~~~
+- Un buffer est alloué à chaque thread en train d'être éxecuté sur ce système. Dès qu'un thread ne devient plus spéculative, alors les buffers écrivent dans la mémoire.
+- Pour contrôler le séquencement des threads, il y a un petit composant utilisant l'interface coprocesseur du mips.
+  |-> "speculation coprocessors"
+
+Classement de threads par degré de spécultation, quand un thread spéculatif d'ordre i envoie un message sur le writebus, seul les ctrls rattaché à des procs éxecutant un thread plus spéculatif (donc d'ordre > i) snoop le bus (rappel => utilisation de l'invalidation sur snoop)
+
+=> Lors d'un accès mémoire => Lecture en L1, si miss (surement invalidé) alors regarde dans son write buffer  puis dans les write buffer des threads de - en - spéculatif, et enfin dans le cache L2.
+
+COUT ET PERFORMANCE
+-------------------
+Cout        : augmente la surface de quelques pourcents.
+Performance : Programme difficille ou impossible à parralléser, cependant ce sont des applications hautements parralléles.
+@InProceedings{2001_nagarajan,
+  author = 	 { Ramadass Nagarajan   	  and
+                   Karthikeyan Sankaralingam 	 and
+                   Doug Burger 	 and
+                   Stephen W. Keckler},
+  title = 	 {A design space evaluation of grid processor architectures},
+  OPTcrossref =  {SBN ~ ISSN:1072-4451 , 0-7695-1369-7},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture },
+  OPTpages = 	 {40-51},
+  OPTyear = 	 {2001},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 { Austin, Texas},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = { IEEE Computer Society },
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+02/02/2005
+
+En quoi consiste un Grid processors architecture?
+ -> tableau d'ALU avec un contrôle limité.
+ -> Les alu sont connecté par un réseau ou circule leur opérande
+ -> Les programmes sont éxécutés en mappant les blocs de manière statique et a executé les isntructions de manières dynamiques
+ -> Executions possible via une chaine d'alu (sorte de pipeline)
+
+Le GPA est conçut en vut d'avoir une grande fréquence d'horloge et une grande exploitation de l'ILP
+Le coeur de calcul d'un GPA consiste en une matrice 2D de noeuds. Chaque noeud contient un buffer d'instruction et une unité d'execution.
+-> noeud peuvent donc réaliser des calculs à grain fins
+-> les noeuds sont interconnecter avec un réseau dédié à la communication de données et d'opérande.
+-> Contrôle assuré par un mécanisme mappant les instructions sur les noeuds
+
+=> Equivalent à une approche VLIW : Ressources alloués statiquement par le compilo mais le lancement est dynamique
+
+MODELE D'EXECUTION
+------------------
+
+Modèle d'execution : traite des groupes d'instructions comme une unité atomique pour le fetch, mappage de ressources des unités d'execution et le commit.
+Dans ce modèle, les groupes d'instructions sont définit par le compileur.
+ -> Un groupe n'a pas de transfert interne de ctrl (c'est à dire un saut prit sera la dernière instruction d'un groupe) (Un bloc peut être un bloc de base ou une trace d'execution ...)
+ -> Données utilisé sont de 3 types : (Modèle Producteur - consommateur)
+    * entrée : valeur produite par un autre groupe et consommé par ce groupe
+    * sortie : valeur produite par le groupe et consommé par un autre groupe -> écriture des données dans un mémoire tampon jusqu'au commit
+    * temporaire : valeur produite et consommé par le groupe -> transimition des données en internes
+
+Compilateur assigne statiquement chaque instruction à un groupe d'alu. Un groupe ne peut être allouer à plus d'une instruction
+
+1) Un groupe est fétché et mapped sur les ALUs
+2) Chaque instruction dans le groupe est écrite dans les buffers d'instructions ( ~ station de réservations)
+3) Lecture des opérandes dans le banc de registres et placement des opérandes dans les alus.
+4) Execution de l'instruction
+5) Une fois que l'execution est terminé, le résultat est renvoyé vers l'alu consomatrice. (Ou vers le banc de registres)
+
+Destination encodé explicitement dans l'instruction
+
+6) Lorsque tte les instructions d'un groupe sont finis => commit : update de la mémoire
+7) Le groupe est libéré des ALUs
+8) Mappage du prochain groupe ...
+
+Il existe un branch register pour les résultats des branchements.
+
+Avantage
+--------
+-> Peu de structures larges impliqué dans l'execution (càd non centralisé, pas de fenêtre de lancement associative, pas de table de renommage de registres, peu d'accès en lecture et écriture simultané)
+-> Execution désordonnée (sans vérification de dépendance large, diffusion des bypass, réseau dédié au forward)
+
+Implémentation
+--------------
+
+ICACHEM -- REG --- REG --- REG --- REG
+            |  \ /  |  \ /  |  \ /  |
+            |  / \  |  / \  |  / \  |
+ICACHE --- ALU --- ALU --- ALU --- ALU --- DCACHE
+            |  \ /  |  \ /  |  \ /  |
+            |  / \  |  / \  |  / \  |
+ICACHE --- ALU --- ALU --- ALU --- ALU --- DCACHE
+            |  \ /  |  \ /  |  \ /  |
+            |  / \  |  / \  |  / \  |
+ICACHE --- ALU --- ALU --- ALU --- ALU --- DCACHE
+            |  \ /  |  \ /  |  \ /  |
+            |  / \  |  / \  |  / \  |
+ICACHE --- ALU --- ALU --- ALU --- ALU --- DCACHE
+
+          BLOC TERMINAISON ET TERMINAISON
+
+
+ALU rangé en matrice de n*m cases.
+Le bloc de terminaison détermine quel groupe d'instructions est mappé et quand celui-ci à terminé (dc commit)
+Chaque alu contient 
+ * des ports d'entrée pour les opérandes
+ * des buffers d'instructions et d'opérandes
+ * un routeur pour délivrer les résultats vers les ports de sorties
+Un prédicteur de branchement va prédire le succès de ce blocs et va fetché et mappé sur la grille le bloc suivant.
+
+Caractéristique influencant les performances :
+- Organisation des ALUs (nombre et position)
+- la latence du réseau d'unterconnection d'un noeud
+- le nombre d'I/O de chaque noeud
+
+Alternatives
+------------
+* Changer le design du réseaux de grille : Préreservations du flow, découpage du message, 
+* Chgt du système mémoire : Format d'instruction compressé, envoyant ce code compréssé au L1. Dcache ~ fifo pour maintenir la cohérence => Utilisation de technique de spéculation.
+* Spéculation de grille
+* Management des frames : Execution de multi thread, thread spéculatif 
+
+
+@Article{2002_ungerer,
+  author = 	 {T. Ungerer and 
+                  B. Robic   and
+                  J. Silc },
+  title = 	 {Multithreaded processors},
+  journal = 	 {The Computer Journal},
+  year = 	 {2002},
+  OPTkey = 	 {},
+  OPTvolume = 	 {45},
+  OPTnumber = 	 {3},
+  OPTpages = 	 {320-348},
+  OPTmonth = 	 {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+17/02/2005
+
+Contrainte de la conception d'un proc multi thread :
+ - Différente logique pour le calcul d'adresse
+ - Les threads doivent avoir une espaces d'adressage commun
+ - Extraction de thread de manière hardware ou software (compilo)
+
+-> implicite multi threading : Chaque architecture va executer de manière concurrentiel différent thread d'un même programme séquentiel (predication de branchement etc...)
+-> explicite multi threading : Execution d'un flots multi programmé
+
+But principal -> recouvrir la latence d'un thread par l'execution d'un autre.
+
+
+Mécanisme minimal :
+- Plusieurs PC
+- Mécanisme pour commuter les threads
+  |-> Potentiellement avoir plusieurs banc de registres permet d'augmenter la commutation
+
+3 approches :
+- multithreading imbriqué  (FMT) : Changement de thread à chaque cycle
+- multithreading bloqué    (VMT) : Changement de thread à chaque évenement (evt induiant une latence => ex div, miss etc ...)
+- multithreading simultané (SMT) : Plusieurs threads actifs en même temps
+
+Fine graine MT
+~~~~~~~~~~~~~~
+L'imbrication de plusieurs threads va limiter la perf de chaque thread
+ -> technique "dependance lookahead" : ajout de bits à chaque inst dans l'isa pour déterminer combien d'inst suivant n'a pas de dépendance avec celle-ci
+ -> technique d'imbrication : chgt de thread à chaque cycle
+
+Diverses "astuces" : Cray-MTA à au moins 128 contextes afin de masquer la latence de la mémoire étant de 128 cycles (Changement de contexte à chaque cycle)
+
+Coarse graine MT
+~~~~~~~~~~~~~~~~
+
+=> Execution d'un thread jusqu'a ce qu'une condition de changement de contexte est atteinte :
+
+ -> Modèle statique
+     -> Chgt explicite (Par instr "switch" ou une instruction "taggé")
+     -> Chgt implicite (Sur load, store, branch etc ...)
+ -> Modèle dynamique
+     -> Chgt sur miss de cache
+     -> Chgt sur evenement (interruption, trap ...)
+     -> Chgt sur profil d'utilisation (trop de chargemement (ou pas accès) etc ...)
+     -> Chgt conditionnel (instruction de switch conditionnelle)
+
+Un plus petit nombre de threads est nécessaire pour atteindre de bonne performance.
+-> Pénalisation d'un thread remplicant souvent la condition de changement de contexte
+
+Avantage de Modèle statique -> le changement de contexte peut être détecter tôt dans le pipeline (Voir tjs dans le même étage).
+
+Simultaneous MT
+~~~~~~~~~~~~~~~
+FMT et CMT sont très performant pour des processeurs scalaire ou VLIW (un flut d'instruction)
+
+L'unité d'IFETCH peut être partagé par plusieurs threads, (Dans ce cas on augmente la probabilité d'aller chercher des instructions non spéculative). 
+De plus l'unité IFECTH peut choisir quel thread privilégié pour aller chercher ces instructions.
+
+ -> Partage de ressources : tous les thread partage un maximum de ressources (ifetch buffer, décodeur, banc de registres, fenêtre d'instruction etc ...)
+ -> Duplication de ressources : Chaque buffer interne appartient à un thread spécifique. Les étages internes peuvent être multiplexé ou dupliqué entre les threads.
+
+Priorité :
+ RR        : Round-Robin
+ ICOUNT    : La priorité est donné au thread ayant le moins d'instructions dans les étages decodes, rename et queue
+ BRCOUNT   : La priorité est donné au thread ayant le moins de branchement (donc le - spéculatif)
+ MISSCOUNT : La priorité est donné au thread ayant le moins de DCACHE miss
+ IQPOSN    : La priorité est donné au thread ayant les plus vieille instructions
+
+SMT peut aussi executer les deux chemins d'un branchement. 
+
+Diverses technique :
+~~~~~~~~~~~~~~~~~~~~
+
+- Division d'un thread en collection de tâches qui sont distribués dans les unités d'executions.
+  -> processeur de trace
+- Processeur "super-threadé" un pipeline d'execution/thread,  peut être alloué par le compilateur
+- dynamic multi threading processor : Création de threads de manière dynamique (sur appel de procédure et déroulement de boucle ...)
+- microthread -> Création d'un microthread de manière explicite => préfetech une donner, calculer en avance la condition de saut ...
+              -> Utilisation des threads "idle"
+- Execution des 2 branches d'un saut -> utilisation des threads "idle"
+                                     -> utilisation de la prédication
+
+Multi-threading et le temps réel
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-> Le chgt de contexte "rapide" est un avantage clé pour les systèmes temps réel.
+-> Le multi threading permet d'avoir la routine d'intérruption et le programme principale dans 2 threads du processeurs
+
+Chip multi processors
+---------------------
+Symetric multiprocessors (SMP) et le Distribued shared Memory multiprocessors (DSM) -> espace mémoire uniforme (UMA)
+un DSM peut également ne pas maintenir la propriété d'espace mémoire uniforme => Communication par passage de message
+
+Cohérence des caches par snooping (SMP) ou directory based (DSM).
+
+3 alternatives de CMP :
+ - mémoire partagé (SMP typique)
+ - L2 partagé
+ - L1 partagé
+partagé les niveaux de caches diminue le délai de communication iter-processeur. Plus d'espaces pour les threads
+
+@InProceedings{2003_sankaralingam,
+  author = 	 { Karthikeyan Sankaralingam   	  and
+                   Ramadass Nagarajan 	 and
+                   Haiming Liu 	 and
+                   Changkyu Kim 	 and
+                   Jaehyuk Huh 	 and
+                   Doug Burger 	 and
+                   Stephen W. Keckler 	 and
+                   Charles R. Moore},
+  title = 	 {Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture},
+  OPTcrossref =  { ISBN:0-7695-1945-8},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the 30th annual international symposium on Computer architecture},
+  OPTpages = 	 {422-433},
+  OPTyear = 	 {2003},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {Volume 31 Issue 2},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {San Diego, California},
+  OPTmonth = 	 {May},
+  OPTorganization = {},
+  OPTpublisher = {ACM Press},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+01/02/2005
+
+Architecture polymorphe : TRIPS
+Peut être configuré pour différente granularité et types de parallélisme => Instruction level paralelism, Thread LP Data LP.
+
+Processeur : Soit on a un général-purpose microprocesseur qui sait tout ou alors on spécialise le processeur :
+ -> Bureautique, network, serveur, scientifique, graphique ou signaux digitaux.
+
+La spécialisation à un défaut :
+ -> Le processeur devient peut performant dans un domaine qui n'est pas sa spécialisation.
+
+Les CMP peuvent être vut de 2 manières :
+ -> Homogène   : Ensemble de processeurs identiques
+ -> Hétérogène : Regroupement de processeurs spécialisé -> mappage d'une application sur cet architecture ...
+    |-> Défauts : * Augmentation de la compléxité
+                  * Sous utilisation des ressources si un thread n'a pas besoin de la spécialité
+
+Une architecture polymorphique est capable de configurer le hard pour exécuter de manière efficace un large spectre d'applications.
+-> Approche synthétique : Utilisation de CMP à grain fin -> synthése de plusieurs éléments de calcul en une large entité logique.
+-> Approche partitionné : Utilisation de CMP à grain grossier => Partitionnement de l'entité la plus large pour exploiter le parrallélisme à grain fin.
+
+Une architecture polymorphe ne va pas surpasser une architecture dédié, mais devrait bien se comporter avec un large spectre d'application.
+
+TRIPS -> Architecture polymorphique, approche partitionné combiné avec un coeur de processeur en grille à grain grossier et avec un système  mémoire on chip adaptatif.
+Objectif -> Avoir un coeur d'architecture qui peut aussi bien être très large que minuscule (scalable)
+
+Architecture TRIPS
+------------------
+Architecture orienté blocs.
+Un programme compilé pour le TRIPS est partitionné en bloc large d'instruction avec un seul point d'entrée, sans boucle et plusieurs point de sorties
+Les blocs valide de manière atomique et les intérruptions sont "blocs précis". (Plus de décision au point de vue instruction mais au point de vue bloc)
+
+Compilateur est résponsable de l'allocation statique de chaque bloc d'instruction dans le le système (Dépendance explicite).
+
+Une opération de flot usuel du proc : Chgt d'un boc depuis la mémoire, chgt dans le moteur de calcul, execution,  reporter les resultats dans la mémoire, chgt d'un autre bloc ...
+
+-> TRIPS est constitué de 4 blocs de 16 coeurs polymorphe. Une grille de 32Ko de mémoire connecter en quadrillage, des ctrl mémoires distribué pour connecter de la mémoire externe.
+-> Chaque blocs est constitué de d'un tableau de noeud d'execution, Il y a un ICACHE L1 par ligne dans la matrice , et une partie du banc de registre par colonne. Sur chaque ligne (droite) il y a également un DCACHE L1. En dessous de la matrice il y a le block de logique de ctrl qui s'occupe du séquencement de ce bloc et de la sélection du prochain bloc. Les caches L1 sont connecté au cache L2 a l'aide d'un interconnect.
+
+-> Chaque noeud d'execution contient une IU, FPU, des stations de réservations, un routeur de connections I/O, un noeud est directement connecter avec ses plus proches voisins, mais peut communiquer avec n'importe quel noeud dans la matrice
+-> Chaque stations de réservations stocke des isntructions et 2 opérandes sources.
+
+3 types principaux de ressources :
+ * hardcoded (ressources utilisées dans tous les mode et non modfiable) ex : interconnect, unité d'execution, cache L1
+ * ressources utilisé dans tous les modes et modifiable
+ * ressources non nécessaires dans tous les modes et pouvant être désactivés.
+
+Gestion du ILP : D-morph
+------------------------
+-> La configuration D-morph traite les buffers d'instructions comme un large, distribué fenêtre de lancement d'instructions. Possibilé d'avoir de l'execution our-of-order
+Le buffer d'instruction doit fournir une large bande passante de chargement d'instruction, un contrôle aggréssif et une spéculation sur les données, une mémoire à faible latence et qui préserve les accès mémoires de manière séquentiels
+
+Vue des buffers comme en trois dimension (x,y sont les coordonées physique dans un bloc et z correspond au nombre de place d'instructions dans chaque noeuds d'ALU.
+Le compilateur va découper le code en hyperblock (morceau de code communicant dans un graphe en 3D et dont il n'y à qu'un net de sortie.) Mappage de ces blocs dans des frames. (Différents slots de buffers sur le même noeuds d'alu). Les A-frame est la zone contenant tous les frame mappant un hyperblock.
+
+Spéculation de Multiblock : Les A-frames vide vont spéculativement chargé et executé un hyperblock. Les A-frames sont traités de manière circulaire : Le buffer de tête étant le moins spéculatif
+
+Instruction fetching -> pc pointe sur les têtes d'hyperblocks. Prédiction sur le prochain hyperblock (et non sur la prochaine instruction). Hyperblock sont codés du style VLIW.
+Interface mémoire : Entrelacement des bancs mémoires -> accès simultané a des adresses non conflictuelles.
+Mémoire secondaire configure le réseau de bank comme un cache à accès non uniform.
+
+Résumé : Prédiction  de fin assuré, grande bande passante pour l'ifecth, Dcache partitioné, execution concourente d'hyperblock (avec le réenvoie des valeur d'interbloc), le Dmorph est capable d'utiliser le buffer d'instrcution comme une fenêtre de lancement out of order
+
+Gestion du TLP : T-morph
+------------------------
+-> fournit un mappage un contrôle pour les multi thread.
+SMT -> cache et unité d'execution sont partagé.
+
+2 stratégies : 
+ - processeurs de lignes -> Partage la matrice d'ALU, en alloue une ou plusieurs lignes par threads. -> chaque thread à un nombre de  ICACHE et un DCACHE proportionnel au nombre de lignes alloué. Attention : La distance du banc de registre n'est pas uniforme (pénalise les lignes inférieurs)
+ - processeurs de frames -> Partage le processeur par un ensemble de frames
+
+|-> Les frames sont partagé entre thread. Un l'intérieur d'un thread, les frmae peuvent être spéculatif (cf D-morph)
+|-> T-morph maintient n PC et n historique de banc de registres
+
+Gestion du DLP : S-morph
+------------------------
+TRIPs est principalement prévut pour les flots multimédia et les calculs scientifiques => contient beaucoup de parrallélisme a niveau donnée
+
+-> fusion des Aframe pour un Super Aframe => Les boucles sont déroullées
+-> mapping reuse : un bloc est gardé dans les stations de réservations pour être utilisé plusieurs fois
+-> Dans les caches, ajout d'une fonctionnalité DMA
+@InProceedings{2004_chaudhuri,
+  author = 	 {Mainak Chaudhuri   and
+                  Mark Heinrich},
+  title = 	 {SMTp: An Architecture for Next-generation Scalable Multi-threading},
+  OPTcrossref =  {},
+  OPTkey = 	 {},
+  OPTbooktitle = {Proceedings of the 31st annual international symposium on Computer architecture},
+  OPTpages = 	 {124-136},
+  OPTyear = 	 {2004},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {0},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {München, Germany},
+  OPTmonth = 	 {},
+  OPTorganization = {},
+  OPTpublisher = {IEEE Computer Society},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+17/03/2005
+
+Modification d'uns SMT pour intégré un protocol de cohérence des threads afin de le placer dans un système à mémoire distribué (DSM).
+
+DSM sont scalable, mais s'ils n'utilisent pas de protocoles de snoop. Le directory based impose des structations de tableaux.
+
+Architecture
+------------
+
+Le processeur à une architecture classique :
+ 9 étages : fetch, decode, issue, lecture1, lecture2, exec, cache accès, commit
+fetch suit la politique ICOUNT (cf 1996\_tullsen)
+=> Il y a 2 threads. Tous est partagé sauf pile des adresses de retours, table de mappage, prédicteur dynamqiue
+
+Un noeud est séparé en deux parties :
+ - le coeur du proc
+ - le contrôlleur mémoire
+
+Le protocole de cohérence est lié à un thread. Celui-ci n'execute que cela (programme dédié donc n'est pas visible de l'extérieur). Il n'est pas aborder de solution dynamique (dès que la cohérence est nécessaire, un thread doit executer ce dernier)
+
+Afin d'éviter les deadlocks (applications tournants sur les threads et le threads gérant le protocole partagent les même ressources (file d'execution etc ...)), il y a des ressources dédié au threads executant le protocles des threads.
+
+Performance
+-----------
+3 limitations :
+- Le protocole de thread souffre de la latence du pipeline
+- Le nombre de registre entiers
+- Le DCACHE-L1 et les CACHE-L2 sont partagés entre les applications tounants sur les threads et le protocole de cohérences des threads
+
+
+@InProceedings{  2004_wang,
+  author = 	 {Nicholas J. Wang and
+		  Justin Quek      and
+                  Todd M. Rafacz   and 
+                  Sanjay J. Pate},
+  title = 	 {Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline},
+  OPTcrossref =  {In the Proceedings of the 2004 International Conference on Dependable Systems and Networks},
+  OPTkey = 	 {},
+  OPTbooktitle = {},
+  OPTpages = 	 {},
+  OPTyear = 	 {2004},
+  OPTeditor = 	 {},
+  OPTvolume = 	 {},
+  OPTnumber = 	 {},
+  OPTseries = 	 {},
+  OPTaddress = 	 {Florence , ITALY},
+  OPTmonth = 	 {june},
+  OPTorganization = {},
+  OPTpublisher = {},
+  OPTnote = 	 {},
+  OPTannote = 	 {}
+}
+
+30/11/2004
+
+Moins de 15 \% des corruptions binaires sont visibles du logiciel, des techniques simples d'overhead diminues de 75\% des fautes.
+
+D'ou viennent les fautes :
+ - Sources externe (pulsation electro magnétique)
+ - Sources interne (fuite, bruit da'alimentation ...)
+
+Pour caractériser ses fautes, ils ont définit un modèle de processeur :
+ - ISA alpha
+ - Superscalaire, ordonnacement dynamique (à 32 entrées)
+ - execution spéculative
+ - prédiction des dépendances mémoires
+ - 12 étages de pipelines
+ - 6 inst lancées/cycle
+
+4 types d'erreurs :
+ - Correspondances à un état de la micro architecture
+ - Arret prématuré de la tâche
+ - Corruption d'une donnée
+ - Rien sur le comportement
+
+85\% des fautes sont masqués
+ 3\% sont invisibles
+12\% réalise une execution erronée
+
+=> Les registres visibles sont les plus vulnérables
+
+Types d'erreurs dut à une execution erronnée :
+ - Inconsistence du banc de registres
+ - Inconsistence mémoire
+ - deadlock ou livelock
+ - Accès à une page virtuel invalide (Inst ou data)
+ - Part en exception
+ - Réalise une instruction non demandé
+ 
+Mécanisme de protection :
+ - Timeout => Evite les lock
+ - Code correcteur d'erreur => sur le banc de registres et sur le pointeur de ce banc (register renaming)
+ - Bit de parité => sur le registre IP (il traverse tous le pipeline)
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/root.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/root.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/root.tex	(revision 3)
@@ -0,0 +1,8 @@
+%\input{\dirroot/section_introduction.tex}
+%\input{\dirroot/section_nomenclature.tex}
+%\input{\dirroot/section_overview.tex}
+%\input{\dirroot/section_stage_ifetch.tex}
+\input{\dirroot/section_component_predictor.tex}
+%\input{\dirroot/section_stage_decod.tex}
+
+\bibliography{\dircommon/biblio}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_component_predictor.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_component_predictor.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_component_predictor.tex	(revision 3)
@@ -0,0 +1,89 @@
+\section{Composant : Unité de Prédictions}
+
+\subsection{Introduction}
+Tout commence par le ``Program Counter'' (PC). Il contient la prochaine adresse du programme. L'étage {\bf Ifetch} demande au cache un paquet d'instructions. Pour ce faire, il envoie au cache une adresse alignée sur une frontière de la taille d'un bloc de ligne du Icache. Ceci permet de n'avoir besoin que d'un seul port de lecture au cache par interface avec le Icache (sinon, un paquet d'instructions peut chevaucher 2 blocs). Le paquet retourné par le cache est stocké dans une file d'attente nommée {\it Ifetch queue}. 
+
+En parallèle, le PC est envoyé au prédicteur de branchement. Le rôle de ce dernier est triple :
+\begin{enumerate}
+\item déterminer la présence d'un branchement (le prochain paquet contient il branchement?)
+\item déterminer la destination du branchement
+\item déterminer la direction du branchement (Est ce que le mécanisme de génération de la prochaine adresse doit prendre l'adresse en séquence ou prendre l'adresse de destination du branchement)
+\end{enumerate}
+
+\subsection{Présence d'un branchement}
+
+Si on pose comme hypothèse que la section code d'un programme est en lecture seule, ceci implique que si le processeur décode un branchement à une adresse donnée, alors pour tous cycles, il y aura toujours le même branchement à cette même adresse. Ce principe est exploité dans les caches et ce base sur la localité temporelle (il y a de grande probabilité pour qu'un branchement soit réutilisé dans un avenir proche).
+
+Ce cache ce nomme couramment {\it Branch Target Buffer} (BTB) (\cite{1983_Lee}). La partie contrôle de ce cache sert à déterminer la présence d'un branchement : un hit/miss du BTB informe de la présence/absence d'un branchement. Avec les hypothèses données, un hit informe la présence d'un branchement, alors qu'un miss informe soit l'absence d'un branchement, ou un branchement mais jamais rencontré ou évincé car rarement utilisé. Ceci est une prédiction de la présence d'un branchement.
+
+Avec une adresse, le processeur demande un paquet d'instruction au cache. Il peut avoir plusieurs instructions par paquet et même plusieurs branchements par paquet. Interroger le BTB avec autant de requêtes que d'adresses possibles dans un paquet est coûteux en surface. La solution retenue ici est d'avoir une BTB associatif N voies où N est un multiple de la taille du paquet. Pour chaque voie du BTB, nous allons tester si l'adresse est contenue dans celle-ci, mais aussi nous devons comparer si l'offset de cette ligne de cache est supérieur ou égal à l'offset de l'adresse courante (nous pouvons avoir un branchement dans un paquet mais ce trouvant avant l'adresse courante.)
+
+%Enfin, en cas de plusieurs branchements, nous n'en sélectionnons qu'un seul (le premier séquentiellement) . Ceci implique que les structures permettant de choisir la direction et la destination n'aurons qu'un seul port de lecture.
+
+\printgraph{MORPHEO_component-prediction_unit-BTB}{0.8}{Branch Target Buffer - Partie Contrôle}
+
+\subsection{Destination}
+Déterminer la présence la présence d'un branchement n'est utile que si nous pouvons déterminer la destination. Nous pouvons regrouper les instructions de l'OpenRisc en trois groupes :
+\begin{enumerate}
+\item {\bf (l.bf, l.bnf, l.jal)} Ces instructions font un déplacement relatif par rapport au PC. Ce déplacement est contenus dans l'encodage de l'instruction. L'adresse de destination est donc fixe au cours du temps.
+\item {\bf (l.jr r!=LR, l.jalr)} Ces instructions réalisent un déplacement absolue. La destination est contenu dans un registre. Il est calculé pendant l'exécution du programme. Deux exécutions du programme avec un environnement différent ne donne pas les mêmes destinations de sauts. 
+\item {\bf (l.jr r=LR)} Ceci est un cas spécial du précèdent : les instructions l.jal et l.jalr sont des appels de procédure. Elle sauvegarde dans le registre {\it Link Register} (LR) l'adresse de retour du branchement. Donc l'instruction l.jr avec r = LR est un retour de procédure. Pour chaque appel de procédure il y a un retour de procédure.
+\end{enumerate}
+
+Pour le premier cas, l'adresse de destination étant donné par l'instruction de branchement et restera inchangée au cours du temps, nous pouvons l'enregistrer dans le BTB. Le numéro de voie fournit par la partie contrôle permet de sélectionner la bonne adresse de destination.
+
+Pour le deuxième cas, nous allons réutilisons l'adresse stocké dans le BTB. (Il y a donc 2 ports d'écritures pour mettre à jour l'adresse : le premier au moment de l'étage décode, le second au moment à l'étage commit. 
+
+Pour le troisième cas, nous nous référons au travaux de Kaeli et Emma (\cite{1991_kaeli} qui constatent que pour chaque appel de procédure, il y a un retour de procédure associé. Pour ce faire, nous utilisons une pile qui va stocker les adresses de retour des appels de procédure. Cette pile porte en général le nom de {\it Return Address Stack} (RAS). A chaque appel de procédure, nous allons empiler l'adresse de retour (PC + 8 (ne pas oublier le Delayed Slot)). Si la pile est pleine, la plus ancienne sera écraser. Dans le cadre d'un retour de procédure, nous dépilons alors le sommet de pile et sera l'adresse de retour. Si la pile est vide, le prédicteur de branchement informe l'étage {\it Ifetch} d'attendre de ne plus être spéculatif. Ceci est réaliser en informant que le prédicteur est occupé.
+
+Afin de sélectionner la bonne adresse de destination, nous devons connaître le type du branchement. Le type sera donc également enregistré dans la BTB.
+
+\printgraph{MORPHEO_component-prediction_unit-address}{0.8}{Génération de l'adresse}
+
+\subsection{Direction}
+
+Le troisième rôle d'un prédicteur de branchement est de déterminer si la partie génératrice d'adresse doit utiliser une adresse en séquence ou doit utiliser l'adresse fournit par le prédicteur de branchement. Pour ce faire, le type de l'instruction est importante : les sauts (l.j, l.jr, l.jal, l.jalr) vont toujours prendre alors que les branchements conditionnels (l.bf et l.bnf) vont dépendre de leur historique.
+
+Les articles \cite{1992_yeh}, \cite{1992_pan} et \cite{1993_yeh} définissent un schéma général des prédicteurs de branchements à deux niveaux. Selon les notations de \cite{1993_yeh}, le premier niveau appelé {\it Branch History Table} (BHT) est une table contenant des registres à décalage. Ces derniers représentent les $c$ derniers directions de branchements survenus. Le deuxième niveau est appelé {\it Pattern History Table} (PHT) qui est une table de compteur à saturation de $d$ bits. Ce compteur permet de sauvegarder le comportement des $2^d$ dernières occurrences. 
+
+\printgraph{MORPHEO_component-prediction_unit-predictor}{0.8}{Predicteur 2 niveaux généraliste}
+
+La figure \label{MORPHEO_component-prediction_unit-predictor} présente un prédicteur 2 niveaux généralistes. Par la suite les BHT et PHT sont considéré comme des structures à correspondance direct. Ceci permet d'économiser de la surface en ne rajoutant aucun Tag. De plus le gain est négligeable. Nous allons maintenant approfondir les deux blocs principaux du choix de la direction : la BHT et la PHT.
+
+\subsubsection{Branch History Table}
+
+Le premier niveau de prédiction contient $2^a$ registres à décalages. Ces registres contiennent les résultats des branchements de $c$ dernier branchement. La table est indexée par les $a$ bits les moins significatif de l'adresse du branchement. Selon la nomenclature de Yeh et Patt (\cite{1992_yeh}, \cite{1993_patt}), si $2^a=1$, alors il y a un seul historique pour tout les branchements, le BHT est dit Prédicteur Global (Global Branch History Register (GBHR) ). Sinon le Prédicteur est dit Local (Per address Branch History Table (PBHT) ). Il existe une troisième version, le Par ensemble (Per set Branch History Register (SBHT) ) mais dont les ensembles sont déterminées par le compilateur ou à partir de l'adresse du branchement, ou encore par un numéro de contexte.
+
+\subsubsection{Pattern History Table}
+
+Le second niveau du prédicteur contient $2^d$ compteur à saturation de $e$ bits (sature à $0$ en cas de décrémentation et à $2^e-1$ dans le cas d'une incrémentation). Le registre est incrémenter dans si le branchement est prit, et est décrémenté dans l'autre cas. Le bit le plus significatif indique la prédiction à prendre : 1 pour prendre, 0 pour continuer en séquence.
+Le bloc {\it index generator} va déterminer le compteur à choisir. Pour ce faire il prend les $b$ bits les moins significations de l'adresse ainsi que la sortie du BHT (soit $c$ bits) et va réaliser un ou exclusif sur l'intersection de ces deux adresses. Le tous revoie une valeur sur $d$ bits. Si l'intersection est nulle, on dit qu'il y a une sélection d'index (Predictor with Index Selection), sinon on dit que l'index est partagée (Predictor with Index Sharing).
+
+Avec la même nomenclature de la sous section précédente, si $2^b=1$, alors il y a un seul compteur par historique (Global Pattern History Table (GPHT) ). Sinon la structure est appelé Per-address Pattern History Table (SPHT) ou Per-set Pattern History Table (PPHT) suivant qu'il y a un pattern par branchement ou par ensemble de branchement. 
+
+Il existe un cas spécial : si le BHT n'existe pas ($c = 0$), alors il y a uniquement l'adresse qui indexe le PHT. Dans ce cas, le prédicteur est alors nommé {\bf Prédicteur bimodal}.
+
+\subsubsection{Intégration}
+
+Chaque prédicteur est efficace sur un type précis pattern. Par exemple les prédicteurs locaux sont performants pour les branchements qui exécute des patterns répétitifs (L'exemple le plus commun étant la boucle énumérée (for)), alors que les prédicteurs globaux sont efficaces pour par exemple des boucles imbriqués. 
+
+De cette constatation, McFarling \cite{1993_mcfarling} à conçut le prédicteur combiné (appelé également le méta prédicteur).  L'objectif de ce prédicteur est de tirer partie de plusieurs prédicteurs différent. Dans son concept général (voir figure \label{MORPHEO_component-prediction_unit-meta_predictor} ), il y a 3 prédicteurs. 2 qui vont prédire la direction à prendre, et le dernier qui va prédire quel prédicteur à le plus de chance d'avoir la bonne prédiction. Ce dernier prédicteur est mis à jour par rapport au succès de sa prédiction. Cette structure peut être récursive : un prédicteur appartenant au méta prédicteur peut lui-même être un méta prédicteur.
+\printgraph{MORPHEO_component-prediction_unit-meta_predictor}{0.8}{Méta prédicteur}
+
+Dans la version définit dans \cite{1993_mcfarling}, il s'agit d'un prédicteur bimodal qui va sélectionner entre un prédicteur global et un prédicteur local.
+
+\subsection{Mise à jour}
+
+Pour mettre à jour les predicteurs de branchements, il faut respecter les résultats des prédictions dans l'ordre de séquence du programme. En particulier pour les registres d'historiques. Fonctionnellement, ils imposent fortement la contrainte d'insertion dans l'ordre du programme. Il est à noter également que les prédictions qui sont effectuées dans le mauvais chemin de la prédiction ne doivent pas mettre à jour les prédicteurs.
+
+Dans un processeur à exécution dans le désordre ({\it Out Of Order}), le {\it Re Order Buffer} est la structure qui va permettre de valider les instructions dans l'ordre. Allons nous utiliser cette structure pour mettre à jour le prédicteur de branchement? Pour répondre à cette question, nous allons déterminer les informations nécessaires à sauvegarder pour la mise à jour.
+
+La BHT et la PHT contiennent un banc de registres, dont les registres sont gérés respectivement comme des registres à décalage ou des compteurs à saturation. Si nous souhaitons minimiser le nombre de ports pour ces bancs de registres, nous devons sauvegarder le contenu du registre (soit respectivement $c$ et $e$ bits). De plus pour mettre à jour le bon registre, il faut posséder l'index. Ce qui augmente de respectivement $a$ et $d$ bits. Or pour le PHT, la génération de l'adresse est en fonction de la sortie du BHT, donc au lieu de sauvegarder l'index complet, il suffit de sauvegarder la partie de l'adresse nécessaire dans ce calcul, soit $b$ bits. De plus, $a$ et $b$ sont les bits les moins significatifs de l'adresses. Nous avons juste besoin de l'union de cette deux champs. Finalement pour un prédicteur à 2 niveaux, il faut $max(a,b)+c+e$ bits pour le mettre à jour. 
+
+Comme le Re Order Buffer ne contient pas que des branchements, nous avons décider d'implémenter une table ne contenant que les branchements et qui ce nomme {\it Branch Update Table} (BUT). Elle est gérée de la même façon que le Re Order Buffer.
+
+%\subsection{Multi-Contexte}
+
+
+
+%\printgraph{MORPHEO_component-prediction_unit}{0.6}{Composant : Unité de Predictions}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_introduction.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_introduction.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_introduction.tex	(revision 3)
@@ -0,0 +1,5 @@
+\section*{Introduction}
+
+Dans ce document nous allons décrire de manière hierarchique le modèle de processeur Morpheo. Pour chacun des blocs, nous allons spécifier les différents paramètres pouvant influencer leur structure. Sur chacun des paramètres, nous allons définir une valeur minimal, maximal, un pas et enfin une valeur moyenne permettant de ce rapprocher au mieux d'un processeur commercial : l'intel Pentium 4 HyperThreading.
+
+Ce dernier fut choisit car il représente un bon exemple dans le domaine des processeurs multi-thread existant. De plus nous sommes relativement proche de sa microarchitecture.
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_nomenclature.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_nomenclature.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_nomenclature.tex	(revision 3)
@@ -0,0 +1,1 @@
+\section{Nomenclature}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_overview.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_overview.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_overview.tex	(revision 3)
@@ -0,0 +1,2 @@
+\section{Vue générale}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_stage_decod.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_stage_decod.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_stage_decod.tex	(revision 3)
@@ -0,0 +1,13 @@
+\section{Etage : Decodage}
+Cet étage à pour fonctionnalité de choisir une unique file d'instruction, et de définir les actions qui devra être réalisé par l'instruction. Les instructions de type branchements (non signalé comme tel par l'étage Ifetch), sont envoyées au prédicteur afin de prédire si ces derniers ne sont pas prit, sinon on stop le décodage. Tous les instructions sont placé dans une file ({\it decod\_queue}) en attendant d'être renommée.
+Cette étage s'occupe aussi des instructions de synchronisation : le modèle de consistance mémoire étant relachés, des instructions de synchronisation ont été définit. Tant que la condition de synchronisation n'est pas valide, le contexte incriminée ne peut pas être élu. L'automate {\it context\_state} va s'occuper des évenements qui ne permettent pas l'élection du thread (synchronisation, flush du pipeline du à un évenement (Exception, Miss de spéculation), accès à un registre spécial)
+
+\printgraph{MORPHEO_stage-decod}{0.8}{Etage : Decodage}
+
+\subsection*{Paramètres}
+\begin{description}
+\item[Largeur de la file :] (1/-/1/?)
+\item[Profondeur de la file :] (2/-/$2^n$/?)
+\item[Nombre d'instruction décodée :] (1/-/1/?)
+\end{description}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_stage_ifetch.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_stage_ifetch.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-morpheo-overview/fr/section_stage_ifetch.tex	(revision 3)
@@ -0,0 +1,13 @@
+\section{Etage : Instructions fetch}
+Cet étage à pour fonction de charger des paquets d'instructions qui vont allimenter le processeur.
+
+Cet étage contient le Program Counter ({\it PC}), qui va être envoyé au predicteur de branchement. Ce dernier retourne la prochaine addresse à demander au chache, et sera stocké dans le {\it PC} alors que la valeur courante est enregistré dans le registre {\it ICACHE\_ADDRESS}. Celui-ci va être envoyé par le cache. Au même instant que l'écriture dans ce registre, une case une file d'attente {\it IFETCH\_QUEUE} est alloué. Les reqûetes au cache sont découplé des réponses, cette technique permet de tirer partie d'un cache non bloquant : les reqûetes sont identifié par le couple \{Numéro de Contexte, Numéro d'entrée dans la file\}. Le Numéro de contexte sert à identifier le Thread émettrice de la requête et donc de pouvoir router la réponse vers la bonne file d'attente. Le deuxième identifiant permet d'indexer une requête particulier. Ceci nous permet d'avoir une unique requête avec ce couple à un instant donnée.
+
+\printgraph{MORPHEO_stage-ifetch}{0.8}{Etage : Instructions fetch}
+
+\subsection*{Paramètres}
+\begin{description}
+\item[Largeur de la file :] (1/-/1/?)
+\item[Profondeur de la file :] (2/-/$2^n$/?)
+\end{description}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-viewer-specification/common/syntax.xml
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-viewer-specification/common/syntax.xml	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-viewer-specification/common/syntax.xml	(revision 3)
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+
+<!-- comment -->
+
+<description>
+   <comment>
+      ...
+   </comment>
+   <entity name="..." 
+           type="..." >
+      <generic name="..." 
+               value="..."
+               min="..."
+               max="..."
+               step="..."
+               default="..."
+               level="..." />
+      <port    name="..."
+               localisation="..." />
+   </entity>
+   <architecture>
+      <component name="..."
+                 type="..."
+                 pos_x="..."
+                 size_x="..."
+                 pos_y="..."
+                 size_y="..." />
+         <port_map name="..."
+                   localisation="..."
+                   component="..."
+                   port="..." />
+      </component>
+   </architecture>
+<description>
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-viewer-specification/fr/root.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-viewer-specification/fr/root.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/document-viewer-specification/fr/root.tex	(revision 3)
@@ -0,0 +1,133 @@
+\Section{Introduction}
+
+L'outil \cpu est un générateur de processeurs hautement paramétrable. A partir d'un fichier de paramètres, cet outil va générer du VHDL synthétisable.
+
+L'outil \viewer permet d'avoir une vue graphique du processeur qui a été généré à partir du fichier de paramètres. 
+
+\Section{Interface}
+
+L'outil prend en entrée 2 informations :
+
+\begin{description}
+\item[name      : ] Nom du modèle ``Top Level''
+\item[directory : ] Localisation du modèle
+\end{description}
+
+La description d'une instance d'un processeur est fortement hiérarchique. A chaque composant du modèle correspond un fichier de configurations. Leur nom est formé comme suit : {\bf [directory]/[name\_father]\_[name\_component].xml}. Le top level n'ayant pas de père, son fichier aura le nom {\bf [directory]/[name].xml}.
+
+\subSection{Fichiers de configurations}
+Nous allons maintenant voir la syntaxe du fichier de configurations. Il ne faut pas confondre le fichier de paramètres qui est utilisé par l'outil \cpu et le fichier de configurations généré par l'outil \cpu et utilisé par l'outil \viewer.
+
+\verbatiminput{\dircommon/syntax.xml}
+
+\begin{description}
+\item[balise description : ] {\it obligatoire et unique} Balise englobante
+\end{description}
+\begin{description}
+\item[balise comment : ] {\it obligatoire et unique} Contient un descriptif du composant décrit.
+\end{description}
+\begin{description}
+\item[balise entity : ] {\it obligatoire et unique} Définition du composant courant
+  \begin{description}
+  \item[attribut name : ] nom d'instance du composant
+  \item[attribut type : ] nom du composant
+  \end{description}
+\end{description}
+\begin{description}
+\item[balise generic : ] {\it nombre quelconque d'occurrence} Paramètre du composant
+  \begin{description}
+  \item[attribut name    : ] Nom du paramètre
+  \item[attribut value   : ] Valeur actuelle du paramètre
+  \item[attribut min     : ] Valeur minimal du paramètre
+  \item[attribut max     : ] Valeur maximal du paramètre
+  \item[attribut step    : ] Pas entre deux valeurs de paramètres (par exemple +1 ou *2)
+  \item[attribut default : ] Valeur par défaut de ce paramètre
+  \item[attribut level   : ] Niveau requis pour que l'utilisateur puisse voir ce paramètre. Le niveau varie de 0 (paramètre jamais affiché) à 5 (affichage de presque aucun des paramètres (mode néophyte))
+  \item[attribut comment : ] Commentaire associé au paramètre
+  \end{description}
+\end{description}
+\begin{description}
+\item[balise port : ] {\it au moins 1 occurrence} Interface du composant. Une interface est un groupe de port cohérent entre eux. On peut par exemple cité l'interface Read et l'interface Write du composant fifo.
+  \begin{description}
+  \item[attribut name         : ] Nom de l'interface
+  \item[attribut localisation : ] Localisation de l'interface sur les bords du composant. Cet attribut peut prendre les valeur {\it North}, {\it South}, {\it East} et {\it West}. L'ordre des interfaces à une incidence. Ces dernières sont ordonnée suivant le sens horaire sur la face concerné. C'est à dire que sur la face Nord les interfaces seront placés de gauche à droite, face ouest de haut en base, face sud de droite à gauche et enfin face ouest de bas en haut.
+  \end{description}
+\end{description}
+\begin{description}
+\item[balise architecture : ] {\it 0 ou 1} 
+\end{description}
+\begin{description}
+\item[balise component : ] {\it nombre quelconque d'occurrences} Sous composant inclue dans le composant courant. Un composant est représenté par un rectangle. 
+  \begin{description}
+  \item[attribut name    : ] nom de l'instance du sous composant
+  \item[attribut type    : ] nom du sous composant
+  \item[attribut pos\_x0 : ] abscisse  du coin inférieur gauche
+  \item[attribut pos\_y0 : ] coordonne du coin supérieur droit 
+  \item[attribut pos\_x1 : ] abscisse  du coin inférieur gauche
+  \item[attribut pos\_y1 : ] coordonne du coin supérieur droit 
+  \end{description}
+\end{description}
+\begin{description}
+\item[balise port\_map : ] {\it au moins 1 occurrence} mapping entre les interfaces du sous composant et des autres sous composant ou du composant englobant.
+  \begin{description}
+  \item[attribut name         : ] nom de l'interface
+  \item[attribut localisation : ] localisation de l'interface sur les bords du sous-composant
+  \item[attribut component    : ] nom du composant avec lequel cet interface est inter-connectée
+  \item[attribut port         : ] nom de l'interface avec lequel cet interface est inter-connectée
+  \end{description}
+\end{description}
+
+\subSection{Sortie écran}
+
+La sortie écran est décomposée en 3 parties : 
+
+\begin{enumerate}
+  \item {\bf Barre de menu :} la barre de menu contient les entrées suivantes 
+    \begin{itemize}
+      \item Fichier
+	\begin{itemize}
+	  \item Ouvrir
+	  \item Sauvegarder
+	  \item Sauvegarder sous
+	  \item Quitter
+	\end{itemize}
+      \item Affichage
+	\begin{itemize}
+	  \item Afficher panneau latéral
+	  \item Afficher nom composants
+	  \item Afficher nom signaux
+	\end{itemize}
+      \item Outils
+	\begin{itemize}
+	  \item Zoom +
+	  \item Zoom -
+	  \item Zoom initial
+	  \item Niveau de configurations (1 à 5)
+	\end{itemize}
+      \item ?
+	\begin{itemize}
+	\item A propos
+	\end{itemize}
+    \end{itemize}
+  \item {\bf Panneau latéral : } le panneau latéral contient le nom et le type du composant actuelle. Ensuite une liste des paramètres du modèle (qui satisfont la condition niveau du paramètre >= niveau de configurations). Chaque survol d'un paramètre affiche un pop-up indiquant le commentaire associé à ce paramètre. Ensuite il affiche le commentaire associé à ce composant.
+  \item {\bf Fenêtre principal : } la fenêtre principal contient une vue schématique du composant. Sur chaque face d'un composant, les interfaces sont uniformément répartie. Les positions des paramètres son exprimé en pourcentage de la fenêtre principal. (c'est donc des coordonné proportionnelle où le point [0,0] est dans le coin inférieur gauche de cet fenêtre et le point [100,100] est dans le coin supérieur droit).
+\end{enumerate}
+
+\Section{Étape}
+
+\begin{enumerate}
+\item Prendre un fichier de configuration et afficher sont contenus
+\item Permettre à l'utilisateur de pouvoir naviguer dans la hiérarchie du composant.
+\item Affichage des Paramètres
+\item Modification des paramètres.
+\end{enumerate}
+
+Quelques fonctionnalités optionnels
+
+\begin{itemize}
+\item Raccourci clavier
+\item Zoom +/-/range
+\item Routage des fils intelligent.
+\item Analyse syntaxique du fichier de configuration
+\end{itemize}
+
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.dat
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.dat	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.dat	(revision 3)
@@ -0,0 +1,13 @@
+1.46 # x4-1\_1\_4-8
+2.37 # x4-1\_2\_2-8
+2.37 # x4-1\_2\_2-4
+2.94 # x4-1\_4\_1-8
+3.27 # x4-1\_4\_1-2
+2.51 # x4-2\_1\_2-8
+2.4  # x4-2\_1\_2-4
+3.38 # x4-2\_2\_1-8
+3.41 # x4-2\_2\_1-4
+3.63 # x4-2\_2\_1-2
+3.94 # x4-4\_1\_1-8
+3.88 # x4-4\_1\_1-4
+3.92 # x4-4\_1\_1-2
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.p
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.p	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_all.p	(revision 3)
@@ -0,0 +1,34 @@
+set size 1.0, 1.0
+set terminal postscript eps enhanced color
+
+set out "../Schema_eps/simulation_all.eps"
+
+unset label
+unset log
+
+set data style boxes
+set boxwidth 0.5
+set style fill solid 1.000000 border -1
+
+set grid
+set xlabel "Architecture"
+set ylabel "Speed Up MT/ST"
+set yrange [0:4]
+   
+set xtics rotate by -25 ('x4-1\_1\_4-8'  0 , \
+			 'x4-1\_2\_2-8'  1 , \
+			 'x4-1\_2\_2-4'  2 , \
+			 'x4-1\_4\_1-8'  3 , \
+			 'x4-1\_4\_1-2'  4 , \
+			 'x4-2\_1\_2-8'  5 , \
+			 'x4-2\_1\_2-4'  6 , \
+			 'x4-2\_2\_1-8'  7 , \
+			 'x4-2\_2\_1-4'  8 , \
+			 'x4-2\_2\_1-2'  9 , \
+			 'x4-4\_1\_1-8'  10, \
+			 'x4-4\_1\_1-4'  11, \
+			 'x4-4\_1\_1-2'  12  \
+			 )			   
+
+plot "simulation_all.dat" notitle
+     
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_occupation.dat
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_occupation.dat	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_occupation.dat	(revision 3)
@@ -0,0 +1,13 @@
+1.46 # x4-1\_1\_4-8
+2.37 # x4-1\_2\_2-8
+2.37 # x4-1\_2\_2-4
+2.94 # x4-1\_4\_1-8
+3.27 # x4-1\_4\_1-2
+2.51 # x4-2\_1\_2-8
+2.4  # x4-2\_1\_2-4
+3.38 # x4-2\_2\_1-8
+3.41 # x4-2\_2\_1-4
+3.63 # x4-2\_2\_1-2
+3.94 # x4-4\_1\_1-8
+3.88 # x4-4\_1\_1-4
+3.92 # x4-4\_1\_1-2 
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_occupation.p
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_occupation.p	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/simulation_occupation.p	(revision 3)
@@ -0,0 +1,34 @@
+set size 1.0, 1.0
+set terminal postscript eps enhanced color
+
+set out "../Schema_eps/simulation_all.eps"
+
+unset label
+unset log
+
+set data style boxes
+set boxwidth 0.5
+set style fill solid 1.000000 border -1
+
+set grid
+set xlabel "Architecture"
+set ylabel "Speed Up MT/ST"
+set yrange [0:4]
+   
+set xtics rotate by -25 ('x4-1\_1\_4-8'  0 , \
+			 'x4-1\_2\_2-8'  1 , \
+			 'x4-1\_2\_2-4'  2 , \
+			 'x4-1\_4\_1-8'  3 , \
+			 'x4-1\_4\_1-2'  4 , \
+			 'x4-2\_1\_2-8'  5 , \
+			 'x4-2\_1\_2-4'  6 , \
+			 'x4-2\_2\_1-8'  7 , \
+			 'x4-2\_2\_1-4'  8 , \
+			 'x4-2\_2\_1-2'  9 , \
+			 'x4-4\_1\_1-8'  10, \
+			 'x4-4\_1\_1-4'  11, \
+			 'x4-4\_1\_1-2'  12  \
+			 )			   
+
+plot "simulation_all.dat" notitle
+     
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.sed
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.sed	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.sed	(revision 3)
@@ -0,0 +1,41 @@
+\def\lang{@LANG}
+\def\file{@FILE}
+\def\dirschema{@DIRSCHEMA}
+\def\dirdoc{@DIRDOC}
+\def\dircommon{\dirdoc/common}
+\def\dirroot{\dirdoc/\lang}
+
+\include{Package/\file}
+
+% Package de variables d'environnement : Titre, command etc ...
+\usepackage{Include/doc-style}
+\usepackage{Package/\file}
+
+%------------------------------------------------------------------------------
+% Début document
+%------------------------------------------------------------------------------
+
+\pagestyle{empty}
+
+\begin{document}
+
+% Créez une page de titre
+\maketitle
+\thispagestyle{empty}
+
+%Table des matières et des figures
+%\tableofcontents
+%\newpage
+%\listoffigures
+
+%------------------------------------------------------------------------------
+% Ajout du corps du documents
+%------------------------------------------------------------------------------
+
+\input{\dirroot/root}
+
+%------------------------------------------------------------------------------
+% Fin d'ajout du corps du document
+%------------------------------------------------------------------------------
+
+\end{document}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.sty	(revision 3)
@@ -0,0 +1,12 @@
+\def\review{YYYY/MM/DD}
+%\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{}
+ 
+\author{}
+
+\affiliation{}
+
+\email{}
+
+\date{\review}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-file_source.tex	(revision 3)
@@ -0,0 +1,1 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty	(revision 3)
@@ -0,0 +1,189 @@
+\typeout{Fichier de style `doc-style.sty'.}
+
+\usepackage{makeidx}
+\usepackage{palatino}
+\usepackage{fancyheadings}
+\usepackage{float}
+\usepackage{verbatim}
+\usepackage{subfigure}
+\usepackage{wrapfig}
+\usepackage[dvips]{graphics}     
+\usepackage{graphicx}
+\usepackage[french]{babel}
+\usepackage[french]{minitoc}
+\usepackage[latin1]{inputenc}  % Pour utiliser les caractères accentués dans votre texte 
+\usepackage{openbib}
+
+\bibliographystyle{plain}
+
+
+
+% Titres de figures en 9 points helvetica gras
+% choisissez selon votre installation LaTeX
+\font\tenhv  = phvb at 8pt
+\font\tenhv  = phvb7t at 8pt
+
+% Fontes en 11 points gras pour les titres de deuxième niveau
+% \font\elvbf  = cmbx10 scaled 1100
+\font\elvbf  = ptmb scaled 1100
+
+% Dimensions des colonnes, espace entre colonnes, et indentation des
+% paragraphes 
+
+\setlength{\hoffset}{-18pt}  	
+\setlength{\oddsidemargin}{0pt} 	% Marge gauche sur pages impaires
+\setlength{\evensidemargin}{9pt} 	% Marge gauche sur pages paires
+\setlength{\topmargin}{0pt} 	% Pas de marge en haut
+\setlength{\marginparwidth}{54pt} 	% Largeur de note dans la marge
+\setlength{\textwidth}{481pt} 	% Largeur de la zone de texte (17cm)
+\setlength{\voffset}{-18pt} 	% Bon pour DOS
+\setlength{\marginparsep}{7pt} 	% Séparation de la marge
+\setlength{\headheight}{13pt} 	% Haut de page
+\setlength{\headsep}{10pt} 	% Entre le haut de page et le texte
+\setlength{\footskip}{27pt} 	% Bas de page + séparation
+\setlength{\textheight}{708pt} 	% Hauteur de la zone de texte (25cm)
+
+%%\setlength{\topsep}{0pt}%
+%%\setlength{\parsep}{0pt plus 1pt}%
+%\setlength{\columnsep}{10mm}
+%
+%\setlength{\parindent}{1pc}
+%\setlength{\listparindent}{\parindent}%
+%\setlength{\itemindent}{\parindent}%
+
+% Rappel: size10.clo
+
+% \normalsize{\@setfontsize\normalsize\@xpt\@xiipt} 
+% \small{\@setfontsize\small\@ixpt{11}}
+% \footnotesize{\@setfontsize\footnotesize\@viiipt{9.5}} 
+% \scriptsize{\@setfontsize\scriptsize\@viipt\@viiipt}
+% \tiny{\@setfontsize\tiny\@vpt\@vipt}
+% \large{\@setfontsize\large\@xiipt{14}} 
+% \Large{\@setfontsize\Large\@xivpt{18}} 
+% \LARGE{\@setfontsize\LARGE\@xviipt{22}} 
+% \huge{\@setfontsize\huge\@xxpt{25}}
+% \Huge{\@setfontsize\Huge\@xxvpt{30}}
+
+
+%% % file, Dimension, légende
+\newcommand{\printgraph}[3]
+ 	   {\begin{figure}[htbp]
+ 	       \centering
+ 	       \includegraphics[scale=#2]{\dirschema/#1.eps}
+ 	       \caption{#3}
+	       \label{#1}
+ 	     \end{figure}
+ 	   }
+
+\newcommand{\printgraphonly}[2]
+ 	   {\begin{figure}[htbp]
+ 	       \centering
+ 	       \includegraphics[scale=#2]{\dirschema/#1.eps}
+	       \label{#1}
+ 	     \end{figure}
+ 	   }
+	   
+\def\@maketitle
+   {
+   \newpage
+%   \null
+   \vskip 1cm
+   \begin{center}
+      {\Large \bf \@title \par} 
+      % Deux lignes vides après le titre
+      \vspace*{24pt} 
+      {
+      \large 
+      \lineskip .5em
+      \begin{tabular}[t]{c}
+         \@author 
+      \end{tabular}
+      \par
+      } 
+      % Un peu d'espace après le nom des auteurs
+      \vskip .5em 
+      {
+       \large 
+      \begin{tabular}[t]{c}
+         \@affiliation 
+      \end{tabular}
+      \par 
+      \ifx \@empty \@email
+      \else
+         \begin{tabular}{r@{~}l}
+            E-mail: & {\tt \@email}
+         \end{tabular}
+         \par
+      \fi
+      \begin{tabular}{r@{~}l}
+        {\tt \@date}
+      \end{tabular}
+      \par
+      }
+      % Une ligne vide après le bloc de titre
+      \vspace*{12pt} 
+   \end{center}
+   } 
+
+\def\abstract
+   {%
+   \centerline{\large\bf R\'esum\'e}%
+   \vspace*{12pt}%
+   \it%
+   }
+
+\def\endabstract
+   {
+   % Une ligne vide après le résumé
+   \vspace*{12pt} 
+   }
+
+% On traduit 'Référence'
+\renewcommand\refname{R\'ef\'erences}
+
+\def\affiliation#1{\gdef\@affiliation{#1}}
+\gdef\@affiliation{}
+
+\def\email#1{\gdef\@email{#1}}
+\gdef\@email{}
+
+\newlength{\@ctmp}
+\newlength{\@figindent}
+\setlength{\@figindent}{1pc}
+
+\long\def\@makecaption#1#2{
+   \vskip 10pt
+
+   \setbox\@tempboxa\hbox{\tenhv\noindent #1.~#2} 
+   \setlength{\@ctmp}{\hsize}
+   \addtolength{\@ctmp}{-\@figindent}\addtolength{\@ctmp}{-\@figindent} 
+   % SI c'est plus long qu'une ligne indentée
+   \ifdim \wd\@tempboxa >\@ctmp
+      % ALORS on définit un paragraphe indenté
+      \begin{list}{}{\leftmargin\@figindent \rightmargin\leftmargin} 
+         \item[]\tenhv #1.~#2\par
+      \end{list}
+   \else
+      % SINON centrer
+      \hbox to\hsize{\hfil\box\@tempboxa\hfil} 
+   \fi}
+
+% Type et espacement des en-têtes
+
+\def\section{\@startsection {section}{1}{\z@}
+   {14pt plus 2pt minus 2pt}{14pt plus 2pt minus 2pt} {\large\bf}} 
+\def\subsection{\@startsection {subsection}{2}{\z@}
+   {13pt plus 2pt minus 2pt}{13pt plus 2pt minus 2pt} {\elvbf}}
+
+\renewcommand\subsubsection{\@startsection {subsubsection}{1}{\z@}%
+        {12pt \@plus -1ex \@minus -.2ex}{-2mm}
+        {\reset@font\normalsize\bfseries}}
+% On ajoute un point après le numéro de section
+
+\newcommand{\Section}[1]{\section{\hskip -1em.~#1}} 
+\newcommand{\subSection}[1]{\subsection{\hskip -1em.~#1}}
+\newcommand{\subsubSection}[1]{\subsubsection{\hskip -1em.~#1}
+  \hskip -2mm.\hskip 2mm} 
+
+\def\registered{{\ooalign {\hfil\raise .05ex\hbox{\scriptsize
+R}\hfil\crcr\mathhexbox20D}}}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.sed
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.sed	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.sed	(revision 3)
@@ -0,0 +1,43 @@
+\documentclass{beamer}
+
+\def\lang{@LANG}
+\def\file{@FILE}
+\def\dirschema{@DIRSCHEMA}
+\def\dirdoc{@DIRDOC}
+\def\dircommon{\dirdoc/common}
+\def\dirroot{\dirdoc/\lang}
+
+
+% Package de variables d'environnement : Titre, command etc ...
+\usepackage{Include/ppt-style}
+\include{Package/\file}
+\usepackage{Package/\file}
+
+%------------------------------------------------------------------------------
+% Début document
+%------------------------------------------------------------------------------
+
+\begin{document}
+
+%Slide de Titre
+\frame{\titlepage}
+
+\section{Plan}
+
+\frame
+{
+  \tableofcontents
+}
+
+
+%------------------------------------------------------------------------------
+% Ajout du corps du documents
+%------------------------------------------------------------------------------
+
+\input{\dirroot/root}
+
+%------------------------------------------------------------------------------
+% Fin d'ajout du corps du document
+%------------------------------------------------------------------------------
+
+\end{document}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.sty	(revision 3)
@@ -0,0 +1,10 @@
+\def\review{YYYY/MM/DD}
+%\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{}
+
+\institute{}
+ 
+\author{}
+
+\date{\review}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-file_source.tex	(revision 3)
@@ -0,0 +1,3 @@
+\usepackage{beamerthemetree}
+
+\setbeameroption{show notes on second screen}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty	(revision 3)
@@ -0,0 +1,23 @@
+\typeout{Fichier de style `ppt-style.sty'.}
+
+\usepackage{graphicx}
+\usepackage{tabularx}
+\usepackage{verbatim}
+\usepackage{picinpar}
+\usepackage[latin1]{inputenc}
+\usepackage[french]{babel}
+\usepackage{pgf,pgfarrows,pgfheaps,pgfnodes,pgfpages,pgfshade}
+
+\usepackage{openbib}
+\bibliographystyle{plain}
+
+
+%% % file, Dimension
+\newcommand{\printgraph}[2]
+ 	   {\begin{figure}[htbp]
+ 	       \centering
+ 	       \includegraphics[scale=#2]{\dirschema/#1.eps}
+	       \label{#1}
+ 	     \end{figure}
+ 	   }
+	   
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/article-morpheo-share_architectural_ressources_between_hardware_context
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/article-morpheo-share_architectural_ressources_between_hardware_context	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/article-morpheo-share_architectural_ressources_between_hardware_context	(revision 3)
@@ -0,0 +1,1 @@
+fr
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-configuration_file_syntax
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-configuration_file_syntax	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-configuration_file_syntax	(revision 3)
@@ -0,0 +1,1 @@
+fr
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-methodology
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-methodology	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-methodology	(revision 3)
@@ -0,0 +1,1 @@
+fr
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-new_component
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-new_component	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-new_component	(revision 3)
@@ -0,0 +1,1 @@
+fr
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-overview
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-overview	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-morpheo-overview	(revision 3)
@@ -0,0 +1,1 @@
+fr
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-viewer-specification
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-viewer-specification	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Language/document-viewer-specification	(revision 3)
@@ -0,0 +1,1 @@
+fr
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile	(revision 3)
@@ -0,0 +1,477 @@
+#-------------------------------------------------------------------------------
+# Filename:    Makefile
+# Description: LaTeX compilation flow
+#-------------------------------------------------------------------------------
+
+#--------------------------------------------------------------------------------
+# User-defined options :
+#--------------------------------------------------------------------------------
+
+TYPE_DOC              	= ("doc" "ppt")
+
+DEFAULT_LANG		= fr
+FILE_SOURCE_SED  	= file_source.sed
+FILE_SOURCE_STY		= file_source.sty
+FILE_SOURCE_TEX		= file_source.tex
+
+#--------------------------------------------------------------------------------
+# Directory
+#--------------------------------------------------------------------------------
+VERSION			= "1.2" # 2007/02/21
+
+DIR_DOCUMENTATION   	= ..
+DIR_INCLUDE		= Include
+DIR_PACKAGE		= Package
+DIR_DOCUMENTS		= Documents
+DIR_LANGUAGE		= Language
+DIR_TYPE		= Type
+DIR_GRAPH		= Graph
+DIR_SCHEMA		= Schema
+DIR_SCHEMA_EPS		= Schema_eps
+DIR_SCHEMA_JPG		= Schema_jpg
+DIR_TEX			= Source
+
+#--------------------------------------------------------------------------------
+# File
+#--------------------------------------------------------------------------------
+
+ALL_FILES 		= $(wildcard $(DIR_TYPE)/*)
+
+TEX_FILES 		= $(wildcard $(DIR_TEX)/*.tex)
+FILES     		= $(patsubst $(DIR_TEX)/%.tex,%    ,$(TEX_FILES))
+DVI_FILES	 	= $(patsubst $(DIR_TEX)/%.tex,%.dvi,$(TEX_FILES))
+PS_FILES  		= $(patsubst $(DIR_TEX)/%.tex,%.ps ,$(TEX_FILES))
+PDF_FILES 		= $(patsubst $(DIR_TEX)/%.tex,%.pdf,$(TEX_FILES))
+EPS_FILES		= $(patsubst $(DIR_GRAPH)/%.p,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_GRAPH)/*.p))		\
+			  $(patsubst $(DIR_SCHEMA)/%.fig,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_SCHEMA)/*.fig))	\
+			  $(patsubst $(DIR_SCHEMA)/%.eps,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_SCHEMA)/*.eps))
+
+#--------------------------------------------------------------------------------
+# User-defined variables:
+#--------------------------------------------------------------------------------
+# Usual commands
+ECHO			= echo
+RM			= rm -fr
+BASENAME		= basename
+CAT			= cat
+EXIT			= exit
+SED			= sed
+TOUCH			= touch
+CP			= cp
+MV			= mv
+CD			= cd
+LS			= ls
+GREP			= grep
+TEST			= test
+MKDIR			= mkdir -p
+READ			= read
+MAKE			= make -s
+PWD			= `pwd`
+# Commands to generate all documents
+FIG2EPS			= fig2dev -L eps
+EPS2JPG			= convert -quality 100
+LATEX     		= latex
+BIBTEX    		= bibtex
+MAKEINDEX 		= makeindex
+DVIPS			= dvips -Ppdf
+PS2PDF			= ps2pdf
+GNUPLOT			= gnuplot
+# Commdans to view the document
+VIEWDVI			= xdvi
+VIEWPS 			= gv  
+VIEWPDF			= xpdf
+
+#--------------------------------------------------------------------------------
+# The reset of this file shall not be editted
+#--------------------------------------------------------------------------------
+.PHONY 			: all clean view help doc doc_all new delete
+.SECONDARY 		: $(DVI_FILES) $(PS_FILES) $(PDF_FILES) $(EPS_FILES) $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_JPG)
+
+all 			: help
+
+doc			: $(DIR_TEX)  $(EPS_FILES) 
+			@											\
+			for file in $(ALL_FILES); do                                				\
+				file=`$(BASENAME) $$file`;							\
+				type=`$(CAT) $(DIR_TYPE)/$$file`;						\
+						           		                			\
+				for lang in `$(CAT) $(DIR_LANGUAGE)/$$file`; do                        		\
+					if $(TEST) ! -f "$(DIR_TEX)/$$file-$$lang.tex"; then			\
+			                        $(ECHO) "s/@LANG/$$lang/"                     >  $$$$;          \
+			                        $(ECHO) "s/@FILE/$$file/"                     >> $$$$;          \
+			                        $(ECHO) "s/@DIRDOC/$(DIR_DOCUMENTS)\/$$file/" >> $$$$;        	\
+			                        $(ECHO) "s/@DIRSCHEMA/$(DIR_SCHEMA_EPS)/"     >> $$$$;        	\
+		        	                $(CAT) $(DIR_INCLUDE)/$$type-$(FILE_SOURCE_SED) | $(SED) -f $$$$ > $(DIR_TEX)/$$file-$$lang.tex; \
+						$(RM)   $$$$;                                        		\
+					fi;									\
+				done;										\
+			done;                                       		                	
+			@$(MAKE) doc_all
+
+doc_all			: $(PDF_FILES)
+
+#--------------------------------------------------------------------------------
+# Generation of the formatted text:
+# regular flow tex -> dvi -> ps -> pdf.
+#--------------------------------------------------------------------------------
+%.pdf 			: %.ps
+			@$(ECHO) "Génération du fichier $*.pdf"
+			@$(PS2PDF) $< $@
+			@$(CP) $@ $(DIR_DOCUMENTATION)
+
+%.ps 			: %.dvi
+			@$(ECHO) "Génération du fichier $*.ps"
+			@$(DVIPS) -o $@ $<
+
+%.dvi 			: $(DIR_TEX)/%.tex
+			@$(ECHO) "Génération du fichier $*.dvi"
+			@#touch $(patsubst %.tex,%.ind,$<)
+			@$(LATEX) $<
+			@$(LATEX) $< > /dev/null
+			@#$(MAKEINDEX) $(patsubst %.tex,%.idx,$<)
+			@citation=`$(GREP) "citation" $*.aux`; \
+	                 if $(TEST) -n "$$citation" ; then  \
+			  $(BIBTEX) $* ; \
+			fi
+			@$(LATEX) $< > /dev/null
+			@$(LATEX) $< > /dev/null
+
+#--------------------------------------------------------------------------------
+# New - Delete - Rename
+#--------------------------------------------------------------------------------
+new			:
+			@											\
+			$(ECHO) "";                       			                		\
+			$(ECHO) "Choose a type of a document    : (0 is	default)";				\
+			CPT=0;                                      		                		\
+			declare -a type_doc=$(TYPE_DOC);							\
+			for type in $${type_doc[@]}; do                                  			\
+				$(ECHO) "$$CPT) $$type";                     		                	\
+				CPT=$$(($$CPT+1));                  		                		\
+			done;                                       		                		\
+			declare -i NUM_TYPE;									\
+			$(READ) NUM_TYPE;			    		                		\
+														\
+			if $(TEST) "$$NUM_TYPE" -ge "$$CPT"; then                               		\
+				NUM_TYPE=0;                                  		        		\
+			fi;											\
+			declare    TYPE=$${type_doc[$$NUM_TYPE]};						\
+														\
+			declare    FILENAME;									\
+			$(ECHO) "";                       			                		\
+			$(ECHO) "Give the name of the documents :";						\
+			$(READ) FILENAME;									\
+														\
+			if $(TEST) -z "$$FILENAME" -o -d "$(DIR_TYPE)/$$FILENAME";				\
+			then											\
+				$(ECHO) "Invalid name : string is empty, or filename is already used";		\
+				$(EXIT);									\
+			fi;											\
+														\
+			$(ECHO) "Create file      : $(DIR_LANGUAGE)/$$FILENAME";                 		\
+			$(ECHO) "                   (Default language : $(DEFAULT_LANG))";			\
+			$(ECHO) "$(DEFAULT_LANG)" > $(DIR_LANGUAGE)/$$FILENAME;                  		\
+														\
+			$(ECHO) "Create file      : $(DIR_TYPE)/$$FILENAME";                    		\
+			$(ECHO) $$TYPE > $(DIR_TYPE)/$$FILENAME;						\
+														\
+			$(ECHO) "Create file      : $(DIR_PACKAGE)/$$FILENAME.sty";                    		\
+			$(CP) $(DIR_INCLUDE)/$$TYPE-$(FILE_SOURCE_STY) $(DIR_PACKAGE)/$$FILENAME.sty;		\
+														\
+			$(ECHO) "Create file      : $(DIR_PACKAGE)/$$FILENAME.tex";                    		\
+			$(CP) $(DIR_INCLUDE)/$$TYPE-$(FILE_SOURCE_TEX) $(DIR_PACKAGE)/$$FILENAME.tex;		\
+														\
+			$(ECHO) "Create directory : $(DIR_DOCUMENTS)/$$FILENAME";                    		\
+			$(ECHO) "Create directory : $(DIR_DOCUMENTS)/$$FILENAME/common";              		\
+			$(ECHO) "Create directory : $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG)"; 		\
+			$(MKDIR) $(DIR_DOCUMENTS)/$$FILENAME/common;						\
+			$(MKDIR) $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG);					\
+														\
+			$(ECHO) "Create file      : $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG)/root.tex"; 	\
+			$(TOUCH) $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG)/root.tex
+
+delete			:
+			@											\
+			declare -a FILES;									\
+			declare -i CPT;         								\
+			declare -i NUM_FILE;									\
+			declare -i NUM_FILE_CONFIRM;								\
+														\
+			$(ECHO) "";                       			                		\
+			$(ECHO) "Choose a document  : (0 by default)";		                		\
+			$(ECHO) "0) ( none )";                               	                		\
+														\
+			CPT=1;                                      		                		\
+			for files in $(ALL_FILES); do                                  				\
+				files=`$(BASENAME) $$files`;                     				\
+				$(ECHO) "$$CPT) $$files";           		                		\
+				FILES[$$CPT]=$$files;				                		\
+				CPT=$$(($$CPT+1));                  		                		\
+			done;                                       		                		\
+			$(READ) NUM_FILE;			    		                		\
+														\
+			if $(TEST) "$$NUM_FILE" -ge "$$CPT"; then                               		\
+				NUM_FILE=0;                                  		        		\
+			fi;											\
+														\
+			$(ECHO) "Please reenter the document id to confirm the delete";         		\
+			$(READ) NUM_FILE_CONFIRM;		    		                		\
+														\
+			if $(TEST) "$$NUM_FILE" -eq "0" -o "$$NUM_FILE" -ne "$$NUM_FILE_CONFIRM"; then          \
+				$(ECHO) "Delete cancelled";							\
+				$(EXIT);                                       		        		\
+			fi;											\
+														\
+			declare    FILENAME;									\
+			FILENAME=$${FILES[$$NUM_FILE]};					      			\
+														\
+			$(ECHO) "Delete file      : $(DIR_TYPE)/$$FILENAME";                   			\
+			$(RM) $(DIR_TYPE)/$$FILENAME;                 						\
+														\
+			$(ECHO) "Delete file      : $(DIR_LANGUAGE)/$$FILENAME";                   		\
+			$(RM) $(DIR_LANGUAGE)/$$FILENAME;                 					\
+														\
+			$(ECHO) "Delete file      : $(DIR_PACKAGE)/$$FILENAME.sty";                    		\
+			$(RM) $(DIR_PACKAGE)/$$FILENAME.sty;							\
+														\
+			$(ECHO) "Delete file      : $(DIR_PACKAGE)/$$FILENAME.tex";                    		\
+			$(RM) $(DIR_PACKAGE)/$$FILENAME.tex;							\
+														\
+			$(ECHO) "Delete directory : $(DIR_DOCUMENTS)/$$FILENAME";                    		\
+			$(RM) $(DIR_DOCUMENTS)/$$FILENAME;
+
+rename			:
+			@											\
+			declare -a FILES;									\
+			declare -i CPT;         								\
+			declare -i NUM_FILE;									\
+														\
+			$(ECHO) "";                       			                		\
+			$(ECHO) "Choose a document  : (0 by default)";		                		\
+			$(ECHO) "0) ( none )";                               	                		\
+														\
+			CPT=1;                                      		                		\
+			for files in $(ALL_FILES); do                                  				\
+				files=`$(BASENAME) $$files`;                   					\
+				$(ECHO) "$$CPT) $$files";           		                		\
+				FILES[$$CPT]=$$files;				                		\
+				CPT=$$(($$CPT+1));                  		                		\
+			done;                                       		                		\
+			$(READ) NUM_FILE;			    		                		\
+														\
+			if $(TEST) "$$NUM_FILE" -ge "$$CPT"; then                               		\
+				NUM_FILE=0;                                  		        		\
+			fi;											\
+														\
+			if $(TEST) "$$NUM_FILE" -eq "0"; then              					\
+				$(ECHO) "Rename cancelled";							\
+				$(EXIT);                                       		        		\
+			fi;											\
+														\
+			declare    FILENAME_SRC;								\
+			declare    FILENAME_DEST;								\
+			FILENAME_SRC=$${FILES[$$NUM_FILE]};					      		\
+														\
+			$(ECHO) "Give the new name of the documents :";						\
+			$(READ) FILENAME_DEST;									\
+														\
+			if $(TEST) -z "$$FILENAME_DEST" -o -d "$(DIR_TYPE)/$$FILENAME_DEST";			\
+			then											\
+				$(ECHO) "Invalid name : string is empty, or filename is already used";		\
+				$(EXIT);									\
+			fi;											\
+														\
+			$(ECHO) "Rename file      : $(DIR_LANGUAGE)/$$FILENAME_SRC";                 		\
+			$(MV) $(DIR_LANGUAGE)/$$FILENAME_SRC    $(DIR_LANGUAGE)/$$FILENAME_DEST;               	\
+														\
+			$(ECHO) "Rename file      : $(DIR_TYPE)/$$FILENAME_SRC";                 		\
+			$(MV) $(DIR_TYPE)/$$FILENAME_SRC        $(DIR_TYPE)/$$FILENAME_DEST;               	\
+														\
+			$(ECHO) "Rename file      : $(DIR_PACKAGE)/$$FILENAME_SRC.sty";                    	\
+			$(MV) $(DIR_PACKAGE)/$$FILENAME_SRC.sty $(DIR_PACKAGE)/$$FILENAME_DEST.sty;		\
+														\
+			$(ECHO) "Rename directory : $(DIR_DOCUMENTS)/$$FILENAME_SRC";                    	\
+			$(MV) $(DIR_DOCUMENTS)/$$FILENAME_SRC   $(DIR_DOCUMENTS)/$$FILENAME_DEST;
+
+#--------------------------------------------------------------------------------
+# View
+#--------------------------------------------------------------------------------
+view			: doc
+			@                                           		                		\
+			declare    SELECT_FILE;									\
+			declare    SELECT_LANG;									\
+			declare    SELECT_FORMAT;								\
+			declare    SELECT_VIEWER;								\
+														\
+														\
+														\
+			$(ECHO) "";                       			                		\
+			$(ECHO) "Choose a document  : (0 by default)";		                		\
+														\
+			declare -i CPT;         								\
+			declare -i NUM_FILE;									\
+			declare -a FILES;									\
+														\
+			CPT=0;                                      		                		\
+			for files in $(ALL_FILES); do                                  				\
+				files=`$(BASENAME) $$files`;                   					\
+				type=`$(CAT) $(DIR_TYPE)/$$files`;						\
+				$(ECHO) "$$CPT) $$type - $$files";           		                	\
+				FILES[$$CPT]=$$files;				                		\
+				CPT=$$(($$CPT+1));                  		                		\
+			done;                                       		                		\
+			$(READ) NUM_FILE;			    		                		\
+														\
+			if $(TEST) "$$NUM_FILE" -ge "$$CPT"; then                               		\
+				NUM_FILE=0;                                  		        		\
+			fi;											\
+														\
+			SELECT_FILE=$${FILES[$$NUM_FILE]};							\
+			$(ECHO) "Document selected  : $$SELECT_FILE";                           		\
+			$(ECHO) "";                                 		                		\
+														\
+														\
+														\
+			$(ECHO) "Choose a language  : (0 by default)";	                        		\
+														\
+			declare -i NUM_LANG;									\
+			declare -a LANG;      									\
+														\
+			CPT=0;						                        		\
+			for lang in `$(CAT) $(DIR_LANGUAGE)/$$SELECT_FILE`; do					\
+			    	$(ECHO) "$$CPT) $$lang";				                	\
+				LANG[$$CPT]=$$lang;				                		\
+				CPT=$$(($$CPT+1));				                        	\
+			done;						                        		\
+			$(READ) NUM_LANG;			    	                        		\
+														\
+			if $(TEST) "$$NUM_LANG" -ge "$$CPT"; then                             			\
+				NUM_LANG=0;	 			                        		\
+			fi;						                        		\
+														\
+			SELECT_LANG=$${LANG[$$NUM_LANG]};							\
+			$(ECHO) "Language selected  : $$SELECT_LANG";                       			\
+			$(ECHO) "";                                 		                		\
+														\
+														\
+														\
+			$(ECHO) "Choose a format    : (0 by default)";	                        		\
+														\
+			declare -i NUM_FORMAT;									\
+			declare -a FORMAT;      								\
+			declare -a VIEWER;      								\
+														\
+			FORMAT=("pdf"      "ps"      "dvi");		                        		\
+			VIEWER=($(VIEWPDF) $(VIEWPS) $(VIEWDVI));	                        		\
+														\
+			CPT=0;						                        		\
+			while [ $$CPT -lt $${#FORMAT[*]} ]; do		                        		\
+			    $(ECHO) "$$CPT) "$${FORMAT[$$CPT]};		                        		\
+			    CPT=$$(($$CPT+1));				                        		\
+			done;						                        		\
+			$(READ) NUM_FORMAT;			    	                        		\
+														\
+			if $(TEST) "$$NUM_FORMAT" -ge "$$CPT"; then                             		\
+				NUM_FORMAT=0;	 			                        		\
+			fi;						                        		\
+														\
+			SELECT_FORMAT=$${FORMAT[$$NUM_FORMAT]};							\
+			SELECT_VIEWER=$${VIEWER[$$NUM_FORMAT]};							\
+			$(ECHO) "Format selected    : $$SELECT_FORMAT";                         		\
+			$(ECHO) "";                                 		                		\
+														\
+														\
+														\
+			$$SELECT_VIEWER "$$SELECT_FILE-$$SELECT_LANG.$$SELECT_FORMAT" &                		\
+														\
+			$(ECHO) "";
+
+#--------------------------------------------------------------------------------
+# The figures directory
+#--------------------------------------------------------------------------------
+$(DIR_SCHEMA_EPS)	:
+			@$(ECHO) "Make directory       : $@"
+			@$(MKDIR) $@
+
+$(DIR_SCHEMA_JPG)	:
+			@$(ECHO) "Make directory       : $@"
+			@$(MKDIR) $@
+
+$(DIR_TEX)       	:
+			@$(ECHO) "Make directory       : $@"
+			@$(MKDIR) $@
+
+$(DIR_SCHEMA_EPS)/%.eps	: $(DIR_SCHEMA)/%.eps $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_JPG)
+			@$(ECHO) "Generate   files     : $*.eps"
+			@$(CP) $(DIR_SCHEMA)/$*.eps $(DIR_SCHEMA_EPS)
+			@$(EPS2JPG) $@ $(DIR_SCHEMA_JPG)/$*.jpg
+
+$(DIR_SCHEMA_EPS)/%.eps	: $(DIR_SCHEMA)/%.fig $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_JPG)
+			@$(ECHO) "Generate   files     : $*.eps"
+			@$(FIG2EPS) $< $@
+			@$(EPS2JPG) $@ $(DIR_SCHEMA_JPG)/$*.jpg
+
+$(DIR_SCHEMA_EPS)/%.eps	: $(DIR_GRAPH)/%.p    $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_JPG)
+			@$(ECHO) "Generate   files     : $*.eps"
+			@$(CD) $(DIR_GRAPH); $(GNUPLOT) $*.p
+			@$(EPS2JPG) $@ $(DIR_SCHEMA_JPG)/$*.jpg
+
+#--------------------------------------------------------------------------------
+# Cleaning
+#--------------------------------------------------------------------------------
+
+clean			:
+			@$(ECHO) "Delete     temporary files              "$(PWD)
+			@$(RM) $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_JPG)  $(DIR_TEX) $(DIR_PACKAGE)/*.aux
+			@$(RM) $(DVI_FILES) $(PS_FILES) $(PDF_FILES)
+			@$(MAKE) clean_rec DIR_CLEAN=.  
+
+#Clean recursive
+clean_rec		:
+			@$(ECHO) "Delete     temporary files in directory $(DIR_CLEAN)"
+			@$(RM)	$(DIR_CLEAN)/*~ 		\
+				$(DIR_CLEAN)/*.aux  		\
+				$(DIR_CLEAN)/*.bbl  		\
+				$(DIR_CLEAN)/*.blg  		\
+				$(DIR_CLEAN)/*.bmt  		\
+				$(DIR_CLEAN)/*.log  		\
+				$(DIR_CLEAN)/*.mtc* 		\
+				$(DIR_CLEAN)/*.toc  		\
+				$(DIR_CLEAN)/*.idx  		\
+				$(DIR_CLEAN)/*.ilg  		\
+				$(DIR_CLEAN)/*.ind  		\
+				$(DIR_CLEAN)/*.out  		\
+				$(DIR_CLEAN)/*.nav  		\
+				$(DIR_CLEAN)/*.snm  		\
+				$(DIR_CLEAN)/missfont.log
+			@# The .bbl file is to be removed if "bibtex" is used.
+			@for files in `$(LS) $(DIR_CLEAN)`; do                              			\
+				if $(TEST) -d $(DIR_CLEAN)/$$files;                         			\
+				then                                                        			\
+					$(MAKE) clean_rec DIR_CLEAN=$(DIR_CLEAN)/$$files;   			\
+				fi;                                                         			\
+			done;
+
+clean_all		: clean
+			@$(ECHO) "Delete     temporary files (all)"
+			@$(RM) $(DIR_DOCUMENTATION)/*.pdf
+
+#--------------------------------------------------------------------------------
+# Help
+#--------------------------------------------------------------------------------
+
+help			:
+			@$(ECHO) "Environnement to generate documents and presentations"
+			@$(ECHO) "Version         : $(VERSION)"
+			@$(ECHO) ""
+			@$(ECHO) "List of rules   :"
+			@$(ECHO) " * all          : Cf rules \"help\""
+			@$(ECHO) " * clean        : Erase generate files"
+			@$(ECHO) " * clean_all    : Erase all generate files"
+			@$(ECHO) " * delete       : Erase all file and directory of a document"
+			@$(ECHO) " * doc          : Generate all documents"
+			@$(ECHO) " * help         : Print this message"
+			@$(ECHO) " * new          : Create all file and directy for a new document"
+			@$(ECHO) " * rename       : Rename a document"
+			@$(ECHO) " * view         : List all document to view"
+			@$(ECHO) ""
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/article-morpheo-share_architectural_ressources_between_hardware_context.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/article-morpheo-share_architectural_ressources_between_hardware_context.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/article-morpheo-share_architectural_ressources_between_hardware_context.sty	(revision 3)
@@ -0,0 +1,12 @@
+\def\review{2007/01/16}
+%\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{Incidence du partage des ressources architecturales entre les contextes matériels}
+
+\author{Mathieu Rosière}
+
+\affiliation{Equipe SOC - Laboratoire d'information de Paris VI - France}
+
+\email{mathieu.rosiere@lip6.fr}
+
+\date{\review}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/article-morpheo-share_architectural_ressources_between_hardware_context.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/article-morpheo-share_architectural_ressources_between_hardware_context.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/article-morpheo-share_architectural_ressources_between_hardware_context.tex	(revision 3)
@@ -0,0 +1,1 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-configuration_file_syntax.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-configuration_file_syntax.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-configuration_file_syntax.sty	(revision 3)
@@ -0,0 +1,11 @@
+\def\review{2006/10/27}
+
+\title{Configuration file syntax}
+ 
+\author{Mathieu Rosière}
+
+\affiliation{Laboratoire d'Informatique de Paris VI - Equipe SOC - France}
+
+\email{mathieu.rosiere{at}lip6.fr}
+
+\date{\review}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-configuration_file_syntax.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-configuration_file_syntax.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-configuration_file_syntax.tex	(revision 3)
@@ -0,0 +1,1 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-methodology.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-methodology.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-methodology.sty	(revision 3)
@@ -0,0 +1,12 @@
+\def\review{YYYY/MM/DD}
+%\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{Morpheo's Methodology}
+ 
+\author{Mathieu Rosière}
+
+\affiliation{Laboratoire d'Informatique de Paris VI - Equipe SOC - France}
+
+\email{mathieu.rosiere@lip6.fr}
+
+\date{\review}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-methodology.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-methodology.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-methodology.tex	(revision 3)
@@ -0,0 +1,1 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-new_component.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-new_component.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-new_component.sty	(revision 3)
@@ -0,0 +1,12 @@
+\def\review{2007/01/08}
+%\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{New Component}
+ 
+\author{Mathieu Rosière}
+
+\affiliation{Laboratoire d'Informatique de Paris VI - Equipe SOC - France}
+
+\email{mathieu.rosiere@lip6.fr}
+
+\date{\review}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-new_component.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-new_component.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-new_component.tex	(revision 3)
@@ -0,0 +1,1 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-overview.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-overview.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-overview.sty	(revision 3)
@@ -0,0 +1,12 @@
+%\def\review{2006/11/17}
+\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{Morpheo's Overview}
+ 
+\author{Mathieu Rosière}
+
+\affiliation{Laboratoire d'Informatique de Paris VI - Equipe SOC - France}
+
+\email{mathieu.rosiere@lip6.fr}
+
+\date{\review}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-overview.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-overview.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-morpheo-overview.tex	(revision 3)
@@ -0,0 +1,1 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-viewer-specification.sty
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-viewer-specification.sty	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-viewer-specification.sty	(revision 3)
@@ -0,0 +1,16 @@
+
+\def\viewer{Viewer~}
+\def\cpu{Morpheo~}
+
+\def\review{2007/02/21}
+%\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{\viewer : Spécification}
+ 
+\author{Philippe Chou, Michaël Lafaye, Mathieu Rosière}
+
+\affiliation{Laboratoire d'Informatique de Paris VI - Equipe SOC - France}
+
+%\email{mathieu.rosiere{at}lip6.fr}
+
+%\date{\review}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-viewer-specification.tex
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-viewer-specification.tex	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Package/document-viewer-specification.tex	(revision 3)
@@ -0,0 +1,1 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/README
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/README	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/README	(revision 3)
@@ -0,0 +1,29 @@
+--------------------------------------------------
+ Table of contents
+--------------------------------------------------
+
+I   - Guide to create a new Document
+
+--------------------------------------------------
+ I   - Guide to create a new Document
+--------------------------------------------------
+
+To create a new document, you can follow this step :
+
+1) Choose a Name to the document (for the next step, we use the name : "name_of_document")
+
+2) In directory <Type>, create the file "name_of_document". Inside, write the type of document ("ppt" for a presentation or "doc" for a document (Type is defined in the head of Makefile))
+
+3) In directory <Language>, create the file "name_of_document". Inside, enumarate the supported language (by example, "fr" and "en")
+
+4) In directory <Package>, create the file "name_of_document.sty" (or copy the file "Include/file_source.sty"). Give the information of review, title (same for each language), author, and author's email.
+
+5) In directory <Documents>, create a directory "name_of_document". Inside, create directory "common" (to stock all document independant of language) and a directory for each language enumerated in step 2. Inside, you must create a file "root.tex", it contend the root of you document. 
+(in your exemple we are :
+<Documents>/name_of_document/
+<Documents>/name_of_document/common/
+<Documents>/name_of_document/en/root.tex
+<Documents>/name_of_document/fr/root.tex
+)
+
+6) All schema (.fig) can be stock in the directory <Schema>
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_Tools_Chain.fig
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_Tools_Chain.fig	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_Tools_Chain.fig	(revision 3)
@@ -0,0 +1,112 @@
+#FIG 3.2  Produced by xfig version 3.2.5-alpha5
+Landscape
+Center
+Metric
+A4      
+100.00
+Single
+-2
+1200 2
+0 32 #c2c2c2
+0 33 #6e6e6e
+0 34 #444444
+0 35 #8e8f8e
+0 36 #717171
+0 37 #aeaeae
+0 38 #333333
+0 39 #949395
+0 40 #747075
+0 41 #555555
+0 42 #b3b3b3
+0 43 #c3c3c3
+0 44 #6d6d6d
+0 45 #454545
+0 46 #8e8e8e
+5 1 0 1 0 7 50 -1 -1 0.000 0 1 0 0 1935.000 6693.750 1710 6930 1935 7020 2160 6930
+5 1 0 1 0 7 50 -1 -1 0.000 0 0 0 0 1935.000 6806.250 1710 6570 1935 6480 2160 6570
+5 1 0 1 0 7 50 -1 -1 0.000 0 1 0 0 1935.000 6333.750 1710 6570 1935 6660 2160 6570
+6 1170 3330 1890 4050
+2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 4
+	 1890 3870 1890 3330 1170 3330 1170 3870
+3 2 0 1 0 11 50 -1 -1 0.000 0 0 0 4
+	 1170 3870 1350 3780 1710 3960 1890 3870
+	 0.000 -1.000 -1.000 0.000
+-6
+6 2880 5400 3600 6120
+2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 4
+	 3600 5940 3600 5400 2880 5400 2880 5940
+3 2 0 1 0 11 50 -1 -1 0.000 0 0 0 4
+	 2880 5940 3060 5850 3420 6030 3600 5940
+	 0.000 -1.000 -1.000 0.000
+-6
+6 2880 7470 3600 8190
+2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 4
+	 3600 8010 3600 7470 2880 7470 2880 8010
+3 2 0 1 0 11 50 -1 -1 0.000 0 0 0 4
+	 2880 8010 3060 7920 3420 8100 3600 8010
+	 0.000 -1.000 -1.000 0.000
+-6
+1 1 0 1 0 11 50 -1 20 0.000 1 0.0000 1530 4680 630 270 1530 4680 2160 4410
+1 1 0 1 0 14 50 -1 20 0.000 1 0.0000 4950 4680 630 270 4950 4680 5580 4680
+1 1 0 1 0 11 50 -1 20 0.000 1 0.0000 2385 2610 630 270 2385 2610 3015 2340
+1 1 0 1 0 14 50 -1 20 0.000 1 0.0000 2385 1620 630 270 2385 1620 3015 1620
+1 1 0 1 0 11 50 -1 20 0.000 1 0.0000 3240 8820 630 270 3240 8820 3870 8820
+2 1 0 1 0 4 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4320 4680 3420 5220 3420 5400
+2 1 0 1 0 4 50 -1 -1 0.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 3240 9090 3240 9450 4950 9450 4950 4950
+2 1 0 1 0 4 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 2160 4680 3060 5220 3060 5400
+2 1 0 1 0 4 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 2880 7740 1350 7740 1350 4950
+2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 1530 3960 1530 4410
+2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2385 2880 1530 3330
+2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2385 1890 2385 2340
+2 1 0 1 0 4 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 2385 2880 3240 3330 3240 5400
+2 4 0 1 0 4 50 -1 20 0.000 0 0 7 0 0 5
+	 2610 6480 3870 6480 3870 7020 2610 7020 2610 6480
+2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3240 7020 3240 7470
+2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3240 8100 3240 8550
+2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3240 6030 3240 6480
+2 1 0 1 0 4 50 -1 -1 0.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 3600 5670 4050 5850 4050 8415 3690 8595
+2 1 0 1 0 4 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3600 7740 4950 7740
+2 1 0 1 0 4 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 2880 5670 1710 5670 1710 4950
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2160 6750 2610 6750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 1710 6570 1710 6930
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 2160 6570 2160 6930
+4 1 0 49 -1 0 12 0.0000 0 165 810 1530 4680 Optimizer\001
+4 1 0 50 -1 0 12 0.0000 0 135 450 3240 7740 .stat\001
+4 1 0 49 -1 0 12 0.0000 0 135 900 3240 6750 Simulation\001
+4 1 0 49 -1 0 12 0.0000 0 135 540 3240 8820 Viewer\001
+4 1 0 49 -1 0 12 0.0000 0 165 900 2385 2610 Gen-Config\001
+4 1 0 50 -1 0 12 0.0000 0 165 360 3240 5670 .cfg\001
+4 1 0 50 -1 0 12 0.0000 0 150 630 1530 3600 .limits\001
+4 1 0 50 -1 0 12 0.0000 0 90 360 1935 6795 exec\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-BTB.fig
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-BTB.fig	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-BTB.fig	(revision 3)
@@ -0,0 +1,148 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6300.000 4350.000 6000 4575 6300 4725 6600 4575
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6300.000 4642.500 6000 4575 6300 4950 6600 4575
+6 5175 3375 6225 3825
+5 1 0 1 0 7 50 -1 -1 3.000 0 1 0 0 5700.000 3262.500 5250 3450 5700 3750 6150 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5250 3450 6150 3450
+-6
+6 6375 3375 7425 3825
+5 1 0 1 0 7 50 -1 -1 3.000 0 1 0 0 6900.000 3262.500 6450 3450 6900 3750 7350 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6450 3450 7350 3450
+-6
+6 5536 2611 5700 2775
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 5618 2693 75 75 5618 2693 5693 2693
+4 1 0 50 -1 0 8 0.0000 4 45 75 5619 2729 =\001
+-6
+6 5850 3000 6075 3225
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 5993 3143 75 75 5993 3143 6068 3143
+4 1 0 50 -1 0 8 0.0000 4 75 135 5994 3179 >=\001
+-6
+6 6736 2611 6900 2775
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 6818 2693 75 75 6818 2693 6893 2693
+4 1 0 50 -1 0 8 0.0000 4 45 75 6819 2729 =\001
+-6
+6 7050 3000 7275 3225
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 7193 3143 75 75 7193 3143 7268 3143
+4 1 0 50 -1 0 8 0.0000 4 75 135 7194 3179 >=\001
+-6
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5325 1575 5325 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5625 2775 5625 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6000 3225 6000 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6525 1575 6525 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6825 2775 6825 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7200 3225 7200 3450
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 0 0 3
+	 3900 975 3900 2400 6600 2400
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 0 0 3
+	 4800 975 4800 2850 6975 2850
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5400 2400 5550 2700
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5775 2850 5925 3150
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6600 2400 6750 2700
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6975 2850 7125 3150
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 0 0 3
+	 4425 975 4425 1275 6300 1275
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5100 1275 5250 1575
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6300 1275 6450 1575
+2 2 0 1 1 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 4200 900 4650 900 4650 1050 4200 1050 4200 900
+2 2 0 1 1 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 4650 1050 4950 1050 4950 900 4650 900 4650 1050
+2 2 0 1 1 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 3600 900 4200 900 4200 1050 3600 1050 3600 900
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5625 1575 5625 2625
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6000 1575 6000 3075
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6825 1575 6825 2625
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7200 1575 7200 3075
+2 1 2 1 4 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5400 900 5400 2250
+2 1 2 1 4 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6600 900 6600 2250
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5250 1500 6150 1500 6150 1650 5250 1650 5250 1500
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6450 1500 7350 1500 7350 1650 6450 1650 6450 1500
+2 2 0 1 4 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5250 900 6150 900 6150 2250 5250 2250 5250 900
+2 2 0 1 4 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6450 900 7350 900 7350 2250 6450 2250 6450 900
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 7200 1800 8100 1800 8100 3750
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 6000 1950 7650 1950 7650 3750
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5700 4050 7500 4050
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6900 3900 7500 3900
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7875 4200 7875 5250
+2 4 0 1 12 7 50 -1 -1 4.000 0 0 7 0 0 5
+	 8250 4200 8250 3750 7500 3750 7500 4200 8250 4200
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 5700 3750 5700 4350 6150 4350 6150 4650
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 6900 3750 6900 4350 6450 4350 6450 4650
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6300 4950 6300 5250
+4 0 0 50 -1 0 10 0.7854 4 105 315 5400 825 valid\001
+4 0 0 50 -1 0 10 0.7854 4 150 705 5775 825 address_src\001
+4 0 0 50 -1 0 8 0.7854 4 105 765 6000 825 (Tag et Offset)\001
+4 1 12 50 -1 0 10 0.0000 4 105 240 7875 4050 min\001
+4 1 0 50 -1 0 10 0.0000 4 105 225 6300 5400 Hit\001
+4 1 0 50 -1 0 10 0.0000 4 120 600 7875 5400 num_way\001
+4 1 4 50 -1 0 10 0.0000 4 135 390 5700 150 Way 0\001
+4 1 4 50 -1 0 10 0.0000 4 135 390 6900 150 Way 1\001
+4 1 1 50 -1 0 8 0.0000 4 75 330 4800 825 Offset\001
+4 1 1 50 -1 0 8 0.0000 4 75 300 4425 825 Index\001
+4 1 1 50 -1 0 8 0.0000 4 90 180 3900 825 Tag\001
+4 2 0 50 -1 0 10 0.0000 4 105 330 6825 4275 Hit 1\001
+4 0 0 50 -1 0 10 0.0000 4 105 330 5775 4275 Hit 0\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-BTB.fig.bak
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-BTB.fig.bak	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-BTB.fig.bak	(revision 3)
@@ -0,0 +1,148 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6300.000 4350.000 6000 4575 6300 4725 6600 4575
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6300.000 4642.500 6000 4575 6300 4950 6600 4575
+6 5175 3375 6225 3825
+5 1 0 1 0 7 50 -1 -1 3.000 0 1 0 0 5700.000 3262.500 5250 3450 5700 3750 6150 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5250 3450 6150 3450
+-6
+6 6375 3375 7425 3825
+5 1 0 1 0 7 50 -1 -1 3.000 0 1 0 0 6900.000 3262.500 6450 3450 6900 3750 7350 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6450 3450 7350 3450
+-6
+6 5536 2611 5700 2775
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 5618 2693 75 75 5618 2693 5693 2693
+4 1 0 50 -1 0 8 0.0000 4 45 75 5619 2729 =\001
+-6
+6 5850 3000 6075 3225
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 5993 3143 75 75 5993 3143 6068 3143
+4 1 0 50 -1 0 8 0.0000 4 75 135 5994 3179 >=\001
+-6
+6 6736 2611 6900 2775
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 6818 2693 75 75 6818 2693 6893 2693
+4 1 0 50 -1 0 8 0.0000 4 45 75 6819 2729 =\001
+-6
+6 7050 3000 7275 3225
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 7193 3143 75 75 7193 3143 7268 3143
+4 1 0 50 -1 0 8 0.0000 4 75 135 7194 3179 >=\001
+-6
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5325 1575 5325 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5625 2775 5625 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6000 3225 6000 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6525 1575 6525 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6825 2775 6825 3450
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7200 3225 7200 3450
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 0 0 3
+	 3900 975 3900 2400 6600 2400
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 0 0 3
+	 4800 975 4800 2850 6975 2850
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5400 2400 5550 2700
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5775 2850 5925 3150
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6600 2400 6750 2700
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6975 2850 7125 3150
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 0 0 3
+	 4425 975 4425 1275 6300 1275
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5100 1275 5250 1575
+2 1 1 1 1 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6300 1275 6450 1575
+2 2 0 1 1 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 4200 900 4650 900 4650 1050 4200 1050 4200 900
+2 2 0 1 1 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 4650 1050 4950 1050 4950 900 4650 900 4650 1050
+2 2 0 1 1 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 3600 900 4200 900 4200 1050 3600 1050 3600 900
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5625 1575 5625 2625
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6000 1575 6000 3075
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6825 1575 6825 2625
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7200 1575 7200 3075
+2 1 2 1 4 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5400 900 5400 2250
+2 1 2 1 4 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6600 900 6600 2250
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5250 1500 6150 1500 6150 1650 5250 1650 5250 1500
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6450 1500 7350 1500 7350 1650 6450 1650 6450 1500
+2 2 0 1 4 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5250 900 6150 900 6150 2250 5250 2250 5250 900
+2 2 0 1 4 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6450 900 7350 900 7350 2250 6450 2250 6450 900
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 7200 1800 8100 1800 8100 3750
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 6000 1950 7650 1950 7650 3750
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5700 4050 7500 4050
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6900 3900 7500 3900
+2 1 3 1 12 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7875 4200 7875 5250
+2 4 0 1 12 7 50 -1 -1 4.000 0 0 7 0 0 5
+	 8250 4200 8250 3750 7500 3750 7500 4200 8250 4200
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 5700 3750 5700 4350 6150 4350 6150 4650
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 6900 3750 6900 4350 6450 4350 6450 4650
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6300 4950 6300 5250
+4 0 0 50 -1 0 10 0.7854 4 105 315 5400 825 valid\001
+4 0 0 50 -1 0 10 0.7854 4 150 705 5775 825 address_src\001
+4 0 0 50 -1 0 8 0.7854 4 105 765 6000 825 (Tag et Offset)\001
+4 1 12 50 -1 0 10 0.0000 4 105 240 7875 4050 min\001
+4 1 0 50 -1 0 10 0.0000 4 105 225 6300 5400 Hit\001
+4 1 0 50 -1 0 10 0.0000 4 120 600 7875 5400 num_way\001
+4 1 4 50 -1 0 10 0.0000 4 135 390 5700 150 Way 0\001
+4 1 4 50 -1 0 10 0.0000 4 135 390 6900 150 Way 1\001
+4 1 1 50 -1 0 8 0.0000 4 75 330 4800 825 Offset\001
+4 1 1 50 -1 0 8 0.0000 4 75 300 4425 825 Index\001
+4 1 1 50 -1 0 8 0.0000 4 90 180 3900 825 Tag\001
+4 2 0 50 -1 0 10 0.0000 4 105 330 6825 4275 Hit 1\001
+4 0 0 50 -1 0 10 0.0000 4 105 330 5775 4275 Hit 0\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-address.fig
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-address.fig	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-address.fig	(revision 3)
@@ -0,0 +1,87 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+1 4 0 1 0 7 50 -1 -1 3.000 1 0.0000 5025 2925 150 150 4875 2925 5175 2925
+2 2 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5
+	 4800 300 5550 300 5550 1500 4800 1500 4800 300
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5
+	 4800 1350 4650 1350 4650 150 5400 150 5400 300
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
+	 4800 975 5550 975
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
+	 4800 825 5550 825
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 3
+	 4800 1800 5025 1950 5250 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4950 1500 4950 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5100 900 5100 1800
+2 2 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5
+	 4800 1800 5250 1800 5250 1950 4800 1950 4800 1800
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 5250 1800 5550 1800 5550 1950 5250 1950 5250 1800
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 3
+	 5250 1800 5400 1950 5550 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5475 900 5475 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5325 1500 5325 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4350 150 4350 900 4800 900
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4050 150 4050 1875 4800 1875
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 4
+	 3150 1200 3150 2100 3750 2100 3750 1200
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1950 3750 1950
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1800 3750 1800
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1650 3750 1650
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1500 3750 1500
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1350 3750 1350
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3450 750 3450 1200
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 5025 1950 5025 2550 4425 2550 4425 2850
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 3450 2100 3450 2550 4125 2550 4125 2850
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 3
+	 3975 2850 4275 3000 4575 2850
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4275 3000 4275 3300
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 5400 1950 5400 2925 5175 2925
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5250 1500 5250 300
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 3975 2850 4575 2850 4575 3000 3975 3000 3975 2850
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4875 2925 4575 2925
+4 0 0 50 -1 0 10 0.7854 4 105 360 4350 75 Index\001
+4 0 0 50 -1 0 10 0.7854 4 120 600 4050 75 num_way\001
+4 2 0 50 -1 0 10 0.0000 4 105 1335 3075 1650 Return Address Stack\001
+4 0 0 50 -1 0 10 0.7854 4 150 780 5025 75 address_dest\001
+4 0 0 50 -1 0 10 0.7854 4 120 270 5400 75 type\001
+4 1 0 50 -1 0 10 0.0000 4 105 450 4275 3450 address\001
+4 1 0 50 -1 0 10 0.0000 4 135 225 5024 2962 jal?\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-address.fig.bak
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-address.fig.bak	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-address.fig.bak	(revision 3)
@@ -0,0 +1,87 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+1 4 0 1 0 7 50 -1 -1 3.000 1 0.0000 5025 2925 150 150 4875 2925 5175 2925
+2 2 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5
+	 4800 300 5550 300 5550 1500 4800 1500 4800 300
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5
+	 4800 1350 4650 1350 4650 150 5400 150 5400 300
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
+	 4800 975 5550 975
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
+	 4800 825 5550 825
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 3
+	 4800 1800 5025 1950 5250 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4950 1500 4950 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5100 900 5100 1800
+2 2 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 5
+	 4800 1800 5250 1800 5250 1950 4800 1950 4800 1800
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 5250 1800 5550 1800 5550 1950 5250 1950 5250 1800
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 3
+	 5250 1800 5400 1950 5550 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5475 900 5475 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5325 1500 5325 1800
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4350 150 4350 900 4800 900
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4050 150 4050 1875 4800 1875
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 4
+	 3150 1200 3150 2100 3750 2100 3750 1200
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1950 3750 1950
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1800 3750 1800
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1650 3750 1650
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1500 3750 1500
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 3150 1350 3750 1350
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3450 750 3450 1200
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 5025 1950 5025 2550 4425 2550 4425 2850
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 3450 2100 3450 2550 4125 2550 4125 2850
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 3
+	 3975 2850 4275 3000 4575 2850
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4275 3000 4275 3300
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 5400 1950 5400 2925 5175 2925
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5250 1500 5250 300
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 3975 2850 4575 2850 4575 3000 3975 3000 3975 2850
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4875 2925 4575 2925
+4 0 0 50 -1 0 10 0.7854 4 105 360 4350 75 Index\001
+4 0 0 50 -1 0 10 0.7854 4 120 600 4050 75 num_way\001
+4 2 0 50 -1 0 10 0.0000 4 105 1335 3075 1650 Return Address Stack\001
+4 0 0 50 -1 0 10 0.7854 4 150 780 5025 75 address_dest\001
+4 0 0 50 -1 0 10 0.7854 4 120 270 5400 75 type\001
+4 1 0 50 -1 0 10 0.0000 4 105 450 4275 3450 address\001
+4 1 0 50 -1 0 10 0.0000 4 135 225 5024 2962 jal?\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-meta_predictor.fig
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-meta_predictor.fig	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-meta_predictor.fig	(revision 3)
@@ -0,0 +1,45 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6600 3450 6900 3450 6900 4950 6600 4950 6600 3450
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 6600 3450 6900 4200 6600 4950
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4500 2850 5100 2850
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4800 2850 4800 3750 5100 3750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4800 3750 4800 4650 5100 4650
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6000 4650 6600 4650
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6000 3750 6600 3750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 6000 2850 6750 2850 6750 3450
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6900 4200 7500 4200
+2 4 0 1 11 11 50 -1 20 0.000 0 0 7 0 0 5
+	 6000 4950 6000 4350 5100 4350 5100 4950 6000 4950
+2 4 0 1 11 11 50 -1 20 0.000 0 0 7 0 0 5
+	 6000 4050 6000 3450 5100 3450 5100 4050 6000 4050
+2 4 0 1 4 4 50 -1 20 0.000 0 0 7 0 0 5
+	 6000 3150 6000 2550 5100 2550 5100 3150 6000 3150
+4 1 0 50 -1 0 10 0.0000 4 105 690 5550 2925 Predictor 1\001
+4 1 0 50 -1 0 10 0.0000 4 105 690 5550 4725 Predictor 3\001
+4 1 0 50 -1 0 10 0.0000 4 105 690 5550 3825 Predictor 2\001
+4 2 0 50 -1 0 10 0.0000 4 105 450 4425 2850 address\001
+4 0 0 50 -1 0 10 0.0000 4 105 285 7575 4200 Take\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-meta_predictor.fig.bak
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-meta_predictor.fig.bak	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-meta_predictor.fig.bak	(revision 3)
@@ -0,0 +1,45 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+2 4 0 1 0 7 50 -1 -1 0.000 0 0 7 0 0 5
+	 6000 3150 6000 2550 5100 2550 5100 3150 6000 3150
+2 4 0 1 0 7 50 -1 -1 0.000 0 0 7 0 0 5
+	 6000 4050 6000 3450 5100 3450 5100 4050 6000 4050
+2 4 0 1 0 7 50 -1 -1 0.000 0 0 7 0 0 5
+	 6000 4950 6000 4350 5100 4350 5100 4950 6000 4950
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6600 3450 6900 3450 6900 4950 6600 4950 6600 3450
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 6600 3450 6900 4200 6600 4950
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4500 2850 5100 2850
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4800 2850 4800 3750 5100 3750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4800 3750 4800 4650 5100 4650
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6000 4650 6600 4650
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6000 3750 6600 3750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 6000 2850 6750 2850 6750 3450
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6900 4200 7500 4200
+4 1 0 50 -1 0 10 0.0000 4 105 690 5550 2925 Predictor 1\001
+4 1 0 50 -1 0 10 0.0000 4 105 690 5550 4725 Predictor 3\001
+4 1 0 50 -1 0 10 0.0000 4 105 690 5550 3825 Predictor 2\001
+4 2 0 50 -1 0 10 0.0000 4 105 450 4425 2850 address\001
+4 0 0 50 -1 0 10 0.0000 4 105 285 7575 4200 Take\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-predictor.fig
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-predictor.fig	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-predictor.fig	(revision 3)
@@ -0,0 +1,109 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6375.000 5737.500 6225 5850 6375 5925 6525 5850
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6375.000 5812.500 6225 5925 6375 6000 6525 5925
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6375.000 5925.000 6225 5925 6375 6075 6525 5925
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6150 3450 6450 3450 6450 4650 6150 4650 6150 3450
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5550 3750 6150 3750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6450 4050 7050 4050
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7950 4050 8550 4050
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4050 3750 4650 3750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4200 3750 4200 4350 6150 4350
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 4350 3825 4500 3675
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5775 3825 5925 3675
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5775 4425 5925 4275
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6675 4125 6825 3975
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 8175 4125 8325 3975
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6150 4650 5250 4950
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6450 4650 7350 4950
+2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2
+	3 0 1.00 60.00 120.00
+	3 0 1.00 60.00 120.00
+	 5625 5700 6525 5700
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6525 5475 6525 5625
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5625 5475 5625 5625
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6225 5100 6225 5250
+2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2
+	3 0 1.00 60.00 120.00
+	3 0 1.00 60.00 120.00
+	 6225 5325 6975 5325
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6975 5100 6975 5250
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6225 4950 6225 6600
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6525 5625 5625 5625
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6225 5250 6975 5250
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6225 5100 6975 5100
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6525 5475 5625 5475
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6525 4950 6525 6600
+2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2
+	3 0 1.00 60.00 120.00
+	3 0 1.00 60.00 120.00
+	 5625 6450 6975 6450
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5625 6225 6975 6225
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6975 6225 6975 6375
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6975 4950 6975 6600
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5625 6375 6975 6375
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5625 6225 5625 6375
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5625 4950 5625 6600
+2 4 0 1 4 4 50 -1 20 0.000 0 0 7 0 0 5
+	 5550 4050 5550 3450 4650 3450 4650 4050 5550 4050
+2 4 0 1 11 11 50 -1 20 0.000 0 0 7 0 0 5
+	 7950 4350 7950 3750 7050 3750 7050 4350 7950 4350
+4 2 0 50 -1 0 10 0.0000 4 105 450 3975 3750 address\001
+4 1 0 50 -1 0 8 0.0000 4 60 45 4425 3675 a\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 5850 4275 b\001
+4 1 0 50 -1 0 8 0.0000 4 60 60 5850 3675 c\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 6750 3975 d\001
+4 1 0 50 -1 0 10 0.0000 4 105 300 5100 3750 BHT\001
+4 1 0 50 -1 0 8 0.0000 4 105 735 5100 3900 (shift register)\001
+4 1 0 50 -1 0 10 0.0000 4 105 300 7500 4050 PHT\001
+4 1 0 50 -1 0 8 0.0000 4 105 480 7500 4200 (counter)\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 6075 5700 b\001
+4 1 0 50 -1 0 8 0.0000 4 60 60 6600 5325 c\001
+4 1 0 50 -1 0 8 0.0000 4 105 645 6600 5175 shift register\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 6300 6450 d\001
+4 1 0 50 -1 0 8 0.0000 4 75 855 6300 6300 counter's address\001
+4 1 0 50 -1 0 8 0.0000 4 75 360 6075 5550 address\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 8250 3975 1\001
+4 0 0 50 -1 0 10 0.0000 4 105 285 8625 4050 Take\001
+4 1 0 50 -1 0 10 1.5708 4 135 960 6300 4050 index generator\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-predictor.fig.bak
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-predictor.fig.bak	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit-predictor.fig.bak	(revision 3)
@@ -0,0 +1,109 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6375.000 5737.500 6225 5850 6375 5925 6525 5850
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6375.000 5812.500 6225 5925 6375 6000 6525 5925
+5 1 0 1 0 7 50 -1 -1 4.000 0 1 0 0 6375.000 5925.000 6225 5925 6375 6075 6525 5925
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6150 3450 6450 3450 6450 4650 6150 4650 6150 3450
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5550 3750 6150 3750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6450 4050 7050 4050
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7950 4050 8550 4050
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4050 3750 4650 3750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4200 3750 4200 4350 6150 4350
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 4350 3825 4500 3675
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5775 3825 5925 3675
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5775 4425 5925 4275
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6675 4125 6825 3975
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 8175 4125 8325 3975
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6150 4650 5250 4950
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6450 4650 7350 4950
+2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2
+	3 0 1.00 60.00 120.00
+	3 0 1.00 60.00 120.00
+	 5625 5700 6525 5700
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6525 5475 6525 5625
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5625 5475 5625 5625
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6225 5100 6225 5250
+2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2
+	3 0 1.00 60.00 120.00
+	3 0 1.00 60.00 120.00
+	 6225 5325 6975 5325
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6975 5100 6975 5250
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6225 4950 6225 6600
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6525 5625 5625 5625
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6225 5250 6975 5250
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6225 5100 6975 5100
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6525 5475 5625 5475
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6525 4950 6525 6600
+2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2
+	3 0 1.00 60.00 120.00
+	3 0 1.00 60.00 120.00
+	 5625 6450 6975 6450
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5625 6225 6975 6225
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6975 6225 6975 6375
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 6975 4950 6975 6600
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5625 6375 6975 6375
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5625 6225 5625 6375
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5625 4950 5625 6600
+2 4 0 1 4 4 50 -1 20 0.000 0 0 7 0 0 5
+	 5550 4050 5550 3450 4650 3450 4650 4050 5550 4050
+2 4 0 1 11 11 50 -1 20 0.000 0 0 7 0 0 5
+	 7950 4350 7950 3750 7050 3750 7050 4350 7950 4350
+4 2 0 50 -1 0 10 0.0000 4 105 450 3975 3750 address\001
+4 1 0 50 -1 0 8 0.0000 4 60 45 4425 3675 a\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 5850 4275 b\001
+4 1 0 50 -1 0 8 0.0000 4 60 60 5850 3675 c\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 6750 3975 d\001
+4 1 0 50 -1 0 10 0.0000 4 105 300 5100 3750 BHT\001
+4 1 0 50 -1 0 8 0.0000 4 105 735 5100 3900 (shift register)\001
+4 1 0 50 -1 0 10 0.0000 4 105 300 7500 4050 PHT\001
+4 1 0 50 -1 0 8 0.0000 4 105 480 7500 4200 (counter)\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 6075 5700 b\001
+4 1 0 50 -1 0 8 0.0000 4 60 60 6600 5325 c\001
+4 1 0 50 -1 0 8 0.0000 4 105 645 6600 5175 shift register\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 6300 6450 d\001
+4 1 0 50 -1 0 8 0.0000 4 75 855 6300 6300 counter's address\001
+4 1 0 50 -1 0 8 0.0000 4 75 360 6075 5550 address\001
+4 1 0 50 -1 0 8 0.0000 4 75 60 8250 3975 1\001
+4 0 0 50 -1 0 10 0.0000 4 105 285 8625 4050 Take\001
+4 1 0 50 -1 0 10 1.5708 4 135 960 6300 4050 index generator\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit.fig
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit.fig	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit.fig	(revision 3)
@@ -0,0 +1,125 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+6 5700 -525 6600 225
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 6450 -225 75 75 6450 -225 6525 -225
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 5850 -375 6150 -375 6150 -225 5850 -225 5850 -375
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 5850 -225 6150 -225 6150 -75 5850 -75 5850 -225
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 3
+	 5850 -75 6000 -225 6150 -75
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 6
+	3 0 1.00 60.00 120.00
+	 6000 -375 6000 -525 5700 -525 5700 225 5925 225 5925 -75
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 6000 -525 6450 -525 6450 -300
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 6450 -150 6450 225 6075 225 6075 -75
+4 1 0 50 -1 0 10 0.0000 4 75 90 6450 -225 +\001
+-6
+6 6300 750 7275 1200
+6 6300 900 6900 1050
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 6825 975 6675 975
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 6525 975 6375 975
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 6900 900 6300 900 6300 1050 6900 1050 6900 900
+-6
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 7275 900 6750 750
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 7275 1050 6750 1200
+-6
+6 4650 1200 5550 1950
+1 1 0 1 0 7 50 -1 -1 0.000 1 0.0000 5100 1500 75 75 5100 1500 5175 1425
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 4650 1800 5550 1800 5550 1950 4650 1950 4650 1800
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5100 1425 5100 1575
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5025 1500 5175 1500
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5100 1800 5100 1575
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5100 1425 5100 1200
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 5475 1875 5325 1875
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 5175 1875 5025 1875
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 4875 1875 4725 1875
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5475 0 5475 -75 5025 -75 5025 1125 5100 1125
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5400 -75 5400 -150 4950 -150 4950 1050 5025 1050
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 3750 -750 4500 -750 4500 600 5250 600
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4500 600 4500 1500 5025 1500
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5325 300 5700 -675
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5325 450 5700 300
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 8625 0 8625 -75 8175 -75 8175 1125 8250 1125
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 8550 -75 8550 -150 8100 -150 8100 1050 8175 1050
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 4500 -750 6750 -750 6750 600 7200 600
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 5
+	3 0 1.00 60.00 120.00
+	 7350 600 7650 600 7650 1500 8250 1500 8250 1200
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 6750 -750 7800 -750 7800 600 8400 600
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 7800 -750 9300 -750 9300 600 9750 600
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 8550 600 9000 600 9000 1500 10275 1500
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 5400 600 5850 600 5850 1650 10275 1650
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 9900 600 10350 600 10350 1350
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 9600 0 10050 0 10050 1200 9600 1200 9600 0
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 8250 0 8700 0 8700 1200 8250 1200 8250 0
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 7050 0 7500 0 7500 1200 7050 1200 7050 0
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5100 0 5550 0 5550 1200 5100 1200 5100 0
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 10275 1350 10425 1350 10425 1800 10275 1800 10275 1350
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 3
+	 10275 1350 10425 1575 10275 1800
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 10425 1575 10800 1575
+4 0 0 50 -1 0 10 0.0000 4 150 1095 10125 525 Choose_predictor\001
+4 0 0 50 -1 0 10 0.0000 4 150 645 9075 1425 local_take\001
+4 0 0 50 -1 0 10 0.0000 4 150 765 5925 1575 global _take\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit.fig.bak
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit.fig.bak	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-prediction_unit.fig.bak	(revision 3)
@@ -0,0 +1,125 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+6 5700 -525 6600 225
+1 3 0 1 0 7 50 -1 -1 3.000 1 0.0000 6450 -225 75 75 6450 -225 6525 -225
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 5850 -375 6150 -375 6150 -225 5850 -225 5850 -375
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 5850 -225 6150 -225 6150 -75 5850 -75 5850 -225
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 3
+	 5850 -75 6000 -225 6150 -75
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 6
+	3 0 1.00 60.00 120.00
+	 6000 -375 6000 -525 5700 -525 5700 225 5925 225 5925 -75
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 6000 -525 6450 -525 6450 -300
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 6450 -150 6450 225 6075 225 6075 -75
+4 1 0 50 -1 0 10 0.0000 4 75 90 6450 -225 +\001
+-6
+6 6300 750 7275 1200
+6 6300 900 6900 1050
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 6825 975 6675 975
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 6525 975 6375 975
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 6900 900 6300 900 6300 1050 6900 1050 6900 900
+-6
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 7275 900 6750 750
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 7275 1050 6750 1200
+-6
+6 4650 1200 5550 1950
+1 1 0 1 0 7 50 -1 -1 0.000 1 0.0000 5100 1500 75 75 5100 1500 5175 1425
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 4650 1800 5550 1800 5550 1950 4650 1950 4650 1800
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5100 1425 5100 1575
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 5025 1500 5175 1500
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5100 1800 5100 1575
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5100 1425 5100 1200
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 5475 1875 5325 1875
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 5175 1875 5025 1875
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	1 0 1.00 60.00 120.00
+	 4875 1875 4725 1875
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5475 0 5475 -75 5025 -75 5025 1125 5100 1125
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5400 -75 5400 -150 4950 -150 4950 1050 5025 1050
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 3750 -750 4500 -750 4500 600 5250 600
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 4500 600 4500 1500 5025 1500
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5325 300 5700 -675
+2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
+	 5325 450 5700 300
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 8625 0 8625 -75 8175 -75 8175 1125 8250 1125
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 8550 -75 8550 -150 8100 -150 8100 1050 8175 1050
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 4500 -750 6750 -750 6750 600 7200 600
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 5
+	3 0 1.00 60.00 120.00
+	 7350 600 7650 600 7650 1500 8250 1500 8250 1200
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 6750 -750 7800 -750 7800 600 8400 600
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 7800 -750 9300 -750 9300 600 9750 600
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 8550 600 9000 600 9000 1500 10275 1500
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4
+	3 0 1.00 60.00 120.00
+	 5400 600 5850 600 5850 1650 10275 1650
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 9900 600 10350 600 10350 1350
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 9600 0 10050 0 10050 1200 9600 1200 9600 0
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 8250 0 8700 0 8700 1200 8250 1200 8250 0
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 7050 0 7500 0 7500 1200 7050 1200 7050 0
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5100 0 5550 0 5550 1200 5100 1200 5100 0
+2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
+	 10275 1350 10425 1350 10425 1800 10275 1800 10275 1350
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 3
+	 10275 1350 10425 1575 10275 1800
+2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 10425 1575 10800 1575
+4 0 0 50 -1 0 10 0.0000 4 150 1095 10125 525 Choose_predictor\001
+4 0 0 50 -1 0 10 0.0000 4 150 645 9075 1425 local_take\001
+4 0 0 50 -1 0 10 0.0000 4 150 765 5925 1575 global _take\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_overview.fig
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_overview.fig	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_overview.fig	(revision 3)
@@ -0,0 +1,259 @@
+#FIG 3.2
+Landscape
+Center
+Metric
+A4      
+100.00
+Single
+-2
+1200 2
+6 1170 4005 8730 7110
+6 7380 5535 7650 5715
+2 1 0 1 0 7 54 -1 20 4.000 0 0 -1 0 0 4
+	 7380 5535 7650 5535 7650 5715 7380 5715
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7560 5535 7560 5715
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7470 5535 7470 5715
+-6
+6 7380 5985 7650 6165
+2 1 0 1 0 7 54 -1 20 4.000 0 0 -1 0 0 4
+	 7380 5985 7650 5985 7650 6165 7380 6165
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7560 5985 7560 6165
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7470 5985 7470 6165
+-6
+6 7380 5085 7650 5265
+2 1 0 1 0 7 54 -1 20 4.000 0 0 -1 0 0 4
+	 7380 5085 7650 5085 7650 5265 7380 5265
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7560 5085 7560 5265
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7470 5085 7470 5265
+-6
+6 1170 4635 2070 5895
+2 1 1 1 0 2 54 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 1665 5490 1260 5490
+2 1 1 1 0 7 54 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 1710 4770 1260 4770
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 1620 5175 2070 5175 2070 4635 1620 4635 1620 5175
+2 1 1 1 0 7 51 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 1620 4905 1170 4905
+2 1 1 1 0 7 51 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 1620 5625 1170 5625
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 1620 5895 2070 5895 2070 5355 1620 5355 1620 5895
+4 1 0 46 -1 0 8 0.0000 0 75 345 1845 4905 dcache\001
+4 1 0 46 -1 0 8 0.0000 0 90 315 1845 5625 icache\001
+4 1 0 45 -1 0 8 0.0000 0 75 135 1845 5040 L1\001
+4 1 0 45 -1 0 8 0.0000 0 75 135 1845 5760 L1\001
+-6
+6 1440 6390 2970 7110
+2 2 0 1 0 5 47 -1 20 0.000 0 0 -1 0 0 5
+	 1710 6390 1440 6390 1440 6570 1710 6570 1710 6390
+2 2 0 1 0 2 53 -1 20 0.000 0 0 7 0 0 5
+	 1710 6930 1440 6930 1440 7110 1710 7110 1710 6930
+2 2 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5
+	 1710 6660 1440 6660 1440 6840 1710 6840 1710 6660
+4 0 0 45 -1 0 8 0.0000 0 105 1080 1890 6750 Unit\351s de lancements\001
+4 0 0 45 -1 0 8 0.0000 0 75 435 1890 7020 Clusters\001
+4 0 0 45 -1 0 8 0.0000 0 75 540 1890 6480 Contextes\001
+-6
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 4320 5940 4770 5940 4770 5310 4320 5310 4320 5940
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 4950 5940 5400 5940 5400 5310 4950 5310 4950 5940
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 5580 5310 5760 5310 5760 5940 5580 5940 5580 5310
+2 1 0 1 0 7 48 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3780 5490 3960 5490
+2 2 0 1 0 5 48 -1 20 0.000 0 0 -1 0 0 5
+	 3780 5310 3285 5310 3285 5850 3780 5850 3780 5310
+2 2 0 1 0 5 47 -1 20 0.000 0 0 -1 0 0 5
+	 3690 5400 3150 5400 3150 5940 3690 5940 3690 5400
+2 1 0 1 0 7 48 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4140 5625 4320 5625
+2 1 0 1 0 7 48 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4770 5625 4950 5625
+2 1 0 1 0 7 48 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5400 5625 5580 5625
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7020 5625 7380 5625
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7020 5625 7380 6075
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 2430 5940 2250 5940 2250 5310 2430 5310 2430 5940
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 2970 5310 2790 5310 2790 5940 2970 5940 2970 5310
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 3960 5310 4140 5310 4140 5940 3960 5940 3960 5310
+2 1 1 1 0 7 48 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3285 5490 2970 5490
+2 1 1 1 0 7 47 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3150 5760 2970 5760
+2 1 0 1 0 7 47 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3690 5760 3960 5760
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 6210 5940 6390 5940 6390 5310 6210 5310 6210 5940
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 6840 5940 7020 5940 7020 5310 6840 5310 6840 5940
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7020 5625 7380 5175
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7650 5175 7830 5175
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7650 5625 7830 5625
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7650 6075 7830 6075
+2 2 2 1 0 7 46 -1 -1 3.000 0 0 -1 0 0 5
+	 7110 6030 5490 6030 5490 5220 7110 5220 7110 6030
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 2430 5220 2250 5220 2250 4590 2430 4590 2430 5220
+2 1 1 1 0 7 52 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2700 4815 2430 4815
+2 1 1 1 0 7 52 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2700 5490 2430 5490
+2 1 0 1 0 2 53 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6390 5715 6840 5715
+2 1 0 1 0 2 54 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6660 5535 6840 5535
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 3
+	 3960 5310 4140 5625 3960 5940
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 3
+	 2970 5310 2790 5625 2970 5940
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 3
+	 2425 5313 2245 5628 2425 5943
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 3
+	 2425 4593 2245 4908 2425 5223
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 7830 6300 8010 6300 8010 4950 7830 4950 7830 6300
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 8190 6300 8550 6300 8550 6030 8190 6030 8190 6300
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8010 6165 8190 6165
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 8190 5940 8550 5940 8550 5670 8190 5670 8190 5940
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8010 5805 8190 5805
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 2
+	 8550 5805 8730 5805
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 8190 5580 8550 5580 8550 5310 8190 5310 8190 5580
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8010 5445 8190 5445
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 2
+	 8550 5445 8730 5445
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8010 5085 8190 5085
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 8190 5220 8550 5220 8550 4950 8190 4950 8190 5220
+2 2 0 1 0 7 50 -1 20 4.000 0 0 -1 0 0 5
+	 5085 5130 4635 5130 4635 4950 5085 4950 5085 5130
+2 1 1 1 0 7 50 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4635 5040 2430 5040
+2 1 0 1 0 7 50 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5040 5310 5040 5130
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 2
+	 8550 5085 8730 5085
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5
+	3 0 1.00 60.00 120.00
+	 8550 6165 8730 6165 8730 4365 4275 4365 4275 4590
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4860 4770 4860 4950
+2 2 0 1 0 7 50 -1 20 4.000 0 0 -1 0 0 5
+	 3105 4590 5355 4590 5355 4770 3105 4770 3105 4590
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5175 4770 5175 5310
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4545 4770 4545 5310
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3510 4770 3510 5310
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 7290 4545 7740 4545 7740 4905 7290 4905 7290 4545
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7515 4365 7515 4545
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7515 4905 7515 5175
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7515 5175 7515 5625
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7515 5625 7515 6075
+2 2 0 1 0 11 51 -1 20 0.000 0 0 -1 0 0 5
+	 2610 6120 5940 6120 5940 4275 2610 4275 2610 6120
+2 2 0 1 0 11 52 -1 20 0.000 0 0 -1 0 0 5
+	 6030 4185 2700 4185 2700 6030 6030 6030 6030 4185
+2 1 1 1 0 7 51 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2790 5760 2430 5760
+2 1 0 1 0 2 51 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5760 5715 6210 5715
+2 1 0 1 0 2 52 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6030 5535 6210 5535
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 3510 5085 3420 5175 3420 5400
+2 1 1 1 0 2 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2250 5625 2070 5625
+2 1 1 1 0 7 50 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2250 4905 2070 4905
+2 2 0 1 0 2 53 -1 20 0.000 0 0 -1 0 0 5
+	 1440 6210 6570 6210 6570 4095 1440 4095 1440 6210
+2 2 0 1 0 2 54 -1 20 0.000 0 0 -1 0 0 5
+	 6660 4005 1530 4005 1530 6120 6660 6120 6660 4005
+4 1 0 45 -1 0 8 0.0000 0 90 300 3420 5670 ifetch\001
+4 1 0 45 -1 0 8 0.0000 0 75 360 4545 5670 decode\001
+4 1 0 45 -1 0 8 0.0000 0 60 360 5175 5670 rename\001
+4 1 0 45 -1 0 8 1.5708 0 75 315 5715 5625 select\001
+4 1 0 45 -1 0 8 1.5708 0 75 315 6345 5625 select\001
+4 1 0 45 -1 0 8 1.5708 0 75 315 6975 5625 select\001
+4 1 0 45 -1 0 8 1.5708 0 120 405 7965 5535 dispatch\001
+4 1 0 45 -1 0 8 0.0000 0 75 315 6300 5130 select\001
+4 1 0 45 -1 0 8 0.0000 0 75 420 8370 6165 execute\001
+4 1 0 45 -1 0 8 0.0000 0 75 420 8370 5805 execute\001
+4 1 0 45 -1 0 8 0.0000 0 75 420 8370 5445 execute\001
+4 1 0 45 -1 0 8 0.0000 0 75 420 8370 5085 execute\001
+4 1 0 50 -1 0 8 0.0000 0 90 405 4860 5085 memory\001
+4 1 0 45 -1 0 8 0.0000 0 90 375 4275 4725 commit\001
+4 1 0 45 -1 0 8 0.0000 0 105 435 7515 4725 registers\001
+-6
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_overview.fig.bak
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_overview.fig.bak	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_overview.fig.bak	(revision 3)
@@ -0,0 +1,257 @@
+#FIG 3.2
+Landscape
+Center
+Metric
+A4      
+100.00
+Single
+-2
+1200 2
+6 7380 5535 7650 5715
+2 1 0 1 0 7 54 -1 20 4.000 0 0 -1 0 0 4
+	 7380 5535 7650 5535 7650 5715 7380 5715
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7560 5535 7560 5715
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7470 5535 7470 5715
+-6
+6 7380 5985 7650 6165
+2 1 0 1 0 7 54 -1 20 4.000 0 0 -1 0 0 4
+	 7380 5985 7650 5985 7650 6165 7380 6165
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7560 5985 7560 6165
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7470 5985 7470 6165
+-6
+6 7380 5085 7650 5265
+2 1 0 1 0 7 54 -1 20 4.000 0 0 -1 0 0 4
+	 7380 5085 7650 5085 7650 5265 7380 5265
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7560 5085 7560 5265
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 0 0 2
+	 7470 5085 7470 5265
+-6
+6 1170 4635 2070 5895
+2 1 1 1 0 2 54 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 1665 5490 1260 5490
+2 1 1 1 0 7 54 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 1710 4770 1260 4770
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 1620 5175 2070 5175 2070 4635 1620 4635 1620 5175
+2 1 1 1 0 7 51 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 1620 4905 1170 4905
+2 1 1 1 0 7 51 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 1620 5625 1170 5625
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 1620 5895 2070 5895 2070 5355 1620 5355 1620 5895
+4 1 0 46 -1 0 6 0.0000 0 60 255 1845 4905 dcache\001
+4 1 0 46 -1 0 6 0.0000 0 60 225 1845 5625 icache\001
+4 1 0 45 -1 0 6 0.0000 0 60 105 1845 5040 L1\001
+4 1 0 45 -1 0 6 0.0000 0 60 105 1845 5760 L1\001
+-6
+6 1440 6390 2655 7110
+2 2 0 1 0 5 47 -1 20 0.000 0 0 -1 0 0 5
+	 1710 6390 1440 6390 1440 6570 1710 6570 1710 6390
+2 2 0 1 0 2 53 -1 20 0.000 0 0 7 0 0 5
+	 1710 6930 1440 6930 1440 7110 1710 7110 1710 6930
+2 2 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5
+	 1710 6660 1440 6660 1440 6840 1710 6840 1710 6660
+4 0 0 45 -1 0 6 0.0000 0 75 750 1890 6750 Unit\351s de lancements\001
+4 0 0 45 -1 0 6 0.0000 0 60 300 1890 7020 Clusters\001
+4 0 0 45 -1 0 6 0.0000 0 60 390 1890 6480 Contextes\001
+-6
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 4320 5940 4770 5940 4770 5310 4320 5310 4320 5940
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 4950 5940 5400 5940 5400 5310 4950 5310 4950 5940
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 5580 5310 5760 5310 5760 5940 5580 5940 5580 5310
+2 1 0 1 0 7 48 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3780 5490 3960 5490
+2 2 0 1 0 5 48 -1 20 0.000 0 0 -1 0 0 5
+	 3780 5310 3285 5310 3285 5850 3780 5850 3780 5310
+2 2 0 1 0 5 47 -1 20 0.000 0 0 -1 0 0 5
+	 3690 5400 3150 5400 3150 5940 3690 5940 3690 5400
+2 1 0 1 0 7 48 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4140 5625 4320 5625
+2 1 0 1 0 7 48 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4770 5625 4950 5625
+2 1 0 1 0 7 48 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5400 5625 5580 5625
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7020 5625 7380 5625
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7020 5625 7380 6075
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 2430 5940 2250 5940 2250 5310 2430 5310 2430 5940
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 2970 5310 2790 5310 2790 5940 2970 5940 2970 5310
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 3960 5310 4140 5310 4140 5940 3960 5940 3960 5310
+2 1 1 1 0 7 48 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3285 5490 2970 5490
+2 1 1 1 0 7 47 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3150 5760 2970 5760
+2 1 0 1 0 7 47 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3690 5760 3960 5760
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 6210 5940 6390 5940 6390 5310 6210 5310 6210 5940
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 6840 5940 7020 5940 7020 5310 6840 5310 6840 5940
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7020 5625 7380 5175
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7650 5175 7830 5175
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7650 5625 7830 5625
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7650 6075 7830 6075
+2 2 2 1 0 7 46 -1 -1 3.000 0 0 -1 0 0 5
+	 7110 6030 5490 6030 5490 5220 7110 5220 7110 6030
+2 2 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+	 2430 5220 2250 5220 2250 4590 2430 4590 2430 5220
+2 1 1 1 0 7 52 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2700 4815 2430 4815
+2 1 1 1 0 7 52 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2700 5490 2430 5490
+2 1 0 1 0 2 53 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6390 5715 6840 5715
+2 1 0 1 0 2 54 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6660 5535 6840 5535
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 3
+	 3960 5310 4140 5625 3960 5940
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 3
+	 2970 5310 2790 5625 2970 5940
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 3
+	 2425 5313 2245 5628 2425 5943
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 3
+	 2425 4593 2245 4908 2425 5223
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 7830 6300 8010 6300 8010 4950 7830 4950 7830 6300
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 8190 6300 8550 6300 8550 6030 8190 6030 8190 6300
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8010 6165 8190 6165
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 8190 5940 8550 5940 8550 5670 8190 5670 8190 5940
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8010 5805 8190 5805
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 2
+	 8550 5805 8730 5805
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 8190 5580 8550 5580 8550 5310 8190 5310 8190 5580
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8010 5445 8190 5445
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 2
+	 8550 5445 8730 5445
+2 1 0 1 0 7 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8010 5085 8190 5085
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 8190 5220 8550 5220 8550 4950 8190 4950 8190 5220
+2 2 0 1 0 7 50 -1 20 4.000 0 0 -1 0 0 5
+	 5085 5130 4635 5130 4635 4950 5085 4950 5085 5130
+2 1 1 1 0 7 50 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4635 5040 2430 5040
+2 1 0 1 0 7 50 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5040 5310 5040 5130
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 0 0 2
+	 8550 5085 8730 5085
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5
+	3 0 1.00 60.00 120.00
+	 8550 6165 8730 6165 8730 4365 4275 4365 4275 4590
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4860 4770 4860 4950
+2 2 0 1 0 7 50 -1 20 4.000 0 0 -1 0 0 5
+	 3105 4590 5355 4590 5355 4770 3105 4770 3105 4590
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5175 4770 5175 5310
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4545 4770 4545 5310
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 3510 4770 3510 5310
+2 2 0 1 0 7 53 -1 20 4.000 0 0 -1 0 0 5
+	 7290 4545 7740 4545 7740 4905 7290 4905 7290 4545
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7515 4365 7515 4545
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7515 4905 7515 5175
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7515 5175 7515 5625
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 7515 5625 7515 6075
+2 2 0 1 0 11 51 -1 20 0.000 0 0 -1 0 0 5
+	 2610 6120 5940 6120 5940 4275 2610 4275 2610 6120
+2 2 0 1 0 11 52 -1 20 0.000 0 0 -1 0 0 5
+	 6030 4185 2700 4185 2700 6030 6030 6030 6030 4185
+2 1 1 1 0 7 51 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2790 5760 2430 5760
+2 1 0 1 0 2 51 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5760 5715 6210 5715
+2 1 0 1 0 2 52 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6030 5535 6210 5535
+2 1 0 1 0 7 45 -1 -1 4.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 3510 5085 3420 5175 3420 5400
+2 1 1 1 0 2 53 -1 -1 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2250 5625 2070 5625
+2 1 1 1 0 7 50 -1 20 4.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 2250 4905 2070 4905
+2 2 0 1 0 2 53 -1 20 0.000 0 0 -1 0 0 5
+	 1440 6210 6570 6210 6570 4095 1440 4095 1440 6210
+2 2 0 1 0 2 54 -1 20 0.000 0 0 -1 0 0 5
+	 6660 4005 1530 4005 1530 6120 6660 6120 6660 4005
+4 1 0 45 -1 0 6 0.0000 0 60 210 3420 5670 ifetch\001
+4 1 0 45 -1 0 6 0.0000 0 60 270 4545 5670 decode\001
+4 1 0 45 -1 0 6 0.0000 0 45 255 5175 5670 rename\001
+4 1 0 45 -1 0 6 1.5708 0 60 225 5715 5625 select\001
+4 1 0 45 -1 0 6 1.5708 0 60 225 6345 5625 select\001
+4 1 0 45 -1 0 6 1.5708 0 60 225 6975 5625 select\001
+4 1 0 45 -1 0 6 1.5708 0 90 285 7965 5535 dispatch\001
+4 1 0 45 -1 0 6 0.0000 0 60 225 6300 5130 select\001
+4 1 0 45 -1 0 6 0.0000 0 60 315 8370 6165 execute\001
+4 1 0 45 -1 0 6 0.0000 0 60 315 8370 5805 execute\001
+4 1 0 45 -1 0 6 0.0000 0 60 315 8370 5445 execute\001
+4 1 0 45 -1 0 6 0.0000 0 60 315 8370 5085 execute\001
+4 1 0 50 -1 0 6 0.0000 0 75 285 4860 5085 memory\001
+4 1 0 45 -1 0 6 0.0000 0 60 255 4275 4725 commit\001
+4 1 0 45 -1 0 6 0.0000 0 75 300 7515 4725 registers\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-decod.fig
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-decod.fig	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-decod.fig	(revision 3)
@@ -0,0 +1,71 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+6 4875 6000 5625 6750
+5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5250.000 6375.000 5475 6450 5475 6300 5325 6150
+	3 0 1.00 60.00 120.00
+5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5250.000 6375.000 5175 6150 5025 6300 5025 6450
+	3 0 1.00 60.00 120.00
+5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5250.000 6300.000 5025 6600 5250 6675 5475 6600
+	3 0 1.00 60.00 120.00
+1 3 0 1 0 7 50 -1 -1 0.000 1 0.0000 5250 6150 75 75 5250 6150 5325 6150
+1 3 0 1 0 7 50 -1 -1 0.000 1 0.0000 5025 6525 75 75 5025 6525 4950 6525
+1 3 0 1 0 7 50 -1 -1 0.000 1 0.0000 5475 6525 75 75 5475 6525 5550 6525
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+	 7500 4800 8400 4800 8400 5400 7500 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 8100 4800 8100 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 7800 4800 7800 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8400 5100 9000 5100
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6900 5100 7500 5100
+2 4 0 1 0 7 50 -1 -1 0.000 0 0 7 0 0 5
+	 6000 5400 6000 4800 6900 4800 6900 5400 6000 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5400 5100 6000 5100
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5400 4800 5100 4800 5100 5400 5400 5400 5400 4800
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 5100 4800 5400 5100 5100 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4500 4950 5100 4950
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4500 5100 5100 5100
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4500 5250 5100 5250
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5250 6000 5250 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5250 7350 5250 6750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 5250 7050 7950 7050 7950 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+	3 0 1.00 60.00 120.00
+	3 0 1.00 60.00 120.00
+	 6450 4800 6450 4200
+4 1 0 50 -1 0 10 0.0000 4 105 345 6450 5175 decod\001
+4 1 0 50 -1 0 10 1.5708 4 135 855 4425 5100 <stage ifetch>\001
+4 1 0 50 -1 0 10 0.0000 4 135 975 5250 7500 <stage commit>\001
+4 1 0 50 -1 0 10 0.0000 4 150 765 7950 4725 decod_queue\001
+4 2 0 50 -1 0 10 0.0000 4 105 330 7875 6975 flush\001
+4 0 0 50 -1 0 10 0.0000 4 150 465 5325 6900 nb_inst\001
+4 0 0 50 -1 0 10 0.0000 4 135 855 5625 6375 context_state\001
+4 1 0 50 -1 0 10 0.0000 4 135 1065 6450 4125 <stage predictor>\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-decod.fig.bak
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-decod.fig.bak	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-decod.fig.bak	(revision 3)
@@ -0,0 +1,71 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+6 4875 6000 5625 6750
+5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5250.000 6375.000 5475 6450 5475 6300 5325 6150
+	3 0 1.00 60.00 120.00
+5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5250.000 6375.000 5175 6150 5025 6300 5025 6450
+	3 0 1.00 60.00 120.00
+5 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5250.000 6300.000 5025 6600 5250 6675 5475 6600
+	3 0 1.00 60.00 120.00
+1 3 0 1 0 7 50 -1 -1 0.000 1 0.0000 5250 6150 75 75 5250 6150 5325 6150
+1 3 0 1 0 7 50 -1 -1 0.000 1 0.0000 5025 6525 75 75 5025 6525 4950 6525
+1 3 0 1 0 7 50 -1 -1 0.000 1 0.0000 5475 6525 75 75 5475 6525 5550 6525
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+	 7500 4800 8400 4800 8400 5400 7500 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 8100 4800 8100 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 7800 4800 7800 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8400 5100 9000 5100
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6900 5100 7500 5100
+2 4 0 1 0 7 50 -1 -1 0.000 0 0 7 0 0 5
+	 6000 5400 6000 4800 6900 4800 6900 5400 6000 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5400 5100 6000 5100
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5400 4800 5100 4800 5100 5400 5400 5400 5400 4800
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 5100 4800 5400 5100 5100 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4500 4950 5100 4950
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4500 5100 5100 5100
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 4500 5250 5100 5250
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5250 6000 5250 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5250 7350 5250 6750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 3
+	3 0 1.00 60.00 120.00
+	3 0 1.00 60.00 120.00
+	 6450 4800 6450 4200 4500 4200
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 5250 7050 7950 7050 7950 5400
+4 1 0 50 -1 0 10 0.0000 4 105 345 6450 5175 decod\001
+4 1 0 50 -1 0 10 0.0000 4 135 855 5250 6375 context_state\001
+4 1 0 50 -1 0 10 1.5708 4 135 855 4425 5100 <stage ifetch>\001
+4 1 0 50 -1 0 10 0.0000 4 135 975 5250 7500 <stage commit>\001
+4 1 0 50 -1 0 10 1.5708 4 135 1065 4425 4200 <stage predictor>\001
+4 1 0 50 -1 0 10 0.0000 4 150 765 7950 4725 decod_queue\001
+4 2 0 50 -1 0 10 0.0000 4 105 330 7875 6975 flush\001
+4 0 0 50 -1 0 10 0.0000 4 150 465 5325 6900 nb_inst\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-ifetch.fig
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-ifetch.fig	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-ifetch.fig	(revision 3)
@@ -0,0 +1,67 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+6 6900 3150 7350 3900
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6900 3150 7350 3150 7350 3900 6900 3900 6900 3150
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 6975 3900 7125 3750 7275 3900
+-6
+6 8400 3150 8850 3900
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 8400 3150 8850 3150 8850 3900 8400 3900 8400 3150
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 8475 3900 8625 3750 8775 3900
+-6
+6 5850 3150 6300 3900
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5850 3150 6300 3150 6300 3900 5850 3900 5850 3150
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 5925 3900 6075 3750 6225 3900
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6900 3525 6300 3525
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 7350 3150 7800 3150 7800 3900 7350 3900 7350 3150
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 7800 3150 7350 3525 7800 3900
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 8100 2700 8100 3375 7800 3375
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8400 3675 7800 3675
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6600 3525 6600 2700
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5850 3525 5250 3525
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+	 6300 4800 8400 4800 8400 5400 6300 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 8100 4800 8100 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 7800 4800 7800 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 7500 4800 7500 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 7200 4800 7200 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6900 4800 6900 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5250 5100 6300 5100
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8400 5100 9000 5100
+4 1 0 50 -1 0 10 0.0000 4 150 780 8625 4125 EVENT_PC\001
+4 1 0 50 -1 0 10 0.0000 4 105 195 7125 4125 PC\001
+4 1 0 50 -1 0 10 0.0000 4 150 1350 6075 4125 ICACHE_ADDRESS\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-ifetch.fig.bak
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-ifetch.fig.bak	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_stage-ifetch.fig.bak	(revision 3)
@@ -0,0 +1,67 @@
+#FIG 3.2
+Landscape
+Center
+Inches
+Letter  
+100.00
+Single
+-2
+1200 2
+6 6900 3150 7350 3900
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 6900 3150 7350 3150 7350 3900 6900 3900 6900 3150
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 6975 3900 7125 3750 7275 3900
+-6
+6 8400 3150 8850 3900
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 8400 3150 8850 3150 8850 3900 8400 3900 8400 3150
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 8475 3900 8625 3750 8775 3900
+-6
+6 5850 3150 6300 3900
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 5850 3150 6300 3150 6300 3900 5850 3900 5850 3150
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 5925 3900 6075 3750 6225 3900
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6900 3525 6300 3525
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+	 7350 3150 7800 3150 7800 3900 7350 3900 7350 3150
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+	 7800 3150 7350 3525 7800 3900
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+	3 0 1.00 60.00 120.00
+	 8100 2700 8100 3375 7800 3375
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8400 3675 7800 3675
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 6600 3525 6600 2700
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5850 3525 5250 3525
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+	 6300 4800 8400 4800 8400 5400 6300 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 8100 4800 8100 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 7800 4800 7800 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 7500 4800 7500 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 7200 4800 7200 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+	 6900 4800 6900 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 5250 5100 6300 5100
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+	3 0 1.00 60.00 120.00
+	 8400 5100 9000 5100
+4 1 0 50 -1 0 10 0.0000 4 150 780 8625 4125 EVENT_PC\001
+4 1 0 50 -1 0 10 0.0000 4 105 195 7125 4125 PC\001
+4 1 0 50 -1 0 10 0.0000 4 150 1350 6075 4125 ICACHE_ADDRESS\001
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/article-morpheo-share_architectural_ressources_between_hardware_context
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/article-morpheo-share_architectural_ressources_between_hardware_context	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/article-morpheo-share_architectural_ressources_between_hardware_context	(revision 3)
@@ -0,0 +1,1 @@
+doc
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-configuration_file_syntax
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-configuration_file_syntax	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-configuration_file_syntax	(revision 3)
@@ -0,0 +1,1 @@
+doc
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-methodology
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-methodology	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-methodology	(revision 3)
@@ -0,0 +1,1 @@
+doc
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-new_component
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-new_component	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-new_component	(revision 3)
@@ -0,0 +1,1 @@
+doc
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-overview
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-overview	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-morpheo-overview	(revision 3)
@@ -0,0 +1,1 @@
+doc
Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-viewer-specification
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-viewer-specification	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Type/document-viewer-specification	(revision 3)
@@ -0,0 +1,1 @@
+doc
Index: /trunk/IPs/systemC/processor/Morpheo/Include/Address.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/Address.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/Address.h	(revision 3)
@@ -0,0 +1,37 @@
+#ifndef morpheo_Address
+#define morpheo_Address
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+namespace morpheo              {
+
+  // get_tag, get_index, get_offset ...............
+  template <typename T>
+  T get_tag    (T value, uint32_t size_tag, uint32_t size_index, uint32_t size_offset) 
+  {
+    const T mask = gen_mask<T>(size_tag   ); 
+    return (value >> (size_index+size_offset)) & mask;
+  }
+  
+  template <typename T>
+  T get_index  (T value, uint32_t size_tag, uint32_t size_index, uint32_t size_offset) 
+  {
+    const T mask = gen_mask<T>(size_index ); 
+    return (value >> (           size_offset)) & mask;
+  }
+  
+  template <typename T>
+  T get_offset (T value, uint32_t size_tag, uint32_t size_index, uint32_t size_offset) 
+  {
+    const T mask = gen_mask<T>(size_offset); 
+    return (value                            ) & mask;
+  }
+
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Include/Average.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/Average.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/Average.h	(revision 3)
@@ -0,0 +1,20 @@
+#ifndef morpheo_Average
+#define morpheo_Average
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+namespace morpheo              {
+
+  inline double average (double   val, double   val_max) {return ((val_max == 0)?0:(val/val_max));}
+  inline double average (uint32_t val, double   val_max) {return (average(static_cast<double>(val),                    val_max ));}
+  inline double average (double   val, uint32_t val_max) {return (average(                    val ,static_cast<double>(val_max)));}
+  inline double average (uint32_t val, uint32_t val_max) {return (average(static_cast<double>(val),static_cast<double>(val_max)));}
+  
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Include/BitManipulation.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/BitManipulation.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/BitManipulation.h	(revision 3)
@@ -0,0 +1,160 @@
+#ifndef morpheo_BitManipulation
+#define morpheo_BitManipulation
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+#include <iostream>
+using namespace std;
+
+namespace morpheo              {
+
+  // gen_mask .....................................
+
+  template <typename T>
+  T gen_mask       (uint32_t size) 
+  { 
+    T mask = 0; 
+    for (uint32_t i=0; i<size; i++)
+      {
+	mask <<= 1;
+	mask  |= 1;
+      }
+    return mask;
+  };
+
+  // shift_left_logic, shift_right_logic ..........
+  template <typename T>
+  T shift_logic_left (uint32_t size, uint32_t data, uint32_t value)  
+  {
+    T mask = gen_mask<T> (size);
+
+    return (mask & ((mask & data) << value));
+  }
+
+  template <typename T>
+  T shift_logic_right (uint32_t size, uint32_t data, uint32_t value)  
+  {
+    T mask = gen_mask<T> (size);
+
+    return (mask & ((mask & data) >> value));
+  }
+
+  // shift_logic ..................................
+  template <typename T>
+  T shift_logic      (uint32_t size, uint32_t data, uint32_t value, bool is_direction_left)
+  {
+    if (is_direction_left == true)
+      return shift_logic_left  <T> (size, data, value);
+    else
+      return shift_logic_right <T> (size, data, value);
+  }
+
+  // shift_left_arithmetic, shift_right_arithmetic 
+  template <typename T>
+  T shift_arithmetic_left (uint32_t size, uint32_t data, uint32_t value)  
+  {
+    bool carry = (data&1) != 0;
+
+    if (carry == false)
+      return shift_logic_left <T> (size,data,value);
+    else
+      {
+	if (value > size)
+	  return gen_mask<T> (size);
+
+	T mask = gen_mask<T> (value);
+	return shift_logic_left <T> (size,data,value) | mask;
+      }
+  }
+
+
+  template <typename T>
+  T shift_arithmetic_right (uint32_t size, uint32_t data, uint32_t value)  
+  {
+    bool carry = (data&(1<<(size-1))) != 0;
+
+    if (carry == false)
+      return shift_logic_right <T> (size,data,value);
+    else
+      {
+	if (value > size)
+	  return gen_mask<T> (size);
+	
+	T mask = gen_mask<T> (value) << (size-value);
+	return ((shift_logic_right <T> (size,data,value)) | mask);
+      }
+  }
+
+  // shift_arithmetic .............................
+  template <typename T>
+  T shift_arithmetic      (uint32_t size, uint32_t data, uint32_t value, bool is_direction_left)
+  {
+    if (is_direction_left == true)
+      return shift_arithmetic_left  <T> (size, data, value);
+    else
+      return shift_arithmetic_right <T> (size, data, value);
+  }
+
+  // shift ........................................
+  template <typename T>
+  T shift            (uint32_t size, uint32_t data, uint32_t value, bool is_direction_left, bool is_shift_arithmetic)
+  {
+    if (is_shift_arithmetic == true)
+      return shift_arithmetic <T> (size, data, value, is_direction_left);
+    else
+      return shift_logic      <T> (size, data, value, is_direction_left);
+  }
+
+  // rotate_left, rotate_right ....................
+
+  template <typename T>
+  T rotate_left    (uint32_t size, uint32_t data, uint32_t value)  
+  {
+    T mask        = gen_mask<T> (size);
+    T rotate_mask = gen_mask<T> (value);
+    T rotate      = rotate_mask & shift_logic_right<T>(size,data,size-value);
+    return (mask & (shift_logic_left <T> (size, data, value) | rotate));
+  }
+
+  template <typename T>
+  T rotate_right    (uint32_t size, uint32_t data, uint32_t value)  
+  {
+    T mask        = gen_mask<T> (size);
+    T rotate_mask = gen_mask<T> (value);
+    T rotate      = shift_logic_left <T> (size,rotate_mask & data,size-value);
+    return (mask & (shift_logic_right<T> (size, data, value) | rotate));
+  }
+
+  // rotate .......................................
+  template <typename T>
+  T rotate         (uint32_t size, uint32_t data, uint32_t value, bool is_direction_left)  
+  {
+    if (is_direction_left == true)
+      return rotate_left  <T> (size, data, value);
+    else
+      return rotate_right <T> (size, data, value);
+  }
+
+  // range ........................................
+  template <typename T>
+  T range          (uint32_t size, uint32_t data, uint32_t index_max, uint32_t index_min)  
+  {
+    return gen_mask<T>(index_max-index_min+1) & shift_logic_left<T> (size, data, index_min);
+  }
+
+  template <typename T>
+  T range          (uint32_t size, uint32_t data, uint32_t nb_bits)  
+  {
+    return gen_mask<T>(nb_bits) & data;
+  }
+
+
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Include/Debug.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/Debug.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/Debug.h	(revision 3)
@@ -0,0 +1,66 @@
+#ifndef DEBUG_H
+#define DEBUG_H
+
+#include "Behavioural/include/Debug_component.h"
+#include <stdio.h>
+#include <string.h>
+#include <iostream>
+#include <sstream>
+#include <string>
+using namespace std;
+
+enum _debug_verbosity 
+  {
+    DEBUG_NONE ,
+    DEBUG_INFO ,
+    DEBUG_TRACE,
+    DEBUG_FUNC ,
+    DEBUG_ALL
+  };
+
+#ifdef DEBUG
+//Debug
+/*
+#  define log_printf(level, component, str... )                                       \
+do                                                                                    \
+{                                                                                     \
+    if ( ( DEBUG_ ## level     <= DEBUG) and                                          \
+         ( DEBUG_ ## component == true ) )                                            \
+      {                                                                               \
+        fprintf(stdout,"<%s> line %d : ",__FILE__,__LINE__);                          \
+        fprintf(stdout,str);                                                          \
+        fprintf(stdout,"\n");                                                         \
+      }                                                                               \
+} while(0)								            
+*/			
+					            
+#  define log_printf(level, component, func, str... )                                 \
+do                                                                                    \
+{                                                                                     \
+    if ( ( DEBUG_ ## level     <= DEBUG) and                                          \
+         ( DEBUG_ ## component == true ) )                                            \
+      {                                                                               \
+        fprintf(stdout,"In file %s, ",__FILE__);                                      \
+        fprintf(stdout,"at line %d, ",__LINE__);                                      \
+        fprintf(stdout,"in function \"%s\" : ",func);                                 \
+        fprintf(stdout,str);                                                          \
+        fprintf(stdout,"\n");                                                         \
+      }                                                                               \
+} while(0)
+
+#else
+// No debug
+/*
+#  define log_printf(level, component, str... )                                       \
+do                                                                                    \
+{                                                                                     \
+} while(0)									      
+*/									      
+#  define log_printf(level, component, func, str... )                                 \
+do                                                                                    \
+{                                                                                     \
+} while(0)
+
+#endif // DEBUG
+
+#endif // !DEBUG_H
Index: /trunk/IPs/systemC/processor/Morpheo/Include/ErrorMorpheo.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/ErrorMorpheo.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/ErrorMorpheo.h	(revision 3)
@@ -0,0 +1,45 @@
+#ifndef morpheo_ErrorMorpheo
+#define morpheo_ErrorMorpheo
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <iostream>
+#include <exception>
+
+using namespace std;
+
+namespace morpheo              {
+
+  class ErrorMorpheo : public exception 
+  {
+    // -----[ fields ]----------------------------------------------------
+  private : string _msg;
+    
+    // -----[ methods ]---------------------------------------------------
+  public  :             ErrorMorpheo  ()           throw() { _msg = "Exception detected ...";}
+  public  :             ErrorMorpheo  (string msg) throw() { _msg = msg;}
+  public  :             ~ErrorMorpheo (void)       throw() {}
+  public  : const char* what          ()    const  throw() { return ( _msg.c_str() );}
+
+  };
+
+  class TestMorpheo : public exception 
+  {
+    // -----[ fields ]----------------------------------------------------
+  private : string _msg;
+    
+    // -----[ methods ]---------------------------------------------------
+  public  :             TestMorpheo   ()           throw() { _msg = "Test error ...";}
+  public  :             TestMorpheo   (string msg) throw() { _msg = msg;}
+  public  :             ~TestMorpheo  (void)       throw() {}
+  public  : const char* what          ()    const  throw() { return ( _msg.c_str() );}
+  };
+
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Include/Message.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/Message.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/Message.h	(revision 3)
@@ -0,0 +1,13 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Routine of Test
+ */
+
+namespace morpheo    {
+
+#define cerr_msg   cerr << "<" << __FILE__ << "> line " << __LINE__ << " : "
+  
+}; // end namespace morpheo
Index: /trunk/IPs/systemC/processor/Morpheo/Include/Percent.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/Percent.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/Percent.h	(revision 3)
@@ -0,0 +1,20 @@
+#ifndef morpheo_Percent
+#define morpheo_Percent
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+namespace morpheo              {
+  
+  inline double percent (double   val, double   val_max) {return ((val_max == 0)?0:(100.0 * val)/val_max);}
+  inline double percent (uint32_t val, double   val_max) {return (percent(static_cast<double>(val),                    val_max ));}
+  inline double percent (double   val, uint32_t val_max) {return (percent(                    val ,static_cast<double>(val_max)));}
+  inline double percent (uint32_t val, uint32_t val_max) {return (percent(static_cast<double>(val),static_cast<double>(val_max)));}
+
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Include/Test.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/Test.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/Test.h	(revision 3)
@@ -0,0 +1,46 @@
+#ifndef TEST_H
+#define TEST_H
+
+#include <iostream>
+#include <sstream>
+#include <stdint.h>
+#include "Include/ErrorMorpheo.h"
+using namespace std;
+
+//-----[ Routine de test ]---------------------------------------
+
+static uint32_t num_test;
+
+template <class T>
+void test_ko (T exp1, T exp2, char * file, uint32_t line)
+{
+  string msg = ("{"+toString(num_test)+"} : Test KO\n" +
+		" * Localisation\n"                    +
+		"   - File : "+file+"\n"               +
+		"   - Line : "+toString(line)+"\n"     +
+		" * Expression is different\n"         +
+		"   - exp1 : "+toString(exp1)+"\n"     +
+		"   - exp2 : "+toString(exp2)+"\n");
+  
+  throw (ErrorMorpheo (msg));
+};
+
+void test_ok ()
+{
+  cout << "{" << num_test << "} : Test OK" << endl;
+
+  num_test ++;
+};
+
+template <class T>
+void test(T exp1, T exp2, char * file, uint32_t line)
+{
+  if (exp1 != exp2)
+    test_ko <T> (exp1,exp2,file,line);
+  else
+    test_ok     ();
+};
+
+#define TEST(type,exp1,exp2) do { test<type> (exp1,exp2,__FILE__,__LINE__);} while(0)
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Include/ToBase2.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/ToBase2.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/ToBase2.h	(revision 3)
@@ -0,0 +1,32 @@
+#ifndef morpheo_ToBase2
+#define morpheo_ToBase2
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo              {
+
+  inline string toBase2 (uint32_t value, uint32_t size)
+  {
+    ostringstream res;
+    uint32_t      mask = 1<<(size-1);
+
+    while (mask != 0)
+      {
+	res  << ((value&mask)?'1':'0');
+	mask >>= 1;
+      }
+
+    return res.str();
+  }
+  
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Include/ToString.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/ToString.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/ToString.h	(revision 3)
@@ -0,0 +1,64 @@
+#ifndef morpheo_Tostring
+#define morpheo_Tostring
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <iosfwd>
+#include <sstream>
+#include <iomanip>
+#include <string>
+#include <limits>
+
+using std::setprecision ; 
+using std::ostringstream ; 
+using std::boolalpha ;
+
+namespace morpheo              {
+  
+  template<typename T> inline std::string toString(const T& x)
+  {
+    ostringstream out;
+    out << x;
+    return out.str();
+  }
+  
+  template<> inline std::string toString<bool>       (const bool& x)
+  {
+    ostringstream out;
+    //out << boolalpha << x;
+    out << x;
+    return out.str();
+  }
+  
+  template<> inline std::string toString<float>      (const float& x)
+  {
+    const int sigdigits = std::numeric_limits<float>::digits10;
+    ostringstream out;
+    out << setprecision(sigdigits) << x;
+    return out.str();
+  }
+  
+  template<> inline std::string toString<double>     (const double& x)
+  {
+    const int sigdigits = std::numeric_limits<double>::digits10;
+    ostringstream out;
+    out << setprecision(sigdigits) << x;
+    return out.str();
+  }
+  
+  template<> inline std::string toString<long double>(const long double& x)
+  {
+    const int sigdigits = std::numeric_limits<long double>::digits10;
+    ostringstream out;
+    out << setprecision(sigdigits) << x;
+    return out.str();
+  }
+  
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Include/Types.h
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Include/Types.h	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Include/Types.h	(revision 3)
@@ -0,0 +1,54 @@
+#ifndef morpheo_Type
+#define morpheo_Type
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include <stdint.h>
+
+namespace morpheo              {
+
+#ifdef SYSTEMC
+
+// Definition of type
+#if ( defined(SC_CLOCK) || defined(SC_INTERNAL) || defined(SC_SIGNAL) || defined(SC_REGISTER) || defined(SC_IN) || defined(SC_OUT) )
+#  error "A type is already defined"
+#endif
+
+#if ( defined(PORT_READ)     || defined(PORT_WRITE)     )
+#  error "Action is already defined"
+#endif
+#if ( defined(INTERNAL_READ) || defined(INTERNAL_WRITE) )
+#  error "Action is already defined"
+#endif
+#if ( defined(SIGNAL_READ)   || defined(SIGNAL_WRITE) )
+#  error "Action is already defined"
+#endif
+#if ( defined(REGISTER_READ) || defined(REGISTER_WRITE) )
+#  error "Action is already defined"
+#endif
+
+#define SC_CLOCK                 sc_in_clk       
+#define SC_INTERNAL(type)        type
+#define SC_SIGNAL(type)          sc_signal<type >
+#define SC_REGISTER(type)        sc_signal<type >
+#define SC_IN(type)              sc_in    <type >
+#define SC_OUT(type)             sc_out   <type >
+			         
+#define PORT_READ(sig)           sig->read()
+#define PORT_WRITE(sig,val)      sig->write(val)
+#define INTERNAL_READ(sig)       (*sig)
+#define INTERNAL_WRITE(sig,val)  (*sig) = val
+#define SIGNAL_READ(sig)         sig->read()
+#define SIGNAL_WRITE(sig,val)    sig->write(val)
+#define REGISTER_READ(sig)       sig->read()
+#define REGISTER_WRITE(sig,val)  sig->write(val)
+
+#endif  
+}; // end namespace morpheo              
+
+#endif
Index: /trunk/IPs/systemC/processor/Morpheo/Makefile
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Makefile	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Makefile	(revision 3)
@@ -0,0 +1,119 @@
+#-----[ Directory ]----------------------------------------------------
+DIR_LIB			= Library
+
+#-----[ Usual Commands ]-----------------------------------------------
+
+RM        		= rm
+ECHO			= echo -e
+CD                  	= cd
+LS              	= ls
+PWD                 	= `pwd`
+TEST			= test
+MAKE			= make -s
+BASENAME		= basename
+CAT			= cat
+MKDIR			= mkdir
+
+#-----[ Particular Commands ]------------------------------------------
+
+#-----[ Options ]------------------------------------------------------
+DIR_DOC			= Documentation/Source
+
+PREFIXE_PATH		= "."
+SUFFIXE_PATH            = ".txt"
+
+#-----[ Rules ]--------------------------------------------------------
+.PHONY			: all help
+
+all			: help
+
+doc			:
+			@$(ECHO) ""
+			@$(ECHO) "=====[ doc ]====================================="
+			@$(ECHO) ""
+			@$(MAKE) -C $(DIR_DOC) view
+
+path			:
+			@$(ECHO) ""
+			@$(ECHO) "=====[ path ]===================================="
+			@$(ECHO) "";
+			@$(ECHO) -n "+ ";
+			@$(BASENAME) $(PWD);
+			@$(ECHO) "| <Top Level>";
+			@$(ECHO) "|";
+			@$(MAKE) path_rec TAB="|    " DIR_PATH=.
+
+path_rec			:
+			@												\
+															\
+			for files in `$(LS) $(DIR_PATH)`; do								\
+			    	if $(TEST) -d $(DIR_PATH)/$$files; 							\
+				then 											\
+					$(ECHO) "$(TAB)+ $$files";							\
+															\
+					if test -f $(DIR_PATH)/$(PREFIXE_PATH)`$(BASENAME) $$files`$(SUFFIXE_PATH);	\
+					then										\
+						$(ECHO) "$(TAB)| <\c";							\
+						$(CAT) $(DIR_PATH)/$(PREFIXE_PATH)`$(BASENAME) $$files`$(SUFFIXE_PATH);	\
+						$(ECHO) ">";								\
+					else										\
+						$(ECHO) "$(TAB)| <No description>";					\
+					fi;										\
+					$(ECHO) "$(TAB)|"; 								\
+															\
+					$(MAKE) path_rec TAB="$(TAB)|    " DIR_PATH=$(DIR_PATH)/$$files;		\
+				fi;											\
+			done;
+
+#~~~~~[ Lib ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+lib 			:
+			@$(ECHO) ""
+			@$(ECHO) "=====[ lib ]====================================="
+			@$(ECHO) ""
+			@$(ECHO) " Function unimplemented"
+			@$(ECHO) ""
+			@$(ECHO) " The library is generate into the directory : $(PWD)/$(DIR_LIB)"
+
+#~~~~~[ Maintenance ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+clean 			:
+			@$(ECHO) ""
+			@$(ECHO) "=====[ clean ]==================================="
+			@$(ECHO) ""
+			@$(ECHO) "Delete     temporary files              "$(PWD)
+			@$(MAKE) clean_rec DIR_CLEAN=.
+
+#Clean recursive
+clean_rec		:
+			@$(ECHO) "Delete     temporary files in directory $(DIR_CLEAN)"
+			@$(RM) -f $(DIR_CLEAN)/*~
+			@										\
+			if $(TEST) -f $(DIR_CLEAN)/Makefile -a "$(DIR_CLEAN)" != ".";			\
+			then 										\
+		       		($(CD) $(DIR_CLEAN); $(MAKE) clean;)                    		\
+			else										\
+				for files in `$(LS) $(DIR_CLEAN)`; do					\
+				    	if $(TEST) -d $(DIR_CLEAN)/$$files; 				\
+					then 								\
+						$(MAKE) clean_rec DIR_CLEAN=$(DIR_CLEAN)/$$files;	\
+					fi;								\
+				done;									\
+			fi;
+
+#~~~~~[ Help ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+help			:
+			@$(ECHO) ""
+			@$(ECHO) "=====[ help ]===================================="
+			@$(ECHO) ""
+			@$(ECHO) " Rules              Description"
+			@$(ECHO) ""
+			@$(ECHO) " all                cf rule \"help\""
+			@$(ECHO) " clean              Delete temporary files"
+			@$(ECHO) " doc                View documentation files"
+			@$(ECHO) " lib                Generate the library to include"
+			@$(ECHO) " help               Print this message"
+			@$(ECHO) " path               Print a little description of each directory"
+			@$(ECHO) ""
+
Index: /trunk/IPs/systemC/processor/Morpheo/Script/execute.sh
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Script/execute.sh	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Script/execute.sh	(revision 3)
@@ -0,0 +1,111 @@
+#!/bin/sh
+
+declare -a COMMAND;
+declare -i CPT_OLD;
+declare -i CPT;
+declare    FILE_CMD=;
+declare    FILE_CPT=;
+declare    FILE_CPU=;
+declare    LOCK_CPT="$HOME/.lock-cpt";
+declare    LOCK_CPU="$HOME/.lock-cpu";
+    
+#-----[ lock ]----------------------------------------------
+function lock ()
+{
+    lockfile -1 $1;
+}
+
+#-----[ unlock ]--------------------------------------------
+function unlock ()
+{
+    rm -f $1;
+}
+
+#-----[ main ]----------------------------------------------
+function main ()
+{
+    # no test, because the script execute_n have make all test
+    FILE_CMD=$1;
+    FILE_CPT=$2;
+    FILE_CPU=$3;
+
+    lock   $LOCK_CPT;
+    if test ! -s $FILE_CPT; then
+	echo "0" > $FILE_CPT;
+    fi;
+    unlock $LOCK_CPT;
+
+    # lit les fichiers ligne par ligne et le place dans un tableau
+    CPT=0;
+
+    while read line; do
+	COMMAND[$CPT]="$line";
+	CPT=$(($CPT+1));
+    done < $1;
+
+    echo "  * <$$> {"`date +"%F %T"`"} is ready";
+
+    # infinite loop
+    CPT_OLD=0;
+    CPT=0;
+
+    while test 1; do
+	# Take a number
+	CPT_OLD=$CPT;
+
+	lock   $LOCK_CPT;
+	CPT=`cat $FILE_CPT`;            # read  the      index
+	echo "$(($CPT+1))" > $FILE_CPT; # write the next index
+	unlock $LOCK_CPT;
+
+	# test if this number is valid
+	if test $CPT -ge ${#COMMAND[*]}; then
+	    CPT=${#COMMAND[*]};
+	fi;
+
+	# test if between the cpt_old and cpt, there are a synchronisation command
+
+#	local -i CPT_SYNC=$CPT_OLD;
+#
+#	while test $CPT_SYNC -lt $CPT; do
+#	    if test -z "${COMMAND[$CPT_SYNC]}"; then
+#		echo "  * <$$> {"`date +"%F %T"`"} synchronisation [$CPT_SYNC]";
+#	    fi;
+#	    CPT_SYNC=$(($CPT_SYNC+1));
+#	done;
+
+	# test if this number is valid
+	if test $CPT -eq ${#COMMAND[*]}; then
+	    break;
+	fi;
+
+	# Test if command is empty !
+	if test ! -z "${COMMAND[$CPT]}"; then
+	    local CUR_DIR=$PWD;
+
+	    mkdir "Task_$CPT"       &> /dev/null;
+	    cd    "Task_$CPT"       &> /dev/null;
+	    echo "  * <$$> {"`date +"%F %T"`"} execute command [$CPT] : ${COMMAND[$CPT]}";
+	    echo "${COMMAND[$CPT]}"  >  "command";
+	    chmod +x                    "command";
+	    eval "${COMMAND[$CPT]}" &>  "output";
+	    cd    $CUR_DIR          &> /dev/null;
+	fi;
+    done;
+
+    echo "  * <$$> {"`date +"%F %T"`"} is done";
+
+    lock   $LOCK_CPU;
+    CPT=`cat $FILE_CPU`;     # read  the      index
+    CPT=$(($CPT-1));
+    echo "$CPT" > $FILE_CPU; # write the next index
+    unlock $LOCK_CPU;
+    
+    if test $CPT -eq 0; then
+	echo "  * <$$> {"`date +"%F %T"`"} All task is executed";
+	rm $FILE_CPU;
+    fi;
+}
+
+#-----[ Corps ]---------------------------------------------
+main $*;
Index: /trunk/IPs/systemC/processor/Morpheo/Script/execute_n.sh
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Script/execute_n.sh	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Script/execute_n.sh	(revision 3)
@@ -0,0 +1,96 @@
+#!/bin/sh
+
+#-----[ variable ]------------------------------------------
+declare -a COMMAND;
+declare -i NB_PROCESS;
+declare -i CPT;
+declare    FILE_CMD;
+declare    FILE_CPT;
+declare    FILE_CPU;
+declare    ID="cpu-$HOSTNAME-$$"
+
+#-----[ usage ]---------------------------------------------
+function usage ()
+{
+    echo "Usage : $0 file [ nb_process ]";
+    echo "      * file       : list of command";
+    echo "      * nb_process : number of process (default (and maximum) is the number of processor)";
+    echo "";
+    echo "Note  - This script, for each command, create a directory : Task_X (X is the number of command), and execute the command in this directory.";
+    echo "      - Two file is generate : \"output\" is the output of the execution, and \"command\" is the command lunch.";
+    echo "      - A command empty (no command on a line of file1) is a synchronisation with all process"
+    echo "      - Don't forgot the final end of line (else the last command is not executed";
+    echo "";
+    exit;
+}
+
+#-----[ nb_cpu ]--------------------------------------------
+function nb_cpu ()
+{
+    local FILE_CPUINFO=/proc/cpuinfo;
+    if test ! -f $FILE_CPUINFO; then
+	echo "\"$FILE_CPUINFO\" don't exist."
+	usage;
+    fi;
+
+    eval "$1=`grep -c \"processor\" $FILE_CPUINFO`";
+}
+
+#-----[ test_usage ]----------------------------------------
+function test_usage ()
+{
+    if test $# -ne 1 -a $# -ne 2; then
+	usage;
+    fi;
+
+    if test ! -f $1; then
+	echo "File \"$1\" don't exist";
+	usage;
+    fi;
+
+    if test ! -s $1; then
+	echo "File \"$1\" is empty";
+	usage;
+    fi;
+}
+
+#-----[ main ]----------------------------------------------
+function main ()
+{
+    nb_cpu NB_PROCESS;
+
+    test_usage $*;
+
+    if test $# -eq 2; then
+	if test $2 -lt $NB_PROCESS; then
+	    NB_PROCESS=$2;
+	fi;
+    fi;
+
+    FILE_CMD=$1;
+    FILE_CPT="$HOME/control-"`basename $1`;
+    FILE_CPU="$HOME/$ID";
+
+    echo "<$0>"                                         ;
+    echo "  * Initialisation ...."                      ;
+    echo "    - host name                : $HOSTNAME"   ;
+    echo "    - number of process        : $NB_PROCESS" ;
+
+    local -i IT_NB_PROCESS=1;
+    local -i PID=$$;
+
+    echo "$NB_PROCESS" > $FILE_CPU;
+
+    # create the same number of thread that processor
+    while test $IT_NB_PROCESS -le $NB_PROCESS; do
+	execute.sh $FILE_CMD $FILE_CPT $FILE_CPU &
+	IT_NB_PROCESS=$(($IT_NB_PROCESS+1));
+
+	if test "$$" -ne $PID; then
+	    break;
+	fi;
+    done
+}
+
+#-----[ Corps ]---------------------------------------------
+main $*;
Index: /trunk/IPs/systemC/processor/Morpheo/Script/lock.sh
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Script/lock.sh	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Script/lock.sh	(revision 3)
@@ -0,0 +1,28 @@
+#!/bin/sh
+
+#-----[ usage ]---------------------------------------------
+function usage ()
+{
+    echo "Usage   : ${0} file";
+    echo "lock file, you can see the lock at \"~/.$(basename file).lock\""
+    exit;
+}
+
+#-----[ lock ]----------------------------------------------
+function lock ()
+{
+    lockfile -1 ${1};
+}
+
+#-----[ main ]----------------------------------------------
+function main ()
+{
+    if test ${#} -ne 1 -o ! -f ${1}; then
+	usage ${*};
+    fi;
+
+    lock "${HOME}/.$(basename ${1}).lock"
+}
+
+#-----[ Corps ]---------------------------------------------
+main ${*}
Index: /trunk/IPs/systemC/processor/Morpheo/Script/log_trace.pl
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Script/log_trace.pl	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Script/log_trace.pl	(revision 3)
@@ -0,0 +1,98 @@
+#! /usr/bin/perl -w
+
+### -------------------------------------------------------------- ###
+#                                                                    #
+# File       : log_trace.pl                                          #
+# Authors    : Sroka Marek                                          #
+# Date       : 20/07/2006                                            #
+# Modif.     : 18/08/2006                                            #
+# Version    : 1.0                                                   #
+#                                                                    #
+# Origin     : this description has been developed by CAO-VLSI team  #
+#              at ASIM laboratory, University Pierre et Marie Curie  #
+#              4 Place Jussieu 75252 Paris Cedex 05 - France         #
+#                                                                    #
+### -------------------------------------------------------------- ###
+
+my $TAB1='|  ';
+my $TAB2='+--';
+
+sub usage() 
+{
+    print "usage : $0 rob_trace_file nm_file\n";
+    print "      * rob_trace_file : Trace file generate by simulation\n";
+    print "      * nm_file        : List of symbol (generate by nm)\n";
+    exit(1);
+}
+
+my $rob = $ARGV[0];
+my $nm  = $ARGV[1];
+
+if (not defined $rob) 
+{
+    usage();
+}
+
+unless (defined $nm) 
+{
+    usage();
+}
+
+my %calls=();
+my %end=();
+
+open (nm_f,$nm) or die "could not open $nm : $!\n";
+
+my $current_section;
+
+while ($line = <nm_f>) 
+{ 
+    if ($line =~ /([0-9a-f]{8}) [Tt] (.*)/) 
+    { 
+        my $addr=hex $1;
+        $calls{$addr}=$2;
+        $end{$current_section} = $addr if (defined $current_section);
+        $current_section=$addr;
+    }
+}
+
+$end{$current_section}=0xffffffff;
+
+close nm_f;
+
+my @pile  = ();
+my $depth = 0;
+open (rob_f,$rob) or die "could not open $rob : $!\n";
+
+print "[ time     ] ","depth"," ","address "," ","function\n";
+
+while (<rob_f>) 
+{
+    if (/(\d+) inst OK - \@([0-9a-f]{8})/) 
+    {
+        my $addr        = hex $2;
+        my $time        = sprintf "%-8d",$1;
+	my $print_addr  = sprintf "%-8x",$addr;
+
+        if (exists $calls{$addr}) 
+	{ 
+	    my $print_depth = sprintf "%-5d",$depth;
+	    $depth = $depth + 1;
+
+            #print "[ $time ] ",$print_depth," ",$print_addr," ",$TAB1x@pile,"[1;32m$calls{$addr}[0m\n";
+	    print "[ $time ] ",$print_depth," ",$print_addr," ",$TAB1 x(@pile-1),$TAB2,"  $calls{$addr}\n";
+            push(@pile,$addr);
+        }
+
+        while (@pile and ($addr < $pile[-1] or $addr >= $end{$pile[-1]})) 
+	{
+	    $depth = $depth - 1;
+	    my $print_depth = sprintf "%-5d",$depth;
+
+            my $end=pop(@pile);
+            #print "[ $time ] ",$print_depth," ","        "," ",$TAB2x@pile,"[0;31m$calls{$end}[0m\n";
+	    print "[ $time ] ",$print_depth," ","        "," ",$TAB1 x@pile,"  $calls{$end}\n";
+	}
+    }
+}
+close rob_f;
Index: /trunk/IPs/systemC/processor/Morpheo/Script/range.sh
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Script/range.sh	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Script/range.sh	(revision 3)
@@ -0,0 +1,58 @@
+#!/bin/sh
+
+#-----[ usage ]---------------------------------------------
+function usage ()
+{
+    echo "Usage   : $0 min max [step [iter]]";
+    echo " * min  : value minimal";
+    echo " * max  : value maximal";
+    echo " * step : step between two value. If no present, step = \"+1\"";
+    echo " * iter : choose the Nième value";
+    exit;
+}
+
+#-----[ range ]---------------------------------------------
+function range ()
+{
+    declare a=$1;
+    declare b=$2;
+    declare step=$3;
+
+    while test $a -le $b; do
+        echo $a;
+        a=$(($a $step));
+    done    
+}
+
+#-----[ range_max ]-----------------------------------------
+function range_max ()
+{
+    declare a=$1;
+    declare b=$2;
+    declare step=$3;
+    declare iter=$4;
+
+    while test $a -le $b -a $iter -gt 1; do
+	a=$(($a $step));
+	iter=$(($iter-1));
+    done;
+
+    if test $iter -eq 1; then
+	echo $a;
+    fi;
+}
+
+#-----[ main ]----------------------------------------------
+function main ()
+{
+    # create operande
+    case $# in
+	2) range $* "+1";;
+	3) range $*     ;;
+	4) range_max $* ;;
+	*) usage $*
+    esac
+}
+
+#-----[ Corps ]---------------------------------------------
+main $*
Index: /trunk/IPs/systemC/processor/Morpheo/Script/simulation.sh
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Script/simulation.sh	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Script/simulation.sh	(revision 3)
@@ -0,0 +1,114 @@
+#!/bin/sh
+
+#-----[ variable ]------------------------------------------
+declare DIR_DEFAULT_EXEC="$SOFT/SpecInt2000.or32";
+#declare DIR_DEFAULT_EXEC="$SOFT/Basic_test.or32";
+declare DIR_CONFIG="$IPS/processor/M_CPU/Configuration_files/Architecture"
+declare DIR_PLATFORMS="$PLATFORMS/Generic";
+declare DEFAULT_EXEC="$DIR_DEFAULT_EXEC/bin/soft.x";
+
+declare CONFIGURATION;
+declare EXECUTE;
+declare NB_CYCLE;
+
+#-----[ usage ]---------------------------------------------
+function usage ()
+{
+    echo "usage : $0 [config [nb_cycle [exec]]]";
+    echo "      * if config is not indicated, execute the more recent executable";
+    echo "      * nb_cycle : number of simulated cycle";
+    echo "      * if exec   is not indicated, execute \"$DEFAULT_EXEC\"";
+    exit 1;
+}
+
+#-----[ test_usage ]----------------------------------------
+function test_usage ()
+{
+    if test $# == 0 -o $# -gt 3;
+	then
+	usage;
+    fi
+}
+
+#-----[ make_arg ]------------------------------------------
+
+function make_arg ()
+{
+    local CONFIG;
+    local EXEC;
+    local CYCLE;
+# Construction du nom de la configuration
+    if [ $# -ge 1 ];
+	then
+	CONFIG="system_"$1""
+	
+    # Recompile l'executable
+	( 
+	    cd $DIR_PLATFORMS;
+
+	    make M_CPU_CONFIGURATION_DIRECTORY="$DIR_CONFIG/m_cpu_configuration_$1" \
+  		 M_CPU_CONFIGURATION_FILENAME="m_cpu_configuration.h"               \
+		 ID="$1";
+	)
+    else
+    # Test la presence du repertoire contenant les binaires
+	if test ! -d $DIR_PLATFORMS/bin;
+	    then
+	    echo "Directory don't exist : \"$DIR_PLATFORMS/bin\", you need a configuration"
+	    usage;
+	fi;
+
+	CONFIG=(`ls -t $DIR_PLATFORMS/bin/*`);
+	CONFIG=`basename ${CONFIG[0]} :`;
+    fi
+
+#nombre de cycle
+    if [ $# -ge 2 ];
+	then
+	CYCLE=$2;
+    fi;
+
+#executable
+    if [ $# -ge 3 ];
+	then
+	if [ -f $2 ];
+	    then
+	    EXEC=$2;
+	else
+	    echo "$2 : file not exist";
+	    usage;
+	fi
+    else
+	EXEC=$DEFAULT_EXEC;
+
+	(cd $DIR_DEFAULT_EXEC; make;)
+
+	if [ $? -ne 0 ]
+	    then
+	    echo "Error of compilation"
+	    exit 1;
+	fi
+    fi
+
+    eval "CONFIGURATION=$CONFIG";
+    eval "EXECUTE=$EXEC";
+    eval "NB_CYCLE=$CYCLE";
+}
+
+#-----[ main ]----------------------------------------------
+function main ()
+{
+    test_usage $*;
+    make_arg   $*;
+
+# Lancement de l'executable
+
+#OPTION=--c
+    OPTION=
+    time $DIR_PLATFORMS/bin/$CONFIGURATION $OPTION $EXECUTE $NB_CYCLE;
+    killall xtty;
+#valgrind --tool=memcheck 
+}
+
+#-----[ Corps ]---------------------------------------------
+main $*;
Index: /trunk/IPs/systemC/processor/Morpheo/Script/unlock.sh
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Script/unlock.sh	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Script/unlock.sh	(revision 3)
@@ -0,0 +1,28 @@
+#!/bin/sh
+
+#-----[ usage ]---------------------------------------------
+function usage ()
+{
+    echo "Usage   : ${0} file";
+    echo "unlock file, you can see the lock at \"~/.$(basename file).lock\""
+    exit;
+}
+
+#-----[ unlock ]--------------------------------------------
+function unlock ()
+{
+    rm -f ${1};
+}
+
+#-----[ main ]----------------------------------------------
+function main ()
+{
+    if test ${#} -ne 1 -o ! -f ${1}; then
+	usage ${*};
+    fi;
+
+    unlock "${HOME}/.$(basename ${1}).lock"
+}
+
+#-----[ Corps ]---------------------------------------------
+main ${*}
Index: /trunk/IPs/systemC/processor/Morpheo/Tools/Viewer/Selftest/data/syntax.xml
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Tools/Viewer/Selftest/data/syntax.xml	(revision 3)
+++ /trunk/IPs/systemC/processor/Morpheo/Tools/Viewer/Selftest/data/syntax.xml	(revision 3)
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="ISO-8859-1" ?>
+
+<!-- comment -->
+
+<description>
+
+   <entity name="..." >
+
+      <generic name="..." value="..." min="..." max="..." step="..." default="..." level="..." />
+
+      <port    name="..." localisation="..." />
+
+   </entity>
+
+   <architecture>
+
+      <component name="..." size_x="..." pos_x="..." size_y="..." pos_y="..." />
+
+         <port_map name="..." localisation="..." map_component="..." map_port="..."/>
+
+      </component>
+
+   </architecture>
+
+<description>
Index: /trunk/IPs/systemC/shared/loadexec.c
===================================================================
--- /trunk/IPs/systemC/shared/loadexec.c	(revision 3)
+++ /trunk/IPs/systemC/shared/loadexec.c	(revision 3)
@@ -0,0 +1,142 @@
+/*
+ * File       : loadexec.c
+ * Author     : Frédéric Pétrot
+ *
+ * Load an executable into an array using the GNU BFD
+ *
+ * $Log: loadexec.c,v $
+ * Revision 1.1.1.1  2006/09/24 23:09:24  kane
+ * Initalisation de l'arborescence CVS
+ *
+ * Revision 1.1  2005/09/20 20:43:43  kane
+ * Init CVS
+ *
+ * Revision 1.1  2003/03/10 10:38:05  fred
+ * Adding the bfd loader for good.
+ *
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bfd.h>
+
+#ifndef TRUE
+#define TRUE true
+#endif
+
+#ifndef FALSE
+#define FALSE false
+#endif
+
+/* Loading the sections sections of file file into the array 
+ * pointed to by emem.
+ * esize is the expected size, but it can be modified by the function if it too 
+ * small for the sections
+ * All sizes and addresses are given in bytes
+ * eoffset is the address of the section with the lowest address among
+ * all required sections.
+ * Code should be self explanatory once you've read the 230 pages of
+ * the BFD documentation :) */
+
+typedef struct raminfo {
+  void *mem;
+  unsigned int  size;
+  unsigned int  ladr;
+  unsigned int  hadr;
+  const char *file;
+  const char **sections;
+} raminfo;
+
+static void bindsection(bfd *exec, asection *sect, PTR x)
+{
+   int i;
+   raminfo *rinfo = x; 
+
+   for (i = 0; rinfo->sections[i]; i++)
+      if (!strcmp(sect->name, rinfo->sections[i]))
+         break;
+   if (!rinfo->sections[i])
+      return;
+
+   if ((sect->flags & SEC_LOAD) && !(sect->flags & SEC_IN_MEMORY)) {
+      bfd_get_section_contents(exec, sect,
+                               rinfo->mem + (sect->vma - rinfo->ladr),
+                               0, bfd_section_size(exec, sect));
+      sect->contents = rinfo->mem;
+   }
+}
+
+static void sectionssize(bfd *exec, asection *sect, PTR x)
+{
+   int i;
+   raminfo *rinfo = x; 
+
+   for (i = 0; rinfo->sections[i]; i++)
+      if (!strcmp(sect->name, rinfo->sections[i]))
+         break;
+   if (!rinfo->sections[i])
+      return;
+
+   rinfo->size += bfd_section_size(exec, sect);
+   rinfo->ladr  = sect->vma < rinfo->ladr ? sect->vma : rinfo->ladr;
+   rinfo->hadr  = sect->vma + rinfo->size > rinfo->hadr ?
+                  sect->vma + rinfo->size : rinfo->hadr;
+}
+
+void loadexec(void **emem, int *esize, int *eoffset, const char *file, const char **sections)
+{
+  bfd      *exec;
+  static   int x;
+  int      i;
+  raminfo  ringo;
+  
+   if (!x)
+      bfd_init();
+
+   exec = bfd_openr(file, NULL);
+
+   if (!exec) {
+      fprintf(stderr, "Cannot open File '%s'\n", file);
+      exit(1);
+   }
+
+   if (bfd_check_format(exec, bfd_object) != TRUE && !(exec->flags & EXEC_P)) {
+      fprintf(stderr, "File %s is not an executable file\n",
+                       bfd_get_filename(exec));
+      exit(1);
+   }
+
+#if 1
+   printf("Loading sections ");
+   for (i = 0; sections[i]; i++)
+      printf("%s%s", sections[i], sections[i+1] ? ", " : " ");
+   printf("from \"%s\"\n",bfd_get_filename(exec));
+   //printf("of executable '%s' for '%s' architecture in format '%s'\n",
+   //        bfd_get_filename(exec), bfd_printable_name(exec), exec->xvec->name);
+#endif
+
+   /* Set input parameters to bindsection */
+   ringo.file     = file;
+   ringo.sections = sections;
+   ringo.size     = 0;
+   ringo.ladr     = ~0;
+   ringo.hadr     = 0;
+   bfd_map_over_sections(exec, sectionssize, &ringo);
+   /* Get output parameters from sectionssize */
+   if (ringo.size < ringo.hadr - ringo.ladr)
+      ringo.size = ringo.hadr - ringo.ladr;
+   *esize         = ringo.size > *esize ? ringo.size : *esize;
+   *eoffset       = ringo.ladr;
+   ringo.mem      = malloc(*esize * sizeof(char));
+   /* Start over again from the start of the memory */
+   bfd_map_over_sections(exec, bindsection, &ringo);
+   /* Get output parameters from bindsection */
+
+   *emem          = ringo.mem;
+
+   if (bfd_close(exec) == FALSE) {
+      bfd_perror(exec->filename);
+      exit(1);
+   }
+}
Index: /trunk/IPs/systemC/shared/macro.h
===================================================================
--- /trunk/IPs/systemC/shared/macro.h	(revision 3)
+++ /trunk/IPs/systemC/shared/macro.h	(revision 3)
@@ -0,0 +1,9 @@
+#ifndef MACRO_H
+#define MACRO_H
+
+#include "processor/M_CPU/Include/debug.h"
+#include "processor/M_CPU/Include/log2.h"
+
+#define ERROR(msg)            do {fprintf(stderr,"<%s> : %s\n",NAME,msg);sc_stop();exit(0);} while(0);
+
+#endif // !MACRO_H
Index: /trunk/IPs/systemC/shared/mapping_memory.h
===================================================================
--- /trunk/IPs/systemC/shared/mapping_memory.h	(revision 3)
+++ /trunk/IPs/systemC/shared/mapping_memory.h	(revision 3)
@@ -0,0 +1,1 @@
+link /users/cao/kane/Project/Morpheo/Tools/newlib/libgloss/or32/include/mapping_memory.h
Index: /trunk/IPs/systemC/shared/soclib_caches_interfaces.h
===================================================================
--- /trunk/IPs/systemC/shared/soclib_caches_interfaces.h	(revision 3)
+++ /trunk/IPs/systemC/shared/soclib_caches_interfaces.h	(revision 3)
@@ -0,0 +1,622 @@
+
+/*************************************************************************************
+ * File : caches_interfaces.h
+ * Date : 27/06/2005
+ * Authors : F.Arzel
+ * Release ; V0.0
+ * It is released under the GNU Public License (hopefully).
+ * 
+ * This file defines a standard "non-blocking cache interface"; separate interfaces
+ * are defined for non-blocking instruction cache and non-blocking data cache.
+ *************************************************************************************/
+
+#ifndef CACHES_INTERFACES_H
+#define CACHES_INTERFACES_H
+
+#include <systemc.h>
+
+/*************************************************************************************
+ ********************************        Type           ******************************
+ *************************************************************************************/
+
+// ===== Type Icache =====
+#define ITYPE_READ           0  // 00
+#define ITYPE_LOCK           1  // 01
+#define ITYPE_INVALIDATE     2  // 10
+#define ITYPE_PREFETCH       3  // 11
+
+// ===== Type Dcache =====
+#define DTYPE_READ           0  // 000
+#define DTYPE_LOCK           1  // 001
+#define DTYPE_INVALIDATE     2  // 010
+#define DTYPE_PREFETCH       3  // 011
+#define DTYPE_WRITE          4  // 100
+#define DTYPE_WRITE_ACK      5  // 101
+#define DTYPE_FLUSH          6  // 110
+                                // 111
+
+// ===== Size access =====
+#define ACCESS_SIZE          2
+#define ACCESS_8             0
+#define ACCESS_16            1
+#define ACCESS_32            2
+#define ACCESS_64            3
+
+// ===== Error       =====
+#define ERR_NO               0  // 00
+#define ERR_BUS              1  // 01
+#define ERR_TLB              2  // 10
+#define ERR_UNKNOW           3  // 11
+
+// Return the number of bytes of a access
+unsigned int access_nb_bytes(sc_uint<ACCESS_SIZE> access)
+{
+  return 1<<access;
+}
+
+/*************************************************************************************
+ ********************************  ICACHE interface     ******************************
+ *************************************************************************************/
+
+/***  ICACHE signals  ***/
+
+template < unsigned short TRDID_SIZE, 
+           unsigned short PKTID_SIZE,
+           unsigned short ADDR_SIZE ,
+	   unsigned short INS_SIZE  ,
+           unsigned short NB_ICACHE  >
+
+struct ICACHE_SIGNALS
+{
+  sc_signal<bool>                   REQ_VAL;
+  sc_signal<bool>                   REQ_ACK;
+  sc_signal<sc_uint<TRDID_SIZE> >   REQ_TRDID;
+  sc_signal<sc_uint<PKTID_SIZE> >   REQ_PKTID;
+  sc_signal<sc_uint<ADDR_SIZE> >    REQ_ADDR;
+  sc_signal<sc_uint<2> >            REQ_TYPE;
+  
+  sc_signal<bool>                   RSP_VAL;
+  sc_signal<bool>                   RSP_ACK;
+  sc_signal<sc_uint<TRDID_SIZE> >   RSP_TRDID;
+  sc_signal<sc_uint<PKTID_SIZE> >   RSP_PKTID;
+  sc_signal<sc_uint<INS_SIZE> >     RSP_INS  [NB_ICACHE];
+  sc_signal<sc_uint<2> >            RSP_ERR;
+
+#ifdef NONAME_RENAME
+  void rename (char * prefixe)
+  {
+    char rename [100];
+
+    sprintf(rename,"%s_REQ_VAL"      ,prefixe);
+    REQ_VAL               .rename(rename);
+    sprintf(rename,"%s_REQ_ACK"      ,prefixe);
+    REQ_ACK               .rename(rename);
+    sprintf(rename,"%s_REQ_TRDID"    ,prefixe);
+    REQ_TRDID             .rename(rename);
+    sprintf(rename,"%s_REQ_PKTID"    ,prefixe);
+    REQ_PKTID             .rename(rename);
+    sprintf(rename,"%s_REQ_ADDR"     ,prefixe);
+    REQ_ADDR              .rename(rename);
+    sprintf(rename,"%s_REQ_TYPE"     ,prefixe);
+    REQ_TYPE              .rename(rename);
+    
+    sprintf(rename,"%s_RSP_VAL"      ,prefixe);
+    RSP_VAL               .rename(rename);
+    sprintf(rename,"%s_RSP_ACK"      ,prefixe);
+    RSP_ACK               .rename(rename);
+    sprintf(rename,"%s_RSP_TRDID"    ,prefixe);
+    RSP_TRDID             .rename(rename);
+    sprintf(rename,"%s_RSP_PKTID"    ,prefixe);
+    RSP_PKTID             .rename(rename);
+    for (unsigned int it_nb_icache = 0; it_nb_icache < NB_ICACHE; it_nb_icache ++)
+      {
+	sprintf(rename,"%s_RSP_INS  [%d]",prefixe,it_nb_icache);
+	RSP_INS [it_nb_icache].rename(rename);
+      }//it_nb_icache
+    sprintf(rename,"%s_RSP_ERR"      ,prefixe);
+    RSP_ERR               .rename(rename);
+  }
+#endif //NONAME_RENAME
+};
+
+/***  ICACHE cache ports  ***/
+
+template< unsigned short TRDID_SIZE, 
+          unsigned short PKTID_SIZE,
+          unsigned short ADDR_SIZE ,
+	  unsigned short INS_SIZE  ,
+          unsigned short NB_ICACHE >
+
+struct ICACHE_CACHE_PORTS
+{
+
+  sc_in <bool>                      REQ_VAL;
+  sc_out<bool>                      REQ_ACK;
+  sc_in <sc_uint<TRDID_SIZE> >      REQ_TRDID;
+  sc_in <sc_uint<PKTID_SIZE> >      REQ_PKTID;
+  sc_in <sc_uint<ADDR_SIZE> >       REQ_ADDR;
+  sc_in <sc_uint<2> >               REQ_TYPE;
+  
+  sc_out<bool>                      RSP_VAL;
+  sc_in <bool>                      RSP_ACK;
+  sc_out<sc_uint<TRDID_SIZE> >      RSP_TRDID;
+  sc_out<sc_uint<PKTID_SIZE> >      RSP_PKTID;
+  sc_out<sc_uint<INS_SIZE> >        RSP_INS [NB_ICACHE];
+  sc_out<sc_uint<2> >               RSP_ERR;
+
+  void operator ()
+    (ICACHE_SIGNALS<TRDID_SIZE,PKTID_SIZE,ADDR_SIZE,INS_SIZE,NB_ICACHE> &signals)
+  {
+    REQ_VAL    (signals.REQ_VAL);
+    REQ_ACK    (signals.REQ_ACK);
+    REQ_TRDID  (signals.REQ_TRDID);
+    REQ_PKTID  (signals.REQ_PKTID);     
+    REQ_ADDR   (signals.REQ_ADDR);
+    REQ_TYPE   (signals.REQ_TYPE);
+    
+    RSP_VAL    (signals.RSP_VAL);
+    RSP_ACK    (signals.RSP_ACK);
+    RSP_TRDID  (signals.RSP_TRDID);
+    RSP_PKTID  (signals.RSP_PKTID);
+    for (unsigned int i = 0; i < NB_ICACHE; i++)
+      RSP_INS[i]    (signals.RSP_INS[i]);
+    RSP_ERR    (signals.RSP_ERR);
+  };
+  
+  void operator ()
+    (ICACHE_CACHE_PORTS<TRDID_SIZE,PKTID_SIZE,ADDR_SIZE,INS_SIZE,NB_ICACHE> &ports)
+  {
+    
+    REQ_VAL    (ports.REQ_VAL);
+    REQ_ACK    (ports.REQ_ACK);
+    REQ_TRDID  (ports.REQ_TRDID);
+    REQ_PKTID  (ports.REQ_PKTID);     
+    REQ_ADDR   (ports.REQ_ADDR);
+    REQ_TYPE   (ports.REQ_TYPE);
+    
+    RSP_VAL    (ports.RSP_VAL);
+    RSP_ACK    (ports.RSP_ACK);
+    RSP_TRDID  (ports.RSP_TRDID);
+    RSP_PKTID  (ports.RSP_PKTID);
+    for (unsigned int i = 0; i < NB_ICACHE; i++)
+      RSP_INS[i]    (ports.RSP_INS[i]);
+    RSP_ERR    (ports.RSP_ERR);
+  };
+
+#ifdef NONAME_RENAME
+  void rename (char * prefixe)
+  {
+    char rename [100];
+
+    sprintf(rename,"%s_REQ_VAL"      ,prefixe);
+    REQ_VAL               .rename(rename);
+    sprintf(rename,"%s_REQ_ACK"      ,prefixe);
+    REQ_ACK               .rename(rename);
+    sprintf(rename,"%s_REQ_TRDID"    ,prefixe);
+    REQ_TRDID             .rename(rename);
+    sprintf(rename,"%s_REQ_PKTID"    ,prefixe);
+    REQ_PKTID             .rename(rename);
+    sprintf(rename,"%s_REQ_ADDR"     ,prefixe);
+    REQ_ADDR              .rename(rename);
+    sprintf(rename,"%s_REQ_TYPE"     ,prefixe);
+    REQ_TYPE              .rename(rename);
+    
+    sprintf(rename,"%s_RSP_VAL"      ,prefixe);
+    RSP_VAL               .rename(rename);
+    sprintf(rename,"%s_RSP_ACK"      ,prefixe);
+    RSP_ACK               .rename(rename);
+    sprintf(rename,"%s_RSP_TRDID"    ,prefixe);
+    RSP_TRDID             .rename(rename);
+    sprintf(rename,"%s_RSP_PKTID"    ,prefixe);
+    RSP_PKTID             .rename(rename);
+    for (unsigned int it_nb_icache = 0; it_nb_icache < NB_ICACHE; it_nb_icache ++)
+      {
+	sprintf(rename,"%s_RSP_INS  [%d]",prefixe,it_nb_icache);
+	RSP_INS [it_nb_icache].rename(rename);
+      }//it_nb_icache
+    sprintf(rename,"%s_RSP_ERR"      ,prefixe);
+    RSP_ERR               .rename(rename);
+  }
+#endif //NONAME_RENAME  
+};
+
+/***  ICACHE processor ports  ***/
+
+template< unsigned short TRDID_SIZE, 
+          unsigned short PKTID_SIZE,
+          unsigned short ADDR_SIZE ,
+	  unsigned short INS_SIZE  ,
+          unsigned short NB_ICACHE >
+
+struct ICACHE_PROCESSOR_PORTS
+{
+
+  sc_out<bool>                   REQ_VAL;
+  sc_in <bool>                   REQ_ACK;
+  sc_out<sc_uint<TRDID_SIZE> >   REQ_TRDID;
+  sc_out<sc_uint<PKTID_SIZE> >   REQ_PKTID;
+  sc_out<sc_uint<ADDR_SIZE> >    REQ_ADDR;
+  sc_out<sc_uint<2> >            REQ_TYPE;
+  
+  sc_in <bool>                   RSP_VAL;
+  sc_out<bool>                   RSP_ACK;
+  sc_in <sc_uint<TRDID_SIZE> >   RSP_TRDID;
+  sc_in <sc_uint<PKTID_SIZE> >   RSP_PKTID;
+  sc_in <sc_uint<INS_SIZE> >     RSP_INS [NB_ICACHE];
+  sc_in <sc_uint<2> >            RSP_ERR;
+
+  void operator ()
+    (ICACHE_SIGNALS<TRDID_SIZE,PKTID_SIZE,ADDR_SIZE,INS_SIZE,NB_ICACHE> &signals)
+  {
+    
+    REQ_VAL    (signals.REQ_VAL);
+    REQ_ACK    (signals.REQ_ACK);
+    REQ_TRDID  (signals.REQ_TRDID);
+    REQ_PKTID  (signals.REQ_PKTID);     
+    REQ_ADDR   (signals.REQ_ADDR);
+    REQ_TYPE   (signals.REQ_TYPE);
+    
+    RSP_VAL    (signals.RSP_VAL);
+    RSP_ACK    (signals.RSP_ACK);
+    RSP_TRDID  (signals.RSP_TRDID);
+    RSP_PKTID  (signals.RSP_PKTID);
+    for (unsigned int i = 0; i < NB_ICACHE; i++)
+      RSP_INS[i]    (signals.RSP_INS[i]);
+    RSP_ERR    (signals.RSP_ERR);
+    
+  };
+  
+  void operator ()
+    (ICACHE_PROCESSOR_PORTS<TRDID_SIZE,PKTID_SIZE,ADDR_SIZE,INS_SIZE,NB_ICACHE> &ports)
+  {
+    
+    REQ_VAL    (ports.REQ_VAL);
+    REQ_ACK    (ports.REQ_ACK);
+    REQ_TRDID  (ports.REQ_TRDID);
+    REQ_PKTID  (ports.REQ_PKTID);     
+    REQ_ADDR   (ports.REQ_ADDR);
+    REQ_TYPE   (ports.REQ_TYPE);
+    
+    RSP_VAL    (ports.RSP_VAL);
+    RSP_ACK    (ports.RSP_ACK);
+    RSP_TRDID  (ports.RSP_TRDID);
+    RSP_PKTID  (ports.RSP_PKTID);
+    for (unsigned int i = 0; i < NB_ICACHE; i++)
+      RSP_INS[i]    (ports.RSP_INS[i]);
+    RSP_ERR    (ports.RSP_ERR);
+    
+  };
+#ifdef NONAME_RENAME
+  void rename (char * prefixe)
+  {
+    char rename [100];
+
+    sprintf(rename,"%s_REQ_VAL"      ,prefixe);
+    REQ_VAL               .rename(rename);
+    sprintf(rename,"%s_REQ_ACK"      ,prefixe);
+    REQ_ACK               .rename(rename);
+    sprintf(rename,"%s_REQ_TRDID"    ,prefixe);
+    REQ_TRDID             .rename(rename);
+    sprintf(rename,"%s_REQ_PKTID"    ,prefixe);
+    REQ_PKTID             .rename(rename);
+    sprintf(rename,"%s_REQ_ADDR"     ,prefixe);
+    REQ_ADDR              .rename(rename);
+    sprintf(rename,"%s_REQ_TYPE"     ,prefixe);
+    REQ_TYPE              .rename(rename);
+    
+    sprintf(rename,"%s_RSP_VAL"      ,prefixe);
+    RSP_VAL               .rename(rename);
+    sprintf(rename,"%s_RSP_ACK"      ,prefixe);
+    RSP_ACK               .rename(rename);
+    sprintf(rename,"%s_RSP_TRDID"    ,prefixe);
+    RSP_TRDID             .rename(rename);
+    sprintf(rename,"%s_RSP_PKTID"    ,prefixe);
+    RSP_PKTID             .rename(rename);
+    for (unsigned int it_nb_icache = 0; it_nb_icache < NB_ICACHE; it_nb_icache ++)
+      {
+	sprintf(rename,"%s_RSP_INS  [%d]",prefixe,it_nb_icache);
+	RSP_INS [it_nb_icache].rename(rename);
+      }//it_nb_icache
+    sprintf(rename,"%s_RSP_ERR"      ,prefixe);
+    RSP_ERR               .rename(rename);
+  }
+#endif //NONAME_RENAME 
+};
+
+/*************************************************************************************
+ ********************************  DCACHE interface     ******************************
+ *************************************************************************************/
+
+/***  DCACHE signals  ***/
+
+template< unsigned short TRDID_SIZE, 
+          unsigned short PKTID_SIZE,
+          unsigned short ADDR_SIZE ,
+          unsigned short DATA_SIZE >
+
+struct DCACHE_SIGNALS
+{
+
+  sc_signal<bool>                     REQ_VAL;
+  sc_signal<bool>                     REQ_ACK;
+  sc_signal<sc_uint<TRDID_SIZE> >     REQ_TRDID;
+  sc_signal<sc_uint<PKTID_SIZE> >     REQ_PKTID;
+  sc_signal<sc_uint<ADDR_SIZE> >      REQ_ADDR;
+  sc_signal<sc_uint<3> >              REQ_TYPE;
+  sc_signal<bool>                     REQ_UNC;
+  sc_signal<sc_uint<ACCESS_SIZE> >    REQ_ACCESS;
+  sc_signal<sc_uint<DATA_SIZE> >      REQ_WDATA;
+  
+  sc_signal<bool>                     RSP_VAL;
+  sc_signal<bool>                     RSP_ACK;
+  sc_signal<sc_uint<TRDID_SIZE> >     RSP_TRDID;
+  sc_signal<sc_uint<PKTID_SIZE> >     RSP_PKTID;
+  sc_signal<sc_uint<DATA_SIZE> >      RSP_RDATA;
+  sc_signal<sc_uint<2> >              RSP_ERR;
+
+#ifdef NONAME_RENAME
+  void rename (char * prefixe)
+  {
+    char rename [100];
+
+    sprintf(rename,"%s_REQ_VAL"      ,prefixe);
+    REQ_VAL               .rename(rename);
+    sprintf(rename,"%s_REQ_ACK"      ,prefixe);
+    REQ_ACK               .rename(rename);
+    sprintf(rename,"%s_REQ_TRDID"    ,prefixe);
+    REQ_TRDID             .rename(rename);
+    sprintf(rename,"%s_REQ_PKTID"    ,prefixe);
+    REQ_PKTID             .rename(rename);
+    sprintf(rename,"%s_REQ_ADDR"     ,prefixe);
+    REQ_ADDR              .rename(rename);
+    sprintf(rename,"%s_REQ_TYPE"     ,prefixe);
+    REQ_TYPE              .rename(rename);
+    sprintf(rename,"%s_REQ_UNC"      ,prefixe);
+    REQ_UNC               .rename(rename);
+    sprintf(rename,"%s_REQ_ACCESS"   ,prefixe);
+    REQ_ACCESS            .rename(rename);
+    sprintf(rename,"%s_REQ_WDATA"    ,prefixe);
+    REQ_WDATA             .rename(rename);
+    
+    sprintf(rename,"%s_RSP_VAL"      ,prefixe);
+    RSP_VAL               .rename(rename);
+    sprintf(rename,"%s_RSP_ACK"      ,prefixe);
+    RSP_ACK               .rename(rename);
+    sprintf(rename,"%s_RSP_TRDID"    ,prefixe);
+    RSP_TRDID             .rename(rename);
+    sprintf(rename,"%s_RSP_PKTID"    ,prefixe);
+    RSP_PKTID             .rename(rename);
+    sprintf(rename,"%s_RSP_RDATA"    ,prefixe);
+    RSP_RDATA             .rename(rename);
+    sprintf(rename,"%s_RSP_ERR"      ,prefixe);
+    RSP_ERR               .rename(rename);
+  }
+#endif //NONAME_RENAME
+};
+
+/***  DCACHE cache ports  ***/
+
+template< unsigned short TRDID_SIZE, 
+          unsigned short PKTID_SIZE,
+          unsigned short ADDR_SIZE,
+          unsigned short DATA_SIZE >
+
+struct DCACHE_CACHE_PORTS
+{
+  sc_in <bool>                     REQ_VAL;
+  sc_out<bool>                     REQ_ACK;
+  sc_in <sc_uint<TRDID_SIZE> >     REQ_TRDID;
+  sc_in <sc_uint<PKTID_SIZE> >     REQ_PKTID;
+  sc_in <sc_uint<ADDR_SIZE> >      REQ_ADDR;
+  sc_in <sc_uint<3> >              REQ_TYPE;
+  sc_in <bool>                     REQ_UNC;
+  sc_in <sc_uint<ACCESS_SIZE> >    REQ_ACCESS;
+  sc_in <sc_uint<DATA_SIZE> >      REQ_WDATA;
+  
+  sc_out<bool>                     RSP_VAL;
+  sc_in <bool>                     RSP_ACK;
+  sc_out<sc_uint<TRDID_SIZE> >     RSP_TRDID;
+  sc_out<sc_uint<PKTID_SIZE> >     RSP_PKTID;
+  sc_out<sc_uint<DATA_SIZE> >      RSP_RDATA;
+  sc_out<sc_uint<2> >              RSP_ERR;
+
+  void operator ()
+    (DCACHE_SIGNALS<TRDID_SIZE,PKTID_SIZE,ADDR_SIZE,DATA_SIZE> &signals)
+  {
+    
+    REQ_VAL    (signals.REQ_VAL);
+    REQ_ACK    (signals.REQ_ACK);
+    REQ_TRDID  (signals.REQ_TRDID);
+    REQ_PKTID  (signals.REQ_PKTID);     
+    REQ_ADDR   (signals.REQ_ADDR);
+    REQ_TYPE   (signals.REQ_TYPE);
+    REQ_UNC    (signals.REQ_UNC);
+    REQ_ACCESS (signals.REQ_ACCESS);
+    REQ_WDATA  (signals.REQ_WDATA);
+    
+    RSP_VAL    (signals.RSP_VAL);
+    RSP_ACK    (signals.RSP_ACK);
+    RSP_TRDID  (signals.RSP_TRDID);
+    RSP_PKTID  (signals.RSP_PKTID);
+    RSP_RDATA  (signals.RSP_RDATA);
+    RSP_ERR    (signals.RSP_ERR);
+    
+  };
+  
+  void operator ()
+    (DCACHE_CACHE_PORTS<TRDID_SIZE,PKTID_SIZE,ADDR_SIZE,DATA_SIZE> &ports)
+  {
+    
+    REQ_VAL    (ports.REQ_VAL);
+    REQ_ACK    (ports.REQ_ACK);
+    REQ_TRDID  (ports.REQ_TRDID);
+    REQ_PKTID  (ports.REQ_PKTID);     
+    REQ_ADDR   (ports.REQ_ADDR);
+    REQ_TYPE   (ports.REQ_TYPE);
+    REQ_UNC    (ports.REQ_UNC);
+    REQ_ACCESS (ports.REQ_ACCESS);
+    REQ_WDATA  (ports.REQ_WDATA);
+    
+    RSP_VAL    (ports.RSP_VAL);
+    RSP_ACK    (ports.RSP_ACK);
+    RSP_TRDID  (ports.RSP_TRDID);
+    RSP_PKTID  (ports.RSP_PKTID);
+    RSP_RDATA  (ports.RSP_RDATA);
+    RSP_ERR    (ports.RSP_ERR);
+    
+  };
+
+#ifdef NONAME_RENAME
+  void rename (char * prefixe)
+  {
+    char rename [100];
+
+    sprintf(rename,"%s_REQ_VAL"      ,prefixe);
+    REQ_VAL               .rename(rename);
+    sprintf(rename,"%s_REQ_ACK"      ,prefixe);
+    REQ_ACK               .rename(rename);
+    sprintf(rename,"%s_REQ_TRDID"    ,prefixe);
+    REQ_TRDID             .rename(rename);
+    sprintf(rename,"%s_REQ_PKTID"    ,prefixe);
+    REQ_PKTID             .rename(rename);
+    sprintf(rename,"%s_REQ_ADDR"     ,prefixe);
+    REQ_ADDR              .rename(rename);
+    sprintf(rename,"%s_REQ_TYPE"     ,prefixe);
+    REQ_TYPE              .rename(rename);
+    sprintf(rename,"%s_REQ_UNC"      ,prefixe);
+    REQ_UNC               .rename(rename);
+    sprintf(rename,"%s_REQ_ACCESS"   ,prefixe);
+    REQ_ACCESS            .rename(rename);
+    sprintf(rename,"%s_REQ_WDATA"    ,prefixe);
+    REQ_WDATA             .rename(rename);
+    
+    sprintf(rename,"%s_RSP_VAL"      ,prefixe);
+    RSP_VAL               .rename(rename);
+    sprintf(rename,"%s_RSP_ACK"      ,prefixe);
+    RSP_ACK               .rename(rename);
+    sprintf(rename,"%s_RSP_TRDID"    ,prefixe);
+    RSP_TRDID             .rename(rename);
+    sprintf(rename,"%s_RSP_PKTID"    ,prefixe);
+    RSP_PKTID             .rename(rename);
+    sprintf(rename,"%s_RSP_RDATA"    ,prefixe);
+    RSP_RDATA             .rename(rename);
+    sprintf(rename,"%s_RSP_ERR"      ,prefixe);
+    RSP_ERR               .rename(rename);
+  }
+#endif //NONAME_RENAME  
+};
+
+/***  DCACHE processor ports  ***/
+
+template< unsigned short TRDID_SIZE, 
+          unsigned short PKTID_SIZE,
+          unsigned short ADDR_SIZE ,
+          unsigned short DATA_SIZE >
+
+struct DCACHE_PROCESSOR_PORTS
+{
+
+  sc_out<bool>                     REQ_VAL;
+  sc_in <bool>                     REQ_ACK;
+  sc_out<sc_uint<TRDID_SIZE> >     REQ_TRDID;
+  sc_out<sc_uint<PKTID_SIZE> >     REQ_PKTID;
+  sc_out<sc_uint<ADDR_SIZE> >      REQ_ADDR;
+  sc_out<sc_uint<3> >              REQ_TYPE;
+  sc_out<bool>                     REQ_UNC;
+  sc_out<sc_uint<ACCESS_SIZE> >    REQ_ACCESS;
+  sc_out<sc_uint<DATA_SIZE> >      REQ_WDATA;
+  
+  sc_in <bool>                     RSP_VAL;
+  sc_out<bool>                     RSP_ACK;
+  sc_in <sc_uint<TRDID_SIZE> >     RSP_TRDID;
+  sc_in <sc_uint<PKTID_SIZE> >     RSP_PKTID;
+  sc_in <sc_uint<DATA_SIZE> >      RSP_RDATA;
+  sc_in <sc_uint<2> >              RSP_ERR;
+
+  void operator ()
+    (DCACHE_SIGNALS<TRDID_SIZE,PKTID_SIZE,ADDR_SIZE,DATA_SIZE> &signals)
+  {
+    
+    REQ_VAL    (signals.REQ_VAL);
+    REQ_ACK    (signals.REQ_ACK);
+    REQ_TRDID  (signals.REQ_TRDID);
+    REQ_PKTID  (signals.REQ_PKTID);     
+    REQ_ADDR   (signals.REQ_ADDR);
+    REQ_TYPE   (signals.REQ_TYPE);
+    REQ_UNC    (signals.REQ_UNC);
+    REQ_ACCESS (signals.REQ_ACCESS);
+    REQ_WDATA  (signals.REQ_WDATA);
+    
+    RSP_VAL    (signals.RSP_VAL);
+    RSP_ACK    (signals.RSP_ACK);
+    RSP_TRDID  (signals.RSP_TRDID);
+    RSP_PKTID  (signals.RSP_PKTID);
+    RSP_RDATA  (signals.RSP_RDATA);
+    RSP_ERR    (signals.RSP_ERR);
+    
+  };
+  
+  void operator ()
+    (DCACHE_PROCESSOR_PORTS<TRDID_SIZE,PKTID_SIZE,ADDR_SIZE,DATA_SIZE> &ports)
+  {
+    
+    REQ_VAL    (ports.REQ_VAL);
+    REQ_ACK    (ports.REQ_ACK);
+    REQ_TRDID  (ports.REQ_TRDID);
+    REQ_PKTID  (ports.REQ_PKTID);     
+    REQ_ADDR   (ports.REQ_ADDR);
+    REQ_TYPE   (ports.REQ_TYPE);
+    REQ_UNC    (ports.REQ_UNC);
+    REQ_ACCESS (ports.REQ_ACCESS);
+    REQ_WDATA  (ports.REQ_WDATA);
+    
+    RSP_VAL    (ports.RSP_VAL);
+    RSP_ACK    (ports.RSP_ACK);
+    RSP_TRDID  (ports.RSP_TRDID);
+    RSP_PKTID  (ports.RSP_PKTID);
+    RSP_RDATA  (ports.RSP_RDATA);
+    RSP_ERR    (ports.RSP_ERR);
+    
+  };
+
+#ifdef NONAME_RENAME
+  void rename (char * prefixe)
+  {
+    char rename [100];
+
+    sprintf(rename,"%s_REQ_VAL"      ,prefixe);
+    REQ_VAL               .rename(rename);
+    sprintf(rename,"%s_REQ_ACK"      ,prefixe);
+    REQ_ACK               .rename(rename);
+    sprintf(rename,"%s_REQ_TRDID"    ,prefixe);
+    REQ_TRDID             .rename(rename);
+    sprintf(rename,"%s_REQ_PKTID"    ,prefixe);
+    REQ_PKTID             .rename(rename);
+    sprintf(rename,"%s_REQ_ADDR"     ,prefixe);
+    REQ_ADDR              .rename(rename);
+    sprintf(rename,"%s_REQ_TYPE"     ,prefixe);
+    REQ_TYPE              .rename(rename);
+    sprintf(rename,"%s_REQ_UNC"      ,prefixe);
+    REQ_UNC               .rename(rename);
+    sprintf(rename,"%s_REQ_ACCESS"   ,prefixe);
+    REQ_ACCESS            .rename(rename);
+    sprintf(rename,"%s_REQ_WDATA"    ,prefixe);
+    REQ_WDATA             .rename(rename);
+    
+    sprintf(rename,"%s_RSP_VAL"      ,prefixe);
+    RSP_VAL               .rename(rename);
+    sprintf(rename,"%s_RSP_ACK"      ,prefixe);
+    RSP_ACK               .rename(rename);
+    sprintf(rename,"%s_RSP_TRDID"    ,prefixe);
+    RSP_TRDID             .rename(rename);
+    sprintf(rename,"%s_RSP_PKTID"    ,prefixe);
+    RSP_PKTID             .rename(rename);
+    sprintf(rename,"%s_RSP_RDATA"    ,prefixe);
+    RSP_RDATA             .rename(rename);
+    sprintf(rename,"%s_RSP_ERR"      ,prefixe);
+    RSP_ERR               .rename(rename);
+  }
+#endif //NONAME_RENAME  
+};
+
+#endif
Index: /trunk/IPs/systemC/shared/soclib_generic_fifo.h
===================================================================
--- /trunk/IPs/systemC/shared/soclib_generic_fifo.h	(revision 3)
+++ /trunk/IPs/systemC/shared/soclib_generic_fifo.h	(revision 3)
@@ -0,0 +1,126 @@
+
+/**************************************************************************
+ * File : soclib_generic_fifo.h
+ * Date : 28/08/2003
+ * author : Alain Greiner 
+ * This program is released under the GNU public license
+ * Copyright : UPMC - LIP6
+ *
+ * This model describes a generic snchronous FIFO.
+ * The two parameters are the number of bit per word (NBIT) and 
+ * the number of word (NWORD)
+ * - The 4 methods init(), simple_put(), simple_get(), put_and_get()
+ * change the internal state of the FIFO, but return no data or status ! 
+ * - The 4 methods rok(), wok(), filled_status() and read() return a 
+ * status or a data, but does not change the FIFO internal state!
+***************************************************************************/
+
+#ifndef SOCLIB_GENERIC_FIFO_H
+#define SOCLIB_GENERIC_FIFO_H
+
+template <unsigned int NWORD,
+          unsigned int NBIT>
+	  
+struct soclib_generic_fifo {
+
+//////////////////////////// 
+// internal FIFO registers
+//////////////////////////// 
+
+sc_signal<sc_uint<NBIT> >	DATA[NWORD];
+sc_signal<int>			PTR;
+sc_signal<int>			PTW;
+sc_signal<int>			STATE;
+
+///////////////////////
+//  method init()
+///////////////////////
+void init()
+{
+	PTR = 0;
+	PTW = 0;
+	STATE = 0;
+}; // end init()
+
+///////////////////////
+// method filled_status()
+///////////////////////
+
+int filled_status()
+{
+  return (int)STATE;
+};
+//end filled_status()
+
+///////////////////////
+// method simple_put()
+///////////////////////
+
+void simple_put(sc_uint<NBIT> din)
+{
+	if (STATE != NWORD) { 
+		STATE = STATE + 1;
+		PTW = (PTW + 1) % NWORD;
+		DATA[PTW] = din; 
+	}
+}; // end simple_put()
+
+///////////////////////
+// method simple_get()
+///////////////////////
+void simple_get()
+{
+	if (STATE != 0) {
+		STATE = STATE - 1;
+		PTR = (PTR + 1) % NWORD;
+	}
+}; // end simple_get()
+
+//////////////////////////
+// method put_and_get()  
+//////////////////////////
+void put_and_get(sc_uint<NBIT> din)
+{
+	if (STATE == NWORD) {
+		STATE = STATE - 1;
+		PTR = (PTR + 1) % NWORD;
+	} else if (STATE == 0) {
+		STATE = STATE + 1;
+		PTW = (PTW + 1) % NWORD;
+		DATA[PTW] = din; 
+	} else {
+		PTR = (PTR + 1) % NWORD;
+		PTW = (PTW + 1) % NWORD;
+		DATA[PTW] = din; 
+	}
+}; // end put_and_get()
+
+////////////////////////
+//  method rok()
+///////////////////////
+bool rok()
+{
+	if(STATE != 0)  return(true);
+	else		return(false);
+}; // end rok()
+
+////////////////////////
+//  method wok()  
+///////////////////////
+bool wok()
+{
+	if(STATE != NWORD)  return(true);
+	else		    return(false);
+}; // end wok()
+
+////////////////////////
+//  method read()
+///////////////////////
+sc_uint<NBIT> read()
+{
+	return(DATA[PTR]);
+}; // end read()
+
+}; // end struct generic_fifo
+
+#endif
Index: /trunk/IPs/systemC/shared/soclib_segment_table.h
===================================================================
--- /trunk/IPs/systemC/shared/soclib_segment_table.h	(revision 3)
+++ /trunk/IPs/systemC/shared/soclib_segment_table.h	(revision 3)
@@ -0,0 +1,637 @@
+///////////////////////////////////////////////////////////////////////////
+// File : soclib_segment_table.h
+// Date : 08/07/2004
+// authors : François Pécheux & Alain Greiner
+//
+// Copyright : UPMC - LIP6
+// This program is released under the GNU public license
+//
+// This object is used to describe the memory mapping and address 
+// decoding scheme. It supports a two level hierarchical interconnect :
+// All VCI initiators and VCI targets share the same address space. 
+// - Several sub-systems can be interconnected thanks to a VCI ADVANCED 
+// global interconnect that can be either a micro-network, or a global system bus.
+// - Each sub-system can contain as many targets as the LSB size allows.
+// They are connected by a VCI ADVANCED local interconnect, that can be
+// a local bus, or a VCI to VCI bridge such as the TARGET_DEMUX 
+// and INITIATOR_MUX components of the SoCLib library.
+// 
+// The VCI ADDRESS is structured as follows (three fields): | MSB | LSB | OFFSET |
+// The MSB bits of the VCI ADDRESS are decoded by the global interconnect
+// to route a VCI CMD/RSP packet to a given sub-system.
+// In each sub-system, the LSB bits of the VCI ADDRESS are decoded by the
+// local interconnect to route the a VCI CMD/RSP packet to the selected target/initiator.
+//
+// If the number of bits of the LSB field is zero, a global "flat" interconnect 
+// is used, and both the VCI target index and the VCI initiator index are coded
+// on 8 bits.
+//
+// The segment table is an associative table that is organized as a 
+// list of segments. This table must be built in the system top cell.
+// 
+// Each segment descriptor contains the following fields:
+//
+// - const char		*name	  : segment name
+// - unsigned int 	base	  : base address
+// - unsigned int 	size	  : segment size (in bytes)
+// - unsigned int	globalindex	: VCI subsystem index 
+// - unsigned int	localindex	: VCI target index in the subsystem
+// - bool 		uncached  : uncached when true
+//
+// The constraints on the memory mapping are the following :
+// 
+// 1/ The system designer must define the number of bits for the address
+// MSB and LSB fields. Both numbers can be zero. (For example the number 
+// of LSB bits will be zero, in case of a "flat" VCI interconnect).
+// 
+// 2/ The (MSB | LSB) bits are indexing a "page" in the address space.
+// Several pages can be mapped to the same VCI target.
+// 
+// 3/ A segment is allocated to a VCI target, and must be contained in 
+// a single page or in several contiguous pages.
+//
+// 4/ Several segments can be mapped to the same VCI target
+// (thanks to the SOCLIB_VCI_MULTIRAM component)
+// 
+// 5/ A given page cannot contain two segments that are not
+// mapped to the same VCI target.
+// 
+// The segment table is used by most SoCLib  components :
+//
+// - The constructors of the VCI interconnect components can use it to build 
+// the ROMs implementing the routing tables 
+// - The constructors of all VCI targets use it to implement the segmentation
+// violation detection mechanism, and allocate the buffers representing 
+// the memory in case of an embedded memory component.
+// - The constructors of several processors (MIPS, SPARC) use it to build 
+// the ROM implementing the uncached table.
+///////////////////////////////////////////////////////////////////////////
+
+#ifndef SEGMENT_TABLE_H
+#define SEGMENT_TABLE_H
+
+#include <list>
+
+using namespace std;
+
+//////////////////////////////////////////////
+//	SEGMENT_TABLE_ENTRY definition
+//////////////////////////////////////////////
+
+struct SEGMENT_TABLE_ENTRY
+{
+
+private:
+
+  const char 		*name;
+  unsigned int 		base;
+  unsigned int 		size;
+  unsigned int 		globalTarget;
+  unsigned int		localTarget;
+  bool                  uncached ;
+  //-----[ SIM2OS - begin ]-----------------------------------------
+  void *                addr_alloc;
+  //-----[ SIM2OS - end   ]-----------------------------------------
+
+public:
+
+// constructor
+
+SEGMENT_TABLE_ENTRY(const char *nm ,
+		    unsigned int ba , 
+		    unsigned int sz ,
+		    unsigned int glt,
+		    unsigned int lct,
+		    bool unc
+		    )
+	{
+	name=nm;
+	base=ba;
+	size=sz;
+	globalTarget=glt;
+	localTarget=lct;
+	uncached=unc;
+  //-----[ SIM2OS - begin ]-----------------------------------------
+	addr_alloc = (void *) 0;
+  //-----[ SIM2OS - end   ]-----------------------------------------
+	}; // end constructor
+
+// basic methods
+
+void print()
+	{ 
+	printf("segment : %s , base = %.8x , size = %.8x , Global target = %d , Local Target = %d , unc = %d, addr_alloc : %.8x\n",
+	       name, base, size, globalTarget, localTarget, uncached, (unsigned int) addr_alloc);
+	};
+
+const char *getName()
+	{
+	return name;
+	};
+
+unsigned int getBase()
+	{
+	return base;
+	};
+
+unsigned int getSize()
+	{
+	return size;
+	};
+
+unsigned int getGlobalTarget()
+	{
+	return globalTarget;
+	};
+	
+unsigned int getLocalTarget()
+	{
+	return localTarget;
+	};
+
+bool getUncached()
+	{
+	return uncached;
+	};
+
+  //-----[ SIM2OS - begin ]-----------------------------------------
+  void * getAddrAlloc()
+  {
+    return addr_alloc;
+  }
+
+  void setAddrAlloc (void * addr)
+  {
+    addr_alloc = addr;
+  }
+  //-----[ SIM2OS - end   ]-----------------------------------------
+
+  };// end struct SEGMENT_TABLE_ENTRY
+
+
+//////////////////////////////////////////////////////////
+//	SegmentTable definition
+//////////////////////////////////////////////////////////
+
+using namespace std;
+
+struct SOCLIB_SEGMENT_TABLE {
+	
+private :
+
+std::list<SEGMENT_TABLE_ENTRY> 	segList;
+int 				MSBNumber;
+int 				LSBNumber;
+unsigned int			defaultTargetGlobalIndex;
+unsigned int			defaultTargetLocalIndex;
+bool 				MSBNumberCalled;
+bool 				defaultTargetCalled;
+bool				LSBNumberCalled;
+
+public :	
+
+//	CONSTRUCTOR
+
+SOCLIB_SEGMENT_TABLE()
+	{
+	MSBNumberCalled=false;
+	LSBNumberCalled=false;
+	defaultTargetCalled=false;
+	};  // end constructor 
+
+//	BASIC METHODS
+
+void setMSBNumber (int number)  
+	{
+	if ((number<0)||(number>16))
+		{
+		cerr << "ERROR in the Segment Table :" << endl ;
+		cerr << "MSB number must be in the [0..16] range !" << endl ;
+		//sc_stop();
+		}
+		MSBNumberCalled=true;
+		MSBNumber=number;
+	};
+
+void setLSBNumber (int number)  
+	{
+	if ((number<0)||(number>16))
+		{
+		cerr << "ERROR in the Segment Table :" << endl ;
+		cerr << "LSB number must be in the [0..16] range !" << endl ;
+		//sc_stop();
+		}
+		LSBNumberCalled=true;		
+		LSBNumber=number;
+	};
+
+int getMSBNumber()
+ 	{
+	return MSBNumber;
+	};
+
+int getLSBNumber()
+	{
+	return LSBNumber;
+	};
+
+void setDefaultTarget (int _defTargetGlobalIndex , int _defTargetLocalIndex)
+        {
+		defaultTargetCalled=true;
+        defaultTargetGlobalIndex=_defTargetGlobalIndex;
+        defaultTargetLocalIndex=_defTargetLocalIndex;
+        };
+
+int getdefaultTargetGlobalIndex()
+        {
+        return defaultTargetGlobalIndex;
+        };
+        
+int getdefaultTargetLocalIndex()
+		{
+		return defaultTargetLocalIndex;
+		};	
+
+void addSegment(const char *nm,
+		unsigned int ba,
+		unsigned int sz,
+		unsigned int glt,
+		unsigned int lct,
+		bool unc)
+	{
+	SEGMENT_TABLE_ENTRY *seg=new SEGMENT_TABLE_ENTRY(nm,ba,sz,glt,lct,unc);
+        segList.push_back(*seg);
+	delete seg;
+	};
+
+  //-----[ SIM2OS - begin ]-----------------------------------------
+  void setAddrAlloc(unsigned int ba  ,
+		    void *       addr)
+  {
+    std::list<SEGMENT_TABLE_ENTRY>::iterator segIterator;
+    // Scan of all list
+    for (segIterator = segList.begin() ; segIterator != segList.end() ; ++segIterator) 
+      {
+	// Find a entry match with number of base 
+	// NOTE : The memory is shared, also we can't have 2 segment with the same base
+	if (ba == (*segIterator).getBase ())
+	  {
+	    (*segIterator).setAddrAlloc(addr);
+	  }
+      }
+  };
+
+  void * getAddrAlloc(unsigned int addr)
+  {
+    std::list<SEGMENT_TABLE_ENTRY>::iterator segIterator;
+
+    // Scan of all list
+    for (segIterator = segList.begin() ; segIterator != segList.end() ; ++segIterator) 
+      {
+	unsigned int addr_min = (*segIterator).getBase ();
+	unsigned int addr_max = addr_min + (*segIterator).getSize ();
+	
+	if ((addr >= addr_min) && (addr <= addr_max))
+	  {
+	    unsigned int offset = (addr-addr_min);
+	    return (void*)((unsigned int)(*segIterator).getAddrAlloc() + offset);
+	  }
+      }
+    return NULL;
+  }
+  //-----[ SIM2OS - end   ]-----------------------------------------
+
+void print()
+	{
+	cout << "\n                 SEGMENT_TABLE\n\n" ;
+	std::list<SEGMENT_TABLE_ENTRY>::iterator iter;
+	for (iter = segList.begin() ; iter != segList.end() ; ++iter)
+		{
+		(*iter).print();
+		}
+	cout << "\n" ;
+	}
+
+void printMSBRoutingTable()
+	{
+	cout << "\n                 MSB ROUTING_TABLE\n\n" ;
+	int size = 1 << MSBNumber+LSBNumber;
+	unsigned int	*tab = new unsigned int[size];
+	initRoutingTable(tab);
+	for(int index = 0 ; index < size ; index++) {
+		if (tab[index]!=0xFFFFFFFF){
+			printf("TAB[%x] = %d\n", index, tab[index]);
+		}
+	}
+	cout << "\n" ;
+	};
+	
+void printLSBRoutingTable(int glt)
+	{
+	printf( "\n    LSB_ROUTING_TABLE OF GLOBAL TARGET :%d \n\n", glt );
+	int size = 1 << MSBNumber+LSBNumber;
+	unsigned int	*tab = new unsigned int[size];
+	initLocalRoutingTable(tab,glt);
+	for(int index = 0 ; index < size ; index++) {
+		if (tab[index]!=0xFFFFFFFF){
+			printf("TAB[%d] = %d\n", index, tab[index]);
+		}
+	}
+	cout << "\n" ;
+	};
+	
+
+
+void initRoutingTable(unsigned int* tab) {
+	if (MSBNumberCalled==false) {
+		cerr << "ERROR in initMSBRoutingTable:" << endl ;
+		cerr << "MSB number has not been defined !" << endl ;
+		//sc_stop();
+	}
+	if (LSBNumberCalled==false) {
+		cout << "WARNING in initMSBRoutingTable:" << endl ;
+		cout << "LSB number has not been defined !" << endl ;
+		cout << "it is set to 0" << endl ;
+		LSBNumberCalled=true;
+		LSBNumber=0;
+	}
+	
+	
+	if (defaultTargetCalled==false) {
+		cerr << "ERROR in initMSBRoutingTable:" << endl ;
+		cerr << "Default Target has not been defined!" << endl ;
+		//sc_stop();
+	}
+
+	int RoutingTableSize = 1 << MSBNumber+LSBNumber;
+	int PageSize         = 1 << (32 - MSBNumber - LSBNumber);
+	
+	// The 0xFFFFFFFF value means "not allocated"
+	for (int i=0 ; i < RoutingTableSize ; i++) {
+		tab[i] = 0xFFFFFFFF;
+	}
+//		printf ( " tableau rempli de 0xFFFFFFFF \n");
+
+	// loop on the segment list
+	std::list<SEGMENT_TABLE_ENTRY>::iterator seg;
+	for (seg = segList.begin() ; seg != segList.end() ; ++seg) {
+		const char    *name   = (*seg).getName();
+		unsigned int  base    = (*seg).getBase();
+		unsigned int  size    = (*seg).getSize();
+		unsigned int globalTarget  = (*seg).getGlobalTarget();
+
+		unsigned int page = base >> (32-MSBNumber - LSBNumber) ;
+		
+		for (int x = (int) size ; x > 0 ; x = x - PageSize) {		     
+			if(tab[page] != 0xFFFFFFFF) {
+		//		printf("\n page n° %x can not be added to cluster %x because it is already allocated to %x\n",page,globalTarget,tab[page]);
+				cerr << "Error in initMSBRoutingTable:" << endl ;
+				cerr << "Segment " << name << " allocated to VCI target " << globalTarget << endl;
+				cerr << "overlap another segment... or is in the same page" << endl;
+				cerr << "as another segment allocated to another VCI target" << endl;
+				//sc_stop();
+		  	} else {
+				tab[page]=globalTarget;
+				
+		//		printf("\n page n° %x allocated to cluster °%x i.e %s \n",page,tab[page],name);
+				}
+			page = page + 1;
+			} // end for x
+	} // end for seg
+	
+	// Default target
+	for (int i=0 ; i < RoutingTableSize ; i++) {
+		if(tab[i] == 0xFFFFFFFF) tab[i] = defaultTargetGlobalIndex;
+	}
+	
+};  // end initRoutingTable()
+
+////////////////////////////////////////////////////////////////
+//		initGlobalRoutingTable()
+//	This method can be used by any global VCI interconnect.
+//	It initializes the routing table that implements 
+//	the VCI address MSB bits decoding ROM.
+//	- The argument is a pointer to the int table that
+//	has been allocated by the constructor of the 
+//	VCI interconnect component.
+//	- Each entry contains a VCI target global index.
+//	The VCI local Target index is not used here
+////////////////////////////////////////////////////////////////
+
+
+void initGlobalRoutingTable(unsigned int* tab) {
+	if (MSBNumberCalled==false) {
+		cerr << "ERROR in initMSBRoutingTable:" << endl ;
+		cerr << "MSB number has not been defined !" << endl ;
+		//sc_stop();
+	}
+	
+	if (defaultTargetCalled==false) {
+		cerr << "ERROR in initMSBRoutingTable:" << endl ;
+		cerr << "Default Target has not been defined!" << endl ;
+		//sc_stop();
+	}
+
+	int RoutingTableSize = 1 << MSBNumber;
+	int PageSize         = 1 << (32 - MSBNumber);
+	
+	// The 0xFFFFFFFF value means "not allocated"
+	for (int i=0 ; i < RoutingTableSize ; i++) {
+		tab[i] = 0xFFFFFFFF;
+	}
+//		printf ( " tableau rempli de 0xFFFFFFFF \n");
+
+	// loop on the segment list
+	std::list<SEGMENT_TABLE_ENTRY>::iterator seg;
+	for (seg = segList.begin() ; seg != segList.end() ; ++seg) {
+		const char    *name   = (*seg).getName();
+		unsigned int  base    = (*seg).getBase();
+		unsigned int  size    = (*seg).getSize();
+		unsigned int globalTarget  = (*seg).getGlobalTarget();
+
+		unsigned int page = base >> (32-MSBNumber) ;
+		
+		for (int x = (int) size ; x > 0 ; x = x - PageSize) {		     
+			if(tab[page] != 0xFFFFFFFF) {
+		//		printf("\n page n° %x can not be added to cluster %x because it is already allocated to %x\n",page,globalTarget,tab[page]);
+				cerr << "Error in initGlobalRoutingTable:" << endl ;
+				cerr << "Segment " << name << " allocated to VCI target " << globalTarget << endl;
+				cerr << "overlap another segment... or is in the same page" << endl;
+				cerr << "as another segment allocated to another VCI target" << endl;
+				//sc_stop();
+		  	} else {
+				tab[page]=globalTarget;
+				
+		//		printf("\n page n° %x allocated to cluster °%x i.e %s \n",page,tab[page],name);
+				}
+			page = page + 1;
+			} // end for x
+	} // end for seg
+	
+	// Default target
+	for (int i=0 ; i < RoutingTableSize ; i++) {
+		if(tab[i] == 0xFFFFFFFF) tab[i] = defaultTargetGlobalIndex;
+	}
+	
+};  // end initGlobalRoutingTable()
+
+
+////////////////////////////////////////////////////////////////
+//		initLocalRoutingTable()
+//	This method can be used by the local VCI interconnect.
+//	It initializes the routing table that implements 
+//	the VCI address LSB bits decoding ROM.
+//	- The argument is a pointer to the char table that
+//	has been allocated by the constructor of the local 
+//	VCI interconnect component.
+//	- Each entry contains a VCI target local index as well as a global index .
+//	- This method needs a parameter : the global index of the subsystem ,
+//	because it only fills the pages corresponding to a segment in this subsystem
+//	other pages are adressed to the Default Target
+////////////////////////////////////////////////////////////////
+
+void initLocalRoutingTable(unsigned int* tab, unsigned int cluster) {
+	if (MSBNumberCalled==false) {
+		cerr << "ERROR in initLocalRoutingTable:" << endl ;
+		cerr << "MSB number has not been defined !" << endl ;
+		//sc_stop();
+	}
+		
+	if (defaultTargetCalled==false) {
+		cerr << "ERROR in initLocalRoutingTable:" << endl ;
+		cerr << "Default Target has not been defined!" << endl ;
+		//sc_stop();
+	}
+
+	int RoutingTableSize = 1 << MSBNumber+LSBNumber;
+	int PageSize         = 1 << (32 - MSBNumber - LSBNumber );
+	
+	// The 0xFF value means "not allocated"
+	for (int i=0 ; i < RoutingTableSize ; i++) {
+		tab[i] = 0xFF;
+	}
+	// printf ( " Local routing table cluster %x: tableau rempli de 0xFF \n",cluster);
+	// loop on the segment list
+	std::list<SEGMENT_TABLE_ENTRY>::iterator seg;
+	for (seg = segList.begin() ; seg != segList.end() ; ++seg) {
+		const char    *name   = (*seg).getName();
+		unsigned int  base    = (*seg).getBase();
+		unsigned int  size    = (*seg).getSize();
+		unsigned int localTarget  = (*seg).getLocalTarget();
+		unsigned int globalTarget = (*seg).getGlobalTarget();
+
+		unsigned int page = base >> (32 - MSBNumber - LSBNumber) ;
+		
+		for (int x = (int) size ; x > 0 ; x = x - PageSize) {		     
+			  if(tab[page] != 0xFF) {
+			  // printf("\n page n° %x ne peut etre adressée à target n°%x car elle est allouée à %x \n",page,localTarget,tab[page]);	
+			  cerr << "Error in initLocalRoutingTable:" << endl ;
+			  cerr << "Segment " << name << " allocated to VCI target " << localTarget << endl;
+			  cerr << "overlap another segment... or is in the same page" << endl;
+			  cerr << "as another segment allocated to another VCI target" << endl;
+			  //sc_stop();
+		  	  } else {
+		  	  	if (globalTarget==cluster){
+			  		tab[page] = localTarget;
+			  		// printf(" page n° %x adressée à target n°%x dans cluster %x i.e %s \n",page,tab[page],cluster,name);
+			  	  }
+			  page = page + 1;
+			  
+			  }
+		} 
+	} // end loop segment list
+
+	for (int i=0 ; i < RoutingTableSize ; i++) {
+		if ((tab[i]==0xFF) && (defaultTargetGlobalIndex==cluster))
+			tab[i]=defaultTargetLocalIndex;
+	}
+		
+};  // end initLocalRoutingTable()
+
+//////////////////////////////////////////////////////////////
+//		getSegmentList()
+//	returns the list of all segments 
+//	allocated to a given VCI target.
+//	This method tests both the local and global VCI target index
+//////////////////////////////////////////////////////////////
+
+std::list<SEGMENT_TABLE_ENTRY> getSegmentList(unsigned int globalIndex,unsigned int localIndex){
+	std::list<SEGMENT_TABLE_ENTRY> targetlist;
+	std::list<SEGMENT_TABLE_ENTRY>::iterator segIterator;
+	unsigned int localTarget;
+	unsigned int globalTarget;
+	
+	for (segIterator = segList.begin() ; segIterator != segList.end() ; ++segIterator) {
+		localTarget=(*segIterator).getLocalTarget();
+		globalTarget=(*segIterator).getGlobalTarget();
+		if ((localTarget==localIndex)&&(globalTarget==globalIndex)){
+			targetlist.push_back(*segIterator);
+		}
+	}
+	return(targetlist);
+	
+}; // end getSegmentList()
+
+////////////////////////////////////////////////////
+// function getTotalsegmentList
+// used to get the whole segmentlist
+///////////////////////////////////////////////////
+
+std::list<SEGMENT_TABLE_ENTRY> getTotalSegmentList()
+{
+
+return(segList);
+
+}; // end getSegmentList()
+
+////////////////////////////////////////////////////////////////
+//		initUncachedTable()
+//	This method can be used by any SoCLib processor.
+//	It initializes an "Uncached Table" that implements 
+//	the address MSB bits decoding ROM.
+//	- The argument is a pointer to the bool table that
+//	has been allocated by the constructor of the processor.
+//	- Each ROM entry contains a boolean that is true when
+//	the adress Ris to an uncached segment.
+///////////////////////////////////////////////////////////////:
+
+void initUncachedTable(bool* tab) {
+	if ((MSBNumberCalled==false)||(LSBNumberCalled==false))
+		{
+		cerr << "ERROR in initUncachedTable:" << endl ;
+		cerr << "MSB or LSB number has not been defined !" << endl ;
+		//sc_stop();
+		}
+
+	int UncachedTableSize  = 1 << (MSBNumber+LSBNumber);
+	int PageSize           = 1 << (32 - (MSBNumber + LSBNumber));
+	
+	for (int i=0 ; i < UncachedTableSize ; i++) 
+		{
+		tab[i] = true;
+		}
+
+	std::list<SEGMENT_TABLE_ENTRY>::iterator iter;
+
+	for (   iter = segList.begin() ; 
+		iter != segList.end() ; 
+		++iter)
+		{
+		unsigned int  base      = (*iter).getBase();
+		unsigned int  size      = (*iter).getSize();
+		bool          uncached  = (*iter).getUncached();
+
+		unsigned int page_index = base >> (32-((MSBNumber + LSBNumber))) ;
+
+		for (int x = (int) size ; x > 0 ; x = x - PageSize) 
+			{		     
+			tab[page_index] = uncached;
+			page_index = page_index + 1;
+			} 
+		} // end for segment list
+};  // end initUncachedTable()
+
+};  // end struct SOCLIB_SEGMENT_TABLE
+
+
+#endif
Index: /trunk/Platforms/Generic/Makefile
===================================================================
--- /trunk/Platforms/Generic/Makefile	(revision 3)
+++ /trunk/Platforms/Generic/Makefile	(revision 3)
@@ -0,0 +1,155 @@
+# Authors			: Rosière Mathieu
+# Modif.   (yyyy/mm/dd)		: 2005/04/04
+# Creation (yyyy/mm/dd) 	: 2005/04/04
+
+SIMULATOR			= systemc
+
+#--------------------------------------
+# Commands
+#--------------------------------------
+RM				= rm -fr
+ECHO				= echo
+GTKWAVE				= gtkwave
+TIME				= time
+MKDIR				= mkdir -p
+DATE				= `date +%Y%m%d-%H%M%S`
+PID				= $$$$
+CXXFILT				= c++filt
+CCACHE				=
+
+#--------------------------------------
+# Compilator
+#--------------------------------------
+CXX				= $(CCACHE) g++
+#CXX				= g++ -fprofile-arcs -ftest-coverage
+
+#DEBUG_LVL			= DEBUG_NONE
+#DEBUG_LVL			= DEBUG_INFO
+#DEBUG_LVL			= DEBUG_STAT
+#DEBUG_LVL			= DEBUG_TRACE
+#DEBUG_LVL			= DEBUG_MAX
+#DEBUG_LVL			= DEBUG_ALL
+
+DEBUG_TIME			= 
+#-DDEBUG_TIME_MIN=45000 -DDEBUG_TIME_MAX=50000
+DEBUG				= -g3
+# -DDEBUG=$(DEBUG_LVL) $(DEBUG_TIME)
+#				  -DM_CPU_COUNT_CALL_GENMEALY
+
+STAT				= 
+#-DM_CPU_STAT
+
+OPT		 		= -O3
+
+OTHER_systemc			=
+
+OTHER_systemcass		= -DNONAME_RENAME		\
+				  -ansi                       	\
+		                  -Wno-long-long              	\
+				  -DCHECK_MULTIWRITING2REGISTER
+
+OTHER_SPECIFIC			= $(OTHER_$(SIMULATOR))
+
+OTHER_COMMON			= -Wall				\
+				  -Wno-deprecated 		\
+				  -Wno-non-template-friend	\
+				  -Wno-pmf-conversions 		\
+				  -Wunused        		\
+				  -DKANE			\
+				  -D$(SIMULATOR)
+
+#				  -Wfatal-errors 		\
+
+# 		                  -pedantic                   	\
+# 				  -Werror			\
+
+OTHER				= $(OTHER_COMMON) $(OTHER_SPECIFIC)
+
+#--------------------------------------
+# variable
+#--------------------------------------
+REP_SRC				= src
+
+REP_OBJ				= obj
+REP_BIN				= bin
+REP_INC				= include
+
+# Directory to include
+INCDIR	 			= -I. -I.. 					\
+				  -I$(TOOLS)/$(SIMULATOR)/include 		\
+				  -I$(IPS) 					\
+				  -I$(REP_INC) 					\
+				  -I$(M_CPU_CONFIGURATION_DIRECTORY)
+
+LIBDIR 				= -L. -L.. 					\
+				  -L$(TOOLS)/$(SIMULATOR)/lib-$(TARGET_ARCH) 	\
+				  -L$(TOOLS)/soclib/lib 			\
+				  -L$(TOOLS)/or1k/lib 				
+
+LIBS		   		= -lm -lsystemc -lsoclib -lbfd -liberty -ldl
+# target architecture
+TARGET_ARCH	 		= linux
+
+MODULE 				= system
+EXE    				= $(REP_BIN)/$(MODULE)_$(ID)
+
+# source files
+MAIN				= main_sc
+OBJS 				= $(patsubst $(REP_SRC)/%.cpp,$(REP_OBJ)/%_$(ID).o,$(wildcard $(REP_SRC)/*.cpp))
+
+CXX_OPT				= $(DEBUG) $(STAT) $(OPT) $(OTHER)           $(INCDIR) 
+LXX_OPT                         = $(DEBUG) $(STAT) $(OPT) $(OTHER) -rdynamic $(LIBDIR)
+
+#--------------------------------------
+# Règles
+#--------------------------------------
+.SUFFIXES			: .cc .cpp .o
+
+# 2 règles : La première pour tester la présence de la date
+#            La seconde  pour générer l'executable
+
+all	 			: id
+
+all2				: test_env $(EXE)
+
+# Test créer la variable d'environnement
+id				:
+ifeq ($(origin M_CPU_CONFIGURATION_DIRECTORY), undefined)
+				$(error "variable M_CPU_CONFIGURATION_DIRECTORY is undefined");
+endif
+ifeq ($(origin M_CPU_CONFIGURATION_FILENAME), undefined)
+				$(error "variable M_CPU_CONFIGURATION_FILENAME is undefined");
+endif
+ifeq ($(origin ID), undefined)
+				@make all2 ID=$(DATE)"-"$(PID)
+else
+				@make all2
+endif
+
+# Test des variables d'environnements
+test_env			: $(M_CPU_CONFIGURATION_DIRECTORY)/$(M_CPU_CONFIGURATION_FILENAME)
+ifeq ($(origin IPS), undefined)
+				$(error "variable IPS     is undefined");
+endif
+ifeq ($(origin TOOLS), undefined)
+				$(error "variable TOOLS   is undefined");
+endif
+				@$(ECHO) "$(ID) : Create directory"
+				@$(MKDIR) $(REP_OBJ) $(REP_BIN)
+
+# Création du fichier exe
+
+$(EXE)				: $(OBJS)
+				@$(ECHO) "$(ID) : Compilation of execute"
+				$(CXX) $(LXX_OPT) -o $@    $< $(LIBS) 2>&1 | $(CXXFILT)
+
+# Fichier objet
+$(REP_OBJ)/%_$(ID).o		: $(REP_SRC)/%.cpp
+				@$(ECHO) "$(ID) : Compilation of files $@"
+				$(CXX) $(CXX_OPT) -o $@ -c $<         2>&1 | $(CXXFILT)
+
+# Maintenance
+clean 				:
+				@$(ECHO) "Delete temporary files"
+				@$(RM) $(REP_OBJ) *~ $(REP_SRC)/*~ $(REP_INC)/*~ *.trace tty*
+				@$(RM) $(REP_BIN)
Index: /trunk/Platforms/Generic/README
===================================================================
--- /trunk/Platforms/Generic/README	(revision 3)
+++ /trunk/Platforms/Generic/README	(revision 3)
@@ -0,0 +1,34 @@
+--------------------------------------------------
+ Table of contents
+--------------------------------------------------
+
+I   - Directory
+II  - Create platform
+III - Create configuration file
+III - Run platform 
+
+--------------------------------------------------
+ I   - Directory
+--------------------------------------------------
+
+include   :
+src       :
+
+--------------------------------------------------
+ II  - Create platform
+--------------------------------------------------
+
+--------------------------------------------------
+ III - Create configuration file
+--------------------------------------------------
+
+--------------------------------------------------
+ IV  - Run platform
+--------------------------------------------------
+
+0) Position environnement variable
+1) Create your platforms
+2) Create your configuration (per example : it's copy in include/m_cpu_param_configuration/m_cpu_param_sscalar.h)
+3) Erase previous compilation : > make realclean
+4) Compil platform            : > make ID="sscalar" MCPU_PARAM="include/m_cpu_param_configuration/m_cpu_param_sscalar.h"
+5) Run simulator              : > bin/system_sscalar.x 10000 $SOFT/Softwares/Debug/bin/soft.x
Index: /trunk/Platforms/Generic/src/main_sc.cpp
===================================================================
--- /trunk/Platforms/Generic/src/main_sc.cpp	(revision 3)
+++ /trunk/Platforms/Generic/src/main_sc.cpp	(revision 3)
@@ -0,0 +1,467 @@
+#include <stdio.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/time.h>
+#include <libgen.h>
+#include <systemc.h>
+#include <cmath>
+
+/*********************************************************************
+ * Inclusion des modèles
+ *********************************************************************/
+#include "shared/macro.h"
+#include "shared/soclib_caches_interfaces.h"
+#include "shared/soclib_segment_table.h"
+#include "shared/mapping_memory.h"
+/*********************************************************************
+ * Inclusion et parametrage du processeur
+ *********************************************************************/
+#include "m_cpu_configuration.h"
+#include "processor/M_CPU/Configuration/m_cpu_configuration.h"
+#include "processor/M_CPU/M_CPU.h"
+
+#include "hierarchy_memory/hierarchy_memory.h"
+
+using namespace hierarchy_memory;
+using namespace std;
+/*********************************************************************
+ * Définitions des paramètres des composants
+ *********************************************************************/
+
+#define WITH_XTTY                             false
+#define NB_CONTEXT                            (M_CPU_NB_CLUSTER * M_CPU_NB_UL * M_CPU_NB_THREAD)
+
+// Parametre du CPU dans un fichier externe
+#define ICACHE_TEMPLATE                       LOG2_M_CPU_NB_CLUSTER + LOG2_M_CPU_NB_UL + LOG2_M_CPU_NB_THREAD+1, (LOG2_M_CPU_SIZE_IFETCH_QUEUE)+1    , M_CPU_SIZE_ADDR_INST, M_CPU_SIZE_INST,M_CPU_NB_INST_FETCH
+#define DCACHE_TEMPLATE                       LOG2_M_CPU_NB_CLUSTER + LOG2_M_CPU_NB_UL + LOG2_M_CPU_NB_THREAD+1, (LOG2_M_CPU_SIZE_LOAD_STORE_QUEUE)+1, M_CPU_SIZE_ADDR_DATA, M_CPU_SIZE_DATA
+
+//#define OFFSET_NB_LINE                        (power2(NB_CONTEXT)/power2(M_CPU_NB_CLUSTER))
+#define OFFSET_NB_LINE                        1
+
+  //                                       nb_line, size_line, size_word, associativity, hit_latence, miss_penality
+#define L1_ICACHE "L1_ICACHE",(128*OFFSET_NB_LINE),        16,         4,             4,           2,             4
+#define L1_DCACHE "L1_DCACHE",(128*OFFSET_NB_LINE),        16,         4,             4,           2,             4
+#define L2_CACHE  "L2_CACHE" ,               16384,        32,         4,             8,           6,           100
+
+#define NB_IPORT                              1 
+#define NB_DPORT                              M_CPU_NB_DATA_ACCESS
+
+#define SIZE_BUFFER_IRSP                      4
+#define SIZE_BUFFER_DRSP                      4
+
+#define HIERARCHY_MEMORY_TEMPLATE             LOG2_M_CPU_NB_CLUSTER + LOG2_M_CPU_NB_UL + LOG2_M_CPU_NB_THREAD+1, (LOG2_M_CPU_SIZE_IFETCH_QUEUE)+1    , M_CPU_SIZE_ADDR_INST, M_CPU_SIZE_INST,M_CPU_NB_INST_FETCH, (LOG2_M_CPU_SIZE_LOAD_STORE_QUEUE)+1, M_CPU_SIZE_ADDR_DATA, M_CPU_SIZE_DATA
+#define MAPPING_TABLE_CLUSTER_TEMPLATE        LOG2_M_CPU_NB_UL, M_CPU_NB_UL, LOG2_M_CPU_NB_INST_SELECT, M_CPU_NB_INST_SELECT
+#define MAPPING_TABLE_UE_TEMPLATE             LOG2_M_CPU_NB_CLUSTER, M_CPU_NB_CLUSTER, LOG2_M_CPU_NB_INST_SELECT, M_CPU_NB_INST_SELECT
+#define MAPPING_TABLE_DISPATCH_TEMPLATE       LOG2_M_CPU_NB_INST_SELECT, M_CPU_NB_INST_SELECT, LOG2_M_CPU_NB_UE, M_CPU_NB_UE
+#define TYPE_TABLE_INST_L_TEMPLATE            LOG2_NB_INST_L, NB_INST_L
+
+
+/*********************************************************************
+ * Variable global
+ *********************************************************************/
+timeval                                           time_begin;
+timeval                                           time_end;
+unsigned int                                      nb_cycles_simulated = 0;
+
+/********************************************************
+ * Déclarations des composants
+ ********************************************************/
+
+UE_CONFIGURATION                                  ** ue_configuration;
+MAPPING_TABLE   <MAPPING_TABLE_CLUSTER_TEMPLATE>  ** mapping_table_cluster;
+MAPPING_TABLE   <MAPPING_TABLE_UE_TEMPLATE>        * mapping_table_ue;
+MAPPING_TABLE   <MAPPING_TABLE_DISPATCH_TEMPLATE>  * mapping_table_dispatch;
+
+TYPE_TABLE      <TYPE_TABLE_INST_L_TEMPLATE>       * type_table_inst_l;
+
+HIERARCHY_MEMORY<HIERARCHY_MEMORY_TEMPLATE>        * memory;
+M_CPU           <M_CPU_CONFIGURATION>              * m_cpu;
+
+/*********************************************************************
+ * print_time
+ *********************************************************************/
+void print_time (timeval time_begin, timeval time_end, unsigned int nb_cycles_simulated, unsigned int nb_cycles_current)
+{
+  double average = (double)(nb_cycles_simulated) / (double)(time_end.tv_sec-time_begin.tv_sec);
+
+  cout << nb_cycles_current << "\t(" << average << " cycles / seconds )" << endl;
+}
+
+/*********************************************************************
+ * clean_exit
+ *********************************************************************/
+void clean_exit ()
+{
+  sc_stop();
+
+  gettimeofday(&time_end       ,NULL);
+  print_time(time_begin,time_end,(unsigned int)sc_simulation_time()-nb_cycles_simulated,(unsigned int)sc_simulation_time());
+
+  delete memory;
+
+  for (unsigned int i = 0; i < M_CPU_NB_CLUSTER; i ++)
+    delete mapping_table_cluster[i];
+  for (unsigned int i = 0; i < M_CPU_NB_UE; i ++)
+    delete ue_configuration[i];
+  
+  delete mapping_table_ue;
+  delete mapping_table_dispatch;
+  delete type_table_inst_l;
+  
+  delete m_cpu;
+}
+
+/*********************************************************************
+ * handler_signal
+ *********************************************************************/
+void handler_signal(int signum)
+{
+  switch (signum)
+    {
+    case SIGTERM :
+    case SIGINT  :
+      {
+	perror("Stop of simulation\n");
+	clean_exit();
+	exit(2);
+	break;
+      }
+    default :
+      {
+	break;
+      }
+    }//end switch signum
+}
+
+/*********************************************************************
+ * simulation
+ *********************************************************************/
+unsigned int simulation ()
+{
+  // Test if can continue the simulation (all thread have not send the stop signal)
+  if (memory->stop() == true)
+    return 0;
+
+  cout << "How many cycle to simulate ? (0 to stop the simulation)" << endl;
+
+  int nb_cycle;
+  cin >> nb_cycle;
+
+  cout << "    ... again " << nb_cycle << " cycles" << endl;
+  return nb_cycle;
+}
+
+/*********************************************************************
+ * power2
+ *********************************************************************/
+// return the Y=2^n with 2^(n-1) < X <= 2^n
+// Warning : possible bug if X > 0x80000000
+uint32_t power2 (uint32_t x)
+{
+  uint32_t mask;
+
+  for (mask = 1; mask < x; mask <<= 1);
+
+  return mask;
+}
+
+/*********************************************************************
+ * usage
+ *********************************************************************/
+
+void usage(char * name_fct)
+{
+  cerr << "usage : " << name_fct << " filename [nb_cycle]" << endl;
+  cerr << "      * filename      : name of binary" << endl;
+  cerr << "      * nb_cycle      : number of cycle to simulate" << endl;
+  exit(1);
+}
+
+/*********************************************************************
+ * sc_main
+ *********************************************************************/
+
+int sc_main(int argc, char* argv[])
+{
+  // Trap signal
+  signal(SIGTERM, handler_signal);
+  signal(SIGINT , handler_signal);
+ 
+  if ( (argc != 2) && 
+       (argc != 3))
+    usage(argv[0]);
+
+  unsigned int nb_cycles        = 0;
+  bool         nb_cycles_define = false;
+  const char *       filename  = argv[1];
+
+  if (argc >= 3)
+    {
+      nb_cycles_define = true;
+      nb_cycles        = atoi(argv[2]);
+    }
+
+  /*********************************************************************
+   * Déclarations des variables pour la simulation
+   *********************************************************************/
+
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  sc_clock                                 CLK ("clock",1,0.5);
+  sc_signal<bool>                          NRESET;
+
+  ICACHE_SIGNALS <ICACHE_TEMPLATE>         ** icache_signals;
+  DCACHE_SIGNALS <DCACHE_TEMPLATE>         ** dcache_signals;
+
+  /********************************************************
+   * Segment table
+   ********************************************************/
+
+  log_printf(INFO,"<sc_main> Table des segments\n");
+  SOCLIB_SEGMENT_TABLE segtable;
+  segtable.setMSBNumber    (8);
+  segtable.setDefaultTarget(0,0);
+  
+  //shared data segment
+  
+  // Add a segment   :name        , address of base    , size               , global index , local index, uncache
+  segtable.addSegment("text"      , TEXT_BASE          , TEXT_SIZE          , 0            ,0           , false);
+  segtable.addSegment("data"      , DATA_CACHED_BASE   , DATA_CACHED_SIZE   , 0            ,0           , false);
+  segtable.addSegment("data_unc"  , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0            ,0           , true );
+  segtable.addSegment("stack"     , STACK_BASE         , STACK_SIZE         , 0            ,0           , false);
+  segtable.addSegment("tty"       , TTY_BASE           , TTY_SIZE           , 0            ,0           , true );
+  segtable.addSegment("sim2os"    , SIM2OS_BASE        , SIM2OS_SIZE        , 0            ,0           , true );
+  segtable.addSegment("ramlock"   , RAMLOCK_BASE       , RAMLOCK_SIZE       , 0            ,0           , true );
+  
+  /********************************************************
+   * Déclaration des signaux
+   ********************************************************/
+  log_printf(INFO,"<sc_main> Déclaration des signaux\n");
+  icache_signals    = new ICACHE_SIGNALS     <ICACHE_TEMPLATE> * [M_CPU_NB_CLUSTER];
+  dcache_signals    = new DCACHE_SIGNALS     <DCACHE_TEMPLATE> * [M_CPU_NB_CLUSTER];
+  
+  
+  for (unsigned int it_m_cpu_nb_cluster = 0; it_m_cpu_nb_cluster < M_CPU_NB_CLUSTER; it_m_cpu_nb_cluster ++)
+    {
+      icache_signals [it_m_cpu_nb_cluster] = new ICACHE_SIGNALS <ICACHE_TEMPLATE> [NB_IPORT];
+      dcache_signals [it_m_cpu_nb_cluster] = new DCACHE_SIGNALS <DCACHE_TEMPLATE> [NB_DPORT];
+    }
+  
+  /********************************************************
+   * Déclaration des composants
+   ********************************************************/
+  
+  log_printf(INFO,"<sc_main> Déclaration des composants\n");
+  
+  // UE_CONFIGURATION
+  
+  ue_configuration        = new UE_CONFIGURATION * [M_CPU_NB_UE];
+  for (unsigned int i = 0; i < M_CPU_NB_UE; i ++)
+    {
+      std::ostringstream name_ue_configuration;
+      name_ue_configuration << "ue_configuration[" << i << "]";
+      ue_configuration[i]     = new UE_CONFIGURATION                                       (name_ue_configuration.str().c_str());
+    }
+  
+  // MAPPING_TABLE (CLUSTER)
+  
+  mapping_table_cluster    = new MAPPING_TABLE <MAPPING_TABLE_CLUSTER_TEMPLATE> * [M_CPU_NB_CLUSTER];
+  for (unsigned int i = 0; i < (M_CPU_NB_CLUSTER); i ++)
+    {
+      std::ostringstream name_mapping_table_cluster;
+      name_mapping_table_cluster << "mapping_table_cluster[" << i << "]";
+      mapping_table_cluster[i] = new MAPPING_TABLE <MAPPING_TABLE_CLUSTER_TEMPLATE> (name_mapping_table_cluster.str().c_str());
+    }
+  
+  // MAPPING_TABLE (UE)
+  std::ostringstream name_mapping_table_ue;
+  name_mapping_table_ue << "mapping_table_ue";
+  mapping_table_ue = new MAPPING_TABLE <MAPPING_TABLE_UE_TEMPLATE>   (name_mapping_table_ue.str().c_str());
+  
+  // MAPPING_TABLE (DISPATCH)
+  std::ostringstream name_mapping_table_dispatch;
+  name_mapping_table_dispatch << "mapping_table_dispatch";
+  mapping_table_dispatch = new MAPPING_TABLE <MAPPING_TABLE_DISPATCH_TEMPLATE>   (name_mapping_table_dispatch.str().c_str());
+  
+  std::ostringstream name_type_table_inst_l;
+  name_type_table_inst_l << "type_table_inst_l";
+  
+  type_table_inst_l = new TYPE_TABLE <TYPE_TABLE_INST_L_TEMPLATE>   (name_type_table_inst_l.str().c_str());
+  
+  // initialisation of internal structure
+  ini_ue_configuration       (ue_configuration);
+  ini_mapping_table_cluster  (mapping_table_cluster);
+  ini_mapping_table_ue       (mapping_table_ue);
+  ini_mapping_table_dispatch (mapping_table_dispatch);
+  ini_type_table_inst_l      (type_table_inst_l);
+
+  // ----- SYSTEM MEMORY -----
+
+  char * name_tty [NB_CONTEXT];
+
+  for (uint32_t num_context = 0; num_context < NB_CONTEXT; num_context ++)
+    {
+      std::ostringstream name_one_tty;
+      name_one_tty << "tty_" << num_context;
+
+      unsigned int size_name = strlen(name_one_tty.str().c_str())+1;
+      name_tty [num_context] = new char [size_name];
+      strncpy(name_tty [num_context],name_one_tty.str().c_str(),size_name);      
+    }
+  
+  param_entity_t<tty::param_t>     param_tty     [1] = {param_entity_t<tty::param_t>     (TTY_BASE    , TTY_SIZE    , tty::param_t ("tty"   , NB_CONTEXT, name_tty,WITH_XTTY))};
+  param_entity_t<ramlock::param_t> param_ramlock [1] = {param_entity_t<ramlock::param_t> (RAMLOCK_BASE, RAMLOCK_SIZE, ramlock::param_t("ramlock", RAMLOCK_SIZE))};
+  param_entity_t<sim2os::param_t>  param_sim2os      =  param_entity_t<sim2os::param_t>  (SIM2OS_BASE, SIM2OS_SIZE, sim2os::param_t("sim2os",&segtable));
+
+  param_cache_t                    param_icache           [1] = { param_cache_t (L1_ICACHE) };
+  param_cache_t                    param_dcache           [1] = { param_cache_t (L1_DCACHE) };
+  param_cache_t                    param_scache           [1] = { param_cache_t (L2_CACHE)};
+
+  cache::cache_multilevel::param_t param_icache_dedicated [M_CPU_NB_CLUSTER];
+  cache::cache_multilevel::param_t param_dcache_dedicated [M_CPU_NB_CLUSTER];
+
+  for (uint32_t num_cluster = 0; num_cluster < M_CPU_NB_CLUSTER; num_cluster ++)
+    {
+      std::ostringstream name_icache_dedicated;
+      name_icache_dedicated << "icache_dedicated[" << num_cluster << "]";
+      
+      param_icache_dedicated [num_cluster] = cache::cache_multilevel::param_t (name_icache_dedicated.str().c_str(),1, NB_IPORT, param_icache);
+      
+      std::ostringstream name_dcache_dedicated;
+      name_dcache_dedicated << "dcache_dedicated[" << num_cluster << "]";
+      param_dcache_dedicated [num_cluster] = cache::cache_multilevel::param_t (name_dcache_dedicated.str().c_str(),1, NB_DPORT, param_dcache);
+    }
+  			    
+  cache::cache_multilevel::param_t param_cache_shared   ("param_cache_shared",1, M_CPU_NB_CLUSTER*(NB_IPORT+NB_DPORT), param_scache);
+
+  cache::param_t                   param_cache ("cache"               ,
+						M_CPU_NB_CLUSTER            ,
+						param_icache_dedicated,
+						param_dcache_dedicated,
+						param_cache_shared    );
+
+  std::ostringstream name_memory;
+  name_memory << basename(argv[0]) << "_memory";
+  memory   = new HIERARCHY_MEMORY <HIERARCHY_MEMORY_TEMPLATE> (name_memory.str().c_str() ,
+							       0               ,
+							       0               ,
+							       &segtable       ,
+							       M_CPU_NB_CLUSTER,
+							       NB_CONTEXT      ,
+							       SIZE_BUFFER_IRSP,
+							       SIZE_BUFFER_DRSP,
+							       hierarchy_memory::param_t(1,param_tty,
+											 1,param_ramlock,
+											 param_sim2os,
+											 param_cache)
+							       );
+  
+  std::ostringstream name_m_cpu;
+  name_m_cpu << basename(argv[0]) << "_m_cpu";
+  m_cpu              = new M_CPU            <M_CPU_CONFIGURATION>       (name_m_cpu.str().c_str() ,
+									 ue_configuration         ,
+									 mapping_table_cluster    ,
+									 mapping_table_ue         ,
+									 mapping_table_dispatch   ,
+									 type_table_inst_l        ,
+									 M_CPU_PARAMETER_USE
+									 );
+  //////////////////////////////////////////////////////////
+  //	Segments Initialisation
+  //////////////////////////////////////////////////////////
+  
+  log_printf(INFO,"<sc_main> Table des segments : initialisation\n");
+  
+  const char	*sections_text  []  = {".text",NULL}; 
+  const char 	*sections_data  []  = {".data",".rodata",".bss",".sdata",".sbss", NULL}; 
+  const char	*sections_stack []  = {".stack",NULL}; 
+
+  memory->init("text"   , filename, sections_text);
+  memory->init("stack"  , filename, sections_stack);
+  memory->init("data"   , filename, sections_data);
+
+  segtable.print();
+
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+
+  log_printf(INFO,"<sc_main> Instanciation des composants\n");
+
+  log_printf(INFO,"<sc_main> Instanciation de l'élément \"memory\"\n");
+  memory->CLK          (CLK);
+  memory->NRESET       (NRESET);
+
+  for (uint32_t x = 0; x < M_CPU_NB_CLUSTER; x ++)
+    {
+      for (uint32_t y = 0; y < NB_IPORT; y ++)
+	memory->ICACHE[x][y] (icache_signals [x][y]);
+      for (uint32_t y = 0; y < NB_DPORT; y ++)
+	memory->DCACHE[x][y] (dcache_signals [x][y]);
+    }
+  
+  log_printf(INFO,"<sc_main> Instanciation de l'élément \"m_cpu\"\n");
+  m_cpu->CLK                   (CLK);
+  m_cpu->NRESET                (NRESET);
+  for (unsigned int it_m_cpu_nb_cluster = 0; it_m_cpu_nb_cluster < M_CPU_NB_CLUSTER; it_m_cpu_nb_cluster++)
+    {
+      m_cpu->ICACHE[it_m_cpu_nb_cluster] (icache_signals[it_m_cpu_nb_cluster][0]);
+
+      for (unsigned int it_nb_dport = 0; it_nb_dport < NB_DPORT; it_nb_dport++)
+	m_cpu->DCACHE[it_m_cpu_nb_cluster][it_nb_dport] (dcache_signals[it_m_cpu_nb_cluster][it_nb_dport]);	
+    }//end it_m_cpu_nb_cluster
+     
+  log_printf(NONE,"<sc_main> Successful Instanciation\n");
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  // Initialisation
+  sc_start(0);
+
+  // Reset
+  NRESET.write(false);
+  sc_start(5);
+  NRESET.write(true);
+
+  // Lunch the simulation
+  cout << "\n<" << argv[0] << "> Simulation : Begin\n\n" << endl;
+
+  nb_cycles_simulated = 0;
+
+  while (1)
+    {
+      unsigned int nb_cycles_simulation;
+
+      if (nb_cycles_define == true)
+	{
+	  nb_cycles_simulation = nb_cycles;
+	  nb_cycles            = 0; // to stop at the next loop :D
+	}
+      else
+	nb_cycles_simulation = simulation();
+
+      if (nb_cycles_simulation == 0)
+	break;
+  
+      gettimeofday(&time_begin     ,NULL);
+      sc_start    (nb_cycles_simulation);
+      gettimeofday(&time_end       ,NULL);
+
+      nb_cycles_simulated += nb_cycles_simulation;
+      
+      print_time(time_begin,time_end,nb_cycles_simulation,(unsigned int)sc_simulation_time());
+    }
+
+  cout << "\n<" << argv[0] << "> Simulation : End\n\n"   << endl;
+
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+  clean_exit ();
+
+  return 0;
+}
Index: /trunk/README
===================================================================
--- /trunk/README	(revision 3)
+++ /trunk/README	(revision 3)
@@ -0,0 +1,33 @@
+--------------------------------------------------
+ Table of contents
+--------------------------------------------------
+
+I   - Directory
+II  - Install
+III - Use a example
+
+--------------------------------------------------
+ I   - Directory 
+--------------------------------------------------
+
+Documents : different document to explain the specific point in environnement
+IPs       : my librairy of component
+Platforms : different plateforms to instance my Ips
+Softwares : different Software to map on a plateforms
+Tools     : developement tools (compiler, simulator ...)
+
+--------------------------------------------------
+ II  - Install
+--------------------------------------------------
+
+--------------------------------------------------
+ III - Use a example
+--------------------------------------------------
+
+1) Take variable      : execute bash script "source environment.sh"
+2) Go in software     : "cd $SOC/Softwares/Debug/"
+3) Compil application : "make"
+4) Go in plateforms   : "cd $SOC/Platforms/Debug/"
+5) Compil plateforms  : "make"
+6) Run simulator      : "bin/system.x 10000 $SOFT/Softwares/Debug/bin/soft.x"
+
Index: /trunk/Softwares/Basic_test.or32/Makefile
===================================================================
--- /trunk/Softwares/Basic_test.or32/Makefile	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/Makefile	(revision 3)
@@ -0,0 +1,119 @@
+# common definition
+include			Makefile.morpheo
+
+#-----[ Directory ]---------------------------------------------------------------
+
+DIR_LOCAL    		= .
+DIR_LOCAL_C		= $(DIR_LOCAL)/src/c
+DIR_LOCAL_ASM		= $(DIR_LOCAL)/src/asm
+DIR_LOCAL_SYS		= $(DIR_LOCAL)/src/sys
+DIR_LOCAL_INC       	= $(DIR_LOCAL)/src/c/include
+
+DIR_GLOBAL     		= $(SOFT)/Global.or32
+DIR_GLOBAL_C		= $(DIR_GLOBAL)/src/c
+DIR_GLOBAL_ASM		= $(DIR_GLOBAL)/src/asm
+DIR_GLOBAL_SYS		= $(DIR_GLOBAL)/src/sys
+DIR_GLOBAL_INC       	= $(DIR_GLOBAL)/include
+
+DIR_INC			= -I$(DIR_LOCAL_INC) -I$(DIR_GLOBAL_INC)
+DIR_OBJ			= obj
+DIR_BIN			= bin
+
+EXE			= soft
+
+#-----[ Files ]-------------------------------------------------------------------
+OBJ_ASM			= $(patsubst $(DIR_LOCAL_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_LOCAL_ASM)/*.s))	\
+			  $(patsubst $(DIR_GLOBAL_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_GLOBAL_ASM)/*.s))
+OBJ_SYS			= $(patsubst $(DIR_LOCAL_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_LOCAL_SYS)/*.s))	\
+			  $(patsubst $(DIR_GLOBAL_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_GLOBAL_SYS)/*.s))
+OBJ_C           	= $(patsubst $(DIR_LOCAL_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_LOCAL_C)/*.c))		\
+			  $(patsubst $(DIR_GLOBAL_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_GLOBAL_C)/*.c))
+
+OBJ			= $(OBJ_SYS) $(OBJ_ASM) $(OBJ_C)
+
+#-----[ Rules ]-------------------------------------------------------------------
+.PRECIOUS		: $(DIR_BIN)/%.x $(DIR_OBJ)/%.o $(DIR_OBJ)/%.a
+
+all 			: test_env $(DIR_BIN)/$(EXE).x.txt
+
+$(DIR_BIN)/%.x.txt	: $(DIR_BIN)/%.x
+			@$(ECHO) "List symbols        of $*"
+			@$(NM)      $(NM_OPT)      $^ > $@.nm
+			@$(ECHO) "Display information of $*"
+			@$(OBJDUMP) $(OBJDUMP_OPT) $^ > $@
+
+$(DIR_BIN)/%.x		: $(OBJ_SYS) $(OBJ) 
+			@$(ECHO) "Linkage             of $*"
+			@$(LD) -o $@ $^ $(LD_OPT)
+
+$(DIR_OBJ)/%.o		: $(DIR_LOCAL_ASM)/%.s	
+			@$(ECHO) "Compile             of $*"
+			@$(CC) $(CC_OPT) $(DIR_INC)    -o $@   -c $^ 
+			@$(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ 
+#			@$(AS) $(AS_OPT) $^ -o $@
+
+$(DIR_OBJ)/%.o		: $(DIR_LOCAL_SYS)/%.s	
+			@$(ECHO) "Compile             of $*"
+			@$(CC) $(CC_OPT) $(DIR_INC)    -o $@   -c $^ 
+			@$(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ 
+#			@$(AS) $(AS_OPT) $^ -o $@
+
+$(DIR_OBJ)/%.o		: $(DIR_LOCAL_C)/%.c
+			@$(ECHO) "Compile             of $*"
+			@$(CC) $(CC_OPT) $(DIR_INC)    -o $@   -c $^ 
+			@$(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ 
+
+$(DIR_OBJ)/%.o		: $(DIR_GLOBAL_ASM)/%.s	
+			@$(ECHO) "Compile             of $*"
+			@$(CC) $(CC_OPT) $(DIR_INC)    -o $@   -c $^ 
+			@$(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ 
+#			@$(AS) $(AS_OPT) $^ -o $@
+
+$(DIR_OBJ)/%.o		: $(DIR_GLOBAL_SYS)/%.s	
+			@$(ECHO) "Compile             of $*"
+			@$(CC) $(CC_OPT) $(DIR_INC)    -o $@   -c $^ 
+			@$(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ 
+#			@$(AS) $(AS_OPT) $^ -o $@
+
+$(DIR_OBJ)/%.o		: $(DIR_GLOBAL_C)/%.c
+			@$(ECHO) "Compile             of $*"
+			@$(CC) $(CC_OPT) $(DIR_INC)    -o $@   -c $^ 
+			@$(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ 
+
+#-----[ Environement ]------------------------------------------------------------
+test_env		:
+# ifeq ($(origin TOOLS), undefined)
+# 			$(error "variable TOOLS is undefined");
+# endif
+# ifeq ($(origin SOFT), undefined)
+# 			$(error "variable SOFT  is undefined");
+# endif
+			@$(MKDIR) $(DIR_OBJ) $(DIR_BIN)
+
+#-----[ Maintenance ]-------------------------------------------------------------
+clean 			:
+			@$(ECHO) "Delete     temporary files              "`$(PWD)`
+			@$(RM) $(DIR_OBJ) $(DIR_BIN)
+			@$(MAKE) clean_rec DIR_CLEAN=.
+
+#Clean recursive
+clean_rec		:
+			@$(ECHO) "Delete     temporary files in directory $(DIR_CLEAN)"
+			@$(RM) -f $(DIR_CLEAN)/*~
+			@for files in `$(LS) $(DIR_CLEAN)`; do					\
+			    	if $(TEST) -d $(DIR_CLEAN)/$$files; 				\
+				then 								\
+					$(MAKE) clean_rec DIR_CLEAN=$(DIR_CLEAN)/$$files;	\
+				fi; 								\
+			done;
+
+#-----[ Help ]--------------------------------------------------------------------
+help			:
+			@$(ECHO) ""
+			@$(ECHO) "List of directive   : "
+			@$(ECHO) " * make             : Compile the software"
+			@$(ECHO) " * make clean       : Erase all files generates"
+			@$(ECHO) " * make bench_list  : View all benchmark"
+			@$(ECHO) " * make bench_exec  : Print the file \"$(FILE_BENCH)\" - it's the Workload"
+			@$(ECHO) " * make bench       : Compile the Benchmark Suite"
+			@$(ECHO) ""
Index: /trunk/Softwares/Basic_test.or32/Makefile.morpheo
===================================================================
--- /trunk/Softwares/Basic_test.or32/Makefile.morpheo	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/Makefile.morpheo	(revision 3)
@@ -0,0 +1,53 @@
+#-----[ Usual commands ]----------------------------------------------------------
+RM			= rm -fr
+MKDIR			= mkdir -p
+ECHO			= echo
+CCACHE			=
+LS			= ls
+TEST			= test
+CAT			= cat
+READ			= read
+SED			= sed
+MAKE			= make -s
+CD			= cd
+PWD			= pwd
+
+#-----[ Directory ]---------------------------------------------------------------
+DIR_LDSCRIPT		= $(TOOLS)/newlib/libgloss/or32
+
+DIR_INCLUDE		= -I$(TOOLS)/newlib/newlib/libc/include/	\
+			  -I$(TOOLS)/newlib/libgloss/or32/include/
+DIR_LIBRARY		= -L$(TOOLS)/newlib/or32-elf/newlib/ 		\
+			  -L$(TOOLS)/newlib/or32-elf/libgloss/or32/ 	\
+			  -L$(TOOLS)/or1k/lib/gcc/or32-elf/3.4.4/
+
+#-----[ To the compilation ]------------------------------------------------------
+OPTIMIZE		= -O3 -fomit-frame-pointer -fdelayed-branch -mror -mcmov -msext -mhard-mul -msoft-div -msoft-float
+#Option :
+# -fomit-frame-pointer 			: n'utilise pas le pointeur de frame
+# -fdelayed-branch   			: utilise les delayed slot
+# ON		OFF
+# -mror   	-mno-ror              	: utilisation de l'instruction l.ror
+# -mcmov   	-mno-cmov       	: utilisation de l'instruction l.cmov
+# -msext	-mno-sext		: utilisation des instructions l.extXX
+# -mhard-mul	-msoft-mul	        : utilisation du multiplieur materiel
+# -mhard-div	-msoft-div              : utilisation du diviseur materiel
+# -mhard-float	-msoft-float      	: utilisation du flottant materiel
+# -msibcall     -mno-sibcall            : Enable sibcall optimization
+# -mlogue	-mno-logue 		: Schedule pro/epi-logue.
+# -maj		-mno-aj     		: Use aligned jumps.
+
+# Tools
+CC			= $(CCACHE) or32-elf-gcc
+AS			=           or32-elf-as
+LD			=           or32-elf-ld
+OBJDUMP			=           or32-elf-objdump
+NM           		=           or32-elf-nm
+
+# Tools's option
+CC_OPT			= $(DIR_INCLUDE) $(OPTIMIZE) -Wlong-long -D__or32__ -DHAVE_LIBC -D__DYNAMIC_REENT__
+# -DHAVE_LIBC
+AS_OPT			=
+LD_OPT			= -T$(DIR_LDSCRIPT)/or32.ld $(DIR_LIBRARY)  -lor32 -lc -lor32 -lc -lm -lgcc
+OBJDUMP_OPT		= -D
+NM_OPT			= -n
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_000_none.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_000_none.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_000_none.s	(revision 3)
@@ -0,0 +1,36 @@
+/********************************************
+ * files               : asm_000_none.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/20
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                :
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.jal
+ *                         l.jr
+ ********************************************
+ */
+	.file	"asm_000_none.s"
+	.section .text
+	.align	4
+
+	.global _asm_000_none
+_asm_000_none :	
+	/* save context */
+	l.addi	r1,r1,0
+
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+	
+_asm_000_none_ok :	
+	l.addi	r11,r0,1
+_asm_000_none_ko :
+	
+	/* load context */
+	l.jr	r9
+	l.addi	r1,r1,0
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_001_add.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_001_add.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_001_add.s	(revision 3)
@@ -0,0 +1,71 @@
+/********************************************
+ * files               : asm_001_add.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/20
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : Addition
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.jal
+ *                         l.jr
+ *                         l.lwz
+ *                         l.movhi
+ *                         l.ori
+ *                         l.sfne
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_001_add.s"
+	.section .text
+	.align	4
+
+	.global _asm_001_add
+_asm_001_add :
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	 0(r1),r20
+	l.sw	 4(r1),r21
+		
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	l.add	r20,r0,r0	/* e + e = e */
+	
+	l.sfne	r20,r0
+	l.bf	_asm_001_add_ko
+	l.addi	r20,r0,1
+
+	l.addi	r21,r0,-1
+	l.add	r21,r21,r20	/* -1 + 1 */
+
+	l.sfne	r21,r0
+	l.bf	_asm_001_add_ko
+	l.movhi	r20,0xdead
+	l.ori  	r20,r0,0xbeaf
+
+	l.add	r21,r20,r0	/* X + e = X */
+	l.sfne	r21,r20
+	l.bf	_asm_001_add_ko
+	l.nop	0	
+
+	l.add	r21,r0,r20	/* e + X = X */
+	l.sfne	r21,r20
+	l.bf	_asm_001_add_ko
+	l.nop	0	
+		
+_asm_001_add_ok :	
+	l.addi	r11,r0,1
+_asm_001_add_ko :
+	
+	/* load context */
+	l.lwz	r21, 4(r1)
+	l.lwz	r20, 0(r1)
+		
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_002_addc.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_002_addc.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_002_addc.s	(revision 3)
@@ -0,0 +1,60 @@
+/********************************************
+ * files               : asm_002_addc.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/20
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : Test the carry
+ * warning             : instructions used
+ *                         l.add
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.jal
+ *                         l.jr
+ *                         l.sfne              
+ ********************************************
+ */
+	.file	"asm_002_addc.s"
+	.section .text
+	.align	4
+
+	.global _asm_002_addc
+_asm_002_addc :	
+	/* save context */
+	l.addi	r1,r1,-12
+	l.sw	0(r1),r20
+	l.sw	4(r1),r21
+	l.sw	8(r1),r22
+	/* Return is KO (default) */
+	l.and   r11,r0,r0
+
+	/*
+	 * R20 = 0x00000001
+	 * R21 = 0xFFFFFFFF
+	 * R22 = 0x00000000 and carry is set
+	 */
+	l.addi	r20,r0, 1
+	l.addi	r21,r0,-1
+	l.add	r22,r20,r21
+
+	/* Add the carry */
+	l.addc	r22,r0,r0
+	
+	l.sfne	r22,r20
+	l.bf	_asm_002_addc_ko
+	l.nop	0
+	
+_asm_002_addc_ok :	
+	l.addi	r11,r0,1
+
+_asm_002_addc_ko :
+	/* load context */
+	l.lwz	r22,8(r1)
+	l.lwz	r21,4(r1)
+	l.lwz	r20,0(r1)
+	l.jr	r9
+	l.addi	r1,r1,12
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_003_extend.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_003_extend.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_003_extend.s	(revision 3)
@@ -0,0 +1,110 @@
+/********************************************
+ * files               : asm_003_extend.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/20
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : l.extbs, l.extbz, l.exthz, l.exths
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.jal
+ *                         l.jr
+ *                         l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_003_extend.s"
+	.section .text
+	.align	4
+
+	.global _asm_003_extend
+_asm_003_extend :	
+	/* save context */
+	l.addi	r1,r1,-12
+	l.sw	0 (r1),r20
+	l.sw	4 (r1),r21
+	l.sw	8 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* WARNING  : gcc don't compile if l.extXX have not two source register */
+
+	/* step 1   : test extend byte */
+
+	/* step 1.1 : test with a variable not signed */
+
+	l.ori   r20,r0,0x007F
+
+	l.extbz	r22,r20
+	l.sfeq	r22,r20
+	l.bnf	_asm_003_extend_ko
+	l.nop	1
+
+	l.extbs	r22,r20
+	l.sfeq	r22,r20
+	l.bnf	_asm_003_extend_ko
+	l.nop	2
+	
+	/* step 1.2 : test with a varibale signed */
+	l.ori   r20,r0,0x0080
+	
+	l.movhi r21,0xFFFF
+	l.ori   r21,r21,0xFF80
+
+	l.extbz	r22,r20
+	l.sfeq	r22,r20
+	l.bnf	_asm_003_extend_ko
+	l.nop	3
+
+	l.extbs	r22,r20
+	l.sfeq	r22,r21
+	l.bnf	_asm_003_extend_ko
+	l.nop	4
+
+	/* step 2   : test extend half word */
+
+	/* step 2.1 : test with a variable not signed */
+
+	l.ori   r20,r0,0x7FFF
+
+	l.exthz	r22,r20
+	l.sfeq	r22,r20
+	l.bnf	_asm_003_extend_ko
+	l.nop	5
+
+	l.exths	r22,r20
+	l.sfeq	r22,r20
+	l.bnf	_asm_003_extend_ko
+	l.nop	6
+	
+	/* step 2.2 : test with a variable signed */
+	l.ori   r20,r0,0x8000
+	
+	l.movhi r21,0xFFFF
+	l.ori   r21,r21,0x8000
+
+	l.exthz	r22,r20
+	l.sfeq	r22,r20
+	l.bnf	_asm_003_extend_ko
+	l.nop	7
+
+	l.exths	r22,r20
+	l.sfeq	r22,r21
+	l.bnf	_asm_003_extend_ko
+	l.nop	8
+
+_asm_003_extend_ok :	
+	l.addi	r11,r0,1
+_asm_003_extend_ko :
+	
+	/* load context */
+	l.lwz	r22,8 (r1)
+	l.lwz	r21,4 (r1)
+	l.lwz	r20,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,12
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_004_sfeq.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_004_sfeq.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_004_sfeq.s	(revision 3)
@@ -0,0 +1,221 @@
+/********************************************
+ * files               : asm_004_sfeq.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sfeq
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_004_sfeq.s"
+	.section .text
+	.align	4
+
+	.global _asm_004_sfeq
+_asm_004_sfeq :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	1	0	1
+	+	+>	|	0	0	0
+	+	+<	|	0	0	0
+	+	-	|	0	0	0
+	-	-=	|	1	1	0
+	-	->	|	0	0	0
+	-	-<	|	0	0	0
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sfeq	r21,r22
+	l.bnf	_asm_004_sfeq_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfeq	r21,r22
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfeq	r21,r22
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sfeq	r21,r22
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sfeq	r21,r22
+	l.bnf	_asm_004_sfeq_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfeq	r21,r22
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfeq	r21,r22
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfeqi	r21,0x7ead
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfeqi	r21,0x7ebd
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfeqi	r21,0x7e9d
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfeqi	r21,0xdead
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfeqi	r21,0xdead
+	l.bnf	_asm_004_sfeq_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfeqi	r21,0xdebd
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfeqi	r21,0xde9d
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfeqi	r21,0x7ead
+	l.bnf	_asm_004_sfeq_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfeqi	r21,0x7ebd
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfeqi	r21,0x7e9d
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfeqi	r21,0xdead
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfeqi	r21,0xdead
+	l.bf 	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfeqi	r21,0xdebd
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfeqi	r21,0xde9d
+	l.bf	_asm_004_sfeq_ko	/* if     set :	error */
+	l.nop	7
+	
+					
+_asm_004_sfeq_ok :	
+	l.addi	r11,r0,1
+_asm_004_sfeq_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_005_sfne.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_005_sfne.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_005_sfne.s	(revision 3)
@@ -0,0 +1,221 @@
+/********************************************
+ * files               : asm_005_sfne.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sfeq
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_005_sfne.s"
+	.section .text
+	.align	4
+
+	.global _asm_005_sfne
+_asm_005_sfne :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	0	1	0
+	+	+>	|	1	1	1
+	+	+<	|	1	1	1
+	+	-	|	1	1	1
+	-	-=	|	0	0	1
+	-	->	|	1	1	1
+	-	-<	|	1	1	1
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sfne	r21,r22
+	l.bf	_asm_005_sfne_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfne	r21,r22
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfne	r21,r22
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sfne	r21,r22
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sfne	r21,r22
+	l.bf	_asm_005_sfne_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfne	r21,r22
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfne	r21,r22
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfnei	r21,0x7ead
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfnei	r21,0x7ebd
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfnei	r21,0x7e9d
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfnei	r21,0xdead
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfnei	r21,0xdead
+	l.bf 	_asm_005_sfne_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfnei	r21,0xdebd
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfnei	r21,0xde9d
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfnei	r21,0x7ead
+	l.bf	_asm_005_sfne_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfnei	r21,0x7ebd
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfnei	r21,0x7e9d
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfnei	r21,0xdead
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfnei	r21,0xdead
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfnei	r21,0xdebd
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfnei	r21,0xde9d
+	l.bnf	_asm_005_sfne_ko	/* if not set :	error */
+	l.nop	7
+	
+					
+_asm_005_sfne_ok :	
+	l.addi	r11,r0,1
+_asm_005_sfne_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_006_sfges.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_006_sfges.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_006_sfges.s	(revision 3)
@@ -0,0 +1,221 @@
+/********************************************
+ * files               : asm_006_sfges.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sfeq
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_006_sfges.s"
+	.section .text
+	.align	4
+
+	.global _asm_006_sfges
+_asm_006_sfges :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	1	0	1
+	+	+>	|	0	0	0
+	+	+<	|	1	0	1
+	+	-   	|	1	0	1
+	-	-=	|	1	1	1
+	-	->	|	0	0	1
+	-	-<	|	1	1	1
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sfges	r21,r22
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfges	r21,r22
+	l.bf	_asm_006_sfges_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfges	r21,r22
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sfges	r21,r22
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sfges	r21,r22
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfges	r21,r22
+	l.bf	_asm_006_sfges_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfges	r21,r22
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfgesi	r21,0x7ead
+	l.bf	_asm_006_sfges_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfgesi	r21,0x7ebd
+	l.bf	_asm_006_sfges_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfgesi	r21,0x7e9d
+	l.bf	_asm_006_sfges_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfgesi	r21,0xdead
+	l.bf	_asm_006_sfges_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfgesi	r21,0xdead
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfgesi	r21,0xdebd
+	l.bf	_asm_006_sfges_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfgesi	r21,0xde9d
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfgesi	r21,0x7ead
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfgesi	r21,0x7ebd
+	l.bf	_asm_006_sfges_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfgesi	r21,0x7e9d
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfgesi	r21,0xdead
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfgesi	r21,0xdead
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfgesi	r21,0xdebd
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfgesi	r21,0xde9d
+	l.bnf	_asm_006_sfges_ko	/* if not set :	error */
+	l.nop	7
+	
+					
+_asm_006_sfges_ok :	
+	l.addi	r11,r0,1
+_asm_006_sfges_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_007_sfgeu.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_007_sfgeu.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_007_sfgeu.s	(revision 3)
@@ -0,0 +1,221 @@
+/********************************************
+ * files               : asm_007_sfgeu.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sfeq
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_007_sfgeu.s"
+	.section .text
+	.align	4
+
+	.global _asm_007_sfgeu
+_asm_007_sfgeu :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	1	1	1
+	+	+>	|	0	1	0
+	+	+<	|	1	1	1
+	+	-   	|	0	0	0
+	-	-=	|	1	1	0
+	-	->	|	0	0	0
+	-	-<	|	1	1	0
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sfgeu	r21,r22
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfgeu	r21,r22
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfgeu	r21,r22
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sfgeu	r21,r22
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sfgeu	r21,r22
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfgeu	r21,r22
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfgeu	r21,r22
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfgeui	r21,0x7ead
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfgeui	r21,0x7ebd
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfgeui	r21,0x7e9d
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfgeui	r21,0xdead
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfgeui	r21,0xdead
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfgeui	r21,0xdebd
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfgeui	r21,0xde9d
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfgeui	r21,0x7ead
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfgeui	r21,0x7ebd
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfgeui	r21,0x7e9d
+	l.bnf	_asm_007_sfgeu_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfgeui	r21,0xdead
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfgeui	r21,0xdead
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfgeui	r21,0xdebd
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfgeui	r21,0xde9d
+	l.bf	_asm_007_sfgeu_ko	/* if     set :	error */
+	l.nop	7
+	
+					
+_asm_007_sfgeu_ok :	
+	l.addi	r11,r0,1
+_asm_007_sfgeu_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_008_sfgts.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_008_sfgts.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_008_sfgts.s	(revision 3)
@@ -0,0 +1,221 @@
+/********************************************
+ * files               : asm_008_sfgts.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sfeq
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_008_sfgts.s"
+	.section .text
+	.align	4
+
+	.global _asm_008_sfgts
+_asm_008_sfgts :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	0	0	0
+	+	+>	|	0	0	0
+	+	+<	|	1	0	1
+	+	-   	|	1	0	1
+	-	-=	|	0	0	1
+	-	->	|	0	0	1
+	-	-<	|	1	1	1
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sfgts	r21,r22
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfgts	r21,r22
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfgts	r21,r22
+	l.bnf	_asm_008_sfgts_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sfgts	r21,r22
+	l.bnf	_asm_008_sfgts_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sfgts	r21,r22
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfgts	r21,r22
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfgts	r21,r22
+	l.bnf	_asm_008_sfgts_ko	/* if not set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfgtsi	r21,0x7ead
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfgtsi	r21,0x7ebd
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfgtsi	r21,0x7e9d
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfgtsi	r21,0xdead
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfgtsi	r21,0xdead
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfgtsi	r21,0xdebd
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfgtsi	r21,0xde9d
+	l.bnf	_asm_008_sfgts_ko	/* if not set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfgtsi	r21,0x7ead
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfgtsi	r21,0x7ebd
+	l.bf	_asm_008_sfgts_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfgtsi	r21,0x7e9d
+	l.bnf	_asm_008_sfgts_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfgtsi	r21,0xdead
+	l.bnf	_asm_008_sfgts_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfgtsi	r21,0xdead
+	l.bnf	_asm_008_sfgts_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfgtsi	r21,0xdebd
+	l.bnf	_asm_008_sfgts_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfgtsi	r21,0xde9d
+	l.bnf	_asm_008_sfgts_ko	/* if not set :	error */
+	l.nop	7
+	
+					
+_asm_008_sfgts_ok :	
+	l.addi	r11,r0,1
+_asm_008_sfgts_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_009_sfgtu.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_009_sfgtu.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_009_sfgtu.s	(revision 3)
@@ -0,0 +1,220 @@
+/********************************************
+ * files               : asm_009_sfgtu.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sfeq
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_009_sfgtu.s"
+	.section .text
+	.align	4
+
+	.global _asm_009_sfgtu
+_asm_009_sfgtu :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	0	1	0
+	+	+>	|	0	1	0
+	+	+<	|	1	1	1
+	+	-   	|	0	0	0
+	-	-=	|	0	0	0
+	-	->	|	0	0	0
+	-	-<	|	1	1	0
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sfgtu	r21,r22
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfgtu	r21,r22
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfgtu	r21,r22
+	l.bnf	_asm_009_sfgtu_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sfgtu	r21,r22
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sfgtu	r21,r22
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfgtu	r21,r22
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfgtu	r21,r22
+	l.bnf	_asm_009_sfgtu_ko	/* if not set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfgtui	r21,0x7ead
+	l.bnf	_asm_009_sfgtu_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfgtui	r21,0x7ebd
+	l.bnf	_asm_009_sfgtu_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfgtui	r21,0x7e9d
+	l.bnf	_asm_009_sfgtu_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfgtui	r21,0xdead
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfgtui	r21,0xdead
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfgtui	r21,0xdebd
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfgtui	r21,0xde9d
+	l.bnf	_asm_009_sfgtu_ko	/* if not set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfgtui	r21,0x7ead
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfgtui	r21,0x7ebd
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfgtui	r21,0x7e9d
+	l.bnf	_asm_009_sfgtu_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfgtui	r21,0xdead
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfgtui	r21,0xdead
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfgtui	r21,0xdebd
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfgtui	r21,0xde9d
+	l.bf	_asm_009_sfgtu_ko	/* if     set :	error */
+	l.nop	7
+						
+_asm_009_sfgtu_ok :	
+	l.addi	r11,r0,1
+_asm_009_sfgtu_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_010_sfles.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_010_sfles.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_010_sfles.s	(revision 3)
@@ -0,0 +1,220 @@
+/********************************************
+ * files               : asm_010_sfles.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sfles
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_010_sfles.s"
+	.section .text
+	.align	4
+
+	.global _asm_010_sfles
+_asm_010_sfles :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	1	1	1
+	+	+>	|	1	1	1
+	+	+<	|	0	1	0
+	+	-	|	0	1	0
+	-	-=	|	1	1	0
+	-	->	|	1	1	0
+	-	-<	|	0	0	0
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sfles	r21,r22
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfles	r21,r22
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfles	r21,r22
+	l.bf	_asm_010_sfles_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sfles	r21,r22
+	l.bf	_asm_010_sfles_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sfles	r21,r22
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfles	r21,r22
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfles	r21,r22
+	l.bf	_asm_010_sfles_ko	/* if     set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sflesi	r21,0x7ead
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sflesi	r21,0x7ebd
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sflesi	r21,0x7e9d
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sflesi	r21,0xdead
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sflesi	r21,0xdead
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sflesi	r21,0xdebd
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sflesi	r21,0xde9d
+	l.bf	_asm_010_sfles_ko	/* if     set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sflesi	r21,0x7ead
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sflesi	r21,0x7ebd
+	l.bnf	_asm_010_sfles_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sflesi	r21,0x7e9d
+	l.bf	_asm_010_sfles_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sflesi	r21,0xdead
+	l.bf	_asm_010_sfles_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sflesi	r21,0xdead
+	l.bf 	_asm_010_sfles_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sflesi	r21,0xdebd
+	l.bf	_asm_010_sfles_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sflesi	r21,0xde9d
+	l.bf	_asm_010_sfles_ko	/* if     set :	error */
+	l.nop	7
+					
+_asm_010_sfles_ok :	
+	l.addi	r11,r0,1
+_asm_010_sfles_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_011_sfleu.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_011_sfleu.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_011_sfleu.s	(revision 3)
@@ -0,0 +1,220 @@
+/********************************************
+ * files               : asm_011_sfleu.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sfleu
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_011_sfleu.s"
+	.section .text
+	.align	4
+
+	.global _asm_011_sfleu
+_asm_011_sfleu :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	1	0	1
+	+	+>	|	1	0	1
+	+	+<	|	0	0	0
+	+	-	|	1	1	1
+	-	-=	|	1	1	1
+	-	->	|	1	1	1
+	-	-<	|	0	0	1
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sfleu	r21,r22
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfleu	r21,r22
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfleu	r21,r22
+	l.bf	_asm_011_sfleu_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sfleu	r21,r22
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sfleu	r21,r22
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfleu	r21,r22
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfleu	r21,r22
+	l.bf	_asm_011_sfleu_ko	/* if     set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfleui	r21,0x7ead
+	l.bf 	_asm_011_sfleu_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfleui	r21,0x7ebd
+	l.bf 	_asm_011_sfleu_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfleui	r21,0x7e9d
+	l.bf 	_asm_011_sfleu_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfleui	r21,0xdead
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfleui	r21,0xdead
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfleui	r21,0xdebd
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfleui	r21,0xde9d
+	l.bf	_asm_011_sfleu_ko	/* if     set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfleui	r21,0x7ead
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfleui	r21,0x7ebd
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfleui	r21,0x7e9d
+	l.bf	_asm_011_sfleu_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfleui	r21,0xdead
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfleui	r21,0xdead
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfleui	r21,0xdebd
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfleui	r21,0xde9d
+	l.bnf	_asm_011_sfleu_ko	/* if not set :	error */
+	l.nop	7
+					
+_asm_011_sfleu_ok :	
+	l.addi	r11,r0,1
+_asm_011_sfleu_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_012_sflts.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_012_sflts.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_012_sflts.s	(revision 3)
@@ -0,0 +1,220 @@
+/********************************************
+ * files               : asm_012_sflts.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sflts
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_012_sflts.s"
+	.section .text
+	.align	4
+
+	.global _asm_012_sflts
+_asm_012_sflts :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	0	1	0
+	+	+>	|	1	1	1
+	+	+<	|	0	1	0
+	+	-	|	0	1	0
+	-	-=	|	0	0	0
+	-	->	|	1	1	0
+	-	-<	|	0	0	0
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sflts	r21,r22
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sflts	r21,r22
+	l.bnf	_asm_012_sflts_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sflts	r21,r22
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sflts	r21,r22
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sflts	r21,r22
+	l.bf 	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sflts	r21,r22
+	l.bnf	_asm_012_sflts_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sflts	r21,r22
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfltsi	r21,0x7ead
+	l.bnf	_asm_012_sflts_ko	/* if not set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfltsi	r21,0x7ebd
+	l.bnf	_asm_012_sflts_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfltsi	r21,0x7e9d
+	l.bnf	_asm_012_sflts_ko	/* if not set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfltsi	r21,0xdead
+	l.bnf	_asm_012_sflts_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfltsi	r21,0xdead
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfltsi	r21,0xdebd
+	l.bnf	_asm_012_sflts_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfltsi	r21,0xde9d
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfltsi	r21,0x7ead
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfltsi	r21,0x7ebd
+	l.bnf	_asm_012_sflts_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfltsi	r21,0x7e9d
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfltsi	r21,0xdead
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfltsi	r21,0xdead
+	l.bf 	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfltsi	r21,0xdebd
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfltsi	r21,0xde9d
+	l.bf	_asm_012_sflts_ko	/* if     set :	error */
+	l.nop	7
+					
+_asm_012_sflts_ok :	
+	l.addi	r11,r0,1
+_asm_012_sflts_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_013_sfltu.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_013_sfltu.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_013_sfltu.s	(revision 3)
@@ -0,0 +1,220 @@
+/********************************************
+ * files               : asm_013_sfltu.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/22
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                : test l.sfltu
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.bnf
+ *                         l.movhi
+ *                         l.jal
+ *                         l.jr
+ *		           l.lwz
+ *                         l.ori
+ *                         l.sw
+ ********************************************
+ */
+	.file	"asm_013_sfltu.s"
+	.section .text
+	.align	4
+
+	.global _asm_013_sfltu
+_asm_013_sfltu :	
+	/* save context */
+	l.addi	r1,r1,-8
+	l.sw	0 (r1),r21
+	l.sw	4 (r1),r22
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Listing of test
+			|	R	I	I
+	Op1	Op2	|	F1	F2	F3
+	----------------+-------------------------------
+	+	+=	|	0	0	0
+	+	+>	|	1	0	1
+	+	+<	|	0	0	0
+	+	-	|	1	1	1
+	-	-=	|	0	0	1
+	-	->	|	1	1	1
+	-	-<	|	0	0	1
+
+	Op1 with :
+	Value on 32 bits		(result F1)
+	Value on 16 bits - extend 1	(result F2)
+	                 - extend 0	(result F3)
+	 */
+
+	/*************************/
+	/* F1 :	VALUE ON 32 BITS */
+	/*************************/
+	
+	/* Op1 : + */
+	l.movhi	r21,0x7ead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : += */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbeaf
+	
+	l.sfltu	r21,r22
+	l.bf	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfltu	r21,r22
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.movhi	r22,0x7ead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfltu	r21,r22
+	l.bf	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbeaf
+
+	l.sfltu	r21,r22
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xdead
+	l.ori   r21,r21,0xbeaf
+
+	/* Op2 : -= */
+		
+	l.sfltu	r21,r22
+	l.bf	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbfaf
+
+	l.sfltu	r21,r22
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.movhi	r22,0xdead
+	l.ori   r22,r22,0xbdaf
+
+	l.sfltu	r21,r22
+	l.bf	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	7
+
+	/************************************/
+	/* F2 :	VALUE ON 16 BITS - extend 1 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfltui	r21,0x7ead
+	l.bf 	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfltui	r21,0x7ebd
+	l.bf 	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfltui	r21,0x7e9d
+	l.bf 	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfltui	r21,0xdead
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0xFFFF
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfltui	r21,0xdead
+	l.bf	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfltui	r21,0xdebd
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfltui	r21,0xde9d
+	l.bf	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	7
+	
+	/************************************/
+	/* F3 :	VALUE ON 16 BITS - extend 0 */
+	/************************************/
+	/* Op1 : + */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0x7ead
+
+	/* Op2 : += */
+	l.sfltui	r21,0x7ead
+	l.bf	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	1
+
+	/* Op2 : +> */
+	l.sfltui	r21,0x7ebd
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	2
+	
+	/* Op2 : +< */
+	l.sfltui	r21,0x7e9d
+	l.bf	_asm_013_sfltu_ko	/* if     set :	error */
+	l.nop	3
+
+	/* Op2 : - */
+	l.sfltui	r21,0xdead
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	4
+	
+	/* Op1 : - */
+	l.movhi	r21,0x0000
+	l.ori   r21,r21,0xdead
+
+	/* Op2 : -= */
+	l.sfltui	r21,0xdead
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	5
+
+	/* Op2 : -> */
+	l.sfltui	r21,0xdebd
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	6
+	
+	/* Op2 : -< */
+	l.sfltui	r21,0xde9d
+	l.bnf	_asm_013_sfltu_ko	/* if not set :	error */
+	l.nop	7
+					
+_asm_013_sfltu_ok :	
+	l.addi	r11,r0,1
+_asm_013_sfltu_ko :	
+	/* load context */
+	l.lwz	r22,4 (r1)
+	l.lwz	r21,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,8
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_014_cmov.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_014_cmov.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_014_cmov.s	(revision 3)
@@ -0,0 +1,69 @@
+/********************************************
+ * files               : asm_014_cmov.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/20
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                :
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.jal
+ *                         l.jr
+ *			   l.lwz
+ *                         l.or
+ *                         l.ori
+ *			   l.sfeq
+ *			   l.sw
+ ********************************************
+ */
+	.file	"asm_014_cmov.s"
+	.section .text
+	.align	4
+
+	.global _asm_014_cmov
+_asm_014_cmov :	
+	/* save context */
+	l.addi	r1,r1,-16
+	l.sw	0 (r1),r20
+	l.sw	4 (r1),r21
+	l.sw	8 (r1),r22
+	l.sw	12(r1),r23	
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	l.and	r20,r0,r0
+	l.movhi	r21,0x5555
+	l.ori	r21,r21,0x5555
+	l.movhi	r22,0xaaaa
+	l.ori	r22,r22,0xaaaa
+
+	/* set flag 1 */
+	l.sfeq	r0,r0
+	l.cmov	r20,r21,r0
+
+	/* set flag 0 */
+	l.sfne	r0,r0
+	l.cmov	r23,r0,r22
+
+	l.or	r20,r20,r23
+	
+	l.sfeqi	r20,-1
+	l.bnf	_asm_014_cmov_ko
+	l.nop	0
+	
+_asm_014_cmov_ok :	
+	l.addi	r11,r0,1
+_asm_014_cmov_ko :
+	
+	/* load context */
+	l.lwz	r23,12(r1)
+	l.lwz	r22,8 (r1)
+	l.lwz	r21,4 (r1)
+	l.lwz	r20,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,16
+	
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_015_shift_rotate.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_015_shift_rotate.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_015_shift_rotate.s	(revision 3)
@@ -0,0 +1,214 @@
+/********************************************
+ * files               : asm_015_shift_rotate.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/20
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                :
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bnf
+ *                         l.jal
+ *                         l.jr
+ *                         l.movhi
+ *                         l.ori
+ *                         l.sfeq
+ ********************************************
+ */
+	.file	"asm_015_shift_rotate.s"
+	.section .text
+	.align	4
+
+	.global _asm_015_shift_rotate
+_asm_015_shift_rotate :	
+	/* save context */
+	l.addi	r1,r1,-16
+	l.sw	0 (r1),r20
+	l.sw	4 (r1),r21
+	l.sw	8 (r1),r22
+	l.sw	12(r1),r23
+	
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	l.movhi	r20, 0x2b3c
+	l.ori	r20,r20,0x4d1a
+
+	l.movhi	r21, 0x1a2b
+	l.ori	r21,r21,0x3c4d
+	l.rori	r22,r21, 4
+	l.rori	r22,r22, 2
+	l.rori	r22,r22, 0
+	l.rori	r22,r22, 3
+	l.rori	r22,r22, 5
+	l.rori	r22,r22, 7
+	l.rori	r22,r22, 3
+
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	1
+
+	l.movhi	r21, 0x1a2b
+	l.ori	r21,r21,0x3c4d
+	
+	l.ori 	r23,r0,1
+	l.ror	r22,r21,r23
+	l.and	r23,r0,r0
+	l.ror	r22,r22,r23		
+	l.ori	r23,r0,5
+	l.ror	r22,r22,r23		
+	l.ori 	r23,r0,2
+	l.ror	r22,r22,r23		
+	l.ori 	r23,r0,5
+	l.ror	r22,r22,r23		
+	l.ori	r23,r0,3
+	l.ror	r22,r22,r23
+	l.ori	r23,r0,8
+	l.ror	r22,r22,r23	
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	2
+
+	l.movhi	r20, 0x4d00
+	l.ori	r20,r20,0x0000
+
+	l.movhi	r21, 0x1a2b
+	l.ori	r21,r21,0x3c4d
+
+	l.slli	r22,r21,4
+	l.slli	r22,r22,0
+	l.slli	r22,r22,10
+	l.slli	r22,r22,7 	
+	l.slli	r22,r22,3 
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	1
+
+	l.movhi	r21, 0x1a2b
+	l.ori	r21,r21,0x3c4d
+
+	l.ori	r23,r0,4
+	l.sll 	r22,r21,r23
+	l.ori	r23,r0,0	
+	l.sll 	r22,r22,r23
+	l.ori	r23,r0,10
+	l.sll 	r22,r22,r23
+	l.ori	r23,r0,7
+	l.sll 	r22,r22,r23	
+	l.ori	r23,r0,3
+	l.sll 	r22,r22,r23
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	1
+
+	l.movhi	r20, 0x0000
+	l.ori	r20,r20,0x001a
+
+	l.movhi	r21, 0x1a2b
+	l.ori	r21,r21,0x3c4d
+
+	l.srli	r22,r21,4
+	l.srli	r22,r22,0
+	l.srli	r22,r22,10
+	l.srli	r22,r22,7 	
+	l.srli	r22,r22,3 
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	1
+
+	l.movhi	r21, 0x1a2b
+	l.ori	r21,r21,0x3c4d
+
+	l.ori	r23,r0,4
+	l.srl 	r22,r21,r23
+	l.ori	r23,r0,0	
+	l.srl 	r22,r22,r23
+	l.ori	r23,r0,10
+	l.srl 	r22,r22,r23
+	l.ori	r23,r0,7
+	l.srl 	r22,r22,r23	
+	l.ori	r23,r0,3
+	l.srl 	r22,r22,r23
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	1
+
+	l.movhi	r20, 0x0000
+	l.ori	r20,r20,0x001a
+
+	l.movhi	r21, 0x1a2b
+	l.ori	r21,r21,0x3c4d
+
+	l.srai	r22,r21,4
+	l.srai	r22,r22,0
+	l.srai	r22,r22,10
+	l.srai	r22,r22,7 	
+	l.srai	r22,r22,3 
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	1
+
+	l.movhi	r21, 0x1a2b
+	l.ori	r21,r21,0x3c4d
+
+	l.ori	r23,r0,4
+	l.sra 	r22,r21,r23
+	l.ori	r23,r0,0	
+	l.sra 	r22,r22,r23
+	l.ori	r23,r0,10
+	l.sra 	r22,r22,r23
+	l.ori	r23,r0,7
+	l.sra 	r22,r22,r23	
+	l.ori	r23,r0,3
+	l.sra 	r22,r22,r23
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	1
+	
+	l.movhi	r20, 0xffff
+	l.ori	r20,r20,0xff8a
+
+	l.movhi	r21, 0x8a2b
+	l.ori	r21,r21,0x3c4d
+
+	l.srai	r22,r21,4
+	l.srai	r22,r22,0
+	l.srai	r22,r22,10
+	l.srai	r22,r22,7 	
+	l.srai	r22,r22,3 
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	1
+
+	l.movhi	r21, 0x8a2b
+	l.ori	r21,r21,0x3c4d
+
+	l.ori	r23,r0,4
+	l.sra 	r22,r21,r23
+	l.ori	r23,r0,0	
+	l.sra 	r22,r22,r23
+	l.ori	r23,r0,10
+	l.sra 	r22,r22,r23
+	l.ori	r23,r0,7
+	l.sra 	r22,r22,r23	
+	l.ori	r23,r0,3
+	l.sra 	r22,r22,r23
+	l.sfeq	r20,r22
+	l.bnf	_asm_015_shift_rotate_ko
+	l.nop	1
+		
+_asm_015_shift_rotate_ok :	
+	l.addi	r11,r0,1
+_asm_015_shift_rotate_ko :
+	
+	/* load context */
+	l.lwz	r23,12(r1)
+	l.lwz	r22,8 (r1)
+	l.lwz	r21,4 (r1)
+	l.lwz	r20,0 (r1)
+	l.jr	r9
+	l.addi	r1,r1,16
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_016_load.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_016_load.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_016_load.s	(revision 3)
@@ -0,0 +1,150 @@
+/********************************************
+ * files               : asm_016_load.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/20
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                :
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.bf
+ *                         l.jal
+ *                         l.jr
+ *			   l.sw
+ ********************************************
+ */
+	.file	"asm_016_load.s"
+	.section .text
+	.align	4
+
+	.global _asm_016_load
+_asm_016_load :	
+	/* save context */
+	l.addi	r1,r1,-16
+	/*      0 (r1) is reserved */
+	l.sw	4 (r1),r20
+	l.sw	8 (r1),r21
+	l.sw	12(r1),r22
+
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/* Value Not Signed */
+ 	l.movhi	r20,0x1234
+	l.ori	r20,r20,0x5678
+		
+	/* TEST BYTES */
+	l.sb	0 (r1), r20
+	l.lbz	r21, 0 (r1)
+	l.extbz	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	l.lbs	r21, 0 (r1)
+	l.extbs	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	/* TEST HALF WORD */
+	l.sh	0 (r1), r20
+	l.lhz	r21, 0 (r1)
+	l.exthz	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	l.lhs	r21, 0 (r1)
+	l.exths	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	/* TEST WORD */
+	l.sw	0 (r1), r20
+	l.lwz	r21, 0 (r1)
+	l.extwz	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	l.lws	r21, 0 (r1)
+	l.extws	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	/* Value Signed */
+ 	l.movhi	r20,0xdead
+	l.ori	r20,r20,0xbeaf
+		
+	/* TEST BYTES */
+	l.sb	0 (r1), r20
+	l.lbz	r21, 0 (r1)
+	l.extbz	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	l.lbs	r21, 0 (r1)
+	l.extbs	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	/* TEST HALF WORD */
+	l.sh	0 (r1), r20
+	l.lhz	r21, 0 (r1)
+	l.exthz	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	l.lhs	r21, 0 (r1)
+	l.exths	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	/* TEST WORD */
+	l.sw	0 (r1), r20
+	l.lwz	r21, 0 (r1)
+	l.extwz	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+
+	l.lws	r21, 0 (r1)
+	l.extws	r22,r20
+
+	l.sfeq	r21,r22
+	l.bnf	_asm_016_load_ko
+	l.nop	1
+			
+_asm_016_load_ok :	
+	l.addi	r11,r0,1
+_asm_016_load_ko :
+	
+	/* load context */
+	l.lwz	r22,12(r1)
+	l.lwz	r21,8 (r1)
+	l.lwz	r20,4 (r1)
+	/*          0 (r1) is reserved */	
+	l.jr	r9
+	l.addi	r1,r1,16
Index: /trunk/Softwares/Basic_test.or32/src/asm/asm_017_mul.s
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/asm/asm_017_mul.s	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/asm/asm_017_mul.s	(revision 3)
@@ -0,0 +1,341 @@
+/********************************************
+ * files               : asm_017_mul.s
+ * authors             : Rosiere Mathieu
+ * date                : 2006/06/20
+ ********************************************
+ * input               : -
+ * output              : 1 test OK
+ *                       0 test KO
+ ********************************************
+ * test                :
+ * warning             : instruction ok 
+ *                         l.addi
+ *                         l.and
+ *                         l.jal
+ *                         l.jr
+ ********************************************
+ */
+	.file	"asm_017_mul.s"
+	.section .text
+	.align	4
+
+	.global _asm_017_mul
+_asm_017_mul :	
+	/* save context */
+	l.addi	r1,r1,-16
+	l.sw	0 (r1),r20
+	l.sw	4 (r1),r21	
+	l.sw	8 (r1),r22
+	l.sw	12(r1),r23
+	
+	/* Return is KO (default)*/
+	l.and   r11,r0,r0
+
+	/*
+	 r20 :	result
+	 r21 :	operand 1
+	 r22 :	operand 2
+	 r23 :	result waited
+	*/
+	
+	/* Operand 1 : positive */
+	l.movhi r21,0x1234
+	l.ori	r21,r21,0x5678
+
+	/* Test 1.1 */
+	l.and	r22,r0,r0
+	l.and	r23,r0,r0
+	
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.muli	r20,r21,0
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 1.2 */
+		
+	l.ori	r22,r0,1
+	l.or 	r23,r0,r21
+	
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.muli	r20,r21,1
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 1.3 */
+		
+	l.ori	r22,r0,2
+	l.slli	r23,r21, 1
+	
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.muli	r20,r21,2
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 1.4 */
+		
+	l.ori	r22,r0,0x11
+	l.movhi r23,0x3579
+	l.ori	r23,r23,0xbdf8
+	
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.muli	r20,r21,0x11
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 1.4 */
+
+	l.addi	r22,r0,-1
+	l.movhi r23,0xedcb
+	l.ori	r23,r23,0xa988
+
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+/*
+	l.muli	r20,r21,-1
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+*/
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 1.5 */
+
+	l.addi	r22,r0,-2
+	
+	l.movhi r23,0xdb97
+	l.ori	r23,r23,0x5310
+
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+/*
+	l.muli	r20,r21,-2
+			
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+*/
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Operand 2 : negative */
+	l.movhi r21,0xdead
+	l.ori	r21,r21,0xbeaf
+
+	/* Test 2.1 */
+	l.and	r22,r0,r0
+	l.and	r23,r0,r0
+	
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.muli	r20,r21,0
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 2.2 */
+		
+	l.ori	r22,r0,1
+	l.or 	r23,r0,r21
+	
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.muli	r20,r21,1
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 2.3 */
+		
+	l.ori	r22,r0,2
+	l.slli	r23,r21, 1
+	
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.muli	r20,r21,2
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 2.4 */
+		
+	l.ori	r22,r0,0x11
+	l.movhi r23,0xc989
+	l.ori	r23,r23,0xa99f
+	
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.muli	r20,r21,0x11
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 2.4 */
+
+	l.addi	r22,r0,-1
+	l.movhi r23,0x2152
+	l.ori	r23,r23,0x4151
+
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+/*
+	l.muli	r20,r21,-1
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+*/
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+
+	/* Test 2.5 */
+
+	l.addi	r22,r0,-2
+
+	l.movhi r23,0x42a4
+	l.ori	r23,r23,0x82a2
+
+	l.mul	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+/*
+	l.muli	r20,r21,-2
+			
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+*/
+	l.mulu	r20,r21,r22
+		
+	l.sfeq	r20,r23
+	l.bnf	_asm_017_mul_ko
+	l.nop	1
+	
+_asm_017_mul_ok :	
+	l.addi	r11,r0,1
+_asm_017_mul_ko :
+	
+	/* load context */
+	l.lwz	r20,0 (r1)
+	l.lwz	r21,4 (r1)	
+	l.lwz	r22,8 (r1)
+	l.lwz	r23,12(r1)
+	l.jr	r9
+	l.addi	r1,r1,16
Index: /trunk/Softwares/Basic_test.or32/src/c/bottles.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/bottles.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/bottles.c	(revision 3)
@@ -0,0 +1,37 @@
+/*
+ * 99 bottles of beer in ansi c
+ *
+ * by Bill Wein: bearheart@bearnet.com
+ *
+ */
+#include "bottles.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+void chug(int beers);
+
+void bottles(int nb_beers)
+{
+  register int beers;
+
+  for(beers = nb_beers; beers; chug(beers--))
+    puts("");
+  
+  puts("\nTime to buy more beer!\n");
+}
+
+void chug(register int beers)
+{
+  char howmany[8], *s;
+  
+  s = beers != 1 ? "s" : "";
+  printf("%d bottle%s of beer on the wall,\n", beers, s);
+  printf("%d bottle%s of beeeeer . . . ,\n", beers, s);
+  printf("Take one down, pass it around,\n");
+  
+  if(--beers) sprintf(howmany, "%d", beers); else strcpy(howmany, "No more");
+  s = beers != 1 ? "s" : "";
+  
+  printf("%s bottle%s of beer on the wall.\n", howmany, s);
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/dhry21a.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/dhry21a.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/dhry21a.c	(revision 3)
@@ -0,0 +1,398 @@
+/*
+ *************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry_1.c (part 2 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ *************************************************************************
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include "dhry.h"
+#include "dhry21.h"
+
+/* Global Variables: */
+
+Rec_Pointer     Ptr_Glob,
+                Next_Ptr_Glob;
+int             Int_Glob;
+Boolean         Bool_Glob;
+char            Ch_1_Glob,
+                Ch_2_Glob;
+int             Arr_1_Glob [50];
+int             Arr_2_Glob [50] [50];
+
+char Reg_Define[] = "Register option selected.";
+
+//extern char     *malloc ();
+//Enumeration     Func_1 ();
+  /* 
+  forward declaration necessary since Enumeration may not simply be int
+  */
+
+#ifndef ROPT
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#else
+#define REG register
+#endif
+
+
+/* variables for time measurement: */
+
+#define Too_Small_Time 2
+                /* Measurements should last at least 2 seconds */
+
+DOUBLE          Begin_Time,
+                End_Time,
+                User_Time;
+
+DOUBLE          Microseconds,
+                Dhrystones_Per_Second,
+                Vax_Mips;
+
+/* end of variables for time measurement */
+
+int main_dhry21 (unsigned int NUMBER_OF_RUNS)
+/*****/
+
+  /* main program, corresponds to procedures        */
+  /* Main and Proc_0 in the Ada version             */
+{
+  DOUBLE   dtime();
+
+        One_Fifty       Int_1_Loc;
+  REG   One_Fifty       Int_2_Loc;
+        One_Fifty       Int_3_Loc;
+  REG   char            Ch_Index;
+        Enumeration     Enum_Loc;
+        Str_30          Str_1_Loc;
+        Str_30          Str_2_Loc;
+  REG   int             Run_Index;
+  REG   int             Number_Of_Runs;
+
+        FILE            *Ap;
+
+  /* Initializations */
+
+  if ((Ap = fopen("dhry.res","a+")) == NULL)
+    {
+       printf("Can not open dhry.res\n\n");
+       exit(1);
+    }
+
+  Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+  Ptr_Glob      = (Rec_Pointer) malloc (sizeof (Rec_Type));
+
+  Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;
+  Ptr_Glob->Discr                       = Ident_1;
+  Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;
+  Ptr_Glob->variant.var_1.Int_Comp      = 40;
+  strcpy (Ptr_Glob->variant.var_1.Str_Comp, 
+          "DHRYSTONE PROGRAM, SOME STRING");
+  strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+  Arr_2_Glob [8][7] = 10;
+        /* Was missing in published program. Without this statement,    */
+        /* Arr_2_Glob [8][7] would have an undefined value.             */
+        /* Warning: With 16-Bit processors and Number_Of_Runs > 32000,  */
+        /* overflow may occur for this array element.                   */
+
+  printf ("\n");
+  printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+  printf ("\n");
+
+  /*
+  if (Reg)
+  {
+    printf ("Program compiled with 'register' attribute\n");
+    printf ("\n");
+  }
+  else
+  {
+    printf ("Program compiled without 'register' attribute\n");
+    printf ("\n");
+  }
+  */
+
+//**********************************************************************
+//  printf ("Please give the number of runs through the benchmark: ");
+//  {
+//    int n;
+//    scanf ("%d", &n);
+//    Number_Of_Runs = n;
+//  }
+//  printf ("\n");
+//**********************************************************************
+
+  Number_Of_Runs = NUMBER_OF_RUNS;
+  
+  printf ("Execution starts, %d runs through Dhrystone\n",Number_Of_Runs);
+
+  /***************/
+  /* Start timer */
+  /***************/
+ 
+  Begin_Time = dtime();
+  
+  for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+  {
+
+    Proc_5();
+    Proc_4();
+      /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+    Int_1_Loc = 2;
+    Int_2_Loc = 3;
+    strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+    Enum_Loc = Ident_2;
+    Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+      /* Bool_Glob == 1 */
+    while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */
+    {
+      Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+        /* Int_3_Loc == 7 */
+      Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+        /* Int_3_Loc == 7 */
+      Int_1_Loc += 1;
+    } /* while */
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+      /* Int_Glob == 5 */
+    Proc_1 (Ptr_Glob);
+    for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+                             /* loop body executed twice */
+    {
+      if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+          /* then, not executed */
+        {
+        Proc_6 (Ident_1, &Enum_Loc);
+        strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+        Int_2_Loc = Run_Index;
+        Int_Glob = Run_Index;
+        }
+    }
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Int_2_Loc = Int_2_Loc * Int_1_Loc;
+    Int_1_Loc = Int_2_Loc / Int_3_Loc;
+    Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+      /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+    Proc_2 (&Int_1_Loc);
+      /* Int_1_Loc == 5 */
+
+  } /* loop "for Run_Index" */
+
+  /**************/
+  /* Stop timer */
+  /**************/
+
+  End_Time = dtime();
+
+  printf ("Execution ends\n");
+  /*******************************************************************
+  printf ("\n");
+  printf ("Final values of the variables used in the benchmark:\n");
+  printf ("\n");
+  printf ("Int_Glob:            %d\n", Int_Glob);
+  printf ("        should be:   %d\n", 5);
+  printf ("Bool_Glob:           %d\n", Bool_Glob);
+  printf ("        should be:   %d\n", 1);
+  printf ("Ch_1_Glob:           %c\n", Ch_1_Glob);
+  printf ("        should be:   %c\n", 'A');
+  printf ("Ch_2_Glob:           %c\n", Ch_2_Glob);
+  printf ("        should be:   %c\n", 'B');
+  printf ("Arr_1_Glob[8]:       %d\n", Arr_1_Glob[8]);
+  printf ("        should be:   %d\n", 7);
+  printf ("Arr_2_Glob[8][7]:    %d\n", Arr_2_Glob[8][7]);
+  printf ("        should be:   Number_Of_Runs + 10\n");
+  printf ("Ptr_Glob->\n");
+  printf ("  Ptr_Comp:          %d\n", (int) Ptr_Glob->Ptr_Comp);
+  printf ("        should be:   (implementation-dependent)\n");
+  printf ("  Discr:             %d\n", Ptr_Glob->Discr);
+  printf ("        should be:   %d\n", 0);
+  printf ("  Enum_Comp:         %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+  printf ("        should be:   %d\n", 2);
+  printf ("  Int_Comp:          %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+  printf ("        should be:   %d\n", 17);
+  printf ("  Str_Comp:          %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  printf ("Next_Ptr_Glob->\n");
+  printf ("  Ptr_Comp:          %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+  printf ("        should be:   (implementation-dependent), same as above\n");
+  printf ("  Discr:             %d\n", Next_Ptr_Glob->Discr);
+  printf ("        should be:   %d\n", 0);
+  printf ("  Enum_Comp:         %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+  printf ("        should be:   %d\n", 1);
+  printf ("  Int_Comp:          %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+  printf ("        should be:   %d\n", 18);
+  printf ("  Str_Comp:          %s\n", Next_Ptr_Glob->variant.var_1.Str_Comp);
+  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  printf ("Int_1_Loc:           %d\n", Int_1_Loc);
+  printf ("        should be:   %d\n", 5);
+  printf ("Int_2_Loc:           %d\n", Int_2_Loc);
+  printf ("        should be:   %d\n", 13);
+  printf ("Int_3_Loc:           %d\n", Int_3_Loc);
+  printf ("        should be:   %d\n", 7);
+  printf ("Enum_Loc:            %d\n", Enum_Loc);
+  printf ("        should be:   %d\n", 1);
+  printf ("Str_1_Loc:           %s\n", Str_1_Loc);
+  printf ("        should be:   DHRYSTONE PROGRAM, 1'ST STRING\n");
+  printf ("Str_2_Loc:           %s\n", Str_2_Loc);
+  printf ("        should be:   DHRYSTONE PROGRAM, 2'ND STRING\n");
+  printf ("\n");
+  ********************************************************************/
+
+  User_Time = End_Time - Begin_Time;
+
+  if (User_Time < Too_Small_Time)
+  {
+    printf ("Measured time too small to obtain meaningful results : %f\n",User_Time);
+    printf ("Please increase number of runs\n");
+    printf ("\n");
+  }
+  else
+  {
+    Microseconds          = User_Time * Mic_secs_Per_Second / (DOUBLE) Number_Of_Runs;
+    Dhrystones_Per_Second = (DOUBLE) Number_Of_Runs / User_Time;
+    Vax_Mips              = Dhrystones_Per_Second / 1757.0;
+
+#ifdef ROPT
+    printf ("Register option selected?  YES\n");
+#else
+    printf ("Register option selected?  NO\n");
+    strcpy(Reg_Define, "Register option not selected.");
+#endif
+
+    printf ("Microseconds for one run through Dhrystone : %.1lf  \n",Microseconds);
+    printf ("Dhrystones per Second                      : %.1lf \n",Dhrystones_Per_Second);
+    printf ("VAX MIPS rating                            : %.3lf \n",Vax_Mips);
+    printf ("\n");
+  
+  fprintf(Ap,"\n");
+  fprintf(Ap,"Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+  fprintf(Ap,"%s\n",Reg_Define);
+
+  fprintf(Ap,"Microseconds for one loop : %.1lf\n",Microseconds);
+  fprintf(Ap,"Dhrystones per second     : %.1lf\n",Dhrystones_Per_Second);
+  fprintf(Ap,"VAX MIPS rating           : %.3lf\n",Vax_Mips);
+  }
+  fclose(Ap);
+  return 0;
+  
+}
+
+void
+Proc_1 (Ptr_Val_Par)
+/******************/
+
+REG Rec_Pointer Ptr_Val_Par;
+    /* executed once */
+{
+  REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;  
+                                        /* == Ptr_Glob_Next */
+  /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */
+  /* corresponds to "rename" in Ada, "with" in Pascal           */
+  
+  structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+  Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+  Next_Record->variant.var_1.Int_Comp 
+        = Ptr_Val_Par->variant.var_1.Int_Comp;
+  Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+  Proc_3 (&Next_Record->Ptr_Comp);
+    /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp 
+                        == Ptr_Glob->Ptr_Comp */
+  if (Next_Record->Discr == Ident_1)
+    /* then, executed */
+  {
+    Next_Record->variant.var_1.Int_Comp = 6;
+    Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, 
+           &Next_Record->variant.var_1.Enum_Comp);
+    Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+    Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, 
+           &Next_Record->variant.var_1.Int_Comp);
+  }
+  else /* not executed */
+    structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+void
+Proc_2 (Int_Par_Ref)
+/******************/
+    /* executed once */
+    /* *Int_Par_Ref == 1, becomes 4 */
+
+One_Fifty   *Int_Par_Ref;
+{
+  One_Fifty  Int_Loc;
+  Enumeration   Enum_Loc;
+
+  Int_Loc = *Int_Par_Ref + 10;
+  do /* executed once */
+    if (Ch_1_Glob == 'A')
+      /* then, executed */
+    {
+      Int_Loc -= 1;
+      *Int_Par_Ref = Int_Loc - Int_Glob;
+      Enum_Loc = Ident_1;
+    } /* if */
+  while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+void
+Proc_3 (Ptr_Ref_Par)
+/******************/
+    /* executed once */
+    /* Ptr_Ref_Par becomes Ptr_Glob */
+
+Rec_Pointer *Ptr_Ref_Par;
+
+{
+  if (Ptr_Glob != Null)
+    /* then, executed */
+    *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+  Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+void
+Proc_4 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Boolean Bool_Loc;
+
+  Bool_Loc = Ch_1_Glob == 'A';
+  Bool_Glob = Bool_Loc | Bool_Glob;
+  Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+void
+Proc_5 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Ch_1_Glob = 'A';
+  Bool_Glob = false;
+} /* Proc_5 */
+
+
+        /* Procedure for the assignment of structures,          */
+        /* if the C compiler doesn't support this feature       */
+#ifdef  NOSTRUCTASSIGN
+memcpy (d, s, l)
+register char   *d;
+register char   *s;
+register int    l;
+{
+        while (l--) *d++ = *s++;
+}
+#endif
Index: /trunk/Softwares/Basic_test.or32/src/c/dhry21b.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/dhry21b.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/dhry21b.c	(revision 3)
@@ -0,0 +1,195 @@
+/*
+ *************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry_2.c (part 3 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ *************************************************************************
+ */
+
+#include "dhry.h"
+#include "dhry21.h"
+#include <string.h>
+
+#ifndef REG
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#else
+#define REG register
+#endif
+
+int     Int_Glob;
+char    Ch_1_Glob;
+
+void
+Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+/*********************************/
+    /* executed once */
+    /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+
+Enumeration  Enum_Val_Par;
+Enumeration *Enum_Ref_Par;
+{
+  *Enum_Ref_Par = Enum_Val_Par;
+  if (! Func_3 (Enum_Val_Par))
+    /* then, not executed */
+    *Enum_Ref_Par = Ident_4;
+  switch (Enum_Val_Par)
+  {
+    case Ident_1: 
+      *Enum_Ref_Par = Ident_1;
+      break;
+    case Ident_2: 
+      if (Int_Glob > 100)
+        /* then */
+      *Enum_Ref_Par = Ident_1;
+      else *Enum_Ref_Par = Ident_4;
+      break;
+    case Ident_3: /* executed */
+      *Enum_Ref_Par = Ident_2;
+      break;
+    case Ident_4: break;
+    case Ident_5: 
+      *Enum_Ref_Par = Ident_3;
+      break;
+  } /* switch */
+} /* Proc_6 */
+
+void
+Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+/**********************************************/
+    /* executed three times                                      */
+    /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */
+    /*                  Int_Par_Ref becomes 7                    */
+    /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+    /*                  Int_Par_Ref becomes 17                   */
+    /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+    /*                  Int_Par_Ref becomes 18                   */
+One_Fifty       Int_1_Par_Val;
+One_Fifty       Int_2_Par_Val;
+One_Fifty      *Int_Par_Ref;
+{
+  One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 2;
+  *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+void
+Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+    /* executed once      */
+    /* Int_Par_Val_1 == 3 */
+    /* Int_Par_Val_2 == 7 */
+Arr_1_Dim       Arr_1_Par_Ref;
+Arr_2_Dim       Arr_2_Par_Ref;
+int             Int_1_Par_Val;
+int             Int_2_Par_Val;
+{
+  REG One_Fifty Int_Index;
+  REG One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 5;
+  Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+  Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+  Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+  for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+    Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+  Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+  Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+  Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+/*************************************************/
+    /* executed three times                                         */
+    /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */
+    /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */
+    /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */
+
+Capital_Letter   Ch_1_Par_Val;
+Capital_Letter   Ch_2_Par_Val;
+{
+  Capital_Letter        Ch_1_Loc;
+  Capital_Letter        Ch_2_Loc;
+
+  Ch_1_Loc = Ch_1_Par_Val;
+  Ch_2_Loc = Ch_1_Loc;
+  if (Ch_2_Loc != Ch_2_Par_Val)
+    /* then, executed */
+    return (Ident_1);
+  else  /* not executed */
+  {
+    Ch_1_Glob = Ch_1_Loc;
+    return (Ident_2);
+   }
+} /* Func_1 */
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+    /* executed once */
+    /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+    /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30  Str_1_Par_Ref;
+Str_30  Str_2_Par_Ref;
+{
+  REG One_Thirty        Int_Loc;
+      Capital_Letter    Ch_Loc ;
+
+  Int_Loc = 2;
+  while (Int_Loc <= 2) /* loop body executed once */
+    if (Func_1 (Str_1_Par_Ref[Int_Loc],
+                Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+      /* then, executed */
+    {
+      Ch_Loc = 'A';
+      Int_Loc += 1;
+    } /* if, while */
+  if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+    /* then, not executed */
+    Int_Loc = 7;
+  if (Ch_Loc == 'R')
+    /* then, not executed */
+    return (true);
+  else /* executed */
+  {
+    if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+      /* then, not executed */
+    {
+      Int_Loc += 7;
+      Int_Glob = Int_Loc;
+      return (true);
+    }
+    else /* executed */
+      return (false);
+  } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+    /* executed once        */
+    /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+  Enumeration Enum_Loc;
+
+  Enum_Loc = Enum_Par_Val;
+  if (Enum_Loc == Ident_3)
+    /* then, executed */
+    return (true);
+  else /* not executed */
+    return (false);
+} /* Func_3 */
Index: /trunk/Softwares/Basic_test.or32/src/c/exec_0.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/exec_0.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/exec_0.c	(revision 3)
@@ -0,0 +1,32 @@
+#include "bool.h"
+#include "func_test.h"
+
+bool exec_0()
+{
+  bool res = false;
+  
+  printf("<exec_0> \n");
+
+  res = (test_01() &&
+	 test_02() &&
+	 test_03() &&
+	 test_04() &&
+	 test_05() &&
+	 test_06() &&
+	 test_07() &&
+	 test_08() &&
+	 test_09() &&
+	 test_10() &&
+	 test_11() &&
+	 test_12() &&
+	 test_13() &&
+	 1);
+  
+  if (res == false)
+    printf("<exec_0> Ko\n");
+  else
+    printf("<exec_0> Ok\n");
+   
+  return (res);
+}
+
Index: /trunk/Softwares/Basic_test.or32/src/c/exec_1.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/exec_1.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/exec_1.c	(revision 3)
@@ -0,0 +1,31 @@
+#include "bool.h"
+#include "func_test.h"
+
+bool exec_1()
+{
+  bool res = false;
+
+  printf("<exec_1>\n");
+
+  res = (test_10() &&
+	 test_13() &&
+	 test_12() &&
+	 test_11() &&
+	 test_01() &&
+	 test_02() &&
+	 test_03() &&
+	 test_06() &&
+	 test_07() &&
+	 test_04() &&
+	 test_05() &&
+	 test_08() &&
+	 test_09() &&
+	 1);
+
+  if (res == false)
+    printf("<exec_1> Ko\n");
+  else
+    printf("<exec_1> Ok\n");
+
+  return res;
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/exec_2.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/exec_2.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/exec_2.c	(revision 3)
@@ -0,0 +1,31 @@
+#include "bool.h"
+#include "func_test.h"
+
+bool exec_2()
+{
+  bool res = false;
+
+  printf("<exec_2>\n");
+  
+  res = (test_07() &&
+	 test_02() &&
+	 test_10() &&
+	 test_01() &&
+	 test_13() &&
+	 test_03() &&
+	 test_12() &&
+	 test_06() &&
+	 test_08() &&
+	 test_04() &&
+	 test_11() &&
+	 test_05() &&
+	 test_09() &&
+	 1);
+
+  if (res == false)
+    printf("<exec_2> Ko\n");
+  else
+    printf("<exec_2> Ok\n");
+
+  return res;
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/exec_3.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/exec_3.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/exec_3.c	(revision 3)
@@ -0,0 +1,31 @@
+#include "bool.h"
+#include "func_test.h"
+
+bool exec_3()
+{
+  bool res = false;
+
+  printf("<exec_3>\n");
+
+  res = (test_05() &&
+	 test_09() &&
+	 test_01() &&
+	 test_10() &&
+	 test_03() &&
+	 test_12() &&
+	 test_02() &&
+	 test_07() &&
+	 test_13() &&
+	 test_04() &&
+	 test_11() &&
+	 test_08() &&
+	 test_06() &&
+	 1);
+  
+  if (res == false)
+    printf("<exec_3> Ko\n");
+  else
+    printf("<exec_3> Ok\n");
+
+  return res;
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_array.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_array.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_array.c	(revision 3)
@@ -0,0 +1,136 @@
+#include "func_array.h"
+
+//-----[ Selection_sort ]--------------------------------------------------
+
+void selection_sort  (int array[], int size) 
+{
+  int i, min, j , tmp;
+  for(i = 0 ; i < size - 1 ; i++) 
+    {
+      min = i;
+
+      // Find indice min
+      for(j = i+1 ; j < size ; j++)
+	if(array[j] < array[min])
+	  min = j;
+
+      if(min != i) // find or not.
+	{
+	  tmp        = array[i];
+	  array[i]   = array[min];
+	  array[min] = tmp;
+	}
+    }
+}
+
+//-----[ insertion_sort ]--------------------------------------------------
+void insertion_sort (int array[], int size) 
+{
+  /* Spécifications externes : Tri du tableau t par insertion séquentielle */
+  int i,pos,j,tmp;
+
+  for (i = 1 ; i < size ; i++) 
+    {
+      /* Calcul de la position d'insertion pos : */
+      /* détermine le plus petit indice pos       / 0 <= pos <= i */
+      /* qui vérifie array[pos] >= array[i] */
+      pos = 0;
+      
+      while(array[pos] < array[i]) 
+	pos++;
+      
+      tmp = array[i]; /* Sauvegarde de t[i] */
+ 
+      for(j = i-1 ; j >= pos  ; j--)
+	array[j+1] = array[j]; /* translation de t[pos..i-1] vers t[pos+1..i] */
+      
+      array[pos] = tmp; /* insertion de t[pos] */
+    }
+}
+
+//-----[ QuickSort ]-------------------------------------------------------
+
+// QuickSort
+void quick_sort (int * array, int debut, int fin)
+{
+  int          gauche, droite;
+  int          pivot;
+
+  pivot = array[debut];
+
+  for(gauche = debut, droite = fin; gauche < droite; )
+    {
+      
+      for(;array[droite] > pivot; droite--);
+            
+      if(gauche != droite)
+	{
+	  array[gauche] = array[droite];
+	  array[droite] = pivot;
+	  gauche++;
+	}
+      
+      for(; array[gauche] < pivot; gauche++);
+            
+      if(gauche != droite)
+	{ 
+	  array[droite] = array[gauche];
+	  array[gauche] = pivot;
+	  droite--;
+	}
+    }
+  
+  if(debut < gauche-1) quick_sort(array, debut   , gauche-1);
+  if(fin   > gauche+1) quick_sort(array, gauche+1, fin     );
+}
+
+//-----[ BubbleSort ]------------------------------------------------------
+
+void bubble_sort (int array[], unsigned int size) 
+{
+  int i   = 0; /* Indice de répétition du tri */
+  int j   = 0; /* Variable de boucle */
+  int tmp = 0; /* Variable de stockage temporaire */
+  
+  /* Booléen marquant l'arrêt du tri si le tableau est ordonné */
+  int en_desordre = 1; 
+  
+  /* Boucle de répétition du tri et le test qui
+     arrête le tri dès que le tableau est ordonné */
+  for(i = 0 ; (i < size) && (en_desordre == 1); i++)
+    {  
+      /* Supposons le tableau ordonné */
+      en_desordre = 0;
+      
+                /* Vérification des éléments des places j et j-1 */
+      for(j = 1 ; j < size - i ; j++) 
+	{
+	  /* Si les 2 éléments sont mal triés */
+	  if(array[j] < array[j-1])
+	    {
+	      /* Inversion des 2 éléments */
+	      tmp        = array[j-1];
+	      array[j-1] = array[j];
+	      array[j]   = tmp;
+	      
+	      /* Le tableau n'est toujours pas trié */
+	      en_desordre = 1;
+	    }
+	}
+    }
+}
+
+//-----[ Algo ]------------------------------------------------------------
+
+void array_tri_croissant (int * array, unsigned int size,int algo)
+{
+  switch (algo)
+    {
+    case 0 : bubble_sort    (array,size);     break;
+    case 1 : selection_sort (array,size);     break;
+    case 2 : insertion_sort (array,size);     break;
+    case 3 : quick_sort     (array,0,size-1); break;
+    default : break;
+    }
+}
+
Index: /trunk/Softwares/Basic_test.or32/src/c/func_endianness.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_endianness.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_endianness.c	(revision 3)
@@ -0,0 +1,20 @@
+#include <stdio.h>
+#include "func_endianness.h"
+
+bool endianness ()
+{
+  union TestEndian test_endian;
+  
+  test_endian.total = 0xFF;
+  
+  if (test_endian.octets.octet1 == 0xFF) 
+    {
+      printf("Little Endian\n");
+      return LittleEndian;
+    }
+  else 
+    {
+      printf("Big Endian\n");
+      return BigEndian;
+    }
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_factoriel.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_factoriel.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_factoriel.c	(revision 3)
@@ -0,0 +1,24 @@
+#include "func_factoriel.h"
+#include "func_math.h"
+
+//-----[ Factoriel ]-------------------------------------------------------
+
+unsigned int fact_recursif (unsigned int x)
+{
+  if ( x <= 1)
+    return 1;
+  
+  return (mul_soft (x , fact_recursif (x-1) ) );
+}
+
+unsigned int fact_iteratif (unsigned int x)
+{
+  unsigned int res= 1;
+  
+  while (x > 1)
+    {
+      res = mul_soft(res,x);
+      x --;
+    }
+  return res;
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_fibonnacci.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_fibonnacci.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_fibonnacci.c	(revision 3)
@@ -0,0 +1,18 @@
+#include "func_fibonnacci.h"
+
+int fibonnacci(int x)
+{
+  int i;
+  int xn   = 0;
+  int xn_1 = 1;
+  int xn_2 = 0;
+
+  for (i=0;i<=x;i++)
+    {
+      xn   = xn_1 + xn_2;
+      xn_2 = xn_1;
+      xn_1 = xn;
+    }
+  
+  return xn;
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_hanoi.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_hanoi.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_hanoi.c	(revision 3)
@@ -0,0 +1,24 @@
+#include "func_hanoi.h"
+
+int hanoi_recursif(char pic_depart, char pic_destination, char pic_transition, int nb_disques)
+{
+  unsigned int nb_move = 0;
+  
+  if (nb_disques == 1)
+    {
+      nb_move = 1;
+    }
+  else
+    {
+      //on modifie les positions des palets 
+      nb_move += hanoi_recursif(pic_depart     , pic_transition  , pic_destination, nb_disques - 1);
+      nb_move += hanoi_recursif(pic_depart     , pic_destination , pic_transition , 1             );
+      nb_move += hanoi_recursif(pic_transition , pic_destination , pic_depart     , nb_disques - 1);
+    }
+  return nb_move;
+}
+
+int hanoi(int nb_disques)
+{
+  return(hanoi_recursif('1', '2', '3', nb_disques));
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_integrity.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_integrity.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_integrity.c	(revision 3)
@@ -0,0 +1,60 @@
+#include <stdio.h>
+#include "func_integrity.h"
+#include "func_io.h"
+
+extern bool  asm_001_add          ();
+extern bool  asm_002_addc         ();
+extern bool  asm_003_extend       ();
+extern bool  asm_004_sfeq         ();
+extern bool  asm_005_sfne         ();
+extern bool  asm_006_sfges        ();
+extern bool  asm_007_sfgeu        ();
+extern bool  asm_008_sfgts        ();
+extern bool  asm_009_sfgtu        ();
+extern bool  asm_010_sfles        ();
+extern bool  asm_011_sfleu        ();
+extern bool  asm_012_sflts        ();
+extern bool  asm_013_sfltu        ();
+extern bool  asm_014_cmov         ();
+extern bool  asm_015_shift_rotate ();
+extern bool  asm_016_load         ();
+extern bool  asm_017_mul          ();
+
+bool test_integrity ()
+{
+  bool res;
+
+  res = 
+    asm_001_add          () &&
+    asm_002_addc         () &&
+    asm_003_extend       () &&
+    asm_004_sfeq         () &&
+    asm_005_sfne         () &&
+    asm_006_sfges        () &&
+    asm_007_sfgeu        () &&
+    asm_008_sfgts        () &&
+    asm_009_sfgtu        () &&
+    asm_010_sfles        () &&
+    asm_011_sfleu        () &&
+    asm_012_sflts        () &&
+    asm_013_sfltu        () &&
+    asm_014_cmov         () &&
+    asm_015_shift_rotate () &&
+    asm_016_load         () &&
+    asm_017_mul          () &&
+    1;
+
+  if (res == true)
+    {
+      print(1);
+      printf("<test_integrity> Test is Ok\n");
+    }
+  
+  else
+    {
+      quit(-1);
+      printf("<test_integrity> Test is Ko\n");
+    }
+  
+  return res;
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_math.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_math.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_math.c	(revision 3)
@@ -0,0 +1,68 @@
+#include "func_math.h"
+
+//-----[ Multiplication ]--------------------------------------------------
+
+// Multiplication rapide
+unsigned int mul_soft(unsigned int op1,
+		      unsigned int op2)
+{
+  unsigned int num_bit,carry;
+  unsigned int op2_aux = op2;
+  unsigned int res     = 0;
+  
+  for(num_bit=0;num_bit<32; num_bit++)
+    {
+      if (op2_aux == 0)
+	break;
+
+      carry   = op2_aux & 1;
+      op2_aux = op2_aux >> 1;
+      
+      if (carry!=0)
+	res += (op1 << num_bit);
+    }
+  return res;
+}
+
+unsigned int mul_hard(unsigned int op1,
+		      unsigned int op2)
+{
+  return op1*op2;
+}
+
+//-----[ Division ]--------------------------------------------------------
+
+unsigned int div_soft( unsigned int op1,
+		       unsigned int op2)
+{
+  unsigned res;
+  
+  if (op2 == 0)
+    return 0;
+  
+  for (res = 0; op1 >= op2; res ++)
+    op1 -= op2;
+  
+  return res;
+}
+
+unsigned int div_hard( unsigned int op1,
+		       unsigned int op2)
+{
+//return (op1/op2);
+  return div_soft(op1,op2);
+}
+
+//-----[ Modulo ]----------------------------------------------------------
+
+unsigned int modulo( unsigned int x,
+		     unsigned int base)
+{
+  if (base==0)
+    return 0;
+  
+  while(x >= base)
+    x -= base;
+  
+  return x;
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_mm.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_mm.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_mm.c	(revision 3)
@@ -0,0 +1,102 @@
+#include "func_mm.h"
+
+void mm_algo1 ( unsigned int    size_matrix 
+	       ,unsigned int ** matrix_a
+	       ,unsigned int ** matrix_b
+	       ,unsigned int ** matrix_d)
+{
+  unsigned int index_i, index_j, index_k;
+ 
+  for (index_i = 0; index_i < size_matrix; index_i ++)
+    for (index_j = 0; index_j < size_matrix; index_j ++)
+      {
+	matrix_d [index_i][index_j] = 0;
+	
+	for (index_k = 0; index_k < size_matrix; index_k ++)
+	  matrix_d [index_i][index_j] += matrix_a[index_i][index_k] * matrix_b[index_k][index_j];
+      }
+}
+
+int mm(unsigned int size_matrix, unsigned int algo)
+{
+  unsigned int matrix_a [size_matrix][size_matrix];
+  unsigned int matrix_b [size_matrix][size_matrix];
+  unsigned int matrix_d [size_matrix][size_matrix];
+  unsigned int sum , sum_ok;
+  unsigned int index_i, index_j;
+  
+  /*
+   * PHASE 1 : Initialisation
+   */
+
+  /* Flush matrix_d */
+  for (index_i = 0; index_i < size_matrix; index_i ++)
+    for (index_j = 0; index_j < size_matrix; index_j ++)
+      {
+	matrix_a [index_i][index_j] = index_i+1;
+	matrix_b [index_i][index_j] = index_i+1;
+	matrix_d [index_i][index_j] = 0;
+      }
+
+  sum = (size_matrix*(size_matrix+1))>>1;
+  /*
+        sum = (N*(N+1))/2;
+    ici sum = (4*5)/2 = 10
+
+              ( 1  1  1  1  )
+              ( 2  2  2  2  )
+	      ( 3  3  3  3  )
+	      ( 4  4  4  4  )
+    ( 1 1 1 1 ) 10 10 10 10 -> 1*sum
+    ( 2 2 2 2 ) 20 20 20 20 -> 2*sum
+    ( 3 3 3 3 ) 30 30 30 30 -> 3*sum
+    ( 4 4 4 4 ) 40 40 40 40 -> 4*sum
+  */
+
+  /*
+   * PHASE 2 : Execution
+   */
+
+  switch (algo)
+    {
+    case 1 :
+      {
+	/* méthode classique */
+
+	unsigned int index_i, index_j, index_k;
+	
+	for (index_i=0;index_i<size_matrix;index_i++)
+	  for (index_j=0;index_j<size_matrix;index_j++)
+	    {
+	      matrix_d [index_i][index_j] = 0;
+	      
+	      for (index_k=0;index_k<size_matrix;index_k++)
+		matrix_d [index_i][index_j] += matrix_a[index_i][index_k] * matrix_b[index_k][index_j];
+	    }
+
+	//mm_algo1(size_matrix, matrix_a, matrix_b, matrix_d);
+	break;
+      }
+    default :break;
+    }/* end switch algo */
+  
+  /*
+   * PHASE 3 : Test
+   */
+
+  sum_ok = 0;
+
+  for (index_i=0;index_i<size_matrix;index_i++)
+    {
+      unsigned int row_sum = (index_i+1)*sum;
+
+      for (index_j=0;index_j<size_matrix;index_j++)
+	if ((matrix_a[index_i][index_j] == index_i+1) &&
+	    (matrix_b[index_i][index_j] == index_i+1) &&
+	    (matrix_d[index_i][index_j] == row_sum)
+	    )
+	  sum_ok ++;
+    }
+  
+  return (sum_ok == (size_matrix * size_matrix) );
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_parite.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_parite.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_parite.c	(revision 3)
@@ -0,0 +1,36 @@
+#include "func_parite.h"
+
+// Renvoye 1 si le nombre de bit a 1 est impaire
+//         0                             paire
+
+bool parite1(int x,int val_parite)
+{
+  int  mask = 1;
+  bool res  = ( (val_parite & mask) ^ mask); //si bit de poids faible à zero alors parité pair
+  
+  while(x!=0)
+    { 
+      res ^= (x & mask);
+      x = x >> 1;
+    }
+   
+  return res;
+}
+
+
+extern unsigned int find_first_one (int x);
+
+bool parite2(int x,int val_parite)
+{
+  unsigned int mask = 1;
+  unsigned int pos;
+  bool         res  = ( (val_parite & mask) ^ mask); //si bit de poids faible à zero alors parité pair
+
+  while ((pos = find_first_one(x)) != 0)
+    {
+      res ^= 1;
+      x    = x >> pos;
+    }
+    
+  return res;
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_premier.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_premier.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_premier.c	(revision 3)
@@ -0,0 +1,35 @@
+#include "func_math.h"
+#include "func_premier.h"
+
+//-----[ Premier ]---------------------------------------------------------
+
+unsigned int premier(unsigned int x)
+{
+  unsigned int it;
+
+  if (x <= 0)
+    return 0;
+  
+  if (x <= 2)
+    return 1;
+
+  for(it=2; it <= (x/2); it++)
+    if (modulo(x,it) == 0)
+      return 0;
+  
+  return 1;
+}
+
+unsigned int n_premier(unsigned int nieme_premier)
+{
+  unsigned int nb_find  = 0;
+  unsigned int res      = 1;
+  while (nb_find < nieme_premier)
+    {
+      res ++;
+      if (premier(res) == 1)
+        nb_find ++;
+    }
+  return res;
+}
+
Index: /trunk/Softwares/Basic_test.or32/src/c/func_test.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_test.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_test.c	(revision 3)
@@ -0,0 +1,617 @@
+#include "func_test.h"
+#include "func_array.h"
+#include "func_endianness.h"
+#include "func_factoriel.h"
+#include "func_fibonnacci.h"
+#include "func_hanoi.h"
+#include "func_integrity.h"
+#include "func_io.h"
+#include "func_math.h"
+#include "func_mm.h"
+#include "func_parite.h"
+#include "func_premier.h"
+#include "func_test.h"
+#include "func_test_io.h"
+
+
+                      // mul_soft
+                      // div_soft
+                      // mul_hard
+                      // div_hard
+                      // modulo
+#define PARAM_06 30   // fibonnacci    max : 43
+#define PARAM_07 15   // n_premier     max : 30
+#define PARAM_08 100  // tri_croissant max : unlimited (200)
+#define PARAM_09 10   // hanoi         max : 12
+#define PARAM_10 15   // mul matrix    max : unlimited (30)
+#define PARAM_11 12   // factoriel_rec max : 12
+#define PARAM_12 12   // factoriel_it  max : 12
+#define PARAM_13 50   // parite        max : unlimited (200)
+
+//----------------------------------
+// TEST 1
+// multiplication software
+//----------------------------------
+int test_01 ()
+{
+  int op1, op2, wait, res, test1;
+#ifdef HAVE_LIBC  
+  printf("Test_01 - mult_soft\n");
+#else
+  print(0xABCD0001);
+#endif
+
+  test1 = 1;
+  {
+#ifdef HAVE_LIBC  
+    printf(" * Test_01a\n");
+#else
+    print(0xABCD001A);
+#endif
+
+    op1     = 40;
+    op2     = 17;
+    wait    = 680; // 0x2a8
+    res     = mul_soft(op1,op2);
+
+    print(res);     
+    test1 &= (wait == res);
+  }
+  {
+#ifdef HAVE_LIBC  
+    printf(" * Test_01b\n");
+#else
+    print(0xABCD001B);
+#endif
+
+    op1     = 1569;
+    op2     = 9835;
+    wait    = 15431115; // 0xEB75CB
+    res     = mul_soft(op1,op2);
+
+    print(res);     
+    test1 &= (wait == res);
+  }
+  
+  return test1;
+}
+
+//----------------------------------
+// TEST 2
+// division       software
+//----------------------------------
+int test_02 ()
+{
+  int op1, op2, wait, res, test2;
+#ifdef HAVE_LIBC
+  printf("Test_02 - div_soft\n");
+#else
+  print(0xABCD0002);
+#endif
+  
+  test2 = 1;
+  {
+#ifdef HAVE_LIBC  
+    printf(" * Test_02a\n");
+#else
+    print(0xABCD002A);
+#endif
+
+    op1     = 680;
+    op2     = 40;
+    wait    = 17; // 0x11
+    res     = div_soft(op1,op2);
+
+    print(res);     
+    test2 &= (wait == res);
+ }
+ {
+#ifdef HAVE_LIBC  
+    printf(" * Test_02b\n");
+#else
+    print(0xABCD002B);
+#endif
+   
+    op1     = 15431115; // eb75cb
+    op2     = 9835;     //   266b
+    wait    = 1569;     //    621
+    res     = div_soft(op1,op2);
+    
+    print(res);     
+    test2 &= (wait == res);
+ }
+  
+  return test2;
+}
+
+//----------------------------------
+// TEST 3
+// multiplication hardware (*)
+//----------------------------------
+int test_03 ()
+{
+  int op1, op2, wait, res;
+#ifdef HAVE_LIBC
+  printf("Test_03 - mul_hard\n");  
+#else
+  print(0xABCD0003);
+#endif
+  
+  op1     = 1569;
+  op2     = 9835;
+  wait    = 15431115; // 0xEB75CB
+  res     = mul_hard(op1,op2);
+
+  print(res);     
+  return (wait == res);
+}
+
+//----------------------------------
+// TEST 4
+// division       hardware (/)
+//----------------------------------
+int test_04 ()
+{
+  int op1, op2, wait, res;
+#ifdef HAVE_LIBC
+  printf("Test_04 - div_hard\n");  
+#else
+  print(0xABCD0004);
+#endif
+  
+  op1     = 15431115;
+  op2     = 9835;
+  wait    = 1569; // 0x621
+  res     = div_hard(op1,op2);
+
+  print(res);     
+  return (wait == res);
+}
+
+
+//----------------------------------
+// TEST 5
+// modulo
+//----------------------------------
+int test_05 ()
+{
+  int op1, op2, wait, res;
+#ifdef HAVE_LIBC
+  printf("Test_05 - modulo\n");  
+#else
+  print(0xABCD0005);
+#endif
+  
+  op1     = 16834;
+  op2     = 563;
+  wait    = 507; // 0x1fb
+  res     = modulo(op1,op2);
+
+  print(res);     
+  return (wait == res);
+}
+
+//----------------------------------
+// TEST 6
+// fibonnacci
+//----------------------------------
+int test_06 ()
+{
+  int it, test;
+  int x     = PARAM_06;
+  int x_max = 43;
+
+  int res  [x_max+1];
+  int wait [x_max+1];
+#ifdef HAVE_LIBC
+  printf("Test_06 - fibonnacci\n");
+#else
+  print(0xABCD0006);
+#endif
+  wait [0]  = 1;          // 1
+  wait [1]  = 2;          // 2
+  wait [2]  = 3;          // 3
+  wait [3]  = 5;          // 5
+  wait [4]  = 8;          // 8
+  wait [5]  = 13;         // d
+  wait [6]  = 21;         // 15
+  wait [7]  = 34;         // 22
+  wait [8]  = 55;         // 37
+  wait [9]  = 89;         // 59
+  wait [10] = 144;        // 90
+  wait [11] = 233;        // e9
+  wait [12] = 377;        // 179
+  wait [13] = 610;        // 262
+  wait [14] = 987;        // 3db
+  wait [15] = 1597;       // 63d
+  wait [16] = 2584;       // a18
+  wait [17] = 4181;       // 1055
+  wait [18] = 6765;       // 1a6d
+  wait [19] = 10946;      // 2ac2
+  wait [20] = 17711;      // 452f
+  wait [21] = 28657;      // 6ff1
+  wait [22] = 46368;      // b520
+  wait [23] = 75025;      // 12511
+  wait [24] = 121393;     // 1da31
+  wait [25] = 196418;     // 2ff42
+  wait [26] = 317811;     // 4d973
+  wait [27] = 514229;     // 7d8b5
+  wait [28] = 832040;     // cb228
+  wait [29] = 1346269;    // 148add
+  wait [30] = 2178309;    // 213d05
+  wait [31] = 3524578;    // 35c7e2
+  wait [32] = 5702887;    // 5704e7
+  wait [33] = 9227465;    // 8cccc9
+  wait [34] = 14930352;   // e3d1b0
+  wait [35] = 24157817;   // 1709e79
+  wait [36] = 39088169;   // 2547029
+  wait [37] = 63245986;   // 3c50ea2
+  wait [38] = 102334155;  // 6197ecb
+  wait [39] = 165580141;  // 9de8d6d
+  wait [40] = 267914296;  // ff80c38
+  wait [41] = 433494437;  // 19d699a5
+  wait [42] = 701408733;  // 29cea5dd
+  wait [43] = 1134903170; // 43a53f82
+  
+  for (it = 0; it <= x ; it ++)
+    {
+      res [it] = fibonnacci (it);
+    }
+  
+  test = 1;
+  
+  for (it = 0; it <= x ; it ++)
+    test &= (res [it] == wait [it]);
+
+  print(test);
+  return (test);
+}
+
+//----------------------------------
+// TEST 7
+// n_premier
+// *
+//----------------------------------
+int test_07 ()
+{
+  unsigned int it, test;
+  unsigned int x     = PARAM_07;  
+  unsigned int x_max = 30;
+  unsigned int res  [x_max+1];
+  unsigned int wait [x_max+1];
+#ifdef HAVE_LIBC
+  printf("Test_07 - n_premier\n");  
+#else
+  print(0xABCD0007);
+#endif
+
+  wait [0] = 1; // 1
+  wait [1] = 2; // 2
+  wait [2] = 3; // 3
+  wait [3] = 5; // 5
+  wait [4] = 7; // 7
+  wait [5] = 11; // b
+  wait [6] = 13; // d
+  wait [7] = 17; // 11
+  wait [8] = 19; // 13
+  wait [9] = 23; // 17
+  wait [10] = 29; // 1d
+  wait [11] = 31; // 1f
+  wait [12] = 37; // 25
+  wait [13] = 41; // 29
+  wait [14] = 43; // 2b
+  wait [15] = 47; // 2f
+  wait [16] = 53; // 35
+  wait [17] = 59; // 3b
+  wait [18] = 61; // 3d
+  wait [19] = 67; // 43
+  wait [20] = 71; // 47
+  wait [21] = 73; // 49
+  wait [22] = 79; // 4f
+  wait [23] = 83; // 53
+  wait [24] = 89; // 59
+  wait [25] = 97; // 61
+  wait [26] = 101; // 65
+  wait [27] = 103; // 67
+  wait [28] = 107; // 6b
+  wait [29] = 109; // 6d
+  wait [30] = 113; // 71
+
+  for (it = 0; it <= x ; it ++)
+    {
+      res [it] = n_premier(it);
+      print (res [it]);
+    }
+    
+  test = 1;
+  
+  for (it = 0; it <= x ; it ++)
+    test &= (res [it] == wait [it]);
+
+  print(test);
+  return (test);
+}
+
+//----------------------------------
+// TEST 8
+// tri_croissant (tableau d'int)
+// tri_croissant (tableau de short)
+// tri_croissant (tableau de char)
+// *
+//----------------------------------
+#include <string.h>
+#include <stdlib.h>
+
+int test_08 ()
+{
+  int       x           = PARAM_08;
+  const int size        = x;
+  const int nb_algo_max = 4;
+  
+  int       array_ref [size];
+  int       array     [nb_algo_max][size];  
+  int       it;
+  int       nb_algo;
+  
+  /* 
+   * PHASE 1 : Initialisation
+   */
+  
+  // Remplir le tableau
+  
+  srand(0);
+  
+  for (it = 0; it < size ; it++)
+    {
+      array_ref [it] = rand();
+      for (nb_algo = 0; nb_algo < nb_algo_max; nb_algo ++)
+	array[nb_algo][it] = array_ref [it];
+    }
+  
+  {
+#ifdef HAVE_LIBC
+  printf("Test_08 - tri_croissant\n");  
+#else
+    print(0xABCD0008);
+#endif
+
+    for (nb_algo = 0; nb_algo < nb_algo_max; nb_algo ++)
+      {
+//	  for (it = 0; it < size ; it++)
+//	    printf("%d ",array [it]);
+//	  printf("\n");
+	  	      
+	  /*
+	   * PHASE 2 : Exécution
+	   */
+#ifdef HAVE_LIBC
+	  printf(" * tri_croissant - algo %d\n",nb_algo);  
+#endif
+	  print(0xABCD08a0 | nb_algo);
+	  array_tri_croissant   (array[nb_algo]  ,size,nb_algo);
+	  print(0xABCD08b0 | nb_algo);
+
+//	  for (it = 0; it < size ; it++)
+//	    printf("%d ",array [it]);
+//	  printf("\n");
+      }
+  }
+
+  /* 
+   * PHASE 3 : Vérification des résultats
+   */
+  
+  // Vérifier le résultat : compte le nombre de case identique par algoritme
+  for (it = 0; it < size ; it++)
+    {
+      int val = array[0][it];
+      
+      for (nb_algo = 1; nb_algo < nb_algo_max; nb_algo ++)
+	if (val != array[nb_algo][it])
+	  return 0;
+    }
+
+  return (1);
+}
+
+//----------------------------------
+// TEST 9 - hanoi
+// 
+//----------------------------------
+int test_09 ()
+{
+  unsigned int it, test;
+  unsigned int x     = PARAM_09;
+  unsigned int x_max = 12;
+  
+  unsigned int res  [x_max+1];
+  unsigned int wait [x_max+1];
+#ifdef HAVE_LIBC
+  printf("Test_09 - hanoi\n");  
+#else
+  print(0xABCD0009);
+#endif
+  
+  wait [1] = 1; // 1
+  wait [2] = 3; // 3
+  wait [3] = 7; // 7
+  wait [4] = 15; // f
+  wait [5] = 31; // 1f
+  wait [6] = 63; // 3f
+  wait [7] = 127; // 7f
+  wait [8] = 255; // ff
+  wait [9] = 511; // 1ff
+  wait [10] = 1023; // 3ff
+  wait [11] = 2047; // 7ff
+  wait [12] = 4095; // fff
+  
+  for (it = 1; it <= x ; it ++)
+    {
+      res [it] = hanoi (it);
+
+      print(res [it]);
+    }
+  
+  test = 1;
+  
+  for (it = 1; it <= x ; it ++)
+    test &= (res [it] == wait [it]);
+
+  print(test);
+  return (test);
+  
+}
+
+//----------------------------------
+// TEST 10
+// multiplication de matrice
+// *
+//----------------------------------
+int test_10 ()
+{
+  int op1, op2, res;
+  int x     = PARAM_10;
+#ifdef HAVE_LIBC
+  printf("Test_10 - multiplication de matrice\n");  
+#else
+  print(0xABCD0010);
+#endif
+  
+  op1     = x;
+  op2     = 1;
+  res     = mm(op1,op2);
+
+  print(res);     
+  return (res);
+}
+
+//----------------------------------
+// TEST 11
+// factoriel_recursif
+//----------------------------------
+int test_11 ()
+{
+  unsigned int it, test;
+  unsigned int x     = PARAM_11;
+  unsigned int x_max = 12;
+  
+  unsigned int res  [x_max+1];
+  unsigned int wait [x_max+1];
+#ifdef HAVE_LIBC
+  printf("Test_11 - factoriel recursif\n");  
+#else
+  print(0xABCD0011);
+#endif
+
+  wait[0]  = 1;         // 1
+  wait[1]  = 1;         // 1
+  wait[2]  = 2;         // 2
+  wait[3]  = 6;         // 6
+  wait[4]  = 24;        // 18
+  wait[5]  = 120;       // 78
+  wait[6]  = 720;       // 2d0
+  wait[7]  = 5040;      // 13b0
+  wait[8]  = 40320;     // 9d80
+  wait[9]  = 362880;    // 58980
+  wait[10] = 3628800;   // 375f00
+  wait[11] = 39916800;  // 2611500
+  wait[12] = 479001600; // 1c8cfc00
+
+  for (it = 0; it <= x ; it ++)
+    res [it] = fact_recursif (it);
+  
+  test = 1;
+  
+  for (it = 0; it <= x ; it ++)
+    test &= (res [it] == wait [it]);
+
+  print(test);
+  return (test);
+}
+
+//----------------------------------
+// TEST 12
+// factoriel_iteratif
+//----------------------------------
+int test_12 ()
+{
+  unsigned int it, test;
+  
+  unsigned int x     = PARAM_12;
+  unsigned int x_max = 12;
+  
+  unsigned int res  [x_max+1];
+  unsigned int wait [x_max+1];
+#ifdef HAVE_LIBC
+  printf("Test_12 - factoriel_iteratif\n");  
+#else
+  print(0xABCD0012);
+#endif
+
+  wait[0]  = 1;         // 1
+  wait[1]  = 1;         // 1
+  wait[2]  = 2;         // 2
+  wait[3]  = 6;         // 6
+  wait[4]  = 24;        // 18
+  wait[5]  = 120;       // 78
+  wait[6]  = 720;       // 2d0
+  wait[7]  = 5040;      // 13b0
+  wait[8]  = 40320;     // 9d80
+  wait[9]  = 362880;    // 58980
+  wait[10] = 3628800;   // 375f00
+  wait[11] = 39916800;  // 2611500
+  wait[12] = 479001600; // 1c8cfc00
+
+  for (it = 0; it <= x ; it ++)
+    res [it] = fact_iteratif (it);
+  
+  test = 1;
+  
+  for (it = 0; it <= x ; it ++)
+    test &= (res [it] == wait [it]);
+
+  print(test);
+  return (test);
+}
+
+//----------------------------------
+// TEST 13
+// parite
+//----------------------------------
+int test_13 ()
+{
+  unsigned int it;
+  unsigned int x     = PARAM_13;
+  unsigned int pair,test;
+  
+#define TEST(a,b) ( ( (a) ^ (b) ) == 0)?1:0
+#ifdef HAVE_LIBC
+  printf("Test_13 - parite\n");  
+#else
+  print(0xABCD0013);
+#endif
+  
+  test = 1;
+
+  pair = 1;
+  srand(0);
+  for (it = 0; (it < x) && (test == 1); it ++)
+    {
+      unsigned int val = (unsigned int) rand();
+      unsigned int val1 = parite1(val,pair);
+      unsigned int val2 = parite2(val,pair);
+      test &= TEST(val1,val2); // Test if 2 implementation produced the same result
+    }
+  print(test);
+
+  pair ^= 1;
+  for (it = 0; (it < x) && (test == 1); it ++)
+    {
+      unsigned int val = (unsigned int) rand();
+      unsigned int val1 = parite1(val,pair);
+      unsigned int val2 = parite2(val,pair);
+      test &= TEST(val1,val2); // Test if 2 implementation produced the same result
+    }
+  print(test);
+  return (test);
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/func_test_io.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_test_io.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_test_io.c	(revision 3)
@@ -0,0 +1,72 @@
+#include "func_test_io.h"
+#include <errno.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+//-----[ func_test_io ]---------------------------------------------------------
+
+bool func_test_io()
+{
+  /*
+  {
+    FILE       * file;
+    const char * filename = "files/write.txt";
+    const char * string   = "La technologie au service de la paix\n";
+
+    printf("Test write in file\n"); 
+    
+    if ((file = fopen (filename,"w")) == NULL)
+      printf("fopen  : Ko - errno : %x - %s\n",errno,strerror(errno));
+    else
+      {
+	printf("fopen  : Ok\n");
+    
+	if (fputs (string,file) == EOF)
+	  printf("fputs  : Ko - errno : %x - %s\n",errno,strerror(errno));
+	else
+	  printf("fputs  : Ok\n");
+
+	if (fputs ("La paix par le pouvoir\n",file) == EOF)
+	  printf("fputs  : Ko - errno : %x - %s\n",errno,strerror(errno));
+	else
+	  printf("fputs  : Ok\n");
+    
+	if (fclose (file) == EOF)
+	  printf("fclose : Ko - errno : %x - %s\n",errno,strerror(errno));
+	else
+	  printf("fclose : Ok\n");
+      }
+  }
+  */
+  {
+    FILE       * file;
+    const char * filename = "files/read.txt";
+    char * string = (char *) malloc (100);
+
+    printf("Test read  in file\n");
+    
+    if ((file = fopen (filename,"r")) == NULL)
+      printf("fopen  : Ko - errno : %x - %s\n",errno,strerror(errno));
+    else
+      {
+	printf("fopen  : Ok\n");
+	string = fgets (string,50,file);
+	
+	while (string != NULL)
+	  {
+	    print (string);
+	    printf("fputs  : %s\n",string);
+	    string = fgets (string,50,file);
+	  }
+	    
+	print(string);
+	
+	if (fclose (file) == EOF)
+	  printf("fclose : Ko - errno : %x - %s\n",errno,strerror(errno));
+	else
+	  printf("fclose : Ok\n");
+      }
+  }
+  return true;
+}// end fct func_test_io
Index: /trunk/Softwares/Basic_test.or32/src/c/func_test_lock.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/func_test_lock.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/func_test_lock.c	(revision 3)
@@ -0,0 +1,86 @@
+#include "func_test_lock.h"
+#include <sys/lock.h>
+__LOCK_INIT(static,lock1);
+static int val1 = 0;
+void test_lock1 ()
+{
+  __lock_init    (lock1);
+  print((unsigned int)lock1.mutex);
+    
+  while (val1 < 100)
+    {
+      __lock_acquire (lock1);
+      print(val1);
+      val1 ++;
+      __lock_release (lock1);
+    }
+
+  __lock_close   (lock1);
+}
+
+__LOCK_INIT(static,lock2);
+static int val2 = 0;
+void test_lock2 ()
+{
+  __lock_init    (lock2);
+  print((unsigned int)lock2.mutex);
+  while (val2 < 100)
+    {
+      if (__lock_try_acquire (lock2) == 1)
+	{
+	  print(val2);
+	  val2 ++;
+	  __lock_release (lock2);
+	}
+    }
+  
+  __lock_close   (lock2);
+}
+
+__LOCK_INIT_RECURSIVE(static,lock_recursive1);
+static int val_recursive1 = 0;
+void test_lock_recursive1 ()
+{
+  __lock_init_recursive    (lock_recursive1);
+  print((unsigned int)lock_recursive1.mutex);
+  
+  while (val_recursive1 < 100)
+    {
+      __lock_acquire_recursive (lock_recursive1);
+      __lock_acquire_recursive (lock_recursive1);
+      print(val_recursive1);
+      val_recursive1 ++;
+      __lock_release_recursive (lock_recursive1);
+      print(val_recursive1);
+      val_recursive1 ++;
+      __lock_release_recursive (lock_recursive1);
+    }
+
+  __lock_close_recursive   (lock_recursive1);
+}
+
+__LOCK_INIT_RECURSIVE(static,lock_recursive2);
+static int val_recursive2 = 0;
+void test_lock_recursive2 ()
+{
+  __lock_init_recursive    (lock_recursive2);
+  print((unsigned int)lock_recursive2.mutex);  
+
+  while (val_recursive2 < 100)
+    {
+      if (__lock_try_acquire_recursive (lock_recursive2) == 1)
+	{
+	  if (__lock_try_acquire_recursive (lock_recursive2) == 1)
+	    {
+	      print(val_recursive2);
+	      val_recursive2 ++;
+	      __lock_release_recursive (lock_recursive2);
+	    }
+	  print(val_recursive2);
+	  val_recursive2 ++;
+	  __lock_release_recursive (lock_recursive2);
+	}
+    }
+  
+  __lock_close_recursive   (lock_recursive2);
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/include/bottles.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/bottles.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/bottles.h	(revision 3)
@@ -0,0 +1,2 @@
+
+void bottles();
Index: /trunk/Softwares/Basic_test.or32/src/c/include/dhry.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/dhry.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/dhry.h	(revision 3)
@@ -0,0 +1,408 @@
+/*
+ *************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry.h (part 1 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *              Siemens Nixdorf Inf. Syst.
+ *              STM OS 32
+ *              Otto-Hahn-Ring 6
+ *              W-8000 Muenchen 83
+ *              Germany
+ *                      Phone:    [+49]-89-636-42436
+ *                                (8-17 Central European Time)
+ *                      UUCP:     weicker@ztivax.uucp@unido.uucp
+ *                      Internet: weicker@ztivax.siemens.com
+ *
+ *              Original Version (in Ada) published in
+ *              "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ *              pp. 1013 - 1030, together with the statistics
+ *              on which the distribution of statements etc. is based.
+ *
+ *              In this C version, the following C library functions are
+ *              used:
+ *              - strcpy, strcmp (inside the measurement loop)
+ *              - printf, scanf (outside the measurement loop)
+ *
+ *  Collection of Results:
+ *              Reinhold Weicker (address see above) and
+ *              
+ *              Rick Richardson
+ *              PC Research. Inc.
+ *              94 Apple Orchard Drive
+ *              Tinton Falls, NJ 07724
+ *                      Phone:  (201) 834-1378 (9-17 EST)
+ *                      UUCP:   ...!uunet!pcrat!rick
+ *
+ *      Please send results to Rick Richardson and/or Reinhold Weicker.
+ *      Complete information should be given on hardware and software
+ *      used. Hardware information includes: Machine type, CPU, type and
+ *      size of caches; for microprocessors: clock frequency, memory speed
+ *      (number of wait states). Software information includes: Compiler
+ *      (and runtime library) manufacturer and version, compilation
+ *      switches, OS version. The Operating System version may give an
+ *      indication about the compiler; Dhrystone itself performs no OS
+ *      calls in the measurement loop.
+ *
+ *      The complete output generated by the program should be mailed
+ *      such that at least some checks for correctness can be made.
+ *
+ *************************************************************************
+ *
+ *  History:    This version C/2.1 has been made for two reasons:
+ *
+ *              1) There is an obvious need for a common C version of
+ *              Dhrystone, since C is at present the most popular system
+ *              programming language for the class of processors
+ *              (microcomputers, minicomputers) where Dhrystone is used
+ *              most. There should be, as far as possible, only one C
+ *              version of Dhrystone such that results can be compared
+ *              without restrictions. In the past, the C versions
+ *              distributed by Rick Richardson (Version 1.1) and by
+ *              Reinhold Weicker had small (though not significant)
+ *              differences.
+ *
+ *              2) As far as it is possible without changes to the
+ *              Dhrystone statistics, optimizing compilers should be
+ *              prevented from removing significant statements.
+ *
+ *              This C version has been developed in cooperation with
+ *              Rick Richardson (Tinton Falls, NJ), it incorporates many
+ *              ideas from the "Version 1.1" distributed previously by
+ *              him over the UNIX network Usenet.
+ *              I also thank Chaim Benedelac (National Semiconductor),
+ *              David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ *              Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ *              for their help with comments on earlier versions of the
+ *              benchmark.
+ *
+ *  Changes:    In the initialization part, this version follows mostly
+ *              Rick Richardson's version distributed via Usenet, not the
+ *              version distributed earlier via floppy disk by Reinhold
+ *              Weicker. As a concession to older compilers, names have
+ *              been made unique within the first 8 characters. Inside the
+ *              measurement loop, this version follows the version
+ *              previously distributed by Reinhold Weicker.
+ *
+ *              At several places in the benchmark, code has been added,
+ *              but within the measurement loop only in branches that
+ *              are not executed. The intention is that optimizing
+ *              compilers should be prevented from moving code out of the
+ *              measurement loop, or from removing code altogether. Since
+ *              the statements that are executed within the measurement
+ *              loop have NOT been changed, the numbers defining the
+ *              "Dhrystone distribution" (distribution of statements,
+ *              operand types and locality) still hold. Except for
+ *              sophisticated optimizing compilers, execution times for
+ *              this version should be the same as for previous versions.
+ *
+ *              Since it has proven difficult to subtract the time for the
+ *              measurement loop overhead in a correct way, the loop check
+ *              has been made a part of the benchmark. This does have
+ *              an impact - though a very minor one - on the distribution
+ *              statistics which have been updated for this version.
+ *
+ *              All changes within the measurement loop are described
+ *              and discussed in the companion paper "Rationale for
+ *              Dhrystone version 2".
+ *
+ *              Because of the self-imposed limitation that the order and
+ *              distribution of the executed statements should not be
+ *              changed, there are still cases where optimizing compilers
+ *              may not generate code for some statements. To a certain
+ *              degree, this is unavoidable for small synthetic
+ *              benchmarks. Users of the benchmark are advised to check
+ *              code listings whether code is generated for all statements
+ *              of Dhrystone.
+ *
+ *              Version 2.1 is identical to version 2.0 distributed via
+ *              the UNIX network Usenet in March 1988 except that it
+ *              corrects some minor deficiencies that were found by users
+ *              of version 2.0. The only change within the measurement
+ *              loop is that a non-executed "else" part was added to the
+ *              "if" statement in Func_3, and a non-executed "else" part
+ *              removed from Proc_3.
+ *
+ *************************************************************************
+ *
+ * Defines:     The following "Defines" are possible:
+ *              -DROPT         (default: Not defined)
+ *                      As an approximation to what an average C
+ *                      programmer might do, the "register" storage class
+ *                      is applied (if enabled by -DROPT)
+ *                      - for local variables, if they are used
+ *                        (dynamically) five or more times
+ *                      - for parameters if they are used (dynamically)
+ *                        six or more times
+ *                      Note that an optimal "register" strategy is
+ *                      compiler-dependent, and that "register"
+ *                      declarations do not necessarily lead to faster
+ *                      execution.
+ *              -DNOSTRUCTASSIGN        (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      assignment of structures.
+ *              -DNOENUMS               (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      enumeration types.
+ *
+ *************************************************************************
+ *
+ *  Compilation model and measurement (IMPORTANT):
+ *
+ *  This C version of Dhrystone consists of three files:
+ *  - dhry.h (this file, containing global definitions and comments)
+ *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ *  The following "ground rules" apply for measurements:
+ *  - Separate compilation
+ *  - No procedure merging
+ *  - Otherwise, compiler optimizations are allowed but should be
+ *    indicated
+ *  - Default results are those without register declarations
+ *  See the companion paper "Rationale for Dhrystone Version 2" for a more
+ *  detailed discussion of these ground rules.
+ *
+ *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ *  models ("small", "medium", "large" etc.) should be given if possible,
+ *  together with a definition of these models for the compiler system
+ *  used.
+ *
+ *************************************************************************
+ *
+ *  Dhrystone (C version) statistics:
+ *
+ *  [Comment from the first distribution, updated for version 2.
+ *   Note that because of language differences, the numbers are slightly
+ *   different from the Ada version.]
+ *
+ *  The following program contains statements of a high level programming
+ *  language (here: C) in a distribution considered representative:
+ *
+ *    assignments                  52 (51.0 %)
+ *    control statements           33 (32.4 %)
+ *    procedure, function calls    17 (16.7 %)
+ *
+ *  103 statements are dynamically executed. The program is balanced with
+ *  respect to the three aspects:
+ *
+ *    - statement type
+ *    - operand type
+ *    - operand locality
+ *         operand global, local, parameter, or constant.
+ *
+ *  The combination of these three aspects is balanced only approximately.
+ *
+ *  1. Statement Type:
+ *  -----------------             number
+ *
+ *     V1 = V2                     9
+ *       (incl. V1 = F(..)
+ *     V = Constant               12
+ *     Assignment,                 7
+ *       with array element
+ *     Assignment,                 6
+ *       with record component
+ *                                --
+ *                                34       34
+ *
+ *     X = Y +|-|"&&"|"|" Z        5
+ *     X = Y +|-|"==" Constant     6
+ *     X = X +|- 1                 3
+ *     X = Y *|/ Z                 2
+ *     X = Expression,             1
+ *           two operators
+ *     X = Expression,             1
+ *           three operators
+ *                                --
+ *                                18       18
+ *
+ *     if ....                    14
+ *       with "else"      7
+ *       without "else"   7
+ *           executed        3
+ *           not executed    4
+ *     for ...                     7  |  counted every time
+ *     while ...                   4  |  the loop condition
+ *     do ... while                1  |  is evaluated
+ *     switch ...                  1
+ *     break                       1
+ *     declaration with            1
+ *       initialization
+ *                                --
+ *                                34       34
+ *
+ *     P (...)  procedure call    11
+ *       user procedure      10
+ *       library procedure    1
+ *     X = F (...)
+ *             function  call      6
+ *       user function        5
+ *       library function     1
+ *                                --
+ *                                17       17
+ *                                        ---
+ *                                        103
+ *
+ *    The average number of parameters in procedure or function calls
+ *    is 1.82 (not counting the function values as implicit parameters).
+ *
+ *
+ *  2. Operators
+ *  ------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *    Arithmetic             32          50.8
+ *
+ *       +                     21          33.3
+ *       -                      7          11.1
+ *       *                      3           4.8
+ *       / (int div)            1           1.6
+ *
+ *    Comparison             27           42.8
+ *
+ *       ==                     9           14.3
+ *       /=                     4            6.3
+ *       >                      1            1.6
+ *       <                      3            4.8
+ *       >=                     1            1.6
+ *       <=                     9           14.3
+ *
+ *    Logic                   4            6.3
+ *
+ *       && (AND-THEN)          1            1.6
+ *       |  (OR)                1            1.6
+ *       !  (NOT)               2            3.2
+ * 
+ *                           --          -----
+ *                           63          100.1
+ *
+ *
+ *  3. Operand Type (counted once per operand reference):
+ *  ---------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *     Integer               175        72.3 %
+ *     Character              45        18.6 %
+ *     Pointer                12         5.0 %
+ *     String30                6         2.5 %
+ *     Array                   2         0.8 %
+ *     Record                  2         0.8 %
+ *                           ---       -------
+ *                           242       100.0 %
+ *
+ *  When there is an access path leading to the final operand (e.g. a
+ *  record component), only the final data type on the access path is
+ *  counted.
+ *
+ *
+ *  4. Operand Locality:
+ *  -------------------
+ *                                number    approximate
+ *                                          percentage
+ *
+ *     local variable              114        47.1 %
+ *     global variable              22         9.1 %
+ *     parameter                    45        18.6 %
+ *        value                        23         9.5 %
+ *        reference                    22         9.1 %
+ *     function result               6         2.5 %
+ *     constant                     55        22.7 %
+ *                                 ---       -------
+ *                                 242       100.0 %
+ *
+ *
+ *  The program does not compute anything meaningful, but it is
+ *  syntactically and semantically correct. All variables have a value
+ *  assigned to them before they are used as a source operand.
+ *
+ *  There has been no explicit effort to account for the effects of a
+ *  cache, or to balance the use of long or short displacements for code
+ *  or data.
+ *
+ *************************************************************************
+ */
+
+#ifndef DHRY
+#define DHRY
+
+/* Compiler and system dependent definitions: */
+
+// #ifdef SIM2OS
+// #define DOUBLE unsigned int
+// #define Mic_secs_Per_Second     1000000
+// #else
+#define DOUBLE float
+#define Mic_secs_Per_Second     1000000.0
+// #endif //SIM2OS
+
+                /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef  NOSTRUCTASSIGN
+#define structassign(d, s)      memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s)      d = s
+#endif
+
+#ifdef  NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+  typedef int   Enumeration;
+#else
+  typedef       enum    {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+                Enumeration;
+#endif
+        /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+                /* for strcpy, strcmp */
+
+#define Null 0 
+                /* Value of a Null pointer */
+#define true  1
+#define false 0
+
+typedef int     One_Thirty;
+typedef int     One_Fifty;
+typedef char    Capital_Letter;
+typedef int     Boolean;
+typedef char    Str_30 [31];
+typedef int     Arr_1_Dim [50];
+typedef int     Arr_2_Dim [50] [50];
+
+typedef struct record 
+    {
+    struct record *Ptr_Comp;
+    Enumeration    Discr;
+    union {
+          struct {
+                  Enumeration Enum_Comp;
+                  int         Int_Comp;
+                  char        Str_Comp [31];
+                  } var_1;
+          struct {
+                  Enumeration E_Comp_2;
+                  char        Str_2_Comp [31];
+                  } var_2;
+          struct {
+                  char        Ch_1_Comp;
+                  char        Ch_2_Comp;
+                  } var_3;
+          } variant;
+      } Rec_Type, *Rec_Pointer;
+
+#endif //!DHRY
Index: /trunk/Softwares/Basic_test.or32/src/c/include/dhry21.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/dhry21.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/dhry21.h	(revision 3)
@@ -0,0 +1,15 @@
+#include "dhry.h"
+
+int main_dhry21 ();
+
+void        Proc_1 (Rec_Pointer);
+void        Proc_2 (One_Fifty *);
+void        Proc_3 (Rec_Pointer *);
+void        Proc_4 ();
+void        Proc_5 ();
+void        Proc_6 (Enumeration, Enumeration*);
+void        Proc_7 (One_Fifty,One_Fifty,One_Fifty*);
+void        Proc_8 (Arr_1_Dim,Arr_2_Dim,int,int);
+Enumeration Func_1 (Capital_Letter,Capital_Letter);
+Boolean     Func_2 (Str_30,Str_30);
+Boolean     Func_3 (Enumeration);
Index: /trunk/Softwares/Basic_test.or32/src/c/include/dico.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/dico.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/dico.h	(revision 3)
@@ -0,0 +1,32 @@
+#ifndef DICO_H
+#define DICO_H
+
+#include "bool.h"
+
+//=====[ dico_t ]==========================================
+
+typedef struct dico_st 
+{
+  void           * key;
+  void           * data;
+  
+  struct dico_st * previous;
+  struct dico_st * next;
+} dico_t;
+
+//=====[ function ]========================================
+
+dico_t * dico_add     (dico_t * dico, 
+		       void   * key ,
+		       void   * data);
+
+dico_t * dico_del     (dico_t * dico, 
+		       void   * key );
+
+bool     dico_present (dico_t * dico, 
+		       void   * key );
+
+void *   dico_give    (dico_t * dico, 
+		       void   * key );
+
+#endif //!DICO_H
Index: /trunk/Softwares/Basic_test.or32/src/c/include/exec.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/exec.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/exec.h	(revision 3)
@@ -0,0 +1,6 @@
+#include "bool.h"
+
+bool exec_0();
+bool exec_1();
+bool exec_2();
+bool exec_3();
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_array.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_array.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_array.h	(revision 3)
@@ -0,0 +1,2 @@
+
+void array_tri_croissant (int * array, unsigned int size,int algo);
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_endianness.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_endianness.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_endianness.h	(revision 3)
@@ -0,0 +1,18 @@
+#include "bool.h"
+
+#define LittleEndian false
+#define BigEndian    true
+
+union TestEndian 
+{
+  unsigned long total;
+  struct 
+  {
+    unsigned char octet1;
+    unsigned char octet2;
+    unsigned char octet3;
+    unsigned char octet4;
+  } octets;
+};
+
+bool endianness ();
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_factoriel.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_factoriel.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_factoriel.h	(revision 3)
@@ -0,0 +1,2 @@
+unsigned int fact_recursif (unsigned int x);
+unsigned int fact_iteratif (unsigned int x);
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_fibonnacci.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_fibonnacci.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_fibonnacci.h	(revision 3)
@@ -0,0 +1,1 @@
+int fibonnacci(int x);
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_hanoi.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_hanoi.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_hanoi.h	(revision 3)
@@ -0,0 +1,1 @@
+int hanoi(int nb_disques);
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_integrity.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_integrity.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_integrity.h	(revision 3)
@@ -0,0 +1,3 @@
+#include "bool.h"
+
+bool test_integrity ();
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_math.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_math.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_math.h	(revision 3)
@@ -0,0 +1,10 @@
+unsigned int mul_soft ( unsigned int op1,
+		        unsigned int op2);
+unsigned int mul_hard ( unsigned int op1,
+		        unsigned int op2);
+unsigned int div_soft ( unsigned int op1,
+		        unsigned int op2);
+unsigned int div_hard ( unsigned int op1,
+		        unsigned int op2);
+unsigned int modulo   ( unsigned int x,
+		        unsigned int base);
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_mm.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_mm.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_mm.h	(revision 3)
@@ -0,0 +1,1 @@
+int mm(unsigned int size_matrix, unsigned int algo);
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_parite.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_parite.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_parite.h	(revision 3)
@@ -0,0 +1,7 @@
+#include "bool.h"
+
+// Renvoye 1 si le nombre de bit a 1 est impaire
+//         0                             paire
+
+bool parite1(int x,int val_parite);
+bool parite2(int x,int val_parite);
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_premier.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_premier.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_premier.h	(revision 3)
@@ -0,0 +1,2 @@
+unsigned int premier(unsigned int x);
+unsigned int n_premier(unsigned int nieme_premier);
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_test.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_test.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_test.h	(revision 3)
@@ -0,0 +1,16 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+int test_01();
+int test_02();
+int test_03();
+int test_04();
+int test_05();
+int test_06();
+int test_07();
+int test_08();
+int test_09();
+int test_10();
+int test_11();
+int test_12();
+int test_13();
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_test_io.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_test_io.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_test_io.h	(revision 3)
@@ -0,0 +1,4 @@
+#include "bool.h"
+
+
+bool func_test_io();
Index: /trunk/Softwares/Basic_test.or32/src/c/include/func_test_lock.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/func_test_lock.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/func_test_lock.h	(revision 3)
@@ -0,0 +1,4 @@
+void test_lock1           ();
+void test_lock2           ();
+void test_lock_recursive1 ();
+void test_lock_recursive2 ();
Index: /trunk/Softwares/Basic_test.or32/src/c/include/test_setjmp.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/test_setjmp.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/test_setjmp.h	(revision 3)
@@ -0,0 +1,2 @@
+
+void test_setjmp ();
Index: /trunk/Softwares/Basic_test.or32/src/c/include/workload.h
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/include/workload.h	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/include/workload.h	(revision 3)
@@ -0,0 +1,16 @@
+#include "dhry21.h"
+#include "exec.h"
+
+/*
+ * Array of function's pointer
+ */
+
+void (*WorkLoad[])() = 
+{ 
+  (void *)exec_0 ,
+  (void *)exec_1 ,
+  (void *)exec_2 ,
+  (void *)exec_3
+};
+
+#define NB_WORKLOAD (sizeof(WorkLoad)/sizeof(void *))
Index: /trunk/Softwares/Basic_test.or32/src/c/main.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/main.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/main.c	(revision 3)
@@ -0,0 +1,242 @@
+#include <sys/lock.h>
+#include <sys/reent.h>
+#include <errno.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <math.h>
+
+#include "bool.h"
+#include "test_setjmp.h"
+#include "func_io.h"
+#include "func_test_io.h"
+#include "func_test_lock.h"
+#include "func_integrity.h"
+#include "thread_info.h"
+#include "cpu_info.h"
+#include "uncached_mask.h"
+#include "bottles.h"
+
+#include "workload.h"
+
+#define verbose_none      0
+#define verbose_low       1
+#define verbose_medium    2
+#define verbose_high      3
+#define VERBOSE_SYSTEM    verbose_none
+#define HAVE_SYSTEM       1
+
+void init_thread  ();
+void exit_thread  ();
+#if (HAVE_SYSTEM != 0)
+void init_system  ();
+void exit_system  ();
+#endif //HAVE_SYSTEM
+
+//~~~~~[ global variable ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+__LOCK_INIT(static,system_lock);
+
+#if (HAVE_SYSTEM != 0)
+static volatile bool         system_init   = false;
+#endif //HAVE_SYSTEM
+static volatile unsigned int nb_thread_run = 0;
+
+//=====[ main ]=================================================================
+/*
+ * All thread execute this routine
+ * Initialize the thread and attribute a Workload at each thread
+ */
+
+int main()
+{
+  init_thread();
+
+/*   test_integrity (); */
+/*   test_setjmp(); */
+/*   func_test_io(); */
+/*   test_lock1(); */
+/*   test_lock2(); */
+/*   test_lock_recursive1(); */
+/*   test_lock_recursive2(); */
+
+  /*
+   * Lunch thread with a Workload
+   */
+#if (VERBOSE_SYSTEM >= verbose_medium)
+  printf("<main> : lunch workload\n");
+#endif //VERBOSE_SYSTEM
+
+  {
+   int pid = (int)getpid();
+
+   if (pid < NB_WORKLOAD)
+     (*WorkLoad[pid])();
+   else
+     printf("<main> pid is %d but the number of function in the workload is %d\n",pid,(int)NB_WORKLOAD);
+  }
+  
+#if (VERBOSE_SYSTEM >= verbose_medium)
+  printf("<main> : exit workload\n");
+#endif //VERBOSE_SYSTEM
+  
+  exit (0);
+}
+
+//-----[ init_thread ]----------------------------------------------------------
+/*
+ * Initialize all thread
+ */
+
+void init_thread()
+{
+  unsigned int pid;
+
+  set_uncached_mask (0x80000000);
+  
+  __lock_init    (system_lock);
+
+  // Test if is the first thread -> initialization of system
+  __lock_acquire (system_lock);
+  pid = nb_thread_run ++;
+  __lock_release (system_lock);
+  
+  // Change parameters of thread
+  //  * Identificator
+  //  * Priority
+  set_thread_id       (pid);
+  set_thread_priority (0xF);
+
+  // Initialize Reentrant structure
+  _REENT_INIT_PTR(_REENT);
+
+#if (HAVE_SYSTEM != 0)
+  if (pid == 0)
+    init_system();
+  
+  while (system_init == false);
+#endif //HAVE_SYSTEM
+
+
+  // Test if is the first thread -> initialization of system
+  atexit (exit_thread);
+
+  print((get_thread_id() << 16) | get_cpu_id());
+  
+#if (VERBOSE_SYSTEM >= verbose_low)
+  printf("<init_thread> Thread[%d] executed on CPU[%d]\n",getpid(),get_cpu_id());
+#endif //VERBOSE_SYSTEM
+}
+
+//-----[ exit_thread ]----------------------------------------------------------
+/*
+ * Free all ressource
+ */
+
+void exit_thread()
+{
+  bool last = false;
+
+#if (VERBOSE_SYSTEM >= verbose_low)
+  printf("<exit_thread> Thread[%d] is finish\n",getpid());
+#endif //VERBOSE_SYSTEM
+  
+  __lock_acquire (system_lock);
+  
+  nb_thread_run --;
+  last = (nb_thread_run == 0)?true:false;
+  
+  __lock_release (system_lock);
+
+#if (HAVE_SYSTEM != 0)
+  if (last == true)
+    exit_system();
+#endif //HAVE_SYSTEM
+
+  quit(getpid());
+
+  while(1);
+}
+
+
+#if (HAVE_SYSTEM != 0)
+//-----[ init_system ]----------------------------------------------------------
+/*
+ * Initialize all system
+ */
+
+void init_system()
+{
+#if (VERBOSE_SYSTEM >= verbose_high)
+  time_t * my_time = (time_t *) malloc (sizeof (time_t));
+
+  if (my_time == NULL)
+    {
+      printf("<init_system> {error} malloc\n");
+      exit(-1);
+    }
+  
+  if (time(my_time) == ((time_t)-1))
+    {
+      printf("<init_system> {error} time\n");
+      exit (-1);
+    }
+  
+  printf("<init_system> System boot     - %s",ctime(my_time));
+
+  free(my_time);
+#else
+#if (VERBOSE_SYSTEM >= verbose_low)
+  printf("<init_system> System boot\n");
+#endif //VERBOSE_SYSTEM
+#endif //VERBOSE_SYSTEM
+
+#if (VERBOSE_SYSTEM >= verbose_medium)
+  printf("\n");
+  printf("@     @    @@@@    @@@@@    @@@@@    @    @   @@@@@@    @@@@     \n");
+  printf("@@   @@   @    @   @    @   @    @   @    @   @        @    @    \n");
+  printf("@ @@@ @   @    @   @@@@@    @@@@@    @@@@@@   @@@@     @    @    \n");
+  printf("@     @   @    @   @    @   @        @    @   @        @    @    \n");
+  printf("@     @    @@@@    @    @   @        @    @   @@@@@@    @@@@     \n");
+  printf("@     @utiple ORganization for a Processor HEterogenous and Open.\n");
+  printf("\n");
+#endif //VERBOSE_SYSTEM
+
+  system_init = true;
+}
+
+//-----[ exit_system ]----------------------------------------------------------
+/*
+ * Free all ressource
+ */
+
+void exit_system()
+{
+#if (VERBOSE_SYSTEM >= verbose_high)
+  time_t * my_time = (time_t *) malloc (sizeof (time_t));
+  
+  if (my_time == NULL)
+    {
+      printf("<exit_system> {error} malloc\n");
+      exit(-1);
+    }
+  
+  if (time(my_time) == ((time_t)-1))
+    {
+      printf("<exit_system> {error} time\n");
+      exit (-1);
+    }
+  
+  printf("<exit_system> System shutdown  - %s",ctime(my_time));
+
+  free (my_time);
+#else
+#if (VERBOSE_SYSTEM >= verbose_medium)
+  printf("<exit_system> System shutdown\n");
+#endif //VERBOSE_SYSTEM
+#endif //VERBOSE_SYSTEM
+}
+#endif //HAVE_SYSTEM
Index: /trunk/Softwares/Basic_test.or32/src/c/test_setjmp.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/test_setjmp.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/test_setjmp.c	(revision 3)
@@ -0,0 +1,49 @@
+#include <setjmp.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+jmp_buf env;
+
+int exec_setjmp (int val_max, int base)
+{
+  int res = -2;
+  int val = setjmp(env); // 1 call = 0, first return of longjmp -> 1, après renvoye X^N
+  
+  if (val < val_max)
+    {
+      print(val);
+      res ++;
+      longjmp (env,base*val);
+    }
+  
+  return res;
+}
+
+int test_setjmp  ()
+{
+  quit(exec_setjmp (366,2));
+  
+  return (1);
+  
+  /*
+  int base = 2;
+  int val,res,it;
+  
+  srand(0);
+  
+  for (it = 0; it < 10; it ++)
+    {
+      val = (rand()%1500);
+      
+      res = exec_setjmp (val,base);
+
+      print(res);
+      
+      //printf("test_setjmp : log2(%d)=%d (%d)\n",val,res,(unsigned int)log2((double)val));
+
+      if ((unsigned int)log2(val) != res)
+	return 0;
+    }
+  return 1;
+  */
+}
Index: /trunk/Softwares/Basic_test.or32/src/c/timers_b.c
===================================================================
--- /trunk/Softwares/Basic_test.or32/src/c/timers_b.c	(revision 3)
+++ /trunk/Softwares/Basic_test.or32/src/c/timers_b.c	(revision 3)
@@ -0,0 +1,489 @@
+/*****************************************************/
+/* Various timer routines.                           */
+/* Al Aburto, aburto@nosc.mil, 18 Feb 1997           */
+/*                                                   */
+/* t = dtime() outputs the current time in seconds.  */
+/* Use CAUTION as some of these routines will mess   */
+/* up when timing across the hour mark!!!            */
+/*                                                   */
+/* For timing I use the 'user' time whenever         */
+/* possible. Using 'user+sys' time is a separate     */
+/* issue.                                            */
+/*                                                   */
+/* Example Usage:                                    */
+/* [timer options added here]                        */
+/* main()                                            */
+/* {                                                 */
+/* double starttime,benchtime,dtime();               */
+/*                                                   */
+/* starttime = dtime();                              */ 
+/* [routine to time]                                 */
+/* benchtime = dtime() - starttime;                  */
+/* }                                                 */
+/*                                                   */
+/* [timer code below added here]                     */
+/*****************************************************/
+
+/***************************************************************/
+/* Timer options. You MUST uncomment one of the options below  */
+/* or compile, for example, with the '-DUNIX' option.          */
+/***************************************************************/
+/* #define Amiga       */
+/* #define UNIX        */
+/* #define UNIX_Old    */
+/* #define VMS         */
+/* #define BORLAND_C   */
+/* #define MSC         */
+/* #define MAC         */
+/* #define IPSC        */
+/* #define FORTRAN_SEC */
+/* #define GTODay      */
+/* #define CTimer      */
+/* #define UXPM        */
+/* #define MAC_TMgr    */
+/* #define PARIX       */
+/* #define POSIX       */
+/* #define WIN32       */
+/* #define POSIX1      */
+/***********************/
+
+/*********************************/
+/* Timer code.                   */
+/*********************************/
+
+/***************************************************/
+/*  SIM2OS dtime().                                */
+/***************************************************/
+#ifdef SIM2OS
+
+#include <time.h>
+#include "dhry.h"
+#include "service_clock.h"
+
+#ifndef MHZ
+#define MHZ (1000000)
+#endif //!MHZ
+
+#ifndef FRQ
+#define FRQ (1*MHZ)
+#endif //!FRQ
+
+DOUBLE dtime()
+{
+  DOUBLE         dtime;
+
+  dtime = (DOUBLE)(service_clock())/(DOUBLE)FRQ;
+  
+  return (dtime);
+}
+#endif
+
+/*******************/
+/*  Amiga dtime()  */
+/*******************/
+#ifdef Amiga
+#include <ctype.h>
+#define HZ 50
+
+double dtime()
+{
+ double q;
+
+ struct tt
+       {
+	long  days;
+	long  minutes;
+	long  ticks;
+       } tt;
+
+ DateStamp(&tt);
+
+ q = ((double)(tt.ticks + (tt.minutes * 60L * 50L))) / (double)HZ;
+
+ return q;
+}
+#endif
+
+/*****************************************************/
+/*  UNIX dtime(). This is the preferred UNIX timer.  */
+/*  Provided by: Markku Kolkka, mk59200@cc.tut.fi    */
+/*  HP-UX Addition by: Bo Thide', bt@irfu.se         */
+/*****************************************************/
+#ifdef UNIX
+#include <sys/time.h>
+#include <sys/resource.h>
+
+#ifdef hpux
+#include <sys/syscall.h>
+#define getrusage(a,b) syscall(SYS_getrusage,a,b)
+#endif
+
+struct rusage rusage;
+
+double dtime()
+{
+ double q;
+ getrusage(RUSAGE_SELF,&rusage);
+ q = (double)(rusage.ru_utime.tv_sec);
+ q = q + (double)(rusage.ru_utime.tv_usec) * 1.0e-06;
+ return q;
+}
+#endif
+
+/***************************************************/
+/*  UNIX_Old dtime(). This is the old UNIX timer.  */
+/*  Make sure HZ is properly defined in param.h !! */
+/***************************************************/
+#ifdef UNIX_Old
+#include <sys/types.h>
+#include <sys/times.h>
+#include <sys/param.h>
+
+#ifndef HZ
+#define HZ 60
+#endif
+
+struct tms tms;
+
+double dtime()
+{
+ double q;
+
+ times(&tms);
+
+ q = (double)(tms.tms_utime) / (double)HZ;
+	
+ return q;
+}
+#endif
+
+/*********************************************************/
+/*  VMS dtime() for VMS systems.                         */
+/*  Provided by: RAMO@uvphys.phys.UVic.CA                */
+/*  Some people have run into problems with this timer.  */
+/*********************************************************/
+#ifdef VMS
+#include time
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+struct tbuffer_t
+      {
+       int proc_user_time;
+       int proc_system_time;
+       int child_user_time;
+       int child_system_time;
+      };
+
+struct tbuffer_t tms;
+
+double dtime()
+{
+ double q;
+
+ times(&tms);
+
+ q = (double)(tms.proc_user_time) / (double)HZ;
+	
+ return q;
+}
+#endif
+
+/******************************/
+/*  BORLAND C dtime() for DOS */
+/******************************/
+#ifdef BORLAND_C
+#include <ctype.h>
+#include <dos.h>
+#include <time.h>
+
+#define HZ 100
+struct time tnow;
+
+double dtime()
+{
+ double q;
+
+ gettime(&tnow);
+
+ q = 60.0 * (double)(tnow.ti_min);
+ q = q + (double)(tnow.ti_sec);
+ q = q + (double)(tnow.ti_hund)/(double)HZ;
+	
+ return q;
+}
+#endif
+
+/**************************************/
+/*  Microsoft C (MSC) dtime() for DOS */
+/**************************************/
+#ifdef MSC
+#include <time.h>
+#include <ctype.h>
+
+#define HZ CLOCKS_PER_SEC
+clock_t tnow;
+
+double dtime()
+{
+ double q;
+
+ tnow = clock();
+
+ q = (double)tnow / (double)HZ;
+	
+ return q;
+}
+#endif
+
+/*************************************/
+/*  Macintosh (MAC) Think C dtime()  */
+/*************************************/
+#ifdef MAC
+#include <time.h>
+
+#define HZ 60
+
+double dtime()
+{
+ double q;
+
+ q = (double)clock() / (double)HZ;
+	
+ return q;
+}
+#endif
+
+/************************************************************/
+/*  iPSC/860 (IPSC) dtime() for i860.                       */
+/*  Provided by: Dan Yergeau, yergeau@gloworm.Stanford.EDU  */
+/************************************************************/
+#ifdef IPSC
+extern double dclock();
+
+double dtime()
+{
+ double q;
+
+ q = dclock();
+	
+ return q;
+}
+#endif
+
+/**************************************************/
+/*  FORTRAN dtime() for Cray type systems.        */
+/*  This is the preferred timer for Cray systems. */
+/**************************************************/
+#ifdef FORTRAN_SEC
+
+fortran double second();
+
+double dtime()
+{
+ double q;
+
+ second(&q);
+	
+ return q;
+}
+#endif
+
+/***********************************************************/
+/*  UNICOS C dtime() for Cray UNICOS systems.  Don't use   */
+/*  unless absolutely necessary as returned time includes  */
+/*  'user+system' time.  Provided by: R. Mike Dority,      */
+/*  dority@craysea.cray.com                                */
+/***********************************************************/
+#ifdef CTimer
+#include <time.h>
+
+double dtime()
+{
+ double    q;
+ clock_t   clock(void);
+
+ q = (double)clock() / (double)CLOCKS_PER_SEC;
+
+ return q;
+}
+#endif
+
+/********************************************/
+/* Another UNIX timer using gettimeofday(). */
+/* However, getrusage() is preferred.       */
+/********************************************/
+#ifdef GTODay
+#include <sys/time.h>
+
+struct timeval tnow;
+
+double dtime()
+{
+ double q;
+
+ gettimeofday(&tnow,NULL);
+ q = (double)tnow.tv_sec + (double)tnow.tv_usec * 1.0e-6;
+
+ return q;
+}
+#endif
+
+/*****************************************************/
+/*  Fujitsu UXP/M timer.                             */
+/*  Provided by: Mathew Lim, ANUSF, M.Lim@anu.edu.au */
+/*****************************************************/
+#ifdef UXPM
+#include <sys/types.h>
+#include <sys/timesu.h>
+struct tmsu rusage;
+
+double dtime()
+{
+ double q;
+
+ timesu(&rusage);
+
+ q = (double)(rusage.tms_utime) * 1.0e-06;
+	
+ return q;
+}
+#endif
+
+/**********************************************/
+/*    Macintosh (MAC_TMgr) Think C dtime()    */
+/*   requires Think C Language Extensions or  */
+/*    #include <MacHeaders> in the prefix     */
+/*  provided by Francis H Schiffer 3rd (fhs)  */
+/*         skipschiffer@genie.geis.com        */
+/**********************************************/
+#ifdef MAC_TMgr
+#include <Timer.h>
+#include <stdlib.h>
+
+static TMTask   mgrTimer;
+static Boolean  mgrInited = false;
+static double   mgrClock;
+
+#define RMV_TIMER RmvTime( (QElemPtr)&mgrTimer )
+#define MAX_TIME  1800000000L
+/* MAX_TIME limits time between calls to */
+/* dtime( ) to no more than 30 minutes   */
+/* this limitation could be removed by   */
+/* creating a completion routine to sum  */
+/* 30 minute segments (fhs 1994 feb 9)   */
+
+static void Remove_timer( )
+{
+ RMV_TIMER;
+ mgrInited = false;
+}
+
+double  dtime( )
+{
+ if( mgrInited ) {
+   RMV_TIMER;
+   mgrClock += (MAX_TIME + mgrTimer.tmCount)*1.0e-6;
+ } else {
+   if( _atexit( &Remove_timer ) == 0 ) mgrInited = true;
+   mgrClock = 0.0;
+ }
+ 
+ if ( mgrInited )
+   {
+    mgrTimer.tmAddr = NULL;
+    mgrTimer.tmCount = 0;
+    mgrTimer.tmWakeUp = 0;
+    mgrTimer.tmReserved = 0;
+    InsTime( (QElemPtr)&mgrTimer );
+    PrimeTime( (QElemPtr)&mgrTimer, -MAX_TIME );
+   }
+ return( mgrClock );
+}
+#endif
+
+/***********************************************************/
+/*  Parsytec GCel timer.                                   */
+/*  Provided by: Georg Wambach, gw@informatik.uni-koeln.de */
+/***********************************************************/
+#ifdef PARIX
+#include <sys/time.h>
+
+double dtime()
+{
+ double q;
+
+ q = (double) (TimeNowHigh()) / (double) CLK_TCK_HIGH;
+
+ return q;
+}
+#endif
+
+/************************************************/
+/*  Sun Solaris POSIX dtime() routine           */
+/*  Provided by: Case Larsen, CTLarsen.lbl.gov  */
+/************************************************/
+#ifdef POSIX
+#include <sys/time.h>
+#include <sys/resource.h>
+#include <sys/rusage.h>
+
+#ifdef __hpux
+#include <sys/syscall.h>
+#endif
+
+struct rusage rusage;
+
+double dtime()
+{
+ double q;
+
+ getrusage(RUSAGE_SELF,&rusage);
+
+ q = (double)(rusage.ru_utime.tv_sec);
+ q = q + (double)(rusage.ru_utime.tv_nsec) * 1.0e-09;
+	
+ return q;
+}
+#endif
+
+
+/****************************************************/
+/*  Windows NT (32 bit) dtime() routine             */
+/*  Provided by: Piers Haken, piersh@microsoft.com  */
+/****************************************************/
+#ifdef WIN32
+#include <windows.h>
+
+double dtime(void)
+{
+ double q;
+
+ q = (double)GetTickCount() * 1.0e-03;
+	
+ return q;
+}
+#endif
+
+/*****************************************************/
+/* Time according to POSIX.1  -  <J.Pelan@qub.ac.uk> */
+/* Ref: "POSIX Programmer's Guide"  O'Reilly & Assoc.*/
+/*****************************************************/
+#ifdef POSIX1
+#define _POSIX_SOURCE 1
+#include <unistd.h>
+#include <limits.h>
+#include <sys/times.h>
+
+struct tms tms;
+
+double dtime()
+{
+ double q;
+ times(&tms);
+ q = (double)tms.tms_utime / (double)CLK_TCK;
+ return q;
+}
+#endif
Index: /trunk/Softwares/Global.or32/include/bool.h
===================================================================
--- /trunk/Softwares/Global.or32/include/bool.h	(revision 3)
+++ /trunk/Softwares/Global.or32/include/bool.h	(revision 3)
@@ -0,0 +1,30 @@
+#ifndef BOOL_H
+#define BOOL_H
+
+// typedef enum{false,true} bool;
+
+#ifndef BOOL
+#define BOOL  int
+#endif 
+
+#ifndef bool
+#define bool  int
+#endif 
+
+#ifndef false
+#define false 0
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE 
+#define TRUE  1
+#endif
+
+#ifndef true 
+#define true  1
+#endif
+
+#endif //!BOOL_H
Index: /trunk/Softwares/Global.or32/include/cpu_info.h
===================================================================
--- /trunk/Softwares/Global.or32/include/cpu_info.h	(revision 3)
+++ /trunk/Softwares/Global.or32/include/cpu_info.h	(revision 3)
@@ -0,0 +1,3 @@
+
+extern unsigned int get_cpu_id();
+extern void         set_cpu_id(unsigned int);
Index: /trunk/Softwares/Global.or32/include/find_one.h
===================================================================
--- /trunk/Softwares/Global.or32/include/find_one.h	(revision 3)
+++ /trunk/Softwares/Global.or32/include/find_one.h	(revision 3)
@@ -0,0 +1,1 @@
+unsigned int  find_first_one (unsigned int val);
Index: /trunk/Softwares/Global.or32/include/func_io.h
===================================================================
--- /trunk/Softwares/Global.or32/include/func_io.h	(revision 3)
+++ /trunk/Softwares/Global.or32/include/func_io.h	(revision 3)
@@ -0,0 +1,4 @@
+#include "mapping_memory.h"
+
+void print(int data);
+void quit (int data);
Index: /trunk/Softwares/Global.or32/include/service_clock.h
===================================================================
--- /trunk/Softwares/Global.or32/include/service_clock.h	(revision 3)
+++ /trunk/Softwares/Global.or32/include/service_clock.h	(revision 3)
@@ -0,0 +1,1 @@
+unsigned int service_clock ();
Index: /trunk/Softwares/Global.or32/include/thread_info.h
===================================================================
--- /trunk/Softwares/Global.or32/include/thread_info.h	(revision 3)
+++ /trunk/Softwares/Global.or32/include/thread_info.h	(revision 3)
@@ -0,0 +1,5 @@
+
+extern unsigned int get_thread_id       ();
+extern void         set_thread_id       (unsigned int);
+extern unsigned int get_thread_priority ();
+extern void         set_thread_priority (unsigned int);
Index: /trunk/Softwares/Global.or32/include/uncached_mask.h
===================================================================
--- /trunk/Softwares/Global.or32/include/uncached_mask.h	(revision 3)
+++ /trunk/Softwares/Global.or32/include/uncached_mask.h	(revision 3)
@@ -0,0 +1,3 @@
+
+extern unsigned int get_uncached_mask       ();
+extern void         set_uncached_mask       (unsigned int);
Index: /trunk/Softwares/Global.or32/src/asm/cpu_info.s
===================================================================
--- /trunk/Softwares/Global.or32/src/asm/cpu_info.s	(revision 3)
+++ /trunk/Softwares/Global.or32/src/asm/cpu_info.s	(revision 3)
@@ -0,0 +1,18 @@
+/*
+ * Manipulation of processor information
+ */
+		
+	.file	"cpu_info.s"
+	.section .text
+	.align	4
+
+	.global _get_cpu_id
+_get_cpu_id :
+	l.jr	r9
+	l.mfspr r11,r0,0xF800  /* R11 <- SPR[31][0] */
+
+	.global _set_cpu_id
+_set_cpu_id :
+	l.jr	r9
+	l.mtspr r0 ,r3,0xF800  /* SPR[31][0] <- r3  */
+
Index: /trunk/Softwares/Global.or32/src/asm/find_one.s
===================================================================
--- /trunk/Softwares/Global.or32/src/asm/find_one.s	(revision 3)
+++ /trunk/Softwares/Global.or32/src/asm/find_one.s	(revision 3)
@@ -0,0 +1,19 @@
+/*
+ * Manipulation of bits
+ */
+		
+	.file	"find_one.s"
+	.section .text
+	.align	4
+
+	.global _find_first_one
+_find_first_one :
+	l.jr	r9
+	l.ff1   r11,r3
+
+/*
+	.global _find_last_one
+_find_last_one :
+	l.jr	r9
+	l.fl1   r11,r3,r0
+*/
Index: /trunk/Softwares/Global.or32/src/asm/thread_info.s
===================================================================
--- /trunk/Softwares/Global.or32/src/asm/thread_info.s	(revision 3)
+++ /trunk/Softwares/Global.or32/src/asm/thread_info.s	(revision 3)
@@ -0,0 +1,28 @@
+/*
+ * Manipulation of thread information
+ */
+		
+	.file	"thread_info.s"
+	.section .text
+	.align	4
+
+	.global _get_thread_id
+_get_thread_id :
+	l.jr	r9				
+	l.mfspr r11,r0,0xF801			/* R11 <- SPR[31][1] */
+	
+	.global _set_thread_id
+_set_thread_id :
+	l.jr	r9
+	l.mtspr r0 ,r3,0xF801			/* SPR[31][1] <- r3  */
+
+	.global _get_thread_priority
+_get_thread_priority :
+	l.jr	r9
+	l.mfspr r11,r0,0xF802			/* R11 <- SPR[31][2] */
+
+	.global _set_thread_priority
+_set_thread_priority :
+	l.jr	r9
+	l.mtspr r0 ,r3,0xF802			/* SPR[31][2] <- r3  */
+	
Index: /trunk/Softwares/Global.or32/src/asm/uncached_mask.s
===================================================================
--- /trunk/Softwares/Global.or32/src/asm/uncached_mask.s	(revision 3)
+++ /trunk/Softwares/Global.or32/src/asm/uncached_mask.s	(revision 3)
@@ -0,0 +1,17 @@
+/*
+ * Manipulation of thread information
+ */
+		
+	.file	"uncached_mask.s"
+	.section .text
+	.align	4
+
+	.global _get_uncached_mask
+_get_uncached_mask :
+	l.jr	r9				
+	l.mfspr r11,r0,0xF803			/* R11 <- SPR[31][3] */
+	
+	.global _set_uncached_mask
+_set_uncached_mask :
+	l.jr	r9
+	l.mtspr r0 ,r3,0xF803			/* SPR[31][1] <- r3  */
Index: /trunk/Softwares/Global.or32/src/c/func_io.c
===================================================================
--- /trunk/Softwares/Global.or32/src/c/func_io.c	(revision 3)
+++ /trunk/Softwares/Global.or32/src/c/func_io.c	(revision 3)
@@ -0,0 +1,16 @@
+#include "func_io.h"
+#include "thread_info.h"
+
+void print(int data)
+{
+  int *show   =(int*)(TTY_BASE + (get_thread_id() << 4) + 8);
+
+  *(show) = data;
+}
+
+void quit (int data)
+{
+  int *stop   =(int*)(TTY_BASE + (get_thread_id() << 4) + 4);
+
+  *(stop) = data;
+}
Index: /trunk/Softwares/Global.or32/src/c/service_clock.c
===================================================================
--- /trunk/Softwares/Global.or32/src/c/service_clock.c	(revision 3)
+++ /trunk/Softwares/Global.or32/src/c/service_clock.c	(revision 3)
@@ -0,0 +1,31 @@
+#include <time.h>
+#include <errno.h>
+#include <sys/lock.h>
+#include "mapping_memory.h"
+#include "sim2os.h"
+#include "service_clock.h"
+
+unsigned int service_clock ()
+{
+  unsigned int * addr   = (unsigned int *)(SIM2OS_BASE);
+  unsigned int   result = -1;
+
+  __lock_init    (service_lock);
+  
+  __lock_acquire (service_lock);
+
+  *(addr+0) = (unsigned int)SERVICE_CLOCK;
+ 
+  // memory synchronisation
+  // (else read (with an address that depend not of store address) can be lunch before a store)
+  asm("l.msync;");
+
+  result    = (clock_t) *(addr+1);
+ 
+  if (result == (clock_t)-1)
+    errno = (int) *(addr+2);
+
+  __lock_release (service_lock);
+
+  return result;
+}
Index: /trunk/Softwares/Global.or32/src/sys/crt0.s
===================================================================
--- /trunk/Softwares/Global.or32/src/sys/crt0.s	(revision 3)
+++ /trunk/Softwares/Global.or32/src/sys/crt0.s	(revision 3)
@@ -0,0 +1,1 @@
+link /users/cao/kane/Project/Morpheo/Tools/newlib/libgloss/or32/crt0.S
Index: /trunk/Softwares/Min.or32/Makefile
===================================================================
--- /trunk/Softwares/Min.or32/Makefile	(revision 3)
+++ /trunk/Softwares/Min.or32/Makefile	(revision 3)
@@ -0,0 +1,88 @@
+# common definition
+include			Makefile.morpheo
+
+#-----[ Directory ]---------------------------------------------------------------
+DIR_SRC			= ./src
+DIR_C			= $(DIR_SRC)/c
+DIR_ASM			= $(DIR_SRC)/asm
+DIR_SYS			= $(DIR_SRC)/sys
+DIR_INC       		= $(DIR_C)/include
+
+DIR_OBJ			= obj
+DIR_BIN			= bin
+
+EXE			= soft
+
+#-----[ Files ]-------------------------------------------------------------------
+OBJ_ASM			= $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s))
+OBJ_SYS			= $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s))
+OBJ_C           	= $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c))
+
+OBJ			= $(OBJ_SYS) $(OBJ_ASM) $(OBJ_C)
+
+#-----[ Rules ]-------------------------------------------------------------------
+.PRECIOUS		: $(DIR_BIN)/%.x $(DIR_OBJ)/%.o $(DIR_OBJ)/%.a
+
+all 			: test_env $(DIR_BIN)/$(EXE).x.txt
+
+$(DIR_BIN)/%.x.txt	: $(DIR_BIN)/%.x
+			@$(ECHO) "List symbols        of $*"
+			@$(NM)      $(NM_OPT)      $^ > $@.nm
+			@$(ECHO) "Display information of $*"
+			@$(OBJDUMP) $(OBJDUMP_OPT) $^ > $@
+
+$(DIR_BIN)/%.x		: $(OBJ_SYS) $(OBJ) 
+			@$(ECHO) "Linkage             of $*"
+			@$(LD) -o $@ $^ $(LD_OPT)
+
+$(DIR_OBJ)/%.o		: $(DIR_ASM)/%.s	
+			@$(ECHO) "Compile             of $*"
+			@$(CC) $(CC_OPT) -I$(DIR_INC)    -o $@   -c $^ 
+			@$(CC) $(CC_OPT) -I$(DIR_INC) -S -o $@.s -c $^ 
+#			@$(AS) $(AS_OPT) $^ -o $@
+
+$(DIR_OBJ)/%.o		: $(DIR_SYS)/%.s	
+			@$(ECHO) "Compile             of $*"
+			@$(CC) $(CC_OPT) -I$(DIR_INC)    -o $@   -c $^ 
+			@$(CC) $(CC_OPT) -I$(DIR_INC) -S -o $@.s -c $^ 
+#			@$(AS) $(AS_OPT) $^ -o $@
+
+$(DIR_OBJ)/%.o		: $(DIR_C)/%.c
+			@$(ECHO) "Compile             of $*"
+			@$(CC) $(CC_OPT) -I$(DIR_INC)    -o $@   -c $^ 
+			@$(CC) $(CC_OPT) -I$(DIR_INC) -S -o $@.s -c $^ 
+
+#-----[ Environement ]------------------------------------------------------------
+test_env		:
+# ifeq ($(origin TOOLS), undefined)
+# 			$(error "variable TOOLS is undefined");
+# endif
+# ifeq ($(origin SOFT), undefined)
+# 			$(error "variable SOFT  is undefined");
+# endif
+			@$(MKDIR) $(DIR_OBJ) $(DIR_BIN)
+
+#-----[ Maintenance ]-------------------------------------------------------------
+clean 			:
+			@$(ECHO) "Delete     temporary files              "`$(PWD)`
+			@$(RM) $(DIR_OBJ) $(DIR_BIN)
+			@$(MAKE) clean_rec DIR_CLEAN=.
+
+#Clean recursive
+clean_rec		:
+			@$(ECHO) "Delete     temporary files in directory $(DIR_CLEAN)"
+			@$(RM) -f $(DIR_CLEAN)/*~
+			@for files in `$(LS) $(DIR_CLEAN)`; do					\
+			    	if $(TEST) -d $(DIR_CLEAN)/$$files; 				\
+				then 								\
+					$(MAKE) clean_rec DIR_CLEAN=$(DIR_CLEAN)/$$files;	\
+				fi; 								\
+			done;
+
+#-----[ Help ]--------------------------------------------------------------------
+help			:
+			@$(ECHO) ""
+			@$(ECHO) "List of directive   : "
+			@$(ECHO) " * make             : Compile the software"
+			@$(ECHO) " * make clean       : Erase all files generates"
+			@$(ECHO) ""
Index: /trunk/Softwares/Min.or32/Makefile.morpheo
===================================================================
--- /trunk/Softwares/Min.or32/Makefile.morpheo	(revision 3)
+++ /trunk/Softwares/Min.or32/Makefile.morpheo	(revision 3)
@@ -0,0 +1,50 @@
+#-----[ Usual commands ]----------------------------------------------------------
+RM			= rm -fr
+MKDIR			= mkdir -p
+ECHO			= echo
+CCACHE			= ccache
+LS			= ls
+TEST			= test
+CAT			= cat
+READ			= read
+SED			= sed
+MAKE			= make -s
+CD			= cd
+PWD			= pwd
+
+#-----[ Directory ]---------------------------------------------------------------
+DIR_LDSCRIPT		= $(DIR_SRC)/ldscript/
+
+DIR_INCLUDE		= 
+DIR_LIBRARY		= 
+
+#-----[ To the compilation ]------------------------------------------------------
+OPTIMIZE		= -O3 -fomit-frame-pointer -fdelayed-branch -mror -mcmov -msext -mhard-mul -msoft-div -msoft-float
+#Option :
+# -fomit-frame-pointer 			: n'utilise pas le pointeur de frame
+# -fdelayed-branch   			: utilise les delayed slot
+# ON		OFF
+# -mror   	-mno-ror              	: utilisation de l'instruction l.ror
+# -mcmov   	-mno-cmov       	: utilisation de l'instruction l.cmov
+# -msext	-mno-sext		: utilisation des instructions l.extXX
+# -mhard-mul	-msoft-mul	        : utilisation du multiplieur materiel
+# -mhard-div	-msoft-div              : utilisation du diviseur materiel
+# -mhard-float	-msoft-float      	: utilisation du flottant materiel
+# -msibcall     -mno-sibcall            : Enable sibcall optimization
+# -mlogue	-mno-logue 		: Schedule pro/epi-logue.
+# -maj		-mno-aj     		: Use aligned jumps.
+
+# Tools
+CC			= $(CCACHE) or32-elf-gcc
+AS			=           or32-elf-as
+LD			=           or32-elf-ld
+OBJDUMP			=           or32-elf-objdump
+NM           		=           or32-elf-nm
+
+# Tools's option
+CC_OPT			= $(DIR_INCLUDE) $(OPTIMIZE5~) -Wlong-long
+# -DHAVE_LIBC
+AS_OPT			=
+LD_OPT			= -T$(DIR_LDSCRIPT)/or32.ld $(DIR_LIBRARY)  
+OBJDUMP_OPT		= -D
+NM_OPT			= -n
Index: /trunk/Softwares/Min.or32/src/asm/cpu_info.s
===================================================================
--- /trunk/Softwares/Min.or32/src/asm/cpu_info.s	(revision 3)
+++ /trunk/Softwares/Min.or32/src/asm/cpu_info.s	(revision 3)
@@ -0,0 +1,18 @@
+/*
+ * Manipulation of processor information
+ */
+		
+	.file	"cpu_info.s"
+	.section .text
+	.align	4
+
+	.global _get_cpu_id
+_get_cpu_id :
+	l.jr	r9
+	l.mfspr r11,r0,0xF800  /* R11 <- SPR[31][0] */
+
+	.global _set_cpu_id
+_set_cpu_id :
+	l.jr	r9
+	l.mtspr r0 ,r3,0xF800  /* SPR[31][0] <- r3  */
+
Index: /trunk/Softwares/Min.or32/src/asm/find_one.s
===================================================================
--- /trunk/Softwares/Min.or32/src/asm/find_one.s	(revision 3)
+++ /trunk/Softwares/Min.or32/src/asm/find_one.s	(revision 3)
@@ -0,0 +1,19 @@
+/*
+ * Manipulation of bits
+ */
+		
+	.file	"find_one.s"
+	.section .text
+	.align	4
+
+	.global _find_first_one
+_find_first_one :
+	l.jr	r9
+	l.ff1   r11,r3
+
+/*
+	.global _find_last_one
+_find_last_one :
+	l.jr	r9
+	l.fl1   r11,r3,r0
+*/
Index: /trunk/Softwares/Min.or32/src/asm/thread_info.s
===================================================================
--- /trunk/Softwares/Min.or32/src/asm/thread_info.s	(revision 3)
+++ /trunk/Softwares/Min.or32/src/asm/thread_info.s	(revision 3)
@@ -0,0 +1,28 @@
+/*
+ * Manipulation of thread information
+ */
+		
+	.file	"thread_info.s"
+	.section .text
+	.align	4
+
+	.global _get_thread_id
+_get_thread_id :
+	l.jr	r9				
+	l.mfspr r11,r0,0xF801			/* R11 <- SPR[31][1] */
+	
+	.global _set_thread_id
+_set_thread_id :
+	l.jr	r9
+	l.mtspr r0 ,r3,0xF801			/* SPR[31][1] <- r3  */
+
+	.global _get_thread_priority
+_get_thread_priority :
+	l.jr	r9
+	l.mfspr r11,r0,0xF802			/* R11 <- SPR[31][2] */
+
+	.global _set_thread_priority
+_set_thread_priority :
+	l.jr	r9
+	l.mtspr r0 ,r3,0xF802			/* SPR[31][2] <- r3  */
+	
Index: /trunk/Softwares/Min.or32/src/c/include/cpu_info.h
===================================================================
--- /trunk/Softwares/Min.or32/src/c/include/cpu_info.h	(revision 3)
+++ /trunk/Softwares/Min.or32/src/c/include/cpu_info.h	(revision 3)
@@ -0,0 +1,3 @@
+
+extern unsigned int get_cpu_id();
+extern void         set_cpu_id(unsigned int);
Index: /trunk/Softwares/Min.or32/src/c/include/thread_info.h
===================================================================
--- /trunk/Softwares/Min.or32/src/c/include/thread_info.h	(revision 3)
+++ /trunk/Softwares/Min.or32/src/c/include/thread_info.h	(revision 3)
@@ -0,0 +1,5 @@
+
+extern unsigned int get_thread_id       ();
+extern void         set_thread_id       (unsigned int);
+extern unsigned int get_thread_priority ();
+extern void         set_thread_priority (unsigned int);
Index: /trunk/Softwares/Min.or32/src/c/main.c
===================================================================
--- /trunk/Softwares/Min.or32/src/c/main.c	(revision 3)
+++ /trunk/Softwares/Min.or32/src/c/main.c	(revision 3)
@@ -0,0 +1,13 @@
+#include "thread_info.h"
+#include "cpu_info.h"
+
+//=====[ main ]=================================================================
+/*
+ * All thread execute this routine
+ * Initialize the thread and attribute a Workload at each thread
+ */
+
+int main()
+{
+  while (1);
+}
Index: /trunk/Softwares/Min.or32/src/ldscript/or32.ld
===================================================================
--- /trunk/Softwares/Min.or32/src/ldscript/or32.ld	(revision 3)
+++ /trunk/Softwares/Min.or32/src/ldscript/or32.ld	(revision 3)
@@ -0,0 +1,92 @@
+ENTRY(_start)
+OUTPUT_ARCH(or32)
+/*
+__DYNAMIC  =  0;
+*/
+
+/*
+ * Memory Mapping
+ */
+
+MEMORY
+{
+	iram     : ORIGIN = 0x00000000, LENGTH = 0x01000000
+	dram     : ORIGIN = 0x10000000, LENGTH = 0x10000000
+	dram_unc : ORIGIN = 0x40000000, LENGTH = 0x01000000
+}
+
+/*
+ * Allocate the stack to be at the top of memory, since the stack
+ * grows down.
+ */
+PROVIDE (_stack       = 0x52000000 - 4);
+PROVIDE (__stack      = 0x52000000 - 4);
+PROVIDE (_stack_alloc = 0x00500000    );
+SECTIONS
+{
+   /*
+    * Code
+    */
+
+   .text : 
+	{
+		*(.text)
+   	} > iram
+
+   /*
+    * Data
+    */
+
+   .rodata : 
+	{
+		*(.rodata);
+		*(.rodata.*);
+	} > dram
+
+   .data : 
+	{
+		sdata   =  .;
+		_sdata  =  .;
+		*(.data)
+		edata   =  .;
+		_edata  =  .;
+	} > dram
+   .bss SIZEOF(.data) + ADDR(.data) :
+	{
+		sbss         = . ;
+		_sbss        = . ;
+		__bss_start  = ALIGN(0x8);
+		___bss_start = ALIGN(0x8);
+		*(.bss)
+		*(COMMON)
+		end          = ALIGN(0x8);
+		_end         = ALIGN(0x8);
+		__end        = ALIGN(0x8);
+		ebss         = .;
+		_ebss        = .;
+	}
+/*
+    .stab  0 (NOLOAD) : 
+        {
+                [ .stab ]
+        }
+        
+    .stabstr  0 (NOLOAD) :
+        {
+                [ .stabstr ]
+        }
+*/
+
+
+   /*
+    * Suppression de la section comment
+    */
+
+   /DISCARD/ :
+	{
+	*(.comment)
+	*(.gnu.*)
+	*(.stab*)
+	}
+}
+
Index: /trunk/Softwares/Min.or32/src/sys/crt0.s
===================================================================
--- /trunk/Softwares/Min.or32/src/sys/crt0.s	(revision 3)
+++ /trunk/Softwares/Min.or32/src/sys/crt0.s	(revision 3)
@@ -0,0 +1,513 @@
+/*
+ * Routine system dependant
+ *  - reset
+ *  - exception handler
+ *  - start / exit
+ */
+
+/*		
+#define DEFAULT_EXCEPTION_HANDLER     \
+	l.addi  r1, r1, -128         ;\
+	l.sw    4(r1), r3            ;\ 
+	l.sw    8(r1), r4	     ;\
+	l.mfspr r3,r0,16             ;\
+	l.mfspr r4,r0,32             ;\
+	l.j default_exception_handler;\
+	l.nop	0                    ;
+*/
+	.file	"crt0.s"
+	/*
+	.section .vector
+	*/
+	.section .text
+	.align	4	
+
+/* ---[ 0x0  : Print a error ]------------------------------------------- */
+
+	.org 0x0
+
+	l.movhi r3,   0xdead
+	l.jal	_quit
+	l.ori	r3,r3,0xdead
+		
+/* ---[ 0x100: RESET exception ]----------------------------------------- */
+        .org 0x100
+	.global _exception_reset
+_exception_reset:
+
+	l.movhi r2,   hi(_start)
+	l.ori   r2,r2,lo(_start)
+	l.jr    r2		 /* Go _start */
+	l.nop	0
+
+/* ---[ 0x200: BUS exception ]------------------------------------------- */
+	.org 0x200
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+	
+
+/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
+	.org 0x300
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
+	.org 0x400
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+
+/* ---[ 0x500: Timer exception ]----------------------------------------- */
+	.org 0x500
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+
+/* ---[ 0x600: Aligment exception ]-------------------------------------- */
+	.org 0x600
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
+	.org 0x700
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+
+/* ---[ 0x800: External interrupt exception ]---------------------------- */
+	.org 0x800
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+
+/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
+	.org 0x900
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
+	.org 0xa00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+		
+/* ---[ 0xb00: Range exception ]----------------------------------------- */
+	.org 0xb00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+
+/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
+	.org 0xc00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+
+/* ---[ 0xd00: Trap exception ]------------------------------------------ */
+	.org 0xd00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+
+/* ---[ 0xe00: Trap exception ]------------------------------------------ */
+	.org 0xe00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	
+/* ---[ 0xf00: Reserved exceptions ]------------------------------------- */
+	.org 0xf00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1000
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1100
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1200
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1300
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1400
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1500
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1600
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1700
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1800
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1900
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1a00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1b00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1c00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1d00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1e00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+	
+	.org 0x1f00
+	/*DEFAULT_EXCEPTION_HANDLER*/
+	l.addi  r1, r1, -128         
+	l.sw    4(r1), r3             
+	l.sw    8(r1), r4	     
+	l.mfspr r3,r0,16             
+	l.mfspr r4,r0,32             
+	l.j default_exception_handler
+	l.nop	0                    
+
+
+/* ========================================================= [ entry ] === */
+
+	.org 0x2000
+	.global _start
+	
+_start:
+	/* Initialise stack */
+
+	l.movhi r1,     hi(_stack)
+	l.ori   r1, r1, lo(_stack)
+	l.addi  r2, r0, -3		  /* 0xFFFF_FFFC */
+
+	l.jal	_get_cpu_id               /* give the id of the cpu */
+	l.and   r1, r1, r2
+
+	l.movhi r4,     hi(_stack_alloc)
+	l.ori   r4, r4, lo(_stack_alloc)
+
+	l.mul	r4, r11,r4
+	l.sub	r1, r1 ,r4                /* each thread have a <<_stack>> with a size <<_stack_alloc>> */
+	l.or	r2, r1, r0                /* copy in frame_pointer register */
+
+	/* Clear BSS */
+/*
+	l.movhi r28,      hi(___bss_start)
+	l.ori   r28, r28, lo(___bss_start)
+	l.movhi r30,      hi(__end)
+	l.ori   r30, r30, lo(__end)
+1:
+        l.sw    (0)(r28), r0
+        l.sfltu r28, r30
+        l.bf    1b
+        l.addi  r28, r28, 4
+*/
+	/* Jump to main program entry point (argc = argv = 0) */
+	l.and	r3,r0,r0
+	l.jal   _main
+	l.and	r4,r0,r0
+	
+	/* If program exits, call exit routine */
+/*
+	l.addi  r3, r11, 0
+	l.jal   __exit
+	l.nop	0
+*/
+/* ====================================== [ default exception handler ] === */
+
+default_exception_handler:
+	l.sw    0x00(r1), r2
+	l.sw    0x0c(r1), r5
+	l.sw    0x10(r1), r6
+	l.sw    0x14(r1), r7
+	l.sw    0x18(r1), r8
+	l.sw    0x1c(r1), r9
+	l.sw    0x20(r1), r10
+	l.sw    0x24(r1), r11
+	l.sw    0x28(r1), r12
+	l.sw    0x2c(r1), r13
+	l.sw    0x30(r1), r14
+	l.sw    0x34(r1), r15
+	l.sw    0x38(r1), r16
+	l.sw    0x3c(r1), r17
+	l.sw    0x40(r1), r18
+	l.sw    0x44(r1), r19
+	l.sw    0x48(r1), r20
+	l.sw    0x4c(r1), r21
+	l.sw    0x50(r1), r22
+	l.sw    0x54(r1), r23
+	l.sw    0x58(r1), r24
+	l.sw    0x5c(r1), r25
+	l.sw    0x60(r1), r26
+	l.sw    0x64(r1), r27
+	l.sw    0x68(r1), r28
+	l.sw    0x6c(r1), r29
+	l.sw    0x70(r1), r30
+	l.sw    0x74(r1), r31
+	l.sw    0x78(r1), r32
+	
+	/*
+	 * Jump to a handler (write in C by example)
+	 */
+	
+	l.jal   _exception_handler
+	l.nop	0
+	
+	l.lwz   r2 , 0x00(r1)
+	l.lwz   r3 , 0x04(r1)
+	l.lwz   r4 , 0x08(r1)
+	l.lwz   r5 , 0x0c(r1)
+	l.lwz   r6 , 0x10(r1)
+	l.lwz   r7 , 0x14(r1)
+	l.lwz   r8 , 0x18(r1)
+	l.lwz   r9 , 0x1c(r1)
+	l.lwz   r10, 0x20(r1)
+	l.lwz   r11, 0x24(r1)
+	l.lwz   r12, 0x28(r1)
+	l.lwz   r13, 0x2c(r1)
+	l.lwz   r14, 0x30(r1)
+	l.lwz   r15, 0x34(r1)
+	l.lwz   r16, 0x38(r1)
+	l.lwz   r17, 0x3c(r1)
+	l.lwz   r18, 0x40(r1)
+	l.lwz   r19, 0x44(r1)
+	l.lwz   r20, 0x48(r1)
+	l.lwz   r21, 0x4c(r1)
+	l.lwz   r22, 0x50(r1)
+	l.lwz   r23, 0x54(r1)
+	l.lwz   r24, 0x58(r1)
+	l.lwz   r25, 0x5c(r1)
+	l.lwz   r26, 0x60(r1)
+	l.lwz   r27, 0x64(r1)
+	l.lwz   r28, 0x68(r1)
+	l.lwz   r29, 0x6c(r1)
+	l.lwz   r30, 0x70(r1)
+	l.lwz   r31, 0x74(r1)
+	l.lwz   r32, 0x78(r1)
+
+	l.addi  r1, r1, 128
+
+	l.rfe
+	l.nop	0
+
Index: /trunk/Softwares/README_SOFT
===================================================================
--- /trunk/Softwares/README_SOFT	(revision 3)
+++ /trunk/Softwares/README_SOFT	(revision 3)
@@ -0,0 +1,25 @@
+--------------------------------------------------
+ Table of contents
+--------------------------------------------------
+
+I   - Directory
+II  - How to create a new Software
+III - Use a example
+
+--------------------------------------------------
+ I   - Directory 
+--------------------------------------------------
+This directory contents all SOFT for your application
+    * src_c    : content all C sources
+    * src_asm  : content all Assembler source
+    * src_evt  : content all Assembler source to manage event (Interrupt, exception ..)
+    * ldscript : content ldscript source
+    * Makefile : directive to compile all tools
+
+--------------------------------------------------
+ II  - How to create a new Software
+--------------------------------------------------
+
+--------------------------------------------------
+ III - Use a example
+--------------------------------------------------
Index: /trunk/Tools/newlib
===================================================================
--- /trunk/Tools/newlib	(revision 3)
+++ /trunk/Tools/newlib	(revision 3)
@@ -0,0 +1,1 @@
+link ../../Tools/newlib-1.14.0
Index: /trunk/Tools/or1k
===================================================================
--- /trunk/Tools/or1k	(revision 3)
+++ /trunk/Tools/or1k	(revision 3)
@@ -0,0 +1,1 @@
+link ../../Tools/or32-elf/
Index: /trunk/Tools/soclib
===================================================================
--- /trunk/Tools/soclib	(revision 3)
+++ /trunk/Tools/soclib	(revision 3)
@@ -0,0 +1,1 @@
+link /users/outil/soc/soclib/
Index: /trunk/Tools/systemc
===================================================================
--- /trunk/Tools/systemc	(revision 3)
+++ /trunk/Tools/systemc	(revision 3)
@@ -0,0 +1,1 @@
+link /users/outil/systemc/systemc-2.1.v1/
Index: /trunk/Tools/systemcass
===================================================================
--- /trunk/Tools/systemcass	(revision 3)
+++ /trunk/Tools/systemcass	(revision 3)
@@ -0,0 +1,1 @@
+link /users/outil/systemc/systemcass/systemcass/latest/i686-Linux.SLA4x/
Index: /trunk/Tools/xilinx
===================================================================
--- /trunk/Tools/xilinx	(revision 3)
+++ /trunk/Tools/xilinx	(revision 3)
@@ -0,0 +1,1 @@
+link /dsk/l1/misc/Xilinx91i/
Index: /trunk/environment.sh
===================================================================
--- /trunk/environment.sh	(revision 3)
+++ /trunk/environment.sh	(revision 3)
@@ -0,0 +1,41 @@
+#!/bin/sh
+
+OS_FOUND=`uname -s`-`uname -m | sed -e 's/i[0-9]/iX/' -e 's/sun4./sun4X/'`
+case $OS_FOUND in
+    "SunOS-sun4X")
+	export TARGET_ARCH=gccsparcOS5
+	export EXE_SUFFIX=
+	;;
+    "Linux-iX86")
+	export TARGET_ARCH=linux
+	export EXE_SUFFIX=
+	;;
+    "FreeBSD-iX86")
+	export TARGET_ARCH=freebsd
+	export EXE_SUFFIX=
+	;;
+    "CYGWIN_NT-5.1-iX86")
+	export TARGET_ARCH=cygwin
+	export EXE_SUFFIX=.exe
+    	;;	
+    *) 
+     echo "Unknown OS found"
+esac
+
+export SOC=$PWD
+export PLATFORMS=$SOC/Platforms
+export SOFT=$SOC/Softwares
+export TOOLS=$SOC/Tools
+export IPS=$SOC/IPs/systemC
+
+export PATH=$PATH:$IPS/processor/M_CPU/Script:$TOOLS/or1k/bin:$TOOLS/soclib/tools/bin-$TARGET_ARCH
+
+echo
+echo "OS found : $OS_FOUND"
+echo ""
+echo "SOC         is set to $SOC"
+echo "PLATFORMS   is set to $PLATFORMS"
+echo "SOFT        is set to $SOFT"
+echo "TOOLS       is set to $TOOLS"
+echo "IPS         is set to $IPS"
+echo
