# RegisterFile_Multi_Banked_0
target_dep	all	RegisterFile_Multi_Banked_0.ngc
target_dep	RegisterFile_Multi_Banked_0.ngc	RegisterFile_Multi_Banked_0.prj
target_dep	RegisterFile_Multi_Banked_0.prj	RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports.vhdl RegisterFile_Multi_Banked_0_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_2_ports.vhdl RegisterFile_Multi_Banked_0.vhdl

# RegisterFile_Multi_Banked_1
target_dep	all	RegisterFile_Multi_Banked_1.ngc
target_dep	RegisterFile_Multi_Banked_1.ngc	RegisterFile_Multi_Banked_1.prj
target_dep	RegisterFile_Multi_Banked_1.prj	RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports.vhdl RegisterFile_Multi_Banked_1_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_2_ports.vhdl RegisterFile_Multi_Banked_1.vhdl