# state_0
target_dep	all	state_0.ngc
target_dep	state_0.ngc	state_0.prj
target_dep	state_0.prj	state_0_Pack.vhdl state_0.vhdl

# state_1
target_dep	all	state_1.ngc
target_dep	state_1.ngc	state_1.prj
target_dep	state_1.prj	state_1_Pack.vhdl state_1.vhdl

# state_2
target_dep	all	state_2.ngc
target_dep	state_2.ngc	state_2.prj
target_dep	state_2.prj	state_2_Pack.vhdl state_2.vhdl

# state_3
target_dep	all	state_3.ngc
target_dep	state_3.ngc	state_3.prj
target_dep	state_3.prj	state_3_Pack.vhdl state_3.vhdl