#    This file is part of MKF.
#
#    MKF is free software; you can redistribute it and/or modify
#    it under the terms of the GNU General Public License as published by
#    the Free Software Foundation; either version 2 of the License, or
#    (at your option) any later version.
#
#    MKF is distributed in the hope that it will be useful,
#    but WITHOUT ANY WARRANTY; without even the implied warranty of
#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#    GNU General Public License for more details.
#
#    You should have received a copy of the GNU General Public License
#    along with MKF; if not, write to the Free Software
#    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
#
#    Copyright (c) 2004 Alexandre Becoulet <alexandre.becoulet@epita.fr>

# used for rm -r with clean rules
var_define		xilinx_rm_r	-r 

var_define		vhdl_m4_defines	XILINX

# Xilinx xst sythesis tool
# (HDL language) .vhdl	->	(netlist) .ngc
# (HDL language) .prj	->	(netlist) .ngc

_if_var_eq		xilinx_target	
  msg_warning		xilinx_target device not defined
_end_if

_if_var_eq		cmd_xilinx_xst
 var_define		cmd_xilinx_xst		xst
_end_if

_if_in_path		{PVAR,cmd_xilinx_xst}

 msg_info		Xilinx synthesis tool ({PVAR,cmd_xilinx_xst}) found
 var_define		use_xilinx_xst		xst

 command_add		vhdl	ngc	echo run -keep_hierarchy yes -iobuf no -ifn {SRC,.*\.vhdl} -ofn {OUT} \
                                        -p {JVAR,xilinx_target} {JVAR,opt_xst} \
                                        -ifmt VHDL | {JVAR,cmd_xilinx_xst}

 command_add		prj	ngc	echo run -keep_hierarchy yes -iobuf no -top {SRC!,.*\.prj} \
                                        -ifn {SRC,.*\.prj} -ofn {OUT} \
                                        -p {JVAR,xilinx_target} {JVAR,opt_xst} \
                                        -ifmt mixed | {JVAR,cmd_xilinx_xst}

#                                        -uc {SRC!,.*\.prj}.xcf 

 clean_add		prj	ngc	{OUT!}.lso {JVAR,xilinx_rm_r}xst

 command_add		vhdl	prj	for i in {SRC,.*\.vhdl} ; do echo "vhdl work $$i" ; done > {OUT}

 command_add		vhdl.m4	vhdl	m4 -P {JLIST,-D,vhdl_m4_defines} {JLIST,-I,inc_dirs} {SRC,.*\.vhdl.m4} > {OUT}

_else
  msg_error		can't find Xilinx xst tool
_end_if

# Xilinx ngdbuild
# (netlist) .ngc	->	(design database) .ngd

_if_var_eq		cmd_xilinx_ngdbuild
 var_define		cmd_xilinx_ngdbuild		ngdbuild
_end_if

_if_in_path		{PVAR,cmd_xilinx_ngdbuild}

 msg_info		Xilinx ngdbuild tool ({PVAR,cmd_xilinx_ngdbuild}) found
 var_define		use_xilinx_ngdbuild		ngdbuild

 command_add		ngc	ngd	{JVAR,cmd_xilinx_ngdbuild} {SRC,system.ngc} \
                                        {SRC,.*\.ucf,-uc } {SRC,.*\.bmm,-bm } \
                                        -p {JVAR,xilinx_target} {JVAR,opt_ngdbuild} {OUT}

 clean_add		ngc	ngd	{OUT!}.bld netlist.lst

_else
  msg_error		can't find Xilinx ngdbuild tool
_end_if

# Xilinx ngcbuild
# (netlist) .ngc	->	(netlist) .ngc

_if_var_eq		cmd_xilinx_ngcbuild
 var_define		cmd_xilinx_ngcbuild		ngcbuild
_end_if

_if_in_path		{PVAR,cmd_xilinx_ngcbuild}

 msg_info		Xilinx ngcbuild tool ({PVAR,cmd_xilinx_ngcbuild}) found
 var_define		use_xilinx_ngcbuild		ngcbuild

 command_add		ngc	ngc	{JVAR,cmd_xilinx_ngcbuild} {SRC,.*\.ngc} {SRC,.*\.ucf,-uc } \
                                        -p {JVAR,xilinx_target} {JVAR,opt_ngcbuild} {OUT}

 clean_add		ngc	ngc	{OUT!}.blc

_else
  msg_error		can't find Xilinx ngcbuild tool
_end_if

# Xilinx map
# (netlist) .ngd	->	(physical design) .ncd

_if_var_eq		cmd_xilinx_map
 var_define		cmd_xilinx_map		map
_end_if

_if_in_path		{PVAR,cmd_xilinx_map}

 msg_info		Xilinx map tool ({PVAR,cmd_xilinx_map}) found
 var_define		use_xilinx_map		map

 command_add		ngd	ncd	{JVAR,cmd_xilinx_map} -u {SRC,.*\.ngd} -o {OUT} \
                                        -p {JVAR,xilinx_target} {JVAR,opt_map}

 clean_add		ngd	ncd	{SRC!,.*\.ngd}.mrp {SRC!,.*\.ngd}.ngm netlist.lst

_else
  msg_error		can't find Xilinx map tool
_end_if

# Xilinx par (place & route)
# (physical design) .ncd	->	(physical design) .ncd

_if_var_eq		cmd_xilinx_par
 var_define		cmd_xilinx_par		par
_end_if

_if_in_path		{PVAR,cmd_xilinx_par}

 msg_info		Xilinx place and route tool ({PVAR,cmd_xilinx_par}) found
 var_define		use_xilinx_par		par

 command_add		ncd	par.ncd	{JVAR,cmd_xilinx_par} -w {JVAR,opt_par} \
                                        {SRC,.*\.ncd} {OUT} {SRC,.*\.pcf}

 clean_add		ncd	par.ncd	{SRC!,.*\.ncd}.par* 

_else
  msg_error		can't find Xilinx par tool
_end_if

# Xilinx bitstream gen
# (physical design) .ncd	->	(physical design) .bit

_if_var_eq		cmd_xilinx_bitgen
 var_define		cmd_xilinx_bitgen		bitgen
_end_if

_if_in_path		{PVAR,cmd_xilinx_bitgen}

 msg_info		Xilinx bitstream generation tool ({PVAR,cmd_xilinx_bitgen}) found
 var_define		use_xilinx_bitgen		bitgen

 command_add		par.ncd	bit	{JVAR,cmd_xilinx_bitgen} -w {JVAR,opt_bitgen} \
                                        {SRC,.*\.ncd} {OUT} {SRC,.*\.pcf}

 clean_add		par.ncd	bit	{SRC!,.*\.ncd}.bgn {SRC!,.*\.ncd}.par* {SRC!,.*\.ncd}.drc

_else
  msg_error		can't find Xilinx bitgen tool
_end_if

# Xilinx data2mem
# (physical design) .bit	->	(physical design) .bit

_if_var_eq		cmd_xilinx_data2mem
 var_define		cmd_xilinx_data2mem		data2mem
_end_if

_if_in_path		{PVAR,cmd_xilinx_data2mem}

 msg_info		Xilinx memory update tool ({PVAR,cmd_xilinx_data2mem}) found
 var_define		use_xilinx_data2mem		data2mem

 command_add		bit	bit	{JVAR,cmd_xilinx_data2mem} -bm {SRC!,*\.bit}_bd.bmm \
                                        -bt {SRC,*\.bit} -bd {SRC,*\.elf} -o b {OUT} \
                                        {JVAR,opt_data2mem}

_else
  msg_error		can't find Xilinx data2mem tool
_end_if