# 
# $Id: Makefile.Synthesis 96 2008-12-16 19:36:25Z moulu $
# 
# [ Description ]
# 
# Makefile
# 

#-----[ Variables ]----------------------------------------

DIR_VHDL			= .
DIR_WORK			= work

FPGA_CFG_FILE_LOCAL		= mkf.info
FPGA_CFG_FILE_GLOBAL_DIR	= $(DIR_MORPHEO)/Behavioural
FPGA_CFG_FILE_GLOBAL   		= configure.mkf 

FPGA_FILES			= $(patsubst $(DIR_CFG_GEN)/%.cfg,%,$(wildcard $(DIR_CFG_GEN)/*.cfg))	\
	  			  $(patsubst $(DIR_CFG_USER)/%.cfg,%,$(wildcard $(DIR_CFG_USER)/*.cfg))

FPGA_LOG_FILES			= $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_GEN)/*.cfg))	\
	  			  $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg))
#-----[ Rules ]--------------------------------------------
.PRECIOUS			: $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.sim.log

vhdl				: execute $(DIR_WORK)
				@\
				declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl));						\
				declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log});						\
				if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;		\
				declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl));						\
				declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log});						\
				if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;		\
				declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)"));		\
				declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log});						\
				if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;

sim				: vhdl
				@\
				declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl));						\
				declare -a log_files=($${vhdl_files[*]/%.vhdl/.sim.log});						\
				if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;

fpga				: sim
				@\
				$(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL);	\
				$(ECHO) "files :::::::: $(FPGA_FILES)";	\
				for file in $(FPGA_FILES); do										\
					declare -a files=($$($(LS) $$file*.vhdl|$(GREP_NOT) "(_Testbench\.)"));				\
					$(ECHO) -e "# $$file"                             >> $(FPGA_CFG_FILE_LOCAL);			\
					$(ECHO) -e "target_dep\tall\t$$file.ngc"          >> $(FPGA_CFG_FILE_LOCAL);			\
					$(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj"	  >> $(FPGA_CFG_FILE_LOCAL);			\
					$(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL);			\
					$(ECHO) -e ""                                     >> $(FPGA_CFG_FILE_LOCAL);			\
				done;					\
				($(XILINX_ENV); cd $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL));				\
				$(MAKE) $(FPGA_LOG_FILES);

$(DIR_LOG)/%.fpga.log     	: 
				@\
				$(ECHO) "Synthetis on FPGA  : $*"; \
				$(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@;

$(DIR_WORK)			:
				@\
				$(ECHO) "Create work-space  : $@"; \
				$(MODELTECH_VLIB) $@;

$(DIR_LOG)/%.sim.log		: $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
				@\
				$(ECHO) "VHDL's Simulation  : $*"; \
				$(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" &> $@; \
				declare -i count=`$(GREP) -ch "Test OK" $@`;		\
				if $(TEST) $$count -ne 0;       			\
				then echo "                     $* ... OK";           	\
				else echo "                     $* ... KO"; exit 1;     \
				fi;

$(DIR_LOG)/%.vhdl.log		: $(DIR_VHDL)/%.vhdl
				@\
				$(ECHO) "VHDL's Compilation : $*"; \
				$(MODELTECH_VCOM) $< &> $@;

synthesis_clean			:
				@\
				if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi; \
				$(RM) $(DIR_WORK) transcript Makefile.mkf $(FPGA_CFG_FILE_LOCAL) *.wlf;

synthesis_clean_all		: synthesis_clean

synthesis_help			:
				@\
				$(ECHO) " -----[ Synthesis ]----------------------------------";\
				$(ECHO) "";\
				$(ECHO) " * vhdl                 : compile all vhdl's file";\
				$(ECHO) " * sim                  : simulate all testbench's file";\
				$(ECHO) " * fpga                 : synthetis with fpga's tools";\
				$(ECHO) "";