id	summary	reporter	owner	description	type	status	priority	milestone	component	resolution	keywords	cc
39	Handle Mips delay slot in exception handler	Nicolas Pouillon	Nicolas Pouillon	"We dont currently handle CAUSE/BD which tells us we are actually in a delay slot. This can make the return address of an interrupt wrong.

We should:
 * Add a bit in cpu_context save/restore mask
 * Copy CAUSE/BD to save/restore mask
 * Substract 4 when restoring PC with BD = 1
"	defect	closed	critical	Preemptive scheduler usage	cpu/mips	invalid