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6:16 PM Changeset [73] by bouyer: 2 structure members with the same semantic is one too much. Keep only …
6:13 PM Changeset [72] by bouyer: Initialize ci_fpcurlwp (not used yet). Add some KASSERT and improve …
6:13 PM Changeset [71] by bouyer: Initialize MIPS_COP_0_TCCONTEXT
6:12 PM Changeset [70] by bouyer: Declare MIPS_COP_0_TCCONTEXT, and use it to keep curlwp from userland.
4:41 PM Changeset [69] by bouyer: disable preemtion until we got infos from the vcache. restore ra …
4:32 PM Changeset [68] by bouyer: Grab kernel_lock for hardware interrupts.

8:06 PM Changeset [67] by bouyer: Explicitely disable interrupts on secondary processors.

10:27 PM Changeset [66] by bouyer: Ack WTI
10:10 PM Changeset [65] by bouyer: Give IPL_HIGH its own interrupt line. Drop lines for soft interrupts, …
9:42 PM Changeset [64] by bouyer: Destroy pmap->pm_obj in pmap_ctor() on failure.
6:53 PM Changeset [63] by bouyer: Properly compute interrupt lines.
1:07 PM Changeset [62] by bouyer: Add IPL_DDB
12:50 PM Changeset [61] by bouyer: merge matt-nb5-mips64-20100518
12:15 PM Changeset [60] by bouyer: Tagging today's matt-nb5-mips64 import.
12:14 PM Changeset [59] by bouyer: Import the NetBSD matt-nb5-mips64 branch as of now

6:47 PM Changeset [58] by bouyer: Allow to bind interrupts to a specific CPU.
5:56 PM Changeset [57] by bouyer: Compare vaddr > VM_MAXUSER_ADDRESS, not < 0
5:55 PM Changeset [56] by bouyer: t8 is now the CURLWP register, don't use it. Save and use S8 instead.
4:24 PM Changeset [55] by bouyer: Merge trap.c from CVS 1.217.12.26
4:22 PM Changeset [54] by bouyer: Merge trap.c CVS 1.217.12.26
4:21 PM Changeset [53] by bouyer: Make SMP kernels build again.
3:13 PM Changeset [52] by bouyer: SOFTFLOAT is now FPEMUL
12:13 PM Changeset [51] by bouyer: Make *_DEBUG build call ddb at splhigh()
12:11 PM Changeset [50] by bouyer: Compare address against VM_MAXUSER_ADDRESS to decide if it's a kernel …

8:06 PM Changeset [49] by bouyer: Properly initialize status reg in PCB.
8:05 PM Changeset [48] by bouyer: splsched() is the same as splhigh() these days.
8:04 PM Changeset [47] by bouyer: Resolve merge conflicts (forgotten after last import)

5:25 PM Changeset [46] by bouyer: Make SOCLIB kernel build after matt-nb5-mips64 merge. Problem with …
8:46 AM Changeset [45] by bouyer: Add missing files from matt-nb5-mips64-20100422
8:45 AM Changeset [44] by bouyer: Add missed files from import
8:41 AM Changeset [43] by bouyer: Undo bad copy
8:34 AM Changeset [42] by bouyer: Add missing files from matt-nb5-mips64
8:32 AM Changeset [41] by bouyer: Add missing files from matt-nb5-mips64
8:27 AM Changeset [40] by bouyer: Merge matt-nb5-mips64-20100422 in trunk
12:07 AM Changeset [39] by bouyer: Tag vendor branch to matt-nb5-mips64-20100422
12:06 AM Changeset [38] by bouyer: Import the NetBSD matt-nb5-mips64 branch as of now, in the vendor branch.

6:50 PM Changeset [37] by bouyer: Work in progress on SMP. Not there yet …
3:55 PM Changeset [36] by bouyer: Enable caches early if !VCACHE

10:50 PM Changeset [35] by bouyer: Make SMP kernel build (and work) with FDT.
7:42 PM Changeset [34] by bouyer: Use the FDT to discover devices and route IRQs.

10:58 PM Changeset [33] by bouyer: Make non-CC, non-MLTIPROCESSOR kernel build and work again Pass FDT …
10:57 PM Changeset [32] by bouyer: Switch boot CPU to 0 again Disable cache again, for non-CC platforms
8:20 PM Changeset [31] by bouyer: Also pass xicu to cpu when there's no CPU info.

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