| 1 | | |
| | 1 | Draft claim statement: |
| | 2 | Multicore Systems-on-Chip are widely claimed to be a future architecture of choice for both mainstream and embedded computing devices. But there is still a shortage of automatic and efficient compilation techniques to map application software onto such platforms. As data communications between cores quickly lead to performance bottlenecks in these architectures, on-chip networks have been proposed to replace buses and increase throughput. But this in itself may remain insufficient, if traffic along such networks is not organised and regulated according to the applications. To put it boldly: applications should be compiled onto the processors and the network altogether. |
| | 3 | |
| | 4 | To tackle this ambitious goal, we feel we should rely on existing formalisms, proposed in the past for neighboring concerns, and which may each contribute in part to the solution. Synchronous languages and polychronous extensions provide a way to deal with explicit schedule constraints in a user-readable syntactic way. Process networks provide a specification style with explicit data-flow concurrency, which departs from strict scheduling concerns (reintroduced later thanks to the first formalism?). Nested loop programs with static control provide a programming style much closer to mainstream sequential languages, but where potential data parallelism and concurrency can be extracted (and be represented then within the second formalism?). |
| | 5 | |
| | 6 | While numerous links do already exist between these formalisms, they are still far from achieving a consistent design flow for compilation. Furthermore, the necessity of mapping process network's virtual data channels towards the actual interconnect resources of the NoC, may lead to additional concerns in the actual definition of the NoC itself, its routing ability, and its programmability in the framework of a dedicated compilation schemata. |
