Changes between Version 2 and Version 3 of VgmnNoirqMono

Timestamp:

Jul 5, 2011, 3:08:48 PM (14 years ago)

Author:

Joel Porquet

Comment:

--

VgmnNoirqMono

@@ -24 +24 @@
     pf.create('common:loader', 'loader')
 
-    vgmn = pf.create('caba:vci_vgmn', 'vgmn0', ...)
+    vgmn = pf.create('caba:vci_vgmn', 'vgmn0', min_latency = 10, fifo_depth = 8, mt = mt)
 
     cpu = pf.create('caba:vci_xcache_wrapper', 'cpu0',
@@ -42 +42 @@
 #   instanciate the coprocessor and its controller
 #
-#   tg = dsx.TaskModel.getByName('tg').getImpl(soclib.HwTask)
-#        # The creation returns two components
-#   ctrl, coproc = tg.instanciate(pf, 'tg0')
-#        # We need now to assign an address to the controller and to connect it
-#        to the interconnect (there is two ports to connect)
-#   ctrl.addSegment('tg_ctrl', 0x70400000, 0x100, False)
-#   ctrl.vci_initiator // vgmn.to_initiator.new()
-#   ctrl.vci_target // vgmn.to_target.new()
+#    tg = dsx.TaskModel.getByName('tg').getImpl(soclib.HwTask)
+#    # The creation returns two components
+#    ctrl, coproc = tg.instanciate(pf, 'tg0')
+#    # We need now to assign an address to the controller and to connect it
+#    # to the interconnect (there is two ports to connect)
+#    ctrl.addSegment('tg_ctrl', 0x70400000, 0x100, False)
+#    ctrl.vci_initiator // vgmn.to_initiator.new()
+#    ctrl.vci_target // vgmn.to_target.new()
 #
-#        # same with ramdac
-#   ramdac = dsx.TaskModel.getByName('ramdac').getImpl(soclib.HwTask)
-#   ctrl, coproc = ramdac.instanciate(pf, 'ramdac0')
-#   ctrl.addSegment('ramdac_ctrl', 0x71400000, 0x100, False)
-#   ctrl.vci_initiator // vgmn.to_initiator.new()
-#   ctrl.vci_target // vgmn.to_target.new()
+#    # same with ramdac
+#    ramdac = dsx.TaskModel.getByName('ramdac').getImpl(soclib.HwTask)
+#    ctrl, coproc = ramdac.instanciate(pf, 'ramdac0')
+#    ctrl.addSegment('ramdac_ctrl', 0x71400000, 0x100, False)
+#    ctrl.vci_initiator // vgmn.to_initiator.new()
+#    ctrl.vci_target // vgmn.to_target.new()
 
 
@@ -65 +65 @@
         ram.addSegment('uram%d'%i, base + 0x400000, 0x100000, False)
         ram.vci // vgmn.to_target.new()
-    ram.addSegment('boot', ...) # Mips boot address, 0x1000 octets, cacheable
-    ram.addSegment('excep', ...) # Mips exception address, 0x1000 octets, cacheable
+    ram.addSegment('boot', 0xbfc00000, 0x1000, True) # Mips boot address, 0x1000 octets, cacheable
+    ram.addSegment('excep', 0x80000080, 0x1000, True) # Mips exception address, 0x1000 octets, cacheable
 
     tty = pf.create('caba:vci_multi_tty', 'tty0', names = ['tty0'])