44 | | # tg = dsx.TaskModel.getByName('tg').getImpl(soclib.HwTask) |
45 | | # # The creation returns two components |
46 | | # ctrl, coproc = tg.instanciate(pf, 'tg0') |
47 | | # # We need now to assign an address to the controller and to connect it |
48 | | # to the interconnect (there is two ports to connect) |
49 | | # ctrl.addSegment('tg_ctrl', 0x70400000, 0x100, False) |
50 | | # ctrl.vci_initiator // vgmn.to_initiator.new() |
51 | | # ctrl.vci_target // vgmn.to_target.new() |
| 44 | # tg = dsx.TaskModel.getByName('tg').getImpl(soclib.HwTask) |
| 45 | # # The creation returns two components |
| 46 | # ctrl, coproc = tg.instanciate(pf, 'tg0') |
| 47 | # # We need now to assign an address to the controller and to connect it |
| 48 | # # to the interconnect (there is two ports to connect) |
| 49 | # ctrl.addSegment('tg_ctrl', 0x70400000, 0x100, False) |
| 50 | # ctrl.vci_initiator // vgmn.to_initiator.new() |
| 51 | # ctrl.vci_target // vgmn.to_target.new() |
53 | | # # same with ramdac |
54 | | # ramdac = dsx.TaskModel.getByName('ramdac').getImpl(soclib.HwTask) |
55 | | # ctrl, coproc = ramdac.instanciate(pf, 'ramdac0') |
56 | | # ctrl.addSegment('ramdac_ctrl', 0x71400000, 0x100, False) |
57 | | # ctrl.vci_initiator // vgmn.to_initiator.new() |
58 | | # ctrl.vci_target // vgmn.to_target.new() |
| 53 | # # same with ramdac |
| 54 | # ramdac = dsx.TaskModel.getByName('ramdac').getImpl(soclib.HwTask) |
| 55 | # ctrl, coproc = ramdac.instanciate(pf, 'ramdac0') |
| 56 | # ctrl.addSegment('ramdac_ctrl', 0x71400000, 0x100, False) |
| 57 | # ctrl.vci_initiator // vgmn.to_initiator.new() |
| 58 | # ctrl.vci_target // vgmn.to_target.new() |
67 | | ram.addSegment('boot', ...) # Mips boot address, 0x1000 octets, cacheable |
68 | | ram.addSegment('excep', ...) # Mips exception address, 0x1000 octets, cacheable |
| 67 | ram.addSegment('boot', 0xbfc00000, 0x1000, True) # Mips boot address, 0x1000 octets, cacheable |
| 68 | ram.addSegment('excep', 0x80000080, 0x1000, True) # Mips exception address, 0x1000 octets, cacheable |