cours2: cpu.h

File cpu.h, 5.5 KB (added by fpecheux, 17 years ago)
Line 
1#ifndef _CPU_H
2#define _CPU_H
3#include "systemc.h"
4
5#include "constants.h"
6#include "fsm.h"
7#include "alu_32.h"
8#include "pc_reg_32.h"
9#include "shift_left_32.h"
10#include "sign_extend_32.h"
11#include "nosign_extend_32.h"
12#include "mux21_5.h"
13#include "mux21_32.h"
14#include "mux81_32.h"
15#include "rf32.h"
16#include "plain_reg_32.h"
17#include "ir_reg_32.h"
18#include "cst4_32.h"
19#include "cst0_32.h"
20
21SC_MODULE(cpu)
22{
23 sc_in<bool> clk;
24 sc_in<bool> reset;
25 sc_out<sc_uint<32> > address;
26 sc_out<sc_uint<2> > memrw;
27 sc_out<sc_uint<32> > dataout;
28 sc_in<sc_uint<32> > datain;
29
30 sc_signal<bool> write_pc;
31 sc_signal<bool> mux_rf_w;
32 sc_signal<bool> mux_rf_r;
33 sc_signal<bool> write_rf;
34 sc_signal<sc_uint<5> > adr_rf_w;
35 sc_signal<sc_uint<5> > adr_rf_r;
36 sc_signal<bool> write_ad;
37 sc_signal<bool> write_dt;
38 sc_signal<bool> write_ir;
39 sc_signal<sc_uint<3> > mux_x;
40 sc_signal<sc_uint<3> > mux_y;
41 sc_signal<bool> mux_addr;
42 sc_signal<sc_uint<3> > alu_op;
43 sc_signal<bool> zero;
44 sc_signal<sc_uint<32> > ir;
45
46 sc_signal<sc_uint<32> > cst0out;
47 sc_signal<sc_uint<32> > cst4out;
48 sc_signal<sc_uint<32> > pcout;
49 sc_signal<sc_uint<32> > rfout;
50 sc_signal<sc_uint<32> > adout;
51 sc_signal<sc_uint<32> > dtout;
52 sc_signal<sc_uint<32> > irsextout;
53 sc_signal<sc_uint<32> > irextout;
54 sc_signal<sc_uint<32> > irshiftout;
55 sc_signal<sc_uint<32> > mux_x_out;
56 sc_signal<sc_uint<32> > mux_y_out;
57 sc_signal<sc_uint<32> > int_dataout;
58 sc_signal<sc_uint<16> > irout15_0;
59 sc_signal<sc_uint<5> > irout15_11;
60 sc_signal<sc_uint<5> > irout20_16;
61 sc_signal<sc_uint<5> > irout25_21;
62
63 pc_reg_32 *pc_1;
64 rf32 *rf32_1;
65 plain_reg_32 *reg_ad_1;
66 plain_reg_32 *reg_dt_1;
67 ir_reg_32 *ir_reg_32_1;
68 mux21_5 *mux_rf_r_1;
69 mux21_5 *mux_rf_w_1;
70 mux81_32 *mux_a_1;
71 mux81_32 *mux_b_1;
72 sign_extend_32 *sign_extend_32_1;
73 nosign_extend_32 *nosign_extend_32_1;
74 shift_left_32 *shift_left_32_1;
75 mux21_32 *mux_addr_1;
76 alu_32 *alu_32_1;
77 cst4_32 *cst4_1;
78 cst0_32 *cst0_1;
79 fsm *fsm_1;
80
81 SC_CTOR(cpu)
82 {
83 // PC_REG_32
84 pc_1=new pc_reg_32("pc_reg_32_1");
85
86 pc_1->clk(clk);
87 pc_1->reset(reset);
88 pc_1->D(dataout);
89 pc_1->PCWrite(write_pc);
90 pc_1->Q(pcout);
91
92 // RF32
93
94 rf32_1=new rf32("rf32_1");
95 rf32_1->clk(clk);
96 rf32_1->RegWrite(write_rf);
97 rf32_1->Addwrite(adr_rf_w);
98 rf32_1->Addrd1(adr_rf_r);
99 rf32_1->Writedata(int_dataout);
100 rf32_1->data1(rfout);
101
102 // AD
103 reg_ad_1=new plain_reg_32("reg_ad_1");
104 reg_ad_1->clk(clk);
105 reg_ad_1->regWrite(write_ad);
106 reg_ad_1->D(int_dataout);
107 reg_ad_1->Q(adout);
108
109 // DT
110 reg_dt_1=new plain_reg_32("reg_dt_1");
111 reg_dt_1->clk(clk);
112 reg_dt_1->regWrite(write_dt);
113 reg_dt_1->D(datain);
114 reg_dt_1->Q(dtout);
115
116 // IR_REG_32
117 ir_reg_32_1=new ir_reg_32("ir_reg_32_1");
118 ir_reg_32_1->clk(clk);
119 ir_reg_32_1->D(datain);
120 ir_reg_32_1->regWrite(write_ir);
121 ir_reg_32_1->Q(ir);
122 ir_reg_32_1->Q15_0(irout15_0);
123 ir_reg_32_1->Q25_21(irout25_21);
124 ir_reg_32_1->Q20_16(irout20_16);
125 ir_reg_32_1->Q15_11(irout15_11);
126
127 // SIGN_EXTEND
128 sign_extend_32_1=new sign_extend_32("sign_extend_32_1");
129 sign_extend_32_1->I(irout15_0);
130 sign_extend_32_1->O(irextout);
131
132 // NOSIGN_EXTEND
133 nosign_extend_32_1=new nosign_extend_32("nosign_extend_32_1");
134 nosign_extend_32_1->I(irout15_0);
135 nosign_extend_32_1->O(irsextout);
136
137 // SHIFT LEFT 2
138 shift_left_32_1=new shift_left_32("shift_left_32_1");
139 shift_left_32_1->I(irextout);
140 shift_left_32_1->O(irshiftout);
141
142 // CST0
143 cst0_1=new cst0_32("cst0_1");
144 cst0_1->S(cst0out);
145
146 // CST4
147 cst4_1=new cst4_32("cst4_1");
148 cst4_1->S(cst4out);
149
150 // MUX21_5 pour RF lecture
151 mux_rf_r_1=new mux21_5("mux_rf_r_1");
152 mux_rf_r_1->IN0(irout25_21);
153 mux_rf_r_1->IN1(irout20_16);
154 mux_rf_r_1->COM(mux_rf_r);
155 mux_rf_r_1->S(adr_rf_r);
156
157 // MUX21_5 pour ADW_RF
158 mux_rf_w_1=new mux21_5("mux_rf_w_1");
159 mux_rf_w_1->IN0(irout20_16);
160 mux_rf_w_1->IN1(irout15_11);
161 mux_rf_w_1->COM(mux_rf_w);
162 mux_rf_w_1->S(adr_rf_w);
163
164 // MUX81_32 pour a
165 mux_a_1=new mux81_32("mux_a_1");
166 mux_a_1->IN0(pcout);
167 mux_a_1->IN1(rfout);
168 mux_a_1->IN2(adout);
169 mux_a_1->IN3(dtout);
170 mux_a_1->IN4(cst0out);
171 mux_a_1->IN5(cst0out);
172 mux_a_1->IN6(cst0out);
173 mux_a_1->IN7(cst0out);
174 mux_a_1->COM(mux_x);
175 mux_a_1->S(mux_x_out);
176
177 // MUX81_32 pour b
178 mux_b_1=new mux81_32("mux_b_1");
179 mux_b_1->IN0(cst0out);
180 mux_b_1->IN1(cst4out);
181 mux_b_1->IN2(adout);
182 mux_b_1->IN3(irextout);
183 mux_b_1->IN4(irshiftout);
184 mux_b_1->IN5(irsextout);
185 mux_b_1->IN6(cst0out);
186 mux_b_1->IN7(cst0out);
187 mux_b_1->COM(mux_y);
188 mux_b_1->S(mux_y_out);
189
190 // MUX21_32 pour le PC et ALUOUT
191 mux_addr_1=new mux21_32("mux_addr_1");
192 mux_addr_1->IN0(adout);
193 mux_addr_1->IN1(pcout);
194 mux_addr_1->COM(mux_addr);
195 mux_addr_1->S(address);
196
197 // ALU
198
199 alu_32_1=new alu_32("alu_32_1");
200 alu_32_1->A(mux_x_out);
201 alu_32_1->B(mux_y_out);
202 alu_32_1->Aluop(alu_op);
203 alu_32_1->Aluout(int_dataout);
204 alu_32_1->zero(zero);
205
206 // FSM
207 fsm_1=new fsm("fsm_1");
208 fsm_1->clk(clk);
209 fsm_1->reset(reset);
210 fsm_1->ir(ir);
211 fsm_1->zero(zero);
212
213 fsm_1->write_pc(write_pc);
214 fsm_1->mux_rf_w(mux_rf_w);
215 fsm_1->write_rf(write_rf);
216 fsm_1->mux_rf_r(mux_rf_r);
217 fsm_1->write_ad(write_ad);
218 fsm_1->write_dt(write_dt);
219 fsm_1->write_ir(write_ir);
220 fsm_1->mux_x(mux_x);
221 fsm_1->mux_y(mux_y);
222 fsm_1->mux_addr(mux_addr);
223 fsm_1->alu_op(alu_op);
224 fsm_1->memrw(memrw);
225
226 SC_METHOD(dataoutext);
227 sensitive << int_dataout;
228 }
229
230 void dataoutext()
231 {
232 dataout.write(int_dataout);
233 }
234};
235#endif