Context Navigation

Back to cours2

cours2: fsm.h

File fsm.h, 8.8 KB (added by fpecheux, 16 years ago)

Line
1	#ifndef _FSM_H
2	#define _FSM_H
3	#include "systemc.h"
4	#include "constants.h"
5
6	#include <iostream>
7	#include <fstream>
8	#include <string>
9	using namespace std;
10
11	#define MEMNOP 0
12	#define MEMREAD 1
13	#define MEMWRITE 2
14
15	#define R_RS 0
16	#define R_RT 1
17
18	#define W_RT 0
19	#define W_RD 1
20
21	#define MUX_ADDR_AD 0
22	#define MUX_ADDR_PC 1
23
24	#define MUX_X_PC 0
25	#define MUX_X_RF 1
26	#define MUX_X_AD 2
27	#define MUX_X_DT 3
28	#define MUX_X_CST0 4
29
30	#define MUX_Y_CST0 0
31	#define MUX_Y_CST4 1
32	#define MUX_Y_AD 2
33	#define MUX_Y_SE32 3
34	#define MUX_Y_SHF2 4
35	#define MUX_Y_NSE32 5
36
37	#define ALU_OP_ADD 2
38	#define ALU_OP_SUB 6
39	#define ALU_OP_OR 7
40
41	#define S_RESET 0
42	#define S_PCPLUS4 1
43	#define S_LW1 2
44	#define S_LW2 3
45	#define S_LW3 4
46	#define S_SW1 5
47	#define S_SW2 6
48	#define S_SW3 7
49	#define S_ADDI1 8
50	#define S_ADDI2 9
51
52	SC_MODULE(fsm)
53	{
54	sc_in<bool> clk;
55	sc_in<bool> reset;
56	sc_in<sc_uint<32> > ir;
57	sc_in<bool> zero;
58
59	sc_out<bool> write_pc;
60	sc_out<bool> mux_rf_w;
61	sc_out<bool> write_rf;
62	sc_out<bool> mux_rf_r;
63	sc_out<bool> write_ad;
64	sc_out<bool> write_dt;
65	sc_out<bool> write_ir;
66	sc_out<sc_uint<3> > mux_x;
67	sc_out<sc_uint<3> > mux_y;
68	sc_out<bool> mux_addr;
69	sc_out<sc_uint<3> > alu_op;
70	sc_out<sc_uint<2> > memrw;
71
72	sc_signal<int> state,next_state;
73
74	SC_CTOR(fsm)
75	{
76
77	SC_METHOD(mReg);
78	sensitive << clk.pos();
79	SC_METHOD(mNextState);
80	sensitive << state << ir << zero;
81	SC_METHOD(mMooreOutputs);
82	sensitive << state;
83	}
84
85	void mReg()
86	{
87	if (reset==0)
88	state=S_RESET;
89	else
90	state=next_state;
91	}
92
93	void mNextState()
94	{
95	sc_uint<32> ir_value=ir.read();
96	switch (state)
97	{
98	case S_RESET: // 0
99	next_state=S_PCPLUS4;
100	break;
101	case S_PCPLUS4: // 1
102	if ((int)ir_value.range(31,26)==OP_LW)
103	next_state=S_LW1;
104	else if ((int)ir_value.range(31,26)==OP_SW)
105	next_state=S_SW1;
106	else if ((int)ir_value.range(31,26)==OP_ADDI)
107	next_state=S_ADDI1;
108	break;
109	case S_LW1: //2
110	next_state=S_LW2;
111	break;
112	case S_LW2: //3
113	next_state=S_LW3;
114	break;
115	case S_LW3: //4
116	next_state=S_PCPLUS4;
117	break;
118	case S_SW1:
119	next_state=S_SW2;
120	break;
121	case S_SW2:
122	next_state=S_SW3;
123	break;
124	case S_SW3:
125	next_state=S_PCPLUS4;
126	break;
127	case S_ADDI1:
128	next_state=S_ADDI2;
129	break;
130	case S_ADDI2:
131	next_state=S_PCPLUS4;
132	break;
133	default:
134	cout << "Erreur dans la fonction mNextState de fsm" << endl ;
135	exit(1);
136	break;
137	}
138	}
139
140	void mMooreOutputs()
141	{
142	sc_uint<32> ir_value=ir.read();
143	switch(state)
144	{
145	case S_RESET:
146	write_pc=0;
147	mux_rf_w=W_RT;
148	write_rf=0;
149	mux_rf_r=R_RS;
150	write_ad=0;
151	write_dt=0;
152	write_ir=1;
153	mux_x=MUX_X_CST0;
154	mux_y=MUX_Y_CST0;
155	mux_addr=MUX_ADDR_PC;
156	alu_op=ALU_OP_ADD;
157	memrw=MEMREAD;
158	break;
159
160	case S_PCPLUS4:
161	write_pc=1;
162	mux_rf_w=W_RT;
163	write_rf=0;
164	mux_rf_r=R_RS;
165	write_ad=0;
166	write_dt=0;
167	write_ir=0;
168	mux_x=MUX_X_PC;
169	mux_y=MUX_Y_CST4;
170	mux_addr=MUX_ADDR_PC;
171	alu_op=ALU_OP_ADD;
172	memrw=MEMNOP;
173	break;
174
175	case S_LW1: // RS+IMD16 -> AD
176	write_pc=0;
177	mux_rf_w=W_RT;
178	write_rf=0;
179	mux_rf_r=R_RS;
180	write_ad=1;
181	write_dt=0;
182	write_ir=0;
183	mux_x=MUX_X_RF;
184	mux_y=MUX_Y_SE32;
185	mux_addr=MUX_ADDR_PC;
186	alu_op=ALU_OP_ADD;
187	memrw=MEMNOP;
188	break;
189
190	case S_LW2:
191	write_pc=0;
192	mux_rf_w=W_RT;
193	write_rf=0;
194	mux_rf_r=R_RS;
195	write_ad=0;
196	write_dt=1;
197	write_ir=0;
198	mux_x=MUX_X_CST0;
199	mux_y=MUX_Y_CST0;
200	mux_addr=MUX_ADDR_AD;
201	alu_op=ALU_OP_ADD;
202	memrw=MEMREAD;
203	break;
204
205	case S_LW3: // DT -> R[20:16], MEM[PC]->IR
206	write_pc=0;
207	mux_rf_w=W_RT;
208	write_rf=1;
209	mux_rf_r=R_RS;
210	write_ad=0;
211	write_dt=0;
212	write_ir=1;
213	mux_x=MUX_X_DT; // DT
214	mux_y=MUX_Y_CST0; //CST0
215	mux_addr=MUX_ADDR_PC;
216	alu_op=ALU_OP_ADD;
217	memrw=MEMREAD;
218	break;
219
220	case S_SW1: // RS+IMD16 -> AD
221	write_pc=0;
222	mux_rf_w=W_RT;
223	write_rf=0;
224	mux_rf_r=R_RS;
225	write_ad=1;
226	write_dt=0;
227	write_ir=0;
228	mux_x=MUX_X_RF;
229	mux_y=MUX_Y_SE32;
230	mux_addr=MUX_ADDR_PC;
231	alu_op=ALU_OP_ADD;
232	memrw=MEMNOP;
233	break;
234
235	case S_SW2: // R[20->16] -> MEM[AD]
236	write_pc=0;
237	mux_rf_w=W_RT;
238	write_rf=0;
239	mux_rf_r=R_RT;
240	write_ad=0;
241	write_dt=0;
242	write_ir=0;
243	mux_x=MUX_X_RF; // RF
244	mux_y=MUX_Y_CST0; // CST0
245	mux_addr=MUX_ADDR_AD;
246	alu_op=ALU_OP_ADD;
247	memrw=MEMWRITE;
248	break;
249
250	case S_SW3: // MEM[PC] -> IR
251	write_pc=0;
252	mux_rf_w=W_RT;
253	write_rf=0;
254	mux_rf_r=R_RS;
255	write_ad=0;
256	write_dt=0;
257	write_ir=1;
258	mux_x=MUX_X_CST0; // CST0
259	mux_y=MUX_Y_CST0; // CST0
260	mux_addr=MUX_ADDR_PC;
261	alu_op=ALU_OP_ADD;
262	memrw=MEMREAD;
263	break;
264
265	case S_ADDI1:
266	write_pc=0;
267	mux_rf_w=W_RT;
268	write_rf=0;
269	mux_rf_r=R_RS;
270	write_ad=1;
271	write_dt=0;
272	write_ir=0;
273	mux_x=MUX_X_RF;
274	mux_y=MUX_Y_SE32;
275	mux_addr=MUX_ADDR_PC;
276	alu_op=ALU_OP_ADD;
277	memrw=MEMNOP;
278	break;
279
280	case S_ADDI2:
281	write_pc=0;
282	mux_rf_w=W_RT;
283	write_rf=1;
284	mux_rf_r=R_RS;
285	write_ad=0;
286	write_dt=0;
287	write_ir=1;
288	mux_x=MUX_X_AD;
289	mux_y=MUX_Y_CST0;
290	mux_addr=MUX_ADDR_PC;
291	alu_op=ALU_OP_ADD;
292	memrw=MEMREAD;
293	break;
294	default:
295	cout << "Erreur dans la fonction mMooreOutputs de fsm" << endl ;
296	exit(1);
297	break;
298	}
299	}
300	};
301	#endif

Download in other formats:

Original Format