1 | #ifndef SOCLIB_VCI_ISS_H |
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2 | #define SOCLIB_VCI_ISS_H |
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3 | |
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4 | #define sc_register sc_signal |
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5 | |
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6 | #include <signal.h> |
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7 | #include <iostream.h> |
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8 | #include <fstream.h> |
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9 | #include <stdlib.h> |
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10 | #include <systemc.h> |
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11 | |
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12 | template < |
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13 | int ADDRSIZE, |
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14 | int CELLSIZE, |
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15 | int ERRSIZE, |
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16 | int PLENSIZE, |
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17 | int CLENSIZE, |
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18 | int SRCIDSIZE, |
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19 | int TRDIDSIZE, |
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20 | int PKTIDSIZE > |
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21 | |
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22 | struct SOCLIB_VCI_ISS : sc_module { |
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23 | |
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24 | sc_in<bool> CLK; |
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25 | sc_in<bool> RESETN; |
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26 | ADVANCED_VCI_INITIATOR<ADDRSIZE, CELLSIZE, ERRSIZE, PLENSIZE, CLENSIZE, SRCIDSIZE, TRDIDSIZE, PKTIDSIZE> VCI_INITIATOR; |
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27 | |
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28 | const char *NAME; |
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29 | sc_register<int> ISS_FSM; |
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30 | sc_register<int> GPR[32]; |
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31 | sc_register<int> PC,IR,EA; |
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32 | |
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33 | enum{ |
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34 | ISS_REQ_IFETCH = 0, |
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35 | ISS_RSP_IFETCH = 1, |
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36 | ISS_DECODE_AND_EXECUTE = 2, |
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37 | ISS_REQ_LOAD = 3, |
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38 | ISS_RSP_LOAD = 4, |
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39 | ISS_REQ_STORE = 5, |
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40 | ISS_RSP_STORE = 6 |
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41 | }; |
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42 | |
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43 | enum { |
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44 | OP_SPECIAL = 0, |
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45 | OP_ADDI = 8, |
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46 | OP_ORI = 13, |
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47 | OP_LW = 35, |
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48 | OP_SW = 43, |
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49 | FUNC_ADD = 32, |
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50 | FUNC_SUB = 34, |
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51 | }; |
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52 | SC_HAS_PROCESS (SOCLIB_VCI_ISS); |
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53 | |
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54 | SOCLIB_VCI_ISS ( |
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55 | sc_module_name insname |
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56 | ) |
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57 | { |
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58 | #ifdef NONAME_RENAME |
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59 | char name[100]; |
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60 | ISS_FSM.rename("ISS_FSM"); |
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61 | PC.rename("PC"); |
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62 | IR.rename("IR"); |
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63 | EA.rename("EA"); |
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64 | for (int j=0 ; j < 32; j++) |
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65 | { |
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66 | sprintf(name,"GPR_%2.2d",j); |
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67 | GPR[j].rename(name); |
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68 | } |
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69 | |
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70 | #endif |
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71 | |
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72 | SC_METHOD (transition); |
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73 | sensitive << CLK.pos(); |
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74 | SC_METHOD (genMoore); |
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75 | sensitive << CLK.neg(); |
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76 | |
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77 | NAME = (char*) strdup(insname); |
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78 | |
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79 | if (NAME == NULL) { |
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80 | perror("malloc"); |
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81 | exit(1); |
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82 | } |
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83 | printf("SOCLIB_VCI_ISS instanciated with name %s\n",NAME); |
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84 | } |
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85 | |
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86 | void transition() |
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87 | { |
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88 | if(RESETN == false) |
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89 | { |
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90 | ISS_FSM = ISS_REQ_IFETCH; |
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91 | IR=0; |
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92 | PC=0x00000000; |
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93 | EA=0; |
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94 | for (int i=0;i<32;i++) |
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95 | GPR[i]=0; |
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96 | } else |
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97 | { |
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98 | printf("ISS_FSM=%d\n",(int)ISS_FSM.read()); |
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99 | switch(ISS_FSM) |
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100 | { |
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101 | case ISS_REQ_IFETCH : |
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102 | if(VCI_INITIATOR.CMDACK == true) |
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103 | { |
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104 | ISS_FSM = ISS_RSP_IFETCH; |
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105 | } |
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106 | break; |
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107 | case ISS_RSP_IFETCH : |
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108 | if(VCI_INITIATOR.RSPVAL == true) |
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109 | { |
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110 | ISS_FSM = ISS_DECODE_AND_EXECUTE; |
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111 | IR = (int) VCI_INITIATOR.RDATA.read(); |
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112 | } |
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113 | break; |
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114 | case ISS_DECODE_AND_EXECUTE : |
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115 | { |
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116 | int opcod=(IR>>26)&0x3F; |
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117 | int rs,rt,rd,func,imm; |
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118 | |
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119 | switch (opcod) |
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120 | { |
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121 | case OP_ADDI: |
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122 | rs=(IR>>21)&0x1F; |
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123 | rt=(IR>>16)&0x1F; |
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124 | imm=(IR&0xFFFF); |
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125 | if (imm & 0x8000) |
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126 | imm |= 0xFFFF0000; |
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127 | |
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128 | GPR[rt]=GPR[rs] + imm; |
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129 | |
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130 | PC=PC+4; |
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131 | ISS_FSM=ISS_REQ_IFETCH; |
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132 | break; |
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133 | case OP_ORI: |
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134 | rs=(IR>>21)&0x1F; |
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135 | rt=(IR>>16)&0x1F; |
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136 | imm=(IR&0xFFFF); |
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137 | if (imm & 0x8000) |
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138 | imm |= 0xFFFF0000; |
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139 | |
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140 | GPR[rt]=GPR[rs] | imm; |
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141 | |
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142 | PC=PC+4; |
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143 | ISS_FSM=ISS_REQ_IFETCH; |
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144 | break; |
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145 | case OP_SPECIAL: |
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146 | rs=(IR>>21)&0x1F; |
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147 | rt=(IR>>16)&0x1F; |
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148 | rd=(IR>>11)&0x1F; |
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149 | func=IR&0x3F; |
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150 | switch (func) |
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151 | { |
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152 | case FUNC_ADD: |
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153 | GPR[rd]=GPR[rs] + GPR[rt]; |
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154 | break; |
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155 | case FUNC_SUB: |
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156 | GPR[rd]=GPR[rs] - GPR[rt]; |
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157 | break; |
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158 | } |
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159 | PC=PC+4; |
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160 | ISS_FSM=ISS_REQ_IFETCH; |
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161 | break; |
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162 | case OP_LW: |
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163 | rs=(IR>>21)&0x1F; |
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164 | imm=(IR&0xFFFF); |
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165 | if (imm & 0x8000) |
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166 | imm |= 0xFFFF0000; |
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167 | EA=GPR[rs]+imm; |
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168 | ISS_FSM=ISS_REQ_LOAD; |
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169 | break; |
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170 | case OP_SW: |
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171 | rs=(IR>>21)&0x1F; |
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172 | imm=(IR&0xFFFF); |
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173 | if (imm & 0x8000) |
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174 | imm |= 0xFFFF0000; |
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175 | EA=GPR[rs]+imm; |
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176 | ISS_FSM=ISS_REQ_STORE; |
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177 | break; |
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178 | } |
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179 | } |
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180 | break; |
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181 | case ISS_REQ_LOAD : |
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182 | if(VCI_INITIATOR.CMDACK == true) |
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183 | { |
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184 | ISS_FSM = ISS_RSP_LOAD; |
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185 | } |
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186 | break; |
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187 | case ISS_RSP_LOAD : |
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188 | if(VCI_INITIATOR.RSPVAL == true) |
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189 | { |
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190 | int rt; |
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191 | rt=(IR>>16)&0x1F; |
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192 | |
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193 | GPR[rt] = (int)VCI_INITIATOR.RDATA.read(); |
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194 | |
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195 | PC=PC+4; |
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196 | ISS_FSM = ISS_REQ_IFETCH; |
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197 | } |
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198 | break; |
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199 | case ISS_REQ_STORE : |
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200 | if(VCI_INITIATOR.CMDACK == true) |
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201 | { |
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202 | ISS_FSM = ISS_RSP_STORE; |
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203 | } |
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204 | break; |
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205 | case ISS_RSP_STORE : |
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206 | if(VCI_INITIATOR.RSPVAL == true) |
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207 | { |
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208 | PC=PC+4; |
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209 | ISS_FSM = ISS_REQ_IFETCH; |
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210 | } |
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211 | break; |
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212 | } |
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213 | } |
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214 | } |
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215 | |
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216 | void genMoore() |
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217 | { |
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218 | int rt; |
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219 | |
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220 | switch (ISS_FSM) |
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221 | { |
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222 | case ISS_REQ_IFETCH: |
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223 | VCI_INITIATOR.CMDVAL = true; |
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224 | VCI_INITIATOR.RSPACK = false; |
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225 | VCI_INITIATOR.ADDRESS = (sc_uint<32>) PC.read(); |
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226 | VCI_INITIATOR.WDATA = 0; |
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227 | VCI_INITIATOR.CMD = VCI_CMD_READ; |
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228 | VCI_INITIATOR.EOP = true; |
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229 | VCI_INITIATOR.BE = 0xF; |
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230 | VCI_INITIATOR.PLEN = 1 << 2; |
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231 | break; |
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232 | case ISS_RSP_IFETCH: |
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233 | VCI_INITIATOR.CMDVAL = false; |
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234 | VCI_INITIATOR.RSPACK = true; |
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235 | break; |
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236 | case ISS_REQ_LOAD: |
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237 | VCI_INITIATOR.CMDVAL = true; |
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238 | VCI_INITIATOR.RSPACK = false; |
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239 | VCI_INITIATOR.ADDRESS = (sc_uint<32>) EA.read(); |
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240 | VCI_INITIATOR.WDATA = 0; |
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241 | VCI_INITIATOR.CMD = VCI_CMD_READ; |
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242 | VCI_INITIATOR.EOP = true; |
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243 | VCI_INITIATOR.BE = 0xF; |
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244 | VCI_INITIATOR.PLEN = 1 << 2; |
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245 | break; |
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246 | case ISS_RSP_LOAD: |
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247 | VCI_INITIATOR.CMDVAL = false; |
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248 | VCI_INITIATOR.RSPACK = true; |
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249 | break; |
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250 | case ISS_REQ_STORE: |
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251 | VCI_INITIATOR.CMDVAL = true; |
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252 | VCI_INITIATOR.RSPACK = false; |
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253 | VCI_INITIATOR.ADDRESS = (sc_uint<32>) EA.read(); |
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254 | rt=(IR>>16)&0x1F; |
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255 | VCI_INITIATOR.WDATA = (sc_uint<32>) GPR[rt]; |
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256 | VCI_INITIATOR.CMD = VCI_CMD_WRITE; |
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257 | VCI_INITIATOR.EOP = true; |
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258 | VCI_INITIATOR.BE = 0xF; |
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259 | VCI_INITIATOR.PLEN = 1 << 2; |
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260 | break; |
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261 | case ISS_RSP_STORE: |
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262 | VCI_INITIATOR.CMDVAL = false; |
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263 | VCI_INITIATOR.RSPACK = true; |
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264 | break; |
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265 | } |
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266 | } |
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267 | |
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268 | }; |
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269 | |
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270 | #endif |
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271 | |
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