cours3: soclib_vci_simpleram.h

File soclib_vci_simpleram.h, 3.6 KB (added by fpecheux, 17 years ago)

Une RAM avec temps d'accès paramétrable

Line 
1#ifndef SOCLIB_VCI_SIMPLERAM_H
2#define SOCLIB_VCI_SIMPLERAM_H
3
4#define sc_register sc_signal
5
6#include <signal.h>
7#include <iostream.h>
8#include <fstream.h>
9#include <stdlib.h>
10#include <systemc.h>
11
12template <
13 int ADDRSIZE,
14 int CELLSIZE,
15 int ERRSIZE,
16 int PLENSIZE,
17 int CLENSIZE,
18 int SRCIDSIZE,
19 int TRDIDSIZE,
20 int PKTIDSIZE >
21
22struct SOCLIB_VCI_SIMPLERAM : sc_module {
23
24 sc_in<bool> CLK;
25 sc_in<bool> RESETN;
26 ADVANCED_VCI_TARGET<ADDRSIZE, CELLSIZE, ERRSIZE, PLENSIZE, CLENSIZE, SRCIDSIZE, TRDIDSIZE, PKTIDSIZE > VCI_TARGET;
27
28 const char *NAME;
29 sc_register<int> TARGET_FSM,DT,REG_EOP,WRITE_COUNTER,READ_COUNTER;
30 sc_register<int> WRITE_COUNTER_INIT,READ_COUNTER_INIT;
31 int mem[1024];
32
33 enum{
34 TARGET_IDLE = 0,
35 TARGET_WRITE_WAIT,
36 TARGET_WRITE,
37 TARGET_READ_WAIT,
38 TARGET_READ,
39 };
40
41 SC_HAS_PROCESS (SOCLIB_VCI_SIMPLERAM);
42
43SOCLIB_VCI_SIMPLERAM (
44 sc_module_name insname // nom de l'instance
45)
46{
47#ifdef NONAME_RENAME
48 TARGET_FSM.rename("TARGET_FSM");
49 DT.rename("DT");
50 REG_EOP.rename("REG_EOP");
51 WRITE_COUNTER.rename("WRITE_COUNTER");
52 WRITE_COUNTER_INIT.rename("WRITE_COUNTER_INIT");
53 READ_COUNTER.rename("READ_COUNTER");
54 READ_COUNTER_INIT.rename("READ_COUNTER_INIT");
55#endif
56
57 SC_METHOD (transition);
58 sensitive << CLK.pos();
59 SC_METHOD (genMoore);
60 sensitive << CLK.neg();
61
62 NAME = (char*) strdup(insname);
63
64 if (NAME == NULL) {
65 perror("malloc");
66 exit(1);
67 }
68 printf("SOCLIB_VCI_SIMPLERAM instanciated with name %s\n",NAME);
69
70 mem[0x00 >> 2]=0x20010010; // addi $1,$0, 0x10
71 mem[0x04 >> 2]=0x20020014; // addi $2,$0, 0x14
72 mem[0x08 >> 2]=0x8c220000; // lw $2,0($1) = 0x11223344
73 mem[0x0C >> 2]=0x8c230004; // lw $3,4($1) = 0x55667788
74 mem[0x10 >> 2]=0x11223344;
75 mem[0x14 >> 2]=0x55667788;
76 WRITE_COUNTER_INIT=3;
77 READ_COUNTER_INIT=3;
78}
79
80void transition()
81{
82 if(RESETN == false)
83 {
84 TARGET_FSM = TARGET_IDLE;
85 } else
86 {
87 switch(TARGET_FSM)
88 {
89 case TARGET_IDLE :
90 if(VCI_TARGET.CMDVAL == true)
91 {
92 REG_EOP= VCI_TARGET.EOP;
93 if (VCI_TARGET.CMD.read() == VCI_CMD_WRITE)
94 {
95 int addr=(int)VCI_TARGET.ADDRESS.read();
96 int wdata=(int)VCI_TARGET.WDATA.read();
97 mem[addr>>2]=wdata;
98 TARGET_FSM = TARGET_WRITE_WAIT;
99 WRITE_COUNTER = WRITE_COUNTER_INIT;
100 }
101 else
102 {
103 int addr=(int)VCI_TARGET.ADDRESS.read();
104 DT = mem[addr>>2];
105
106 TARGET_FSM = TARGET_READ_WAIT;
107 READ_COUNTER = READ_COUNTER_INIT;
108 }
109 }
110 break;
111 case TARGET_WRITE_WAIT :
112 WRITE_COUNTER=WRITE_COUNTER-1;
113 if (WRITE_COUNTER==1)
114 TARGET_FSM=TARGET_WRITE;
115 break;
116 case TARGET_READ_WAIT :
117 READ_COUNTER=READ_COUNTER-1;
118 if (READ_COUNTER==1)
119 TARGET_FSM=TARGET_READ;
120 break;
121 case TARGET_READ :
122 case TARGET_WRITE :
123 if(VCI_TARGET.RSPACK == true)
124 {
125 TARGET_FSM = TARGET_IDLE;
126 }
127 break;
128 } // end switch TARGET FSM
129 }
130}
131
132void genMoore()
133{
134 switch (TARGET_FSM)
135 {
136 case TARGET_IDLE:
137 VCI_TARGET.CMDACK = true;
138 VCI_TARGET.RSPVAL = false;
139 break;
140 case TARGET_WRITE_WAIT:
141 VCI_TARGET.CMDACK = false;
142 VCI_TARGET.RSPVAL = false;
143 break;
144 case TARGET_READ_WAIT:
145 VCI_TARGET.CMDACK = false;
146 VCI_TARGET.RSPVAL = false;
147 break;
148 case TARGET_WRITE:
149 VCI_TARGET.CMDACK = false;
150 VCI_TARGET.RSPVAL = true;
151 VCI_TARGET.RDATA = 0;
152 VCI_TARGET.RERROR = 0;
153 VCI_TARGET.REOP = REG_EOP;
154 break;
155 case TARGET_READ:
156 VCI_TARGET.CMDACK = false;
157 VCI_TARGET.RSPVAL = true;
158 VCI_TARGET.RDATA = (sc_uint<32>) DT;
159 VCI_TARGET.RERROR = 0;
160 VCI_TARGET.REOP = REG_EOP;
161 break;
162 }
163}
164
165};
166#endif