1 | #ifndef SOCLIB_VCI_SIMPLERAM_H |
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2 | #define SOCLIB_VCI_SIMPLERAM_H |
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3 | |
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4 | #define sc_register sc_signal |
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5 | |
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6 | #include <signal.h> |
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7 | #include <iostream.h> |
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8 | #include <fstream.h> |
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9 | #include <stdlib.h> |
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10 | #include <systemc.h> |
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11 | |
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12 | template < |
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13 | int ADDRSIZE, |
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14 | int CELLSIZE, |
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15 | int ERRSIZE, |
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16 | int PLENSIZE, |
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17 | int CLENSIZE, |
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18 | int SRCIDSIZE, |
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19 | int TRDIDSIZE, |
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20 | int PKTIDSIZE > |
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21 | |
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22 | struct SOCLIB_VCI_SIMPLERAM : sc_module { |
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23 | |
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24 | sc_in<bool> CLK; |
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25 | sc_in<bool> RESETN; |
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26 | ADVANCED_VCI_TARGET<ADDRSIZE, CELLSIZE, ERRSIZE, PLENSIZE, CLENSIZE, SRCIDSIZE, TRDIDSIZE, PKTIDSIZE > VCI_TARGET; |
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27 | |
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28 | const char *NAME; |
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29 | sc_register<int> TARGET_FSM,DT,REG_EOP,WRITE_COUNTER,READ_COUNTER; |
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30 | sc_register<int> WRITE_COUNTER_INIT,READ_COUNTER_INIT; |
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31 | int mem[1024]; |
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32 | |
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33 | enum{ |
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34 | TARGET_IDLE = 0, |
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35 | TARGET_WRITE_WAIT, |
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36 | TARGET_WRITE, |
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37 | TARGET_READ_WAIT, |
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38 | TARGET_READ, |
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39 | }; |
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40 | |
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41 | SC_HAS_PROCESS (SOCLIB_VCI_SIMPLERAM); |
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42 | |
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43 | SOCLIB_VCI_SIMPLERAM ( |
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44 | sc_module_name insname // nom de l'instance |
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45 | ) |
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46 | { |
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47 | #ifdef NONAME_RENAME |
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48 | TARGET_FSM.rename("TARGET_FSM"); |
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49 | DT.rename("DT"); |
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50 | REG_EOP.rename("REG_EOP"); |
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51 | WRITE_COUNTER.rename("WRITE_COUNTER"); |
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52 | WRITE_COUNTER_INIT.rename("WRITE_COUNTER_INIT"); |
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53 | READ_COUNTER.rename("READ_COUNTER"); |
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54 | READ_COUNTER_INIT.rename("READ_COUNTER_INIT"); |
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55 | #endif |
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56 | |
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57 | SC_METHOD (transition); |
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58 | sensitive << CLK.pos(); |
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59 | SC_METHOD (genMoore); |
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60 | sensitive << CLK.neg(); |
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61 | |
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62 | NAME = (char*) strdup(insname); |
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63 | |
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64 | if (NAME == NULL) { |
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65 | perror("malloc"); |
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66 | exit(1); |
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67 | } |
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68 | printf("SOCLIB_VCI_SIMPLERAM instanciated with name %s\n",NAME); |
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69 | |
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70 | mem[0x00 >> 2]=0x20010010; // addi $1,$0, 0x10 |
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71 | mem[0x04 >> 2]=0x20020014; // addi $2,$0, 0x14 |
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72 | mem[0x08 >> 2]=0x8c220000; // lw $2,0($1) = 0x11223344 |
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73 | mem[0x0C >> 2]=0x8c230004; // lw $3,4($1) = 0x55667788 |
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74 | mem[0x10 >> 2]=0x11223344; |
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75 | mem[0x14 >> 2]=0x55667788; |
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76 | WRITE_COUNTER_INIT=3; |
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77 | READ_COUNTER_INIT=3; |
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78 | } |
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79 | |
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80 | void transition() |
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81 | { |
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82 | if(RESETN == false) |
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83 | { |
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84 | TARGET_FSM = TARGET_IDLE; |
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85 | } else |
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86 | { |
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87 | switch(TARGET_FSM) |
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88 | { |
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89 | case TARGET_IDLE : |
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90 | if(VCI_TARGET.CMDVAL == true) |
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91 | { |
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92 | REG_EOP= VCI_TARGET.EOP; |
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93 | if (VCI_TARGET.CMD.read() == VCI_CMD_WRITE) |
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94 | { |
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95 | int addr=(int)VCI_TARGET.ADDRESS.read(); |
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96 | int wdata=(int)VCI_TARGET.WDATA.read(); |
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97 | mem[addr>>2]=wdata; |
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98 | TARGET_FSM = TARGET_WRITE_WAIT; |
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99 | WRITE_COUNTER = WRITE_COUNTER_INIT; |
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100 | } |
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101 | else |
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102 | { |
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103 | int addr=(int)VCI_TARGET.ADDRESS.read(); |
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104 | DT = mem[addr>>2]; |
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105 | |
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106 | TARGET_FSM = TARGET_READ_WAIT; |
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107 | READ_COUNTER = READ_COUNTER_INIT; |
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108 | } |
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109 | } |
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110 | break; |
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111 | case TARGET_WRITE_WAIT : |
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112 | WRITE_COUNTER=WRITE_COUNTER-1; |
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113 | if (WRITE_COUNTER==1) |
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114 | TARGET_FSM=TARGET_WRITE; |
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115 | break; |
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116 | case TARGET_READ_WAIT : |
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117 | READ_COUNTER=READ_COUNTER-1; |
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118 | if (READ_COUNTER==1) |
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119 | TARGET_FSM=TARGET_READ; |
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120 | break; |
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121 | case TARGET_READ : |
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122 | case TARGET_WRITE : |
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123 | if(VCI_TARGET.RSPACK == true) |
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124 | { |
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125 | TARGET_FSM = TARGET_IDLE; |
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126 | } |
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127 | break; |
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128 | } // end switch TARGET FSM |
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129 | } |
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130 | } |
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131 | |
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132 | void genMoore() |
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133 | { |
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134 | switch (TARGET_FSM) |
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135 | { |
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136 | case TARGET_IDLE: |
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137 | VCI_TARGET.CMDACK = true; |
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138 | VCI_TARGET.RSPVAL = false; |
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139 | break; |
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140 | case TARGET_WRITE_WAIT: |
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141 | VCI_TARGET.CMDACK = false; |
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142 | VCI_TARGET.RSPVAL = false; |
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143 | break; |
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144 | case TARGET_READ_WAIT: |
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145 | VCI_TARGET.CMDACK = false; |
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146 | VCI_TARGET.RSPVAL = false; |
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147 | break; |
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148 | case TARGET_WRITE: |
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149 | VCI_TARGET.CMDACK = false; |
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150 | VCI_TARGET.RSPVAL = true; |
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151 | VCI_TARGET.RDATA = 0; |
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152 | VCI_TARGET.RERROR = 0; |
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153 | VCI_TARGET.REOP = REG_EOP; |
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154 | break; |
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155 | case TARGET_READ: |
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156 | VCI_TARGET.CMDACK = false; |
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157 | VCI_TARGET.RSPVAL = true; |
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158 | VCI_TARGET.RDATA = (sc_uint<32>) DT; |
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159 | VCI_TARGET.RERROR = 0; |
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160 | VCI_TARGET.REOP = REG_EOP; |
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161 | break; |
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162 | } |
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163 | } |
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164 | |
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165 | }; |
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166 | #endif |
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