cours3: system.cpp

File system.cpp, 2.6 KB (added by fpecheux, 17 years ago)

La topcell du système MIPS avec simpleram

Line 
1// Step 1.1: C/C++ mandatory includes
2
3#include <stdio.h>
4#include <stdarg.h>
5#include <stdlib.h>
6#include <signal.h>
7
8// Step 1.2: Soclib includes
9
10#include "shared/soclib_mapping_table.h"
11#include "shared/soclib_vci_interfaces.h"
12#include "soclib_vci_simpleram.h"
13#include "soclib_vci_iss.h"
14
15// Step 1.3: Address space segmemtation include
16
17// Step 2.1: Defining VCI parameters and address decoding bits
18
19#define CELLSIZE 4 // Data are 4 cells(=8bits) wide=32 bits
20#define ERRSIZE 1 // Error size is 1 bit
21#define PLENSIZE 1 //
22#define CLENSIZE 1 //
23#define TRDIDSIZE 1 // TRDID unused
24#define PKTIDSIZE 1 // PKTID unused too
25
26// Step 2.2: Defining system parameters for decoding and memory mapping
27
28#define ADDRSIZE 32
29#define SRCIDSIZE 8
30
31#define SEGTYPEMASK 0x00300000
32
33// Step 3: Defining custom values for system parameterization
34
35// Step 5: the sc_main function
36////////////////////////////////////////////////////
37// MAIN
38////////////////////////////////////////////////////
39
40int sc_main (int argc, char *argv[])
41{
42// Step 5.1: Creating the segment table
43////////////////////////////////////////////////////
44// SEGMENT_TABLE DEFINITION
45////////////////////////////////////////////////////
46
47// Step 5.1: Declaring all the toplevel signals
48///////////////////////////////////////////////////////
49// SIGNALS DECLARATION
50//////////////////////////////////////////////////////
51
52 sc_clock signal_clk ("signal_clk");
53 sc_signal < bool > signal_resetn ("signal_resetn");
54
55 ADVANCED_VCI_SIGNALS <VCI_PARAM> link ("link");
56
57// Step 5.2: Instanciating the system components
58/////////////////////////////////////////////////////////
59// INSTANCIATED COMPONENTS
60/////////////////////////////////////////////////////////
61
62 SOCLIB_VCI_ISS < VCI_PARAM > i0 ("i0");
63 SOCLIB_VCI_SIMPLERAM < VCI_PARAM > t0 ("t0");
64
65// Step 5.3: Initializing the system memories with appropriate code and data
66//////////////////////////////////////////////////////////
67// Segments Initialisation
68//////////////////////////////////////////////////////////
69
70// Step 5.4: Building the toplevel netlist
71//////////////////////////////////////////////////////////
72// Net-List
73//////////////////////////////////////////////////////////
74
75 i0.CLK(signal_clk);
76 i0.RESETN(signal_resetn);
77 i0.VCI_INITIATOR(link);
78
79 t0.CLK(signal_clk);
80 t0.RESETN(signal_resetn);
81 t0.VCI_TARGET(link);
82
83 sc_start(sc_core::sc_time(0, SC_NS));
84 signal_resetn = false;
85 sc_start(sc_core::sc_time(1, SC_NS));
86 signal_resetn = true;
87
88 sc_start();
89 return EXIT_SUCCESS;
90};