cours5: node.h

File node.h, 7.4 KB (added by fpecheux, 16 years ago)

Un noeud du réseau

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1
2/*
3 * SOCLIB_LGPL_HEADER_BEGIN
4 *
5 * This file is part of SoCLib, GNU LGPLv2.1.
6 *
7 * SoCLib is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU Lesser General Public License as published
9 * by the Free Software Foundation; version 2.1 of the License.
10 *
11 * SoCLib is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with SoCLib; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * SOCLIB_LGPL_HEADER_END
22 *
23 * Copyright (c) UPMC, Lip6, SoC
24 */
25
26#ifndef _NODE_H
27#define _NODE_H
28
29#include <iostream>
30#include <cstdlib>
31
32#include "mapping_table.h"
33#include "mips32.h"
34#include "vci_xcache_wrapper.h"
35#include "vci_ram.h"
36#include "vci_multi_tty.h"
37#include "vci_uart.h"
38#include "vci_timer.h"
39#include "vci_icu.h"
40#include "vci_vgmn.h"
41#include "../segmentation.h"
42
43SC_MODULE(node)
44{
45 sc_core::sc_in<bool> p_clk;
46 sc_core::sc_in<bool> p_resetn;
47 sc_core::sc_out<bool> p_tx;
48 sc_core::sc_in<bool> p_rx;
49 sc_core::sc_out<bool> p_tx_en;
50 sc_core::sc_out<bool> p_rx_en;
51
52 uint32_t m_ident;
53
54 node(sc_core::sc_module_name nm, int ident, char *softname)
55 : sc_core::sc_module(nm),
56 m_ident(ident)
57 {
58 using namespace sc_core;
59 using soclib::common::IntTab;
60 using soclib::common::Segment;
61
62 ////////////////////////////////////////////////////////////////////
63 // Part 2 : Mapping table //
64 ////////////////////////////////////////////////////////////////////
65
66 soclib::common::MappingTable *maptab;
67 maptab = new soclib::common::MappingTable(32, IntTab(8), IntTab(8), 0x00300000);
68
69 maptab->add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), true));
70 maptab->add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), true));
71 maptab->add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), true));
72 maptab->add(Segment("data" , DATA_BASE , DATA_SIZE , IntTab(0), true));
73
74 maptab->add(Segment("tty" , TTY_BASE , TTY_SIZE , IntTab(1), false));
75 maptab->add(Segment("uart" , UART_BASE , UART_SIZE , IntTab(2), false));
76 maptab->add(Segment("timer" , TIMER_BASE , TIMER_SIZE , IntTab(3), false));
77 maptab->add(Segment("icu" , ICU_BASE , ICU_SIZE , IntTab(4), false));
78
79 // Define our VCI parameters
80 typedef soclib::caba::VciParams<4,6,32,1,1,1,8,1,1,1> vci_param;
81
82 ////////////////////////////////////////////////////////////////////
83 // Part 3 : Signals declaration //
84 ////////////////////////////////////////////////////////////////////
85
86 sc_core::sc_signal<bool> *s_mips_it0;
87 sc_core::sc_signal<bool> *s_mips_it1;
88 sc_core::sc_signal<bool> *s_mips_it2;
89 sc_core::sc_signal<bool> *s_mips_it3;
90 sc_core::sc_signal<bool> *s_mips_it4;
91 sc_core::sc_signal<bool> *s_mips_it5;
92 sc_core::sc_signal<bool> *s_tty_irq;
93 sc_core::sc_signal<bool> *s_uart_irq;
94 sc_core::sc_signal<bool> *s_timer_irq;
95 soclib::caba::VciSignals<vci_param> *s_m;
96 soclib::caba::VciSignals<vci_param> *s_ram;
97 soclib::caba::VciSignals<vci_param> *s_tty;
98 soclib::caba::VciSignals<vci_param> *s_uart;
99 soclib::caba::VciSignals<vci_param> *s_timer;
100 soclib::caba::VciSignals<vci_param> *s_icu;
101 soclib::caba::VciSignals<vci_param> *s_sensor;
102
103 s_mips_it0 = new sc_core::sc_signal<bool> ("s_mips_it0");
104 s_mips_it1 = new sc_core::sc_signal<bool> ("s_mips_it1");
105 s_mips_it2 = new sc_core::sc_signal<bool> ("s_mips_it2");
106 s_mips_it3 = new sc_core::sc_signal<bool> ("s_mips_it3");
107 s_mips_it4 = new sc_core::sc_signal<bool> ("s_mips_it4");
108 s_mips_it5 = new sc_core::sc_signal<bool> ("s_mips_it5");
109
110 s_tty_irq = new sc_core::sc_signal<bool> ("s_tty_irq");
111 s_uart_irq = new sc_core::sc_signal<bool> ("s_uart_irq");
112 s_timer_irq = new sc_core::sc_signal<bool> ("s_timer_irq");
113 s_m = new soclib::caba::VciSignals<vci_param> ("s_m");
114 s_ram = new soclib::caba::VciSignals<vci_param> ("s_ram");
115 s_tty = new soclib::caba::VciSignals<vci_param> ("s_tty");
116 s_uart = new soclib::caba::VciSignals<vci_param> ("s_uart");
117 s_timer = new soclib::caba::VciSignals<vci_param> ("s_timer");
118 s_icu = new soclib::caba::VciSignals<vci_param> ("s_icu");
119
120 ////////////////////////////////////////////////////////////////////
121 // Part 4 : instances //
122 ////////////////////////////////////////////////////////////////////
123
124 soclib::caba::VciXcacheWrapper<vci_param, soclib::common::Mips32ElIss > *cache;
125 soclib::common::Loader *loader;
126 soclib::caba::VciRam<vci_param> *ram;
127 soclib::caba::VciMultiTty<vci_param> *tty;
128 soclib::caba::VciUart<vci_param> *uart;
129 soclib::caba::VciTimer<vci_param> *timer;
130 soclib::caba::VciIcu<vci_param> *icu;
131 soclib::caba::VciVgmn<vci_param> *vgmn;
132
133 cache = new soclib::caba::VciXcacheWrapper<vci_param, soclib::common::Mips32ElIss >
134 ("cache",0 , *maptab,IntTab(0), 4,1,8, 4,1,8);
135 loader = new soclib::common::Loader(softname);
136 ram = new soclib::caba::VciRam<vci_param>("ram", IntTab(0), *maptab, *loader);
137 char ttyname[20];
138 sprintf(ttyname,"tty%d",m_ident);
139 tty = new soclib::caba::VciMultiTty<vci_param> ("tty",IntTab(1), *maptab, ttyname, NULL);
140 uart = new soclib::caba::VciUart<vci_param>("uart",IntTab(2), *maptab,false,m_ident);
141 timer = new soclib::caba::VciTimer<vci_param>("timer", IntTab(3), *maptab, 1);
142 icu = new soclib::caba::VciIcu<vci_param>("icu",IntTab(4), *maptab,2);
143 vgmn = new soclib::caba::VciVgmn<vci_param>("vgmn",*maptab, 1, 5, 2, 8);
144
145 ////////////////////////////////////////////////////////////////////
146 // Part 5 : netlist //
147 ////////////////////////////////////////////////////////////////////
148
149 cache->p_clk(p_clk);
150 cache->p_resetn(p_resetn);
151 cache->p_irq[0](*s_mips_it0);
152 cache->p_irq[1](*s_mips_it1);
153 cache->p_irq[2](*s_mips_it2);
154 cache->p_irq[3](*s_mips_it3);
155 cache->p_irq[4](*s_mips_it4);
156 cache->p_irq[5](*s_mips_it5);
157 cache->p_vci(*s_m);
158
159 ram->p_clk(p_clk);
160 ram->p_resetn(p_resetn);
161 ram->p_vci(*s_ram);
162
163 tty->p_clk(p_clk);
164 tty->p_resetn(p_resetn);
165 tty->p_irq[0](*s_tty_irq);
166 tty->p_vci(*s_tty);
167
168 uart->p_clk(p_clk);
169 uart->p_resetn(p_resetn);
170 uart->p_irq(*s_uart_irq);
171 uart->p_vci(*s_uart);
172 uart->p_tx(p_tx);
173 uart->p_rx(p_rx);
174 uart->p_tx_en(p_tx_en);
175 uart->p_rx_en(p_rx_en);
176
177 timer->p_clk(p_clk);
178 timer->p_resetn(p_resetn);
179 timer->p_vci(*s_timer);
180 timer->p_irq[0](*s_timer_irq);
181
182 icu->p_clk(p_clk);
183 icu->p_resetn(p_resetn);
184 icu->p_vci(*s_icu);
185 icu->p_irq_in[0](*s_uart_irq);
186 icu->p_irq_in[1](*s_timer_irq);
187 icu->p_irq(*s_mips_it0);
188
189 vgmn->p_clk(p_clk);
190 vgmn->p_resetn(p_resetn);
191 vgmn->p_to_initiator[0](*s_m);
192 vgmn->p_to_target[0](*s_ram);
193 vgmn->p_to_target[1](*s_tty);
194 vgmn->p_to_target[2](*s_uart);
195 vgmn->p_to_target[3](*s_timer);
196 vgmn->p_to_target[4](*s_icu);
197 }
198};
199#endif
200