ToolsCourseTp3: am2901_ctl.vbe

File am2901_ctl.vbe, 3.0 KB (added by cobell, 16 years ago)
Line 
1ENTITY  am2901_ctl  IS
2
3PORT(
4    -- Input/Output from and to the data-path.
5
6    -- Command for selecting operands R and S.
7    ops_mx : out BIT_VECTOR(2 downto 0);
8    opr_mx : out BIT_VECTOR(1 downto 0);
9   
10    -- ALU commands and auxiliary terminals.
11    alu_k    : out BIT_VECTOR(4 downto 0);
12    alu_cout : in BIT;
13    alu_over : in BIT;
14   
15    -- RAM, ACCU shifter commands and auxiliary terminals.
16    -- ("acc_sh" is same as "ram_sh")
17    ram_sh : out BIT_VECTOR(1 downto 0);
18   
19    -- Output multiplexer commnand (for X bus).
20    out_mx : out BIT;
21   
22    -- ACCU controls terminals.
23    -- ("acc_ck" directly comes from the plots)
24    acc_wen : out BIT;
25   
26    -- Data bus terminals.
27    alu_f  : in BIT_VECTOR(3 downto 0);
28    alu_np : in BIT_VECTOR(3 downto 0);
29    alu_ng : in BIT_VECTOR(3 downto 0);
30   
31    -- Input/Output from and to the plots.
32   
33    -- ALU terminals from/to plots.
34    -- core_ncout :   out BIT;
35    core_np   : out BIT;
36    core_ng   : out BIT;
37    core_over : out BIT;
38    core_zero : out BIT;
39   
40    -- RAM, ACCU shifter terminals from/to plots.
41    -- RAM and ACCU I/O plots controls.
42    core_sh_right : out BIT;
43    core_sh_left  : out BIT;
44   
45    -- Data bus terminals from/to the plots.
46    i : in BIT_VECTOR(8 downto 0);
47   
48    noe : in  BIT;
49    oe  : out BIT;
50   
51    -- +
52    a : in BIT_VECTOR(3 downto 0);
53    b : in BIT_VECTOR(3 downto 0);
54   
55    deca  : out BIT_VECTOR(15 downto 0);
56    decb  : out BIT_VECTOR(15 downto 0);
57    decwb : out BIT_VECTOR(15 downto 0);
58   
59    -- Power supply connectors.
60    vdd : in    BIT;
61    vss : in    BIT
62   
63    );
64
65END am2901_ctl;
66 
67
68ARCHITECTURE  behavior_data_flow  OF  am2901_ctl  IS
69
70    -- Internals bus.
71    SIGNAL alu_p : BIT_VECTOR(3 downto 0);
72    SIGNAL alu_g : BIT_VECTOR(3 downto 0);
73    -- Internals signals.
74    SIGNAL ram_wri : BIT;
75    SIGNAL interm : BIT_VECTOR (15 downto 0);
76
77BEGIN
78
79    -- *************** ACCU and RAM multiplexer control **************
80       
81    -- Completer
82   
83    -- ******************** S multiplexer control ********************
84   
85    -- Completer
86   
87    -- ******************** R multiplexer control ********************
88   
89    -- Completer
90   
91    -- ******************** X multiplexer control ********************
92       
93    -- Completer
94   
95    -- ************************* ALU control *************************
96   
97    -- ** ALU commands **
98   
99    -- Completer
100   
101    -- ** Compute of ALU flags **
102    -- * Propagate *
103   
104    -- Completer   
105   
106    -- * Generate *
107   
108    -- Completer
109   
110    -- * Zero and Overflow *
111   
112    -- Completer
113   
114    -- ************************* ACCU control ************************
115   
116    -- Compute of ACCU write enable.
117   
118    -- Completer
119   
120    -- ************************** RAM control ************************
121   
122    -- ** Compute of RAM write enable **
123   
124    -- Completer
125   
126    -- ** RAM and ACCU I/O plots controls **
127   
128    -- Completer
129   
130    -- ** RAM shifter I/O **
131   
132    -- Completer
133   
134    -- +
135   
136    -- Completer
137
138END  behavior_data_flow;