1 | ENTITY am2901_ctl IS |
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2 | |
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3 | PORT( |
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4 | -- Input/Output from and to the data-path. |
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5 | |
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6 | -- Command for selecting operands R and S. |
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7 | ops_mx : out BIT_VECTOR(2 downto 0); |
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8 | opr_mx : out BIT_VECTOR(1 downto 0); |
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9 | |
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10 | -- ALU commands and auxiliary terminals. |
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11 | alu_k : out BIT_VECTOR(4 downto 0); |
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12 | alu_cout : in BIT; |
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13 | alu_over : in BIT; |
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14 | |
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15 | -- RAM, ACCU shifter commands and auxiliary terminals. |
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16 | -- ("acc_sh" is same as "ram_sh") |
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17 | ram_sh : out BIT_VECTOR(1 downto 0); |
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18 | |
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19 | -- Output multiplexer commnand (for X bus). |
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20 | out_mx : out BIT; |
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21 | |
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22 | -- ACCU controls terminals. |
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23 | -- ("acc_ck" directly comes from the plots) |
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24 | acc_wen : out BIT; |
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25 | |
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26 | -- Data bus terminals. |
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27 | alu_f : in BIT_VECTOR(3 downto 0); |
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28 | alu_np : in BIT_VECTOR(3 downto 0); |
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29 | alu_ng : in BIT_VECTOR(3 downto 0); |
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30 | |
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31 | -- Input/Output from and to the plots. |
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32 | |
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33 | -- ALU terminals from/to plots. |
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34 | -- core_ncout : out BIT; |
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35 | core_np : out BIT; |
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36 | core_ng : out BIT; |
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37 | core_over : out BIT; |
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38 | core_zero : out BIT; |
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39 | |
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40 | -- RAM, ACCU shifter terminals from/to plots. |
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41 | -- RAM and ACCU I/O plots controls. |
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42 | core_sh_right : out BIT; |
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43 | core_sh_left : out BIT; |
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44 | |
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45 | -- Data bus terminals from/to the plots. |
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46 | i : in BIT_VECTOR(8 downto 0); |
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47 | |
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48 | noe : in BIT; |
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49 | oe : out BIT; |
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50 | |
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51 | -- + |
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52 | a : in BIT_VECTOR(3 downto 0); |
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53 | b : in BIT_VECTOR(3 downto 0); |
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54 | |
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55 | deca : out BIT_VECTOR(15 downto 0); |
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56 | decb : out BIT_VECTOR(15 downto 0); |
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57 | decwb : out BIT_VECTOR(15 downto 0); |
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58 | |
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59 | -- Power supply connectors. |
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60 | vdd : in BIT; |
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61 | vss : in BIT |
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62 | |
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63 | ); |
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64 | |
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65 | END am2901_ctl; |
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66 | |
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67 | |
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68 | ARCHITECTURE behavior_data_flow OF am2901_ctl IS |
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69 | |
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70 | -- Internals bus. |
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71 | SIGNAL alu_p : BIT_VECTOR(3 downto 0); |
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72 | SIGNAL alu_g : BIT_VECTOR(3 downto 0); |
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73 | -- Internals signals. |
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74 | SIGNAL ram_wri : BIT; |
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75 | SIGNAL interm : BIT_VECTOR (15 downto 0); |
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76 | |
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77 | BEGIN |
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78 | |
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79 | -- *************** ACCU and RAM multiplexer control ************** |
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80 | |
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81 | -- Completer |
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82 | |
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83 | -- ******************** S multiplexer control ******************** |
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84 | |
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85 | -- Completer |
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86 | |
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87 | -- ******************** R multiplexer control ******************** |
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88 | |
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89 | -- Completer |
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90 | |
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91 | -- ******************** X multiplexer control ******************** |
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92 | |
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93 | -- Completer |
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94 | |
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95 | -- ************************* ALU control ************************* |
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96 | |
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97 | -- ** ALU commands ** |
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98 | |
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99 | -- Completer |
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100 | |
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101 | -- ** Compute of ALU flags ** |
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102 | -- * Propagate * |
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103 | |
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104 | -- Completer |
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105 | |
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106 | -- * Generate * |
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107 | |
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108 | -- Completer |
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109 | |
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110 | -- * Zero and Overflow * |
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111 | |
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112 | -- Completer |
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113 | |
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114 | -- ************************* ACCU control ************************ |
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115 | |
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116 | -- Compute of ACCU write enable. |
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117 | |
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118 | -- Completer |
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119 | |
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120 | -- ************************** RAM control ************************ |
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121 | |
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122 | -- ** Compute of RAM write enable ** |
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123 | |
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124 | -- Completer |
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125 | |
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126 | -- ** RAM and ACCU I/O plots controls ** |
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127 | |
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128 | -- Completer |
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129 | |
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130 | -- ** RAM shifter I/O ** |
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131 | |
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132 | -- Completer |
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133 | |
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134 | -- + |
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135 | |
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136 | -- Completer |
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137 | |
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138 | END behavior_data_flow; |
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