ToolsCourseTp3: am2901_dpt.vbe

File am2901_dpt.vbe, 22.2 KB (added by cobell, 18 years ago)
Line 
1ENTITY am2901_dpt IS
2
3PORT(
4 -- Command for selecting operands R and S.
5 ops_mx : in BIT_VECTOR(2 downto 0);
6 opr_mx : in BIT_VECTOR(1 downto 0);
7
8 -- ALU commands and auxiliary terminals.
9 alu_k : in BIT_VECTOR(4 downto 0);
10 alu_cin : in BIT;
11 alu_cout : out BIT;
12 alu_over : inout BIT;
13
14 -- RAM, ACCU shifter commands and auxiliary terminals.
15 ram_sh : in BIT_VECTOR(1 downto 0);
16 acc_sh : in BIT_VECTOR(1 downto 0);
17 -- RAM shifter inputs.
18 ram_i_up : in BIT;
19 ram_i_down : in BIT;
20 -- ACCU shifter inputs.
21 acc_i_up : in BIT;
22 acc_i_down : in BIT;
23 -- ACCU shifter outputs ("acc_scout" is "acc_q_up").
24 acc_q_up : out BIT;
25 acc_q_down : out BIT;
26
27 -- Output multiplexer commnand (for X bus).
28 out_mx : in BIT;
29
30 -- ACCU controls terminals.
31 acc_ck : in BIT;
32 acc_wen : in BIT;
33
34 -- Register file controls terminals.
35 ram_ck : in BIT_VECTOR(15 downto 0) ; -- Register clocks (ck).
36 b_w : in BIT_VECTOR(15 downto 0) ; -- Write enable
37 a : in BIT_VECTOR(15 downto 0) ; -- Register A address.
38 b : in BIT_VECTOR(15 downto 0) ; -- Register B address.
39
40 -- Data buses terminals.
41 opr_d : in BIT_VECTOR(3 downto 0);
42 alu_f : inout BIT_VECTOR(3 downto 0);
43 alu_np : out BIT_VECTOR(3 downto 0);
44 alu_ng : out BIT_VECTOR(3 downto 0);
45 out_x : out BIT_VECTOR(3 downto 0);
46
47 -- Power supply connectors.
48 vdd : in BIT;
49 vss : in BIT
50 );
51
52END am2901_dpt;
53
54
55ARCHITECTURE behavior_data_flow OF am2901_dpt IS
56
57 -- Internals bus.
58 SIGNAL ops_ns : BIT_VECTOR(3 downto 0);
59 SIGNAL opr_nr : BIT_VECTOR(3 downto 0);
60 SIGNAL ram_d : BIT_VECTOR(3 downto 0);
61 SIGNAL acc_d : BIT_VECTOR(3 downto 0);
62
63 -- Internal registers.
64 -- ACCU master/slave.
65 SIGNAL acc_s_q : REG_VECTOR(3 downto 0) REGISTER;
66 SIGNAL acc_m_q : REG_VECTOR(3 downto 0) REGISTER;
67 -- Internal ACCU clock signals.
68 SIGNAL acc_ws : BIT;
69 -- RAM SIGNALS
70 SIGNAL ram_adra : BIT_VECTOR(15 DOWNTO 0);
71 SIGNAL ram_adrb : BIT_VECTOR(15 DOWNTO 0);
72 -- RAM masters.
73 SIGNAL ram_m_r0 : REG_VECTOR(3 downto 0) REGISTER;
74 SIGNAL ram_m_r1 : REG_VECTOR(3 downto 0) REGISTER;
75 SIGNAL ram_m_r2 : REG_VECTOR(3 downto 0) REGISTER;
76 SIGNAL ram_m_r3 : REG_VECTOR(3 downto 0) REGISTER;
77 SIGNAL ram_m_r4 : REG_VECTOR(3 downto 0) REGISTER;
78 SIGNAL ram_m_r5 : REG_VECTOR(3 downto 0) REGISTER;
79 SIGNAL ram_m_r6 : REG_VECTOR(3 downto 0) REGISTER;
80 SIGNAL ram_m_r7 : REG_VECTOR(3 downto 0) REGISTER;
81 SIGNAL ram_m_r8 : REG_VECTOR(3 downto 0) REGISTER;
82 SIGNAL ram_m_r9 : REG_VECTOR(3 downto 0) REGISTER;
83 SIGNAL ram_m_r10 : REG_VECTOR(3 downto 0) REGISTER;
84 SIGNAL ram_m_r11 : REG_VECTOR(3 downto 0) REGISTER;
85 SIGNAL ram_m_r12 : REG_VECTOR(3 downto 0) REGISTER;
86 SIGNAL ram_m_r13 : REG_VECTOR(3 downto 0) REGISTER;
87 SIGNAL ram_m_r14 : REG_VECTOR(3 downto 0) REGISTER;
88 SIGNAL ram_m_r15 : REG_VECTOR(3 downto 0) REGISTER;
89 -- RAM slaves.
90 SIGNAL ram_s_r0 : REG_VECTOR(3 downto 0) REGISTER;
91 SIGNAL ram_s_r1 : REG_VECTOR(3 downto 0) REGISTER;
92 SIGNAL ram_s_r2 : REG_VECTOR(3 downto 0) REGISTER;
93 SIGNAL ram_s_r3 : REG_VECTOR(3 downto 0) REGISTER;
94 SIGNAL ram_s_r4 : REG_VECTOR(3 downto 0) REGISTER;
95 SIGNAL ram_s_r5 : REG_VECTOR(3 downto 0) REGISTER;
96 SIGNAL ram_s_r6 : REG_VECTOR(3 downto 0) REGISTER;
97 SIGNAL ram_s_r7 : REG_VECTOR(3 downto 0) REGISTER;
98 SIGNAL ram_s_r8 : REG_VECTOR(3 downto 0) REGISTER;
99 SIGNAL ram_s_r9 : REG_VECTOR(3 downto 0) REGISTER;
100 SIGNAL ram_s_r10 : REG_VECTOR(3 downto 0) REGISTER;
101 SIGNAL ram_s_r11 : REG_VECTOR(3 downto 0) REGISTER;
102 SIGNAL ram_s_r12 : REG_VECTOR(3 downto 0) REGISTER;
103 SIGNAL ram_s_r13 : REG_VECTOR(3 downto 0) REGISTER;
104 SIGNAL ram_s_r14 : REG_VECTOR(3 downto 0) REGISTER;
105 SIGNAL ram_s_r15 : REG_VECTOR(3 downto 0) REGISTER;
106 -- Internal RAM clocks signals.
107 -- Masters write enable.
108 SIGNAL ram_wmd0 :BIT;
109 SIGNAL ram_wmd1 :BIT;
110 SIGNAL ram_wmd2 :BIT;
111 SIGNAL ram_wmd3 :BIT;
112 SIGNAL ram_wmd4 :BIT;
113 SIGNAL ram_wmd5 :BIT;
114 SIGNAL ram_wmd6 :BIT;
115 SIGNAL ram_wmd7 :BIT;
116 SIGNAL ram_wmd8 :BIT;
117 SIGNAL ram_wmd9 :BIT;
118 SIGNAL ram_wmd10 :BIT;
119 SIGNAL ram_wmd11 :BIT;
120 SIGNAL ram_wmd12 :BIT;
121 SIGNAL ram_wmd13 :BIT;
122 SIGNAL ram_wmd14 :BIT;
123 SIGNAL ram_wmd15 :BIT;
124 -- Slaves write enable.
125 SIGNAL ram_ws0 :BIT;
126 SIGNAL ram_ws1 :BIT;
127 SIGNAL ram_ws2 :BIT;
128 SIGNAL ram_ws3 :BIT;
129 SIGNAL ram_ws4 :BIT;
130 SIGNAL ram_ws5 :BIT;
131 SIGNAL ram_ws6 :BIT;
132 SIGNAL ram_ws7 :BIT;
133 SIGNAL ram_ws8 :BIT;
134 SIGNAL ram_ws9 :BIT;
135 SIGNAL ram_ws10 :BIT;
136 SIGNAL ram_ws11 :BIT;
137 SIGNAL ram_ws12 :BIT;
138 SIGNAL ram_ws13 :BIT;
139 SIGNAL ram_ws14 :BIT;
140 SIGNAL ram_ws15 :BIT;
141 -- Output mux bus RA and RB.
142 SIGNAL ram_ra : MUX_VECTOR(3 downto 0) BUS;
143 SIGNAL ram_rb : MUX_VECTOR(3 downto 0) BUS;
144 -- Internal ALU signals.
145 SIGNAL alu_cry : BIT_VECTOR(4 downto 0);
146 SIGNAL alu_s : BIT_VECTOR(3 downto 0);
147 SIGNAL alu_r : BIT_VECTOR(3 downto 0);
148
149
150
151 SIGNAL sig_acc : BIT_VECTOR(3 downto 0);
152
153 SIGNAL sig_ram0 : BIT_VECTOR(3 downto 0);
154 SIGNAL sig_ram1 : BIT_VECTOR(3 downto 0);
155 SIGNAL sig_ram2 : BIT_VECTOR(3 downto 0);
156 SIGNAL sig_ram3 : BIT_VECTOR(3 downto 0);
157 SIGNAL sig_ram4 : BIT_VECTOR(3 downto 0);
158 SIGNAL sig_ram5 : BIT_VECTOR(3 downto 0);
159 SIGNAL sig_ram6 : BIT_VECTOR(3 downto 0);
160 SIGNAL sig_ram7 : BIT_VECTOR(3 downto 0);
161 SIGNAL sig_ram8 : BIT_VECTOR(3 downto 0);
162 SIGNAL sig_ram9 : BIT_VECTOR(3 downto 0);
163 SIGNAL sig_ram10 : BIT_VECTOR(3 downto 0);
164 SIGNAL sig_ram11 : BIT_VECTOR(3 downto 0);
165 SIGNAL sig_ram12 : BIT_VECTOR(3 downto 0);
166 SIGNAL sig_ram13 : BIT_VECTOR(3 downto 0);
167 SIGNAL sig_ram14 : BIT_VECTOR(3 downto 0);
168 SIGNAL sig_ram15 : BIT_VECTOR(3 downto 0);
169
170 SIGNAL ram_ck0 :BIT;
171 SIGNAL ram_ck1 :BIT;
172 SIGNAL ram_ck2 :BIT;
173 SIGNAL ram_ck3 :BIT;
174 SIGNAL ram_ck4 :BIT;
175 SIGNAL ram_ck5 :BIT;
176 SIGNAL ram_ck6 :BIT;
177 SIGNAL ram_ck7 :BIT;
178 SIGNAL ram_ck8 :BIT;
179 SIGNAL ram_ck9 :BIT;
180 SIGNAL ram_ck10 :BIT;
181 SIGNAL ram_ck11 :BIT;
182 SIGNAL ram_ck12 :BIT;
183 SIGNAL ram_ck13 :BIT;
184 SIGNAL ram_ck14 :BIT;
185 SIGNAL ram_ck15 :BIT;
186
187BEGIN
188
189 -- ******************* RAM shifter description *******************
190
191 -- RAM shifter control code :
192 -- 1) "00" : UP shift.
193 -- 2) "01" : DOWN shift.
194 -- 3) either "10" or "11" : NO shift.
195 WITH ram_sh(1 downto 0) SELECT
196 ram_d <= alu_f(2 downto 0)&ram_i_down WHEN B"00",
197 ram_i_up&alu_f(3 downto 1) WHEN B"01",
198 alu_f(3 downto 0) WHEN B"10" | B"11";
199
200 -- ****************** ACCU shifter description *******************
201 acc_q_down <= acc_s_q(0);
202
203 -- ACCU shifter control code :
204 -- 1) "00" : UP shift accu.
205 -- 2) "01" : DOWN shift accu.
206 -- 3) either "10" or "11" : write accu with no shift.
207 WITH acc_sh(1 downto 0) SELECT
208 acc_d <= acc_s_q(2 downto 0)&acc_i_down WHEN B"00",
209 acc_i_up&acc_s_q(3 downto 1) WHEN B"01",
210 alu_f(3 downto 0) WHEN B"10" | B"11";
211
212 -- ****************** S multiplexer description ******************
213 WITH ops_mx(2 downto 0) SELECT
214 ops_ns <= not acc_s_q WHEN B"000",
215 not ram_rb WHEN B"001",
216 not ram_ra WHEN B"010" | B"011",
217 "1111" WHEN B"100" | B"101" | B"110" | B"111";
218
219 -- ****************** R multiplexer description ******************
220 WITH opr_mx(1 downto 0) SELECT
221 opr_nr <= not ram_ra WHEN B"00",
222 not opr_d WHEN B"01",
223 "1111" WHEN B"10" | B"11";
224
225 -- ****************** X multiplexer description ******************
226 WITH out_mx SELECT
227 out_x <= alu_f WHEN B"0",
228 ram_ra WHEN B"1";
229
230 -- *********************** ALU description ***********************
231 alu_cry(0) <= alu_cin;
232 alu_cout <= alu_cry(4);
233 alu_over <= alu_cry(3);
234
235 -- Inversion of R and S operands.
236 alu_s <= not ops_ns WHEN alu_k(1) = '0' ELSE ops_ns;
237 alu_r <= not opr_nr WHEN alu_k(0) = '0' ELSE opr_nr;
238
239 -- Compute of nP and nG.
240 alu_np <= not (alu_s or alu_r);
241 alu_ng <= not (alu_s and alu_r);
242
243 -- Arithmetic adder description.
244 alu_cry(4 downto 1) <= (alu_s and alu_r )
245 or (alu_s and alu_cry(3 downto 0))
246 or (alu_cry(3 downto 0) and alu_r);
247
248 -- Select the ALU output.
249 WITH alu_k(4 downto 2) SELECT
250 alu_f <= alu_s xor alu_r xor alu_cry(3 downto 0) WHEN B"000",
251 (alu_s or alu_r) xor alu_cry(3 downto 0) WHEN B"001",
252 (alu_s and alu_r) xor alu_cry(3 downto 0) WHEN B"010",
253 alu_cry(3 downto 0) WHEN B"011",
254 not (alu_s xor alu_r) WHEN B"100",
255 not (alu_s or alu_r) WHEN B"101",
256 not (alu_s and alu_r) WHEN B"110",
257 B"1111" WHEN B"111";
258
259 -- ********************** ACCU description ************************
260 -- Modification tenant compte du front montant de l'horloge
261 acc_ws <= not acc_ck;
262 acc_q_up <= acc_s_q(3);
263
264 WITH acc_wen SELECT
265 sig_acc <= acc_d WHEN B"1" , -- Mode normal
266 acc_s_q WHEN OTHERS ; -- Reprise du registre
267
268 -- A chaque cycle, on ecrit dans acc_s_q
269
270 -- Echantillonnage lorsque ck=0 et memorisation sur front montant
271 acc_ck:BLOCK(acc_ws = '1')
272 BEGIN
273 acc_m_q <= GUARDED sig_acc;
274 END BLOCK acc_ck;
275
276 -- Slave register write.
277 -- Echantillonnage lorsque ck=1 et memorisation sur front descendant
278 acc_ws:BLOCK(acc_ck = '1')
279 BEGIN
280 acc_s_q <= GUARDED acc_m_q;
281 END BLOCK acc_ws;
282
283 -- *********************** RAM description ***********************
284
285 -- Select B register.
286 ram_adrb(0 ) <= b(0 ) ;
287 ram_adrb(1 ) <= b(1 ) ;
288 ram_adrb(2 ) <= b(2 ) ;
289 ram_adrb(3 ) <= b(3 ) ;
290 ram_adrb(4 ) <= b(4 ) ;
291 ram_adrb(5 ) <= b(5 ) ;
292 ram_adrb(6 ) <= b(6 ) ;
293 ram_adrb(7 ) <= b(7 ) ;
294 ram_adrb(8 ) <= b(8 ) ;
295 ram_adrb(9 ) <= b(9 ) ;
296 ram_adrb(10) <= b(10) ;
297 ram_adrb(11) <= b(11) ;
298 ram_adrb(12) <= b(12) ;
299 ram_adrb(13) <= b(13) ;
300 ram_adrb(14) <= b(14) ;
301 ram_adrb(15) <= b(15) ;
302
303 -- Select A register.
304 ram_adra(0 ) <= a(0 ) ;
305 ram_adra(1 ) <= a(1 ) ;
306 ram_adra(2 ) <= a(2 ) ;
307 ram_adra(3 ) <= a(3 ) ;
308 ram_adra(4 ) <= a(4 ) ;
309 ram_adra(5 ) <= a(5 ) ;
310 ram_adra(6 ) <= a(6 ) ;
311 ram_adra(7 ) <= a(7 ) ;
312 ram_adra(8 ) <= a(8 ) ;
313 ram_adra(9 ) <= a(9 ) ;
314 ram_adra(10) <= a(10) ;
315 ram_adra(11) <= a(11) ;
316 ram_adra(12) <= a(12) ;
317 ram_adra(13) <= a(13) ;
318 ram_adra(14) <= a(14) ;
319 ram_adra(15) <= a(15) ;
320
321 -- Write master enable signals for b
322 ram_wmd0 <= b_w(0 );
323 ram_wmd1 <= b_w(1 );
324 ram_wmd2 <= b_w(2 );
325 ram_wmd3 <= b_w(3 );
326 ram_wmd4 <= b_w(4 );
327 ram_wmd5 <= b_w(5 );
328 ram_wmd6 <= b_w(6 );
329 ram_wmd7 <= b_w(7 );
330 ram_wmd8 <= b_w(8 );
331 ram_wmd9 <= b_w(9 );
332 ram_wmd10 <= b_w(10);
333 ram_wmd11 <= b_w(11);
334 ram_wmd12 <= b_w(12);
335 ram_wmd13 <= b_w(13);
336 ram_wmd14 <= b_w(14);
337 ram_wmd15 <= b_w(15);
338
339 -- Write slave enable signals.
340 ram_ws0 <= not ram_ck(0 ) ;
341 ram_ws1 <= not ram_ck(1 ) ;
342 ram_ws2 <= not ram_ck(2 ) ;
343 ram_ws3 <= not ram_ck(3 ) ;
344 ram_ws4 <= not ram_ck(4 ) ;
345 ram_ws5 <= not ram_ck(5 ) ;
346 ram_ws6 <= not ram_ck(6 ) ;
347 ram_ws7 <= not ram_ck(7 ) ;
348 ram_ws8 <= not ram_ck(8 ) ;
349 ram_ws9 <= not ram_ck(9 ) ;
350 ram_ws10 <= not ram_ck(10) ;
351 ram_ws11 <= not ram_ck(11) ;
352 ram_ws12 <= not ram_ck(12) ;
353 ram_ws13 <= not ram_ck(13) ;
354 ram_ws14 <= not ram_ck(14) ;
355 ram_ws15 <= not ram_ck(15) ;
356
357 ram_ck0 <= ram_ck(0 ) ;
358 ram_ck1 <= ram_ck(1 ) ;
359 ram_ck2 <= ram_ck(2 ) ;
360 ram_ck3 <= ram_ck(3 ) ;
361 ram_ck4 <= ram_ck(4 ) ;
362 ram_ck5 <= ram_ck(5 ) ;
363 ram_ck6 <= ram_ck(6 ) ;
364 ram_ck7 <= ram_ck(7 ) ;
365 ram_ck8 <= ram_ck(8 ) ;
366 ram_ck9 <= ram_ck(9 ) ;
367 ram_ck10 <= ram_ck(10) ;
368 ram_ck11 <= ram_ck(11) ;
369 ram_ck12 <= ram_ck(12) ;
370 ram_ck13 <= ram_ck(13) ;
371 ram_ck14 <= ram_ck(14) ;
372 ram_ck15 <= ram_ck(15) ;
373
374
375 WITH ram_wmd0 SELECT
376 sig_ram0 <= ram_d WHEN B"1" , -- Mode ecriture
377 ram_s_r0 WHEN OTHERS ;
378
379 WITH ram_wmd1 SELECT
380 sig_ram1 <= ram_d WHEN B"1" , -- Mode ecriture
381 ram_s_r1 WHEN OTHERS ;
382
383 WITH ram_wmd2 SELECT
384 sig_ram2 <= ram_d WHEN B"1" , -- Mode ecriture
385 ram_s_r2 WHEN OTHERS ;
386
387 WITH ram_wmd3 SELECT
388 sig_ram3 <= ram_d WHEN B"1" , -- Mode ecriture
389 ram_s_r3 WHEN OTHERS ;
390
391 WITH ram_wmd4 SELECT
392 sig_ram4 <= ram_d WHEN B"1" , -- Mode ecriture
393 ram_s_r4 WHEN OTHERS ;
394
395 WITH ram_wmd5 SELECT
396 sig_ram5 <= ram_d WHEN B"1" , -- Mode ecriture
397 ram_s_r5 WHEN OTHERS ;
398
399 WITH ram_wmd6 SELECT
400 sig_ram6 <= ram_d WHEN B"1" , -- Mode ecriture
401 ram_s_r6 WHEN OTHERS ;
402
403 WITH ram_wmd7 SELECT
404 sig_ram7 <= ram_d WHEN B"1" , -- Mode ecriture
405 ram_s_r7 WHEN OTHERS ;
406
407 WITH ram_wmd8 SELECT
408 sig_ram8 <= ram_d WHEN B"1" , -- Mode ecriture
409 ram_s_r8 WHEN OTHERS ;
410
411 WITH ram_wmd9 SELECT
412 sig_ram9 <= ram_d WHEN B"1" , -- Mode ecriture
413 ram_s_r9 WHEN OTHERS ;
414
415 WITH ram_wmd10 SELECT
416 sig_ram10 <= ram_d WHEN B"1" , -- Mode ecriture
417 ram_s_r10 WHEN OTHERS ;
418
419 WITH ram_wmd11 SELECT
420 sig_ram11 <= ram_d WHEN B"1" , -- Mode ecriture
421 ram_s_r11 WHEN OTHERS ;
422
423 WITH ram_wmd12 SELECT
424 sig_ram12 <= ram_d WHEN B"1" , -- Mode ecriture
425 ram_s_r12 WHEN OTHERS ;
426
427 WITH ram_wmd13 SELECT
428 sig_ram13 <= ram_d WHEN B"1" , -- Mode ecriture
429 ram_s_r13 WHEN OTHERS ;
430
431 WITH ram_wmd14 SELECT
432 sig_ram14 <= ram_d WHEN B"1" , -- Mode ecriture
433 ram_s_r14 WHEN OTHERS ;
434
435 WITH ram_wmd15 SELECT
436 sig_ram15 <= ram_d WHEN B"1" , -- Mode ecriture
437 ram_s_r15 WHEN OTHERS ;
438
439 -- Write registers description.
440
441 -- Echantillonnage lorsque ck=0 et memorisation sur front montant
442 wm0 :BLOCK(ram_ws0 = '1') BEGIN ram_m_r0 <= GUARDED sig_ram0 ; END BLOCK wm0 ;
443 wm1 :BLOCK(ram_ws1 = '1') BEGIN ram_m_r1 <= GUARDED sig_ram1 ; END BLOCK wm1 ;
444 wm2 :BLOCK(ram_ws2 = '1') BEGIN ram_m_r2 <= GUARDED sig_ram2 ; END BLOCK wm2 ;
445 wm3 :BLOCK(ram_ws3 = '1') BEGIN ram_m_r3 <= GUARDED sig_ram3 ; END BLOCK wm3 ;
446 wm4 :BLOCK(ram_ws4 = '1') BEGIN ram_m_r4 <= GUARDED sig_ram4 ; END BLOCK wm4 ;
447 wm5 :BLOCK(ram_ws5 = '1') BEGIN ram_m_r5 <= GUARDED sig_ram5 ; END BLOCK wm5 ;
448 wm6 :BLOCK(ram_ws6 = '1') BEGIN ram_m_r6 <= GUARDED sig_ram6 ; END BLOCK wm6 ;
449 wm7 :BLOCK(ram_ws7 = '1') BEGIN ram_m_r7 <= GUARDED sig_ram7 ; END BLOCK wm7 ;
450 wm8 :BLOCK(ram_ws8 = '1') BEGIN ram_m_r8 <= GUARDED sig_ram8 ; END BLOCK wm8 ;
451 wm9 :BLOCK(ram_ws9 = '1') BEGIN ram_m_r9 <= GUARDED sig_ram9 ; END BLOCK wm9 ;
452 wm10:BLOCK(ram_ws10 = '1') BEGIN ram_m_r10 <= GUARDED sig_ram10 ; END BLOCK wm10;
453 wm11:BLOCK(ram_ws11 = '1') BEGIN ram_m_r11 <= GUARDED sig_ram11 ; END BLOCK wm11;
454 wm12:BLOCK(ram_ws12 = '1') BEGIN ram_m_r12 <= GUARDED sig_ram12 ; END BLOCK wm12;
455 wm13:BLOCK(ram_ws13 = '1') BEGIN ram_m_r13 <= GUARDED sig_ram13 ; END BLOCK wm13;
456 wm14:BLOCK(ram_ws14 = '1') BEGIN ram_m_r14 <= GUARDED sig_ram14 ; END BLOCK wm14;
457 wm15:BLOCK(ram_ws15 = '1') BEGIN ram_m_r15 <= GUARDED sig_ram15 ; END BLOCK wm15;
458
459 -- Write slave registers description.
460 -- Echantillonnage lorsque ck=1 et memorisation sur front descendant
461 ws0 :BLOCK(ram_ck0 = '1') BEGIN ram_s_r0 <= GUARDED ram_m_r0 ; END BLOCK ws0 ;
462 ws1 :BLOCK(ram_ck1 = '1') BEGIN ram_s_r1 <= GUARDED ram_m_r1 ; END BLOCK ws1 ;
463 ws2 :BLOCK(ram_ck2 = '1') BEGIN ram_s_r2 <= GUARDED ram_m_r2 ; END BLOCK ws2 ;
464 ws3 :BLOCK(ram_ck3 = '1') BEGIN ram_s_r3 <= GUARDED ram_m_r3 ; END BLOCK ws3 ;
465 ws4 :BLOCK(ram_ck4 = '1') BEGIN ram_s_r4 <= GUARDED ram_m_r4 ; END BLOCK ws4 ;
466 ws5 :BLOCK(ram_ck5 = '1') BEGIN ram_s_r5 <= GUARDED ram_m_r5 ; END BLOCK ws5 ;
467 ws6 :BLOCK(ram_ck6 = '1') BEGIN ram_s_r6 <= GUARDED ram_m_r6 ; END BLOCK ws6 ;
468 ws7 :BLOCK(ram_ck7 = '1') BEGIN ram_s_r7 <= GUARDED ram_m_r7 ; END BLOCK ws7 ;
469 ws8 :BLOCK(ram_ck8 = '1') BEGIN ram_s_r8 <= GUARDED ram_m_r8 ; END BLOCK ws8 ;
470 ws9 :BLOCK(ram_ck9 = '1') BEGIN ram_s_r9 <= GUARDED ram_m_r9 ; END BLOCK ws9 ;
471 ws10:BLOCK(ram_ck10 = '1') BEGIN ram_s_r10 <= GUARDED ram_m_r10; END BLOCK ws10;
472 ws11:BLOCK(ram_ck11 = '1') BEGIN ram_s_r11 <= GUARDED ram_m_r11; END BLOCK ws11;
473 ws12:BLOCK(ram_ck12 = '1') BEGIN ram_s_r12 <= GUARDED ram_m_r12; END BLOCK ws12;
474 ws13:BLOCK(ram_ck13 = '1') BEGIN ram_s_r13 <= GUARDED ram_m_r13; END BLOCK ws13;
475 ws14:BLOCK(ram_ck14 = '1') BEGIN ram_s_r14 <= GUARDED ram_m_r14; END BLOCK ws14;
476 ws15:BLOCK(ram_ck15 = '1') BEGIN ram_s_r15 <= GUARDED ram_m_r15; END BLOCK ws15;
477
478 -- Select register to write on tristate bus RA.
479 wa0 :BLOCK(ram_adra(0 )) BEGIN ram_ra <= GUARDED ram_s_r0 ; END BLOCK wa0 ;
480 wa1 :BLOCK(ram_adra(1 )) BEGIN ram_ra <= GUARDED ram_s_r1 ; END BLOCK wa1 ;
481 wa2 :BLOCK(ram_adra(2 )) BEGIN ram_ra <= GUARDED ram_s_r2 ; END BLOCK wa2 ;
482 wa3 :BLOCK(ram_adra(3 )) BEGIN ram_ra <= GUARDED ram_s_r3 ; END BLOCK wa3 ;
483 wa4 :BLOCK(ram_adra(4 )) BEGIN ram_ra <= GUARDED ram_s_r4 ; END BLOCK wa4 ;
484 wa5 :BLOCK(ram_adra(5 )) BEGIN ram_ra <= GUARDED ram_s_r5 ; END BLOCK wa5 ;
485 wa6 :BLOCK(ram_adra(6 )) BEGIN ram_ra <= GUARDED ram_s_r6 ; END BLOCK wa6 ;
486 wa7 :BLOCK(ram_adra(7 )) BEGIN ram_ra <= GUARDED ram_s_r7 ; END BLOCK wa7 ;
487 wa8 :BLOCK(ram_adra(8 )) BEGIN ram_ra <= GUARDED ram_s_r8 ; END BLOCK wa8 ;
488 wa9 :BLOCK(ram_adra(9 )) BEGIN ram_ra <= GUARDED ram_s_r9 ; END BLOCK wa9 ;
489 wa10:BLOCK(ram_adra(10)) BEGIN ram_ra <= GUARDED ram_s_r10; END BLOCK wa10;
490 wa11:BLOCK(ram_adra(11)) BEGIN ram_ra <= GUARDED ram_s_r11; END BLOCK wa11;
491 wa12:BLOCK(ram_adra(12)) BEGIN ram_ra <= GUARDED ram_s_r12; END BLOCK wa12;
492 wa13:BLOCK(ram_adra(13)) BEGIN ram_ra <= GUARDED ram_s_r13; END BLOCK wa13;
493 wa14:BLOCK(ram_adra(14)) BEGIN ram_ra <= GUARDED ram_s_r14; END BLOCK wa14;
494 wa15:BLOCK(ram_adra(15)) BEGIN ram_ra <= GUARDED ram_s_r15; END BLOCK wa15;
495
496 -- Select register to write on tristate bus RB.
497 wb0 :BLOCK(ram_adrb(0 )) BEGIN ram_rb <= GUARDED ram_s_r0 ; END BLOCK wb0 ;
498 wb1 :BLOCK(ram_adrb(1 )) BEGIN ram_rb <= GUARDED ram_s_r1 ; END BLOCK wb1 ;
499 wb2 :BLOCK(ram_adrb(2 )) BEGIN ram_rb <= GUARDED ram_s_r2 ; END BLOCK wb2 ;
500 wb3 :BLOCK(ram_adrb(3 )) BEGIN ram_rb <= GUARDED ram_s_r3 ; END BLOCK wb3 ;
501 wb4 :BLOCK(ram_adrb(4 )) BEGIN ram_rb <= GUARDED ram_s_r4 ; END BLOCK wb4 ;
502 wb5 :BLOCK(ram_adrb(5 )) BEGIN ram_rb <= GUARDED ram_s_r5 ; END BLOCK wb5 ;
503 wb6 :BLOCK(ram_adrb(6 )) BEGIN ram_rb <= GUARDED ram_s_r6 ; END BLOCK wb6 ;
504 wb7 :BLOCK(ram_adrb(7 )) BEGIN ram_rb <= GUARDED ram_s_r7 ; END BLOCK wb7 ;
505 wb8 :BLOCK(ram_adrb(8 )) BEGIN ram_rb <= GUARDED ram_s_r8 ; END BLOCK wb8 ;
506 wb9 :BLOCK(ram_adrb(9 )) BEGIN ram_rb <= GUARDED ram_s_r9 ; END BLOCK wb9 ;
507 wb10:BLOCK(ram_adrb(10)) BEGIN ram_rb <= GUARDED ram_s_r10; END BLOCK wb10;
508 wb11:BLOCK(ram_adrb(11)) BEGIN ram_rb <= GUARDED ram_s_r11; END BLOCK wb11;
509 wb12:BLOCK(ram_adrb(12)) BEGIN ram_rb <= GUARDED ram_s_r12; END BLOCK wb12;
510 wb13:BLOCK(ram_adrb(13)) BEGIN ram_rb <= GUARDED ram_s_r13; END BLOCK wb13;
511 wb14:BLOCK(ram_adrb(14)) BEGIN ram_rb <= GUARDED ram_s_r14; END BLOCK wb14;
512 wb15:BLOCK(ram_adrb(15)) BEGIN ram_rb <= GUARDED ram_s_r15; END BLOCK wb15;
513
514 -- ********************* Power supply check **********************
515 ASSERT(vss = '0')
516 REPORT "Power supply VSS badly connected." SEVERITY WARNING;
517 ASSERT(vdd = '1')
518 REPORT "Power supply VDD badly connected." SEVERITY WARNING;
519
520END behavior_data_flow;