ToolsCourseTp4: amd2901_dpt.py

File amd2901_dpt.py, 6.0 KB (added by anne, 19 years ago)
Line 
1#!/usr/bin/env python
2
3from stratus import *
4
5
6class amd2901_dpt ( Model ) :
7
8 def Interface ( self ) :
9
10 # Command for selecting operands R and S.
11 self.ops_mx = SignalIn ( "ops_mx", 3 )
12 self.opr_mx = SignalIn ( "opr_mx", 2 )
13
14 # ALU commands and auxiliary terminals.
15 self.alu_k = SignalIn ( "alu_k", 5 )
16 self.alu_cin = SignalIn ( "alu_cin", 1 )
17 self.alu_cout = SignalOut ( "alu_cout", 1 )
18 self.alu_over = SignalInOut ( "alu_over", 1 )
19
20 # RAM, ACCU shifter commands and auxiliary terminals.
21 self.ram_sh = SignalIn ( "ram_sh", 2 )
22 self.acc_sh = SignalIn ( "acc_sh", 2 )
23
24 # RAM shifter inputs
25 self.ram_i_up = SignalIn ( "ram_i_up", 1 )
26 self.ram_i_down = SignalIn ( "ram_i_down", 1 )
27
28 # ACCU shifter inputs.
29 self.acc_i_up = SignalIn ( "acc_i_up", 1 )
30 self.acc_i_down = SignalIn ( "acc_i_down", 1 )
31
32 # ACCU shifter outputs ("acc_scout" is "acc_q_up").
33 self.acc_q_down = SignalOut ( "acc_q_down", 1 )
34 self.acc_q_up = SignalOut ( "acc_q_up", 1 )
35
36 # Output multiplexer commnand (for X bus).
37 self.out_mx = SignalIn ( "out_mx", 1 )
38
39 # ACCU controls terminals.
40 self.acc_ck = SignalIn ( "acc_ck", 1 )
41 self.acc_wen = SignalIn ( "acc_wen", 1 )
42
43 # Register file controls terminals.
44 self.ram_ck = SignalIn ( "ram_ck", 16 ) # Register clocks (ck)
45 self.b_w = SignalIn ( "b_w", 16 ) # Write enable
46 self.a = SignalIn ( "a", 16 ) # Register A address.
47 self.b = SignalIn ( "b", 16 ) # Register B address.
48
49 # Data buses terminals.
50 self.opr_d = SignalIn ( "opr_d", 4 )
51 self.alu_f = SignalInOut ( "alu_f", 4 )
52 self.alu_np = SignalOut ( "alu_np", 4 )
53 self.alu_ng = SignalOut ( "alu_ng", 4 )
54 self.out_x = SignalOut ( "out_x", 4 )
55
56 # Power supply connectors.
57 self.vdd = VddIn ( "vdd" )
58 self.vss = VssIn ( "vss" )
59
60
61 def Netlist ( self ) :
62
63 Generate ( "DpgenSff", "sff_4bits", param = {'nbit' : 4} )
64 Generate ( "DpgenNbuse", "nbuse_4bits", param = {'nbit' : 4} )
65 Generate ( "DpgenInv", "inv_drive8_4bits", param = {'nbit' : 4, 'drive' : 8} )
66
67 # List of Signals
68 ram_d = Signal ( "ram_d", 4 )
69 ram_nra = Signal ( "ram_nra", 4 )
70 ram_nrb = Signal ( "ram_nrb", 4 )
71 ram_ra = Signal ( "ram_ra", 4 )
72 ram_rb = Signal ( "ram_rb", 4 )
73
74 # Array of Signals
75 ram_q = []
76 for i in range ( 16 ) : ram_q += [Signal ( "ram_q%ld" % i, 4 )]
77
78 # Register file description.
79 self.ram_reg = {}
80 self.ram_ntsa = {}
81 self.ram_ntsb = {}
82
83 for i in range ( 16 ) :
84 # Register part.
85 self.ram_reg[i] = Inst ( "sff_4bits", "ram_reg%ld" % i
86 , map = { 'wen' : self.b_w[i]
87 , 'ck' : self.ram_ck[i]
88 , 'i0' : ram_d
89 , 'q' : ram_q[i]
90 , 'vdd' : self.vdd
91 , 'vss' : self.vss
92 }
93 )
94
95 # Tristate for A output.
96 self.ram_ntsa[i] = Inst ( "nbuse_4bits", "ram_ntsa%ld" % i
97 , map = { 'cmd' : self.a[i]
98 , 'i0' : ram_q[i]
99 , 'nq' : ram_nra
100 , 'vdd' : self.vdd
101 , 'vss' : self.vss
102 }
103 )
104
105
106 # Tristate for B output.
107 self.ram_ntsb[i] = Inst ( "nbuse_4bits", "ram_ntsb%ld" % i
108 , map = { 'cmd' : self.b[i]
109 , 'i0' : ram_q[i]
110 , 'nq' : ram_nrb
111 , 'vdd' : self.vdd
112 , 'vss' : self.vss
113 }
114 )
115
116
117 # Output drivers for A & B output.
118 self.inv_ra = Inst ( "inv_drive8_4bits", "inv_ra"
119 , map = { 'i0' : ram_nra
120 , 'nq' : ram_ra
121 , 'vdd' : self.vdd
122 , 'vss' : self.vss
123 }
124 )
125
126 self.inv_rb = Inst ( "inv_drive8_4bits", "inv_rb"
127 , map = { 'i0' : ram_nrb
128 , 'nq' : ram_rb
129 , 'vdd' : self.vdd
130 , 'vss' : self.vss
131 }
132 )
133
134 # --------------------------------------------------------------
135 # RAM shifter.
136 ##### A COMPLETER #####
137
138 # *********************** Operand S ************************
139 ##### A COMPLETER #####
140
141 # *********************** Operand R ************************
142 ##### A COMPLETER #####
143
144 # *********************** ALU Description ******************
145 ##### A COMPLETER #####
146
147 # Compute of "generate".
148 ##### A COMPLETER #####
149
150 # Compute of "propagate".
151 ##### A COMPLETER #####
152
153 # Compute of carry.
154 ##### A COMPLETER #####
155
156 # Logical and arithmetical operators.
157 ##### A COMPLETER #####
158
159 # Output.
160 ##### A COMPLETER #####
161
162 # ******************** ACCU Description ********************
163 ##### A COMPLETER #####
164
165 # ******************* Output Multiplexer *******************
166 ##### A COMPLETER #####
167