| 1 | #!/usr/bin/env python
|
|---|
| 2 |
|
|---|
| 3 | from stratus import *
|
|---|
| 4 |
|
|---|
| 5 |
|
|---|
| 6 | class contest ( Model ) :
|
|---|
| 7 |
|
|---|
| 8 | def Interface ( self ) :
|
|---|
| 9 |
|
|---|
| 10 | # Command for selecting operands R and S.
|
|---|
| 11 | self.ops_mx = SignalIn ( "ops_mx", 3 )
|
|---|
| 12 | self.opr_mx = SignalIn ( "opr_mx", 2 )
|
|---|
| 13 |
|
|---|
| 14 | # ALU commands and auxiliary terminals.
|
|---|
| 15 | self.alu_k = SignalIn ( "alu_k", 5 )
|
|---|
| 16 | self.alu_cin = SignalIn ( "alu_cin", 1 )
|
|---|
| 17 | self.alu_cout = SignalOut ( "alu_cout", 1 )
|
|---|
| 18 | self.alu_over = SignalInOut ( "alu_over", 1 )
|
|---|
| 19 |
|
|---|
| 20 | # RAM, ACCU shifter commands and auxiliary terminals.
|
|---|
| 21 | self.ram_sh = SignalIn ( "ram_sh", 2 )
|
|---|
| 22 | self.acc_sh = SignalIn ( "acc_sh", 2 )
|
|---|
| 23 |
|
|---|
| 24 | # RAM shifter inputs
|
|---|
| 25 | self.ram_i_up = SignalIn ( "ram_i_up", 1 )
|
|---|
| 26 | self.ram_i_down = SignalIn ( "ram_i_down", 1 )
|
|---|
| 27 |
|
|---|
| 28 | # ACCU shifter inputs.
|
|---|
| 29 | self.acc_i_up = SignalIn ( "acc_i_up", 1 )
|
|---|
| 30 | self.acc_i_down = SignalIn ( "acc_i_down", 1 )
|
|---|
| 31 |
|
|---|
| 32 | # ACCU shifter outputs ("acc_scout" is "acc_q_up").
|
|---|
| 33 | self.acc_q_down = SignalOut ( "acc_q_down", 1 )
|
|---|
| 34 | self.acc_q_up = SignalOut ( "acc_q_up", 1 )
|
|---|
| 35 |
|
|---|
| 36 | # Output multiplexer commnand (for X bus).
|
|---|
| 37 | self.out_mx = SignalIn ( "out_mx", 1 )
|
|---|
| 38 |
|
|---|
| 39 | # ACCU controls terminals.
|
|---|
| 40 | self.acc_ck = SignalIn ( "acc_ck", 1 )
|
|---|
| 41 | self.acc_wen = SignalIn ( "acc_wen", 1 )
|
|---|
| 42 |
|
|---|
| 43 | # Register file controls terminals.
|
|---|
| 44 | self.ram_ck = SignalIn ( "ram_ck", 16 ) # Register clocks (ck)
|
|---|
| 45 | self.b_w = SignalIn ( "b_w", 16 ) # Write enable
|
|---|
| 46 | self.a = SignalIn ( "a", 16 ) # Register A address.
|
|---|
| 47 | self.b = SignalIn ( "b", 16 ) # Register B address.
|
|---|
| 48 |
|
|---|
| 49 | # Data buses terminals.
|
|---|
| 50 | self.opr_d = SignalIn ( "opr_d", 4 )
|
|---|
| 51 | self.alu_f = SignalInOut ( "alu_f", 4 )
|
|---|
| 52 | self.alu_np = SignalOut ( "alu_np", 4 )
|
|---|
| 53 | self.alu_ng = SignalOut ( "alu_ng", 4 )
|
|---|
| 54 | self.out_x = SignalOut ( "out_x", 4 )
|
|---|
| 55 |
|
|---|
| 56 | # Power supply connectors.
|
|---|
| 57 | self.vdd = VddIn ( "vdd" )
|
|---|
| 58 | self.vss = VssIn ( "vss" )
|
|---|
| 59 |
|
|---|
| 60 |
|
|---|
| 61 | def Netlist ( self ) :
|
|---|
| 62 |
|
|---|
| 63 | Generate ( "DpgenSff", "sff_4bits", param = {'nbit' : 4, 'physical' : True} )
|
|---|
| 64 | Generate ( "DpgenNbuse", "nbuse_4bits", param = {'nbit' : 4, 'physical' : True} )
|
|---|
| 65 | Generate ( "DpgenInv", "inv_drive8_4bits", param = {'nbit' : 4, 'drive' : 8, 'physical' : True} )
|
|---|
| 66 | Generate ( "DpgenMux2", "mux2_4bits", param = {'nbit' : 4, 'physical' : True} )
|
|---|
| 67 | Generate ( "DpgenNand2mask", "nand2mask_0b0000_4bits", param = {'nbit' : 4, 'const' : "0b0000", 'physical' : True} )
|
|---|
| 68 | Generate ( "DpgenXnor2", "xnor2_4bits", param = {'nbit' : 4, 'physical' : True} )
|
|---|
| 69 | Generate ( "DpgenNand2", "nand2_4bits", param = {'nbit' : 4, 'physical' : True} )
|
|---|
| 70 | Generate ( "DpgenNor2", "nor2_4bits", param = {'nbit' : 4, 'physical' : True} )
|
|---|
| 71 | Generate ( "DpgenXor2", "xor2_4bits", param = {'nbit' : 4, 'physical' : True} )
|
|---|
| 72 | Generate ( "DpgenXnor2", "xnor2_drive4_4bits", param = {'nbit' : 4, 'drive' : 4, 'physical' : True} )
|
|---|
| 73 | Generate ( "DpgenBuff", "buff_2bits", param = {'nbit' : 2, 'physical' : True} )
|
|---|
| 74 |
|
|---|
| 75 | # List of Signals
|
|---|
| 76 | ram_d = Signal ( "ram_d", 4 )
|
|---|
| 77 | ram_nra = Signal ( "ram_nra", 4 )
|
|---|
| 78 | ram_nrb = Signal ( "ram_nrb", 4 )
|
|---|
| 79 | ram_ra = Signal ( "ram_ra", 4 )
|
|---|
| 80 | ram_rb = Signal ( "ram_rb", 4 )
|
|---|
| 81 |
|
|---|
| 82 | mux_shram = Signal ( "mux_shram", 4 )
|
|---|
| 83 | acc_q = Signal ( "acc_q", 4 )
|
|---|
| 84 | ops0_out = Signal ( "ops0_out", 4 )
|
|---|
| 85 | ops1_out = Signal ( "ops1_out", 4 )
|
|---|
| 86 | opr0_out = Signal ( "opr0_out", 4 )
|
|---|
| 87 | alu_ns = Signal ( "alu_ns", 4 )
|
|---|
| 88 | alu_nr = Signal ( "alu_nr", 4 )
|
|---|
| 89 | alu_int0 = Signal ( "alu_int0", 4 )
|
|---|
| 90 | alu_int1 = Signal ( "alu_int1", 4 )
|
|---|
| 91 | alu_int2 = Signal ( "alu_int2", 4 )
|
|---|
| 92 | alu_int3 = Signal ( "alu_int3", 4 )
|
|---|
| 93 | alu_int4 = Signal ( "alu_int4", 4 )
|
|---|
| 94 | alu_int5 = Signal ( "alu_int5", 4 )
|
|---|
| 95 | alu_int6 = Signal ( "alu_int6", 4 )
|
|---|
| 96 | alu_int7 = Signal ( "alu_int7", 4 )
|
|---|
| 97 | mux_shacc0 = Signal ( "mux_shacc0", 4 )
|
|---|
| 98 | mux_shacc1 = Signal ( "mux_shacc1", 4 )
|
|---|
| 99 | carry = Signal ( "carry", 2 )
|
|---|
| 100 |
|
|---|
| 101 | # Array of Signals
|
|---|
| 102 | ram_q = []
|
|---|
| 103 | for i in range ( 16 ) : ram_q += [Signal ( "ram_q%ld" % i, 4 )]
|
|---|
| 104 |
|
|---|
| 105 | # Register file description.
|
|---|
| 106 | self.ram_reg = {}
|
|---|
| 107 | self.ram_ntsa = {}
|
|---|
| 108 | self.ram_ntsb = {}
|
|---|
| 109 |
|
|---|
| 110 | for i in range ( 16 ) :
|
|---|
| 111 | # Register part.
|
|---|
| 112 | self.ram_reg[i] = Inst ( "sff_4bits", "ram_reg%ld" % i
|
|---|
| 113 | , map = { 'wen' : self.b_w[i]
|
|---|
| 114 | , 'ck' : self.ram_ck[i]
|
|---|
| 115 | , 'i0' : ram_d
|
|---|
| 116 | , 'q' : ram_q[i]
|
|---|
| 117 | , 'vdd' : self.vdd
|
|---|
| 118 | , 'vss' : self.vss
|
|---|
| 119 | }
|
|---|
| 120 | )
|
|---|
| 121 |
|
|---|
| 122 | # Tristate for A output.
|
|---|
| 123 | self.ram_ntsa[i] = Inst ( "nbuse_4bits", "ram_ntsa%ld" % i
|
|---|
| 124 | , map = { 'cmd' : self.a[i]
|
|---|
| 125 | , 'i0' : ram_q[i]
|
|---|
| 126 | , 'nq' : ram_nra
|
|---|
| 127 | , 'vdd' : self.vdd
|
|---|
| 128 | , 'vss' : self.vss
|
|---|
| 129 | }
|
|---|
| 130 | )
|
|---|
| 131 |
|
|---|
| 132 |
|
|---|
| 133 | # Tristate for B output.
|
|---|
| 134 | self.ram_ntsb[i] = Inst ( "nbuse_4bits", "ram_ntsb%ld" % i
|
|---|
| 135 | , map = { 'cmd' : self.b[i]
|
|---|
| 136 | , 'i0' : ram_q[i]
|
|---|
| 137 | , 'nq' : ram_nrb
|
|---|
| 138 | , 'vdd' : self.vdd
|
|---|
| 139 | , 'vss' : self.vss
|
|---|
| 140 | }
|
|---|
| 141 | )
|
|---|
| 142 |
|
|---|
| 143 |
|
|---|
| 144 | # Output drivers for A & B output.
|
|---|
| 145 | self.inv_ra = Inst ( "inv_drive8_4bits", "inv_ra"
|
|---|
| 146 | , map = { 'i0' : ram_nra
|
|---|
| 147 | , 'nq' : ram_ra
|
|---|
| 148 | , 'vdd' : self.vdd
|
|---|
| 149 | , 'vss' : self.vss
|
|---|
| 150 | }
|
|---|
| 151 | )
|
|---|
| 152 |
|
|---|
| 153 | self.inv_rb = Inst ( "inv_drive8_4bits", "inv_rb"
|
|---|
| 154 | , map = { 'i0' : ram_nrb
|
|---|
| 155 | , 'nq' : ram_rb
|
|---|
| 156 | , 'vdd' : self.vdd
|
|---|
| 157 | , 'vss' : self.vss
|
|---|
| 158 | }
|
|---|
| 159 | )
|
|---|
| 160 |
|
|---|
| 161 | # --------------------------------------------------------------
|
|---|
| 162 | # RAM shifter.
|
|---|
| 163 | self.mx2_ram_sh0 = Inst ( "mux2_4bits", "mx2_ram_sh0"
|
|---|
| 164 | , map = { 'i0' : Cat ( self.alu_f[2:0], self.ram_i_down )
|
|---|
| 165 | , 'i1' : Cat ( self.ram_i_up, self.alu_f[3:1] )
|
|---|
| 166 | , 'cmd' : self.ram_sh[0]
|
|---|
| 167 | , 'q' : mux_shram
|
|---|
| 168 | , 'vdd' : self.vdd
|
|---|
| 169 | , 'vss' : self.vss
|
|---|
| 170 | }
|
|---|
| 171 | )
|
|---|
| 172 | self.mx2_ram_sh1 = Inst ( "mux2_4bits", "mx2_ram_sh1"
|
|---|
| 173 | , map = { 'i0' : mux_shram
|
|---|
| 174 | , 'i1' : self.alu_f
|
|---|
| 175 | , 'cmd' : self.ram_sh[1]
|
|---|
| 176 | , 'q' : ram_d
|
|---|
| 177 | , 'vdd' : self.vdd
|
|---|
| 178 | , 'vss' : self.vss
|
|---|
| 179 | }
|
|---|
| 180 | )
|
|---|
| 181 |
|
|---|
| 182 |
|
|---|
| 183 | # --------------------------------------------------------------
|
|---|
| 184 | # Operand S.
|
|---|
| 185 | self.mx2_ops0 = Inst ( "mux2_4bits", "mx2_ops0"
|
|---|
| 186 | , map = { 'i0' : acc_q
|
|---|
| 187 | , 'i1' : ram_rb
|
|---|
| 188 | , 'cmd' : self.ops_mx[0]
|
|---|
| 189 | , 'q' : ops0_out
|
|---|
| 190 | , 'vdd' : self.vdd
|
|---|
| 191 | , 'vss' : self.vss
|
|---|
| 192 | }
|
|---|
| 193 | )
|
|---|
| 194 | self.mx2_ops1 = Inst ( "mux2_4bits", "mx2_ops1"
|
|---|
| 195 | , map = { 'i0' : ops0_out
|
|---|
| 196 | , 'i1' : ram_ra
|
|---|
| 197 | , 'cmd' : self.ops_mx[1]
|
|---|
| 198 | , 'q' : ops1_out
|
|---|
| 199 | , 'vdd' : self.vdd
|
|---|
| 200 | , 'vss' : self.vss
|
|---|
| 201 | }
|
|---|
| 202 | )
|
|---|
| 203 | self.nand2mask_s = Inst ( "nand2mask_0b0000_4bits", "nand2mask_s"
|
|---|
| 204 | , map = { 'i0' : ops1_out
|
|---|
| 205 | , 'cmd' : self.ops_mx[2]
|
|---|
| 206 | , 'nq' : alu_ns
|
|---|
| 207 | , 'vdd' : self.vdd
|
|---|
| 208 | , 'vss' : self.vss
|
|---|
| 209 | }
|
|---|
| 210 | )
|
|---|
| 211 |
|
|---|
| 212 | # --------------------------------------------------------------
|
|---|
| 213 | # Operand R.
|
|---|
| 214 | self.mx2_opr0 = Inst ( "mux2_4bits", "mx2_opr0"
|
|---|
| 215 | , map = { 'i0' : ram_ra
|
|---|
| 216 | , 'i1' : self.opr_d
|
|---|
| 217 | , 'cmd' : self.opr_mx[0]
|
|---|
| 218 | , 'q' : opr0_out
|
|---|
| 219 | , 'vdd' : self.vdd
|
|---|
| 220 | , 'vss' : self.vss
|
|---|
| 221 | }
|
|---|
| 222 | )
|
|---|
| 223 | self.nand2mask_r = Inst ( "nand2mask_0b0000_4bits", "nand2mask_r"
|
|---|
| 224 | , map = { 'i0' : opr0_out
|
|---|
| 225 | , 'cmd' : self.opr_mx[1]
|
|---|
| 226 | , 'nq' : alu_nr
|
|---|
| 227 | , 'vdd' : self.vdd
|
|---|
| 228 | , 'vss' : self.vss
|
|---|
| 229 | }
|
|---|
| 230 | )
|
|---|
| 231 |
|
|---|
| 232 | # --------------------------------------------------------------
|
|---|
| 233 | # ALU Description.
|
|---|
| 234 | self.xnor2_alu0 = Inst ( "xnor2_4bits", "xnor2_alu0"
|
|---|
| 235 | , map = { 'i0' : alu_nr
|
|---|
| 236 | , 'i1' : Cat ( self.alu_k[0]
|
|---|
| 237 | , self.alu_k[0]
|
|---|
| 238 | , self.alu_k[0]
|
|---|
| 239 | , self.alu_k[0]
|
|---|
| 240 | )
|
|---|
| 241 | , 'nq' : alu_int0
|
|---|
| 242 | , 'vdd' : self.vdd
|
|---|
| 243 | , 'vss' : self.vss
|
|---|
| 244 | }
|
|---|
| 245 | )
|
|---|
| 246 |
|
|---|
| 247 | self.xnor2_alu1 = Inst ( "xnor2_4bits", "xnor2_alu1"
|
|---|
| 248 | , map = { 'i0' : alu_ns
|
|---|
| 249 | , 'i1' : Cat ( self.alu_k[1]
|
|---|
| 250 | , self.alu_k[1]
|
|---|
| 251 | , self.alu_k[1]
|
|---|
| 252 | , self.alu_k[1]
|
|---|
| 253 | )
|
|---|
| 254 | , 'nq' : alu_int1
|
|---|
| 255 | , 'vdd' : self.vdd
|
|---|
| 256 | , 'vss' : self.vss
|
|---|
| 257 | }
|
|---|
| 258 | )
|
|---|
| 259 |
|
|---|
| 260 | # Compute of "generate".
|
|---|
| 261 | self.nand2_ng = Inst ( "nand2_4bits", "nand2_ng"
|
|---|
| 262 | , map = { 'i0' : alu_int0
|
|---|
| 263 | , 'i1' : alu_int1
|
|---|
| 264 | , 'nq' : self.alu_ng
|
|---|
| 265 | , 'vdd' : self.vdd
|
|---|
| 266 | , 'vss' : self.vss
|
|---|
| 267 | }
|
|---|
| 268 | )
|
|---|
| 269 |
|
|---|
| 270 | # Compute of "propagate".
|
|---|
| 271 | self.nor2_np = Inst ( "nor2_4bits", "nor2_np"
|
|---|
| 272 | , map = { 'i0' : alu_int0
|
|---|
| 273 | , 'i1' : alu_int1
|
|---|
| 274 | , 'nq' : self.alu_np
|
|---|
| 275 | , 'vdd' : self.vdd
|
|---|
| 276 | , 'vss' : self.vss
|
|---|
| 277 | }
|
|---|
| 278 | )
|
|---|
| 279 |
|
|---|
| 280 | # Compute of carry.
|
|---|
| 281 | self.inv_np = Inst ( "inv_drive8_4bits", "inv_np"
|
|---|
| 282 | , map = { 'i0' : self.alu_np
|
|---|
| 283 | , 'nq' : alu_int2
|
|---|
| 284 | , 'vdd' : self.vdd
|
|---|
| 285 | , 'vss' : self.vss
|
|---|
| 286 | }
|
|---|
| 287 | )
|
|---|
| 288 | self.nand2_cout_in = Inst ( "nand2_4bits", "nand2_cout_in"
|
|---|
| 289 | , map = { 'i0' : alu_int2
|
|---|
| 290 | , 'i1' : Cat ( self.alu_over, carry, self.alu_cin )
|
|---|
| 291 | , 'nq' : alu_int3
|
|---|
| 292 | , 'vdd' : self.vdd
|
|---|
| 293 | , 'vss' : self.vss
|
|---|
| 294 | }
|
|---|
| 295 | )
|
|---|
| 296 | self.nand2_cout = Inst ( "nand2_4bits", "nand2_cout"
|
|---|
| 297 | , map = { 'i0' : alu_int3
|
|---|
| 298 | , 'i1' : self.alu_ng
|
|---|
| 299 | , 'nq' : Cat ( self.alu_cout, self.alu_over, carry )
|
|---|
| 300 | , 'vdd' : self.vdd
|
|---|
| 301 | , 'vss' : self.vss
|
|---|
| 302 | }
|
|---|
| 303 | )
|
|---|
| 304 |
|
|---|
| 305 | # Logical and arithmetical operators.
|
|---|
| 306 | self.nor2_alu_int7 = Inst ( "nor2_4bits", "nor2_alu_int7"
|
|---|
| 307 | , map = { 'i0' : Cat ( self.alu_over
|
|---|
| 308 | , carry
|
|---|
| 309 | , self.alu_cin
|
|---|
| 310 | )
|
|---|
| 311 | , 'i1' : Cat ( self.alu_k[4]
|
|---|
| 312 | , self.alu_k[4]
|
|---|
| 313 | , self.alu_k[4]
|
|---|
| 314 | , self.alu_k[4]
|
|---|
| 315 | )
|
|---|
| 316 | , 'nq' : alu_int7
|
|---|
| 317 | , 'vdd' : self.vdd
|
|---|
| 318 | , 'vss' : self.vss
|
|---|
| 319 | }
|
|---|
| 320 | )
|
|---|
| 321 |
|
|---|
| 322 | self.nor2_alu_int4 = Inst ( "nor2_4bits", "nor2_alu_int4"
|
|---|
| 323 | , map = { 'i0' : self.alu_ng
|
|---|
| 324 | , 'i1' : Cat ( self.alu_k[2]
|
|---|
| 325 | , self.alu_k[2]
|
|---|
| 326 | , self.alu_k[2]
|
|---|
| 327 | , self.alu_k[2]
|
|---|
| 328 | )
|
|---|
| 329 | , 'nq' : alu_int4
|
|---|
| 330 | , 'vdd' : self.vdd
|
|---|
| 331 | , 'vss' : self.vss
|
|---|
| 332 | }
|
|---|
| 333 | )
|
|---|
| 334 |
|
|---|
| 335 | self.nor2_alu_int5 = Inst ( "nor2_4bits", "nor2_alu_int5"
|
|---|
| 336 | , map = { 'i0' : self.alu_np
|
|---|
| 337 | , 'i1' : Cat ( self.alu_k[3]
|
|---|
| 338 | , self.alu_k[3]
|
|---|
| 339 | , self.alu_k[3]
|
|---|
| 340 | , self.alu_k[3]
|
|---|
| 341 | )
|
|---|
| 342 | , 'nq' : alu_int5
|
|---|
| 343 | , 'vdd' : self.vdd
|
|---|
| 344 | , 'vss' : self.vss
|
|---|
| 345 | }
|
|---|
| 346 | )
|
|---|
| 347 |
|
|---|
| 348 | self.xor2_alu_int6 = Inst ("xor2_4bits", "xor2_alu_int6"
|
|---|
| 349 | , map = { 'i0' : alu_int4
|
|---|
| 350 | , 'i1' : alu_int5
|
|---|
| 351 | , 'q' : alu_int6
|
|---|
| 352 | , 'vdd' : self.vdd
|
|---|
| 353 | , 'vss' : self.vss
|
|---|
| 354 | }
|
|---|
| 355 | )
|
|---|
| 356 |
|
|---|
| 357 | # Output.
|
|---|
| 358 | self.xnor2_alu_f = Inst ( "xnor2_drive4_4bits", "xnor2_alu_f"
|
|---|
| 359 | , map = { 'i0' : alu_int6
|
|---|
| 360 | , 'i1' : alu_int7
|
|---|
| 361 | , 'nq' : self.alu_f
|
|---|
| 362 | , 'vdd' : self.vdd
|
|---|
| 363 | , 'vss' : self.vss
|
|---|
| 364 | }
|
|---|
| 365 | )
|
|---|
| 366 |
|
|---|
| 367 | # --------------------------------------------------------------
|
|---|
| 368 | # ACCU Description.
|
|---|
| 369 | self.mx2_acc_sh0 = Inst ( "mux2_4bits", "mx2_acc_sh0"
|
|---|
| 370 | , map = { 'i0' : Cat ( acc_q[2:0], self.acc_i_down )
|
|---|
| 371 | , 'i1' : Cat ( self.acc_i_up, acc_q[3:1] )
|
|---|
| 372 | , 'cmd' : self.acc_sh[0]
|
|---|
| 373 | , 'q' : mux_shacc0
|
|---|
| 374 | , 'vdd' : self.vdd
|
|---|
| 375 | , 'vss' : self.vss
|
|---|
| 376 | }
|
|---|
| 377 | )
|
|---|
| 378 | self.mx2_acc_sh1 = Inst ( "mux2_4bits", "mx2_acc_sh1"
|
|---|
| 379 | , map = { 'i0' : mux_shacc0
|
|---|
| 380 | , 'i1' : self.alu_f
|
|---|
| 381 | , 'cmd' : self.acc_sh[1]
|
|---|
| 382 | , 'q' : mux_shacc1
|
|---|
| 383 | , 'vdd' : self.vdd
|
|---|
| 384 | , 'vss' : self.vss
|
|---|
| 385 | }
|
|---|
| 386 | )
|
|---|
| 387 | self.acc_reg = Inst ( "sff_4bits", "acc_reg"
|
|---|
| 388 | , map = { 'wen' : self.acc_wen
|
|---|
| 389 | , 'ck' : self.acc_ck
|
|---|
| 390 | , 'i0' : mux_shacc1
|
|---|
| 391 | , 'q' : acc_q
|
|---|
| 392 | , 'vdd' : self.vdd
|
|---|
| 393 | , 'vss' : self.vss
|
|---|
| 394 | }
|
|---|
| 395 | )
|
|---|
| 396 | self.acc_buff = Inst ( "buff_2bits", "acc_buff0"
|
|---|
| 397 | , map = { 'i0' : Cat ( acc_q[0], acc_q[3] )
|
|---|
| 398 | , 'q' : Cat ( self.acc_q_down, self.acc_q_up )
|
|---|
| 399 | , 'vdd' : self.vdd
|
|---|
| 400 | , 'vss' : self.vss
|
|---|
| 401 | }
|
|---|
| 402 | )
|
|---|
| 403 |
|
|---|
| 404 | # --------------------------------------------------------------
|
|---|
| 405 | # Output Multiplexer.
|
|---|
| 406 | self.mx2_out = Inst ( "mux2_4bits", "mx2_out"
|
|---|
| 407 | , map = { 'i0' : self.alu_f
|
|---|
| 408 | , 'i1' : ram_ra
|
|---|
| 409 | , 'cmd' : self.out_mx
|
|---|
| 410 | , 'q' : self.out_x
|
|---|
| 411 | , 'vdd' : self.vdd
|
|---|
| 412 | , 'vss' : self.vss
|
|---|
| 413 | }
|
|---|
| 414 | )
|
|---|
| 415 |
|
|---|
| 416 |
|
|---|
| 417 | def Layout (self):
|
|---|
| 418 |
|
|---|
| 419 | Place ( self.acc_buff, NOSYM, XY(0,0) )
|
|---|
| 420 | PlaceRight ( self.acc_reg, NOSYM )
|
|---|
| 421 | PlaceRight ( self.inv_np, NOSYM )
|
|---|
| 422 | PlaceRight ( self.inv_ra, NOSYM )
|
|---|
| 423 | PlaceRight ( self.inv_rb, NOSYM )
|
|---|
| 424 | PlaceRight ( self.mx2_acc_sh0, NOSYM )
|
|---|
| 425 | PlaceRight ( self.mx2_acc_sh1, NOSYM )
|
|---|
| 426 | PlaceRight ( self.mx2_opr0, NOSYM )
|
|---|
| 427 | PlaceRight ( self.mx2_ops0, NOSYM )
|
|---|
| 428 | PlaceRight ( self.mx2_ops1, NOSYM )
|
|---|
| 429 | PlaceRight ( self.mx2_out, NOSYM )
|
|---|
| 430 | PlaceRight ( self.mx2_ram_sh0, NOSYM )
|
|---|
| 431 | PlaceRight ( self.mx2_ram_sh1, NOSYM )
|
|---|
| 432 | PlaceRight ( self.nand2_cout_in, NOSYM )
|
|---|
| 433 | PlaceRight ( self.nand2_cout, NOSYM )
|
|---|
| 434 | PlaceRight ( self.nand2mask_r, NOSYM )
|
|---|
| 435 | PlaceRight ( self.nand2mask_s, NOSYM )
|
|---|
| 436 | PlaceRight ( self.nand2_ng, NOSYM )
|
|---|
| 437 | PlaceRight ( self.nor2_alu_int4, NOSYM )
|
|---|
| 438 | PlaceRight ( self.nor2_alu_int5, NOSYM )
|
|---|
| 439 | PlaceRight ( self.nor2_alu_int7, NOSYM )
|
|---|
| 440 | PlaceRight ( self.nor2_np, NOSYM )
|
|---|
| 441 | PlaceRight ( self.ram_ntsa[ 0], NOSYM )
|
|---|
| 442 | PlaceRight ( self.ram_ntsa[10], NOSYM )
|
|---|
| 443 | PlaceRight ( self.ram_ntsa[11], NOSYM )
|
|---|
| 444 | PlaceRight ( self.ram_ntsa[12], NOSYM )
|
|---|
| 445 | PlaceRight ( self.ram_ntsa[13], NOSYM )
|
|---|
| 446 | PlaceRight ( self.ram_ntsa[14], NOSYM )
|
|---|
| 447 | PlaceRight ( self.ram_ntsa[15], NOSYM )
|
|---|
| 448 | PlaceRight ( self.ram_ntsa[ 1], NOSYM )
|
|---|
| 449 | PlaceRight ( self.ram_ntsa[ 2], NOSYM )
|
|---|
| 450 | PlaceRight ( self.ram_ntsa[ 3], NOSYM )
|
|---|
| 451 | PlaceRight ( self.ram_ntsa[ 4], NOSYM )
|
|---|
| 452 | PlaceRight ( self.ram_ntsa[ 5], NOSYM )
|
|---|
| 453 | PlaceRight ( self.ram_ntsa[ 6], NOSYM )
|
|---|
| 454 | PlaceRight ( self.ram_ntsa[ 7], NOSYM )
|
|---|
| 455 | PlaceRight ( self.ram_ntsa[ 8], NOSYM )
|
|---|
| 456 | PlaceRight ( self.ram_ntsa[ 9], NOSYM )
|
|---|
| 457 | PlaceRight ( self.ram_ntsb[ 0], NOSYM )
|
|---|
| 458 | PlaceRight ( self.ram_ntsb[10], NOSYM )
|
|---|
| 459 | PlaceRight ( self.ram_ntsb[11], NOSYM )
|
|---|
| 460 | PlaceRight ( self.ram_ntsb[12], NOSYM )
|
|---|
| 461 | PlaceRight ( self.ram_ntsb[13], NOSYM )
|
|---|
| 462 | PlaceRight ( self.ram_ntsb[14], NOSYM )
|
|---|
| 463 | PlaceRight ( self.ram_ntsb[15], NOSYM )
|
|---|
| 464 | PlaceRight ( self.ram_ntsb[ 1], NOSYM )
|
|---|
| 465 | PlaceRight ( self.ram_ntsb[ 2], NOSYM )
|
|---|
| 466 | PlaceRight ( self.ram_ntsb[ 3], NOSYM )
|
|---|
| 467 | PlaceRight ( self.ram_ntsb[ 4], NOSYM )
|
|---|
| 468 | PlaceRight ( self.ram_ntsb[ 5], NOSYM )
|
|---|
| 469 | PlaceRight ( self.ram_ntsb[ 6], NOSYM )
|
|---|
| 470 | PlaceRight ( self.ram_ntsb[ 7], NOSYM )
|
|---|
| 471 | PlaceRight ( self.ram_ntsb[ 8], NOSYM )
|
|---|
| 472 | PlaceRight ( self.ram_ntsb[ 9], NOSYM )
|
|---|
| 473 | PlaceRight ( self.ram_reg[10], NOSYM )
|
|---|
| 474 | PlaceRight ( self.ram_reg[11], NOSYM )
|
|---|
| 475 | PlaceRight ( self.ram_reg[12], NOSYM )
|
|---|
| 476 | PlaceRight ( self.ram_reg[13], NOSYM )
|
|---|
| 477 | PlaceRight ( self.ram_reg[14], NOSYM )
|
|---|
| 478 | PlaceRight ( self.ram_reg[15], NOSYM )
|
|---|
| 479 | PlaceRight ( self.ram_reg[ 0], NOSYM )
|
|---|
| 480 | PlaceRight ( self.ram_reg[ 1], NOSYM )
|
|---|
| 481 | PlaceRight ( self.ram_reg[ 2], NOSYM )
|
|---|
| 482 | PlaceRight ( self.ram_reg[ 3], NOSYM )
|
|---|
| 483 | PlaceRight ( self.ram_reg[ 4], NOSYM )
|
|---|
| 484 | PlaceRight ( self.ram_reg[ 5], NOSYM )
|
|---|
| 485 | PlaceRight ( self.ram_reg[ 6], NOSYM )
|
|---|
| 486 | PlaceRight ( self.ram_reg[ 7], NOSYM )
|
|---|
| 487 | PlaceRight ( self.ram_reg[ 8], NOSYM )
|
|---|
| 488 | PlaceRight ( self.ram_reg[ 9], NOSYM )
|
|---|
| 489 | PlaceRight ( self.xnor2_alu0, NOSYM )
|
|---|
| 490 | PlaceRight ( self.xnor2_alu1, NOSYM )
|
|---|
| 491 | PlaceRight ( self.xnor2_alu_f, NOSYM )
|
|---|
| 492 | PlaceRight ( self.xor2_alu_int6, NOSYM )
|
|---|
| 493 |
|
|---|
| 494 | ResizeAb ( 0, 0, 0, 50 );
|
|---|
| 495 |
|
|---|
| 496 |
|
|---|
| 497 | def StratusScript ():
|
|---|
| 498 | if globals().has_key ( "__editor" ):
|
|---|
| 499 | setEditor ( __editor )
|
|---|
| 500 |
|
|---|
| 501 | datapath = contest ( "contest" )
|
|---|
| 502 |
|
|---|
| 503 | datapath.Interface()
|
|---|
| 504 | datapath.Netlist ()
|
|---|
| 505 | #datapath.View ( message="After Netlist Generation" )
|
|---|
| 506 | datapath.Layout ()
|
|---|
| 507 | #datapath.View ( message="After Layout Generation" )
|
|---|
| 508 | datapath.Save (PHYSICAL)
|
|---|
| 509 |
|
|---|
| 510 |
|
|---|
| 511 | if __name__ == "__main__" :
|
|---|
| 512 | StratusScript ()
|
|---|
