Changes between Version 2 and Version 3 of ToolsCourseTp4

Timestamp:

May 4, 2007, 12:22:09 PM (17 years ago)

Author:

anne

Comment:

--

ToolsCourseTp4

@@ -38 +38 @@
 # definition de la cellule
 class circuit ( Model ):
- # declaration des connecteurs
- def Interface ( self ):
-  self.a = SignalIn ( "a" , 4 )
-  self.b = SignalIn ( "b" , 4 )
-  self.c = SignalIn ( "c" , 4 )
-  self.v = SignalIn ( "v" , 1 )
-  self.cout = SignalOut ( "cout", 1 )
-  self.s = SignalOut ( "s" , 4 )
-  self.cmd = SignalIn ( "cmd" , 1 )
-  self.vdd = VddIn ( "vdd" )
-  self.vss = VssIn ( "vss" )
- # instanciation des operateurs
- def Netlist ( self ):
-  # declaration des signaux internes
-  d_aux = Signal ( "d_aux", 4 )
-  e_aux = Signal ( "e_aux", 4 )
-  ovr = Signal ( "ovr" , 1 )
-  # generation
-  Generate ( "DpgenNand2", "instance_nand2_4bits"
-            , param = { ’nbit’ : 4 }
-            )
-  # instanciation
-  self.instance_nand2_4bits = Inst ( "instance_nand2_4bits"
-                                    , map = { ’i0’ : Cat ( self.v
-                                                          , self.v
-                                                          , self.v
-                                                          , self.v )
-                                              , ’i1’ : self.a
-                                              , ’nq’ : d_aux
-                                              , ’vdd’ : self.vdd
-                                              , ’vss’ : self.vss
-                                              }
-                                     )
-  Generate ( "DpgenOr2", "instance_or2_4bits"
-           , param = { ’nbit’ : 4 }
-            )
-  self.instance_or2_4bits = Inst ( "instance_or2_4bits"
-                                 , map = { ’i0’ : d_aux
-                                         , ’i1’ : self.b
-                                         , ’q’ : e_aux
-                                         , ’vdd’ : self.vdd
-                                         , ’vss’ : self.vss
-                                         }
-                                  )
-  Generate ( "DpgenAdsb2f", "instance_add2_4bits"
-           , param = { ’nbit’ : 4 }
-           ) 
-  self.instance_add2_4bits = Inst ( "instance_add2_4bits"
+  # declaration des connecteurs
+  def Interface ( self ):
+    self.a = SignalIn ( "a" , 4 )
+    self.b = SignalIn ( "b" , 4 )
+    self.c = SignalIn ( "c" , 4 )
+    self.v = SignalIn ( "v" , 1 )
+    self.cout = SignalOut ( "cout", 1 )
+    self.s = SignalOut ( "s" , 4 )
+    self.cmd = SignalIn ( "cmd" , 1 )
+    self.vdd = VddIn ( "vdd" )
+    self.vss = VssIn ( "vss" )
+  # instanciation des operateurs
+  def Netlist ( self ):
+    # declaration des signaux internes
+    d_aux = Signal ( "d_aux", 4 )
+    e_aux = Signal ( "e_aux", 4 )
+    ovr = Signal ( "ovr" , 1 )
+    # generation
+    Generate ( "DpgenNand2", "instance_nand2_4bits"
+              , param = { ’nbit’ : 4 }
+              )
+    # instanciation
+    self.instance_nand2_4bits = Inst ( "instance_nand2_4bits"
+                                      , map = { ’i0’ : Cat ( self.v
+                                                            , self.v
+                                                            , self.v
+                                                            , self.v )
+                                                , ’i1’ : self.a
+                                                , ’nq’ : d_aux
+                                                , ’vdd’ : self.vdd
+                                                , ’vss’ : self.vss
+                                                }
+                                       )
+    Generate ( "DpgenOr2", "instance_or2_4bits"
+             , param = { ’nbit’ : 4 }
+              )
+    self.instance_or2_4bits = Inst ( "instance_or2_4bits"
+                                   , map = { ’i0’ : d_aux
+                                           , ’i1’ : self.b
+                                           , ’q’ : e_aux
+                                           , ’vdd’ : self.vdd
+                                           , ’vss’ : self.vss
+                                           }
+                                    )
+    Generate ( "DpgenAdsb2f", "instance_add2_4bits"
+             , param = { ’nbit’ : 4 }
+             ) 
+    self.instance_add2_4bits = Inst ( "instance_add2_4bits"
                                   , map = { ’i0’ : e_aux
                                           , ’i1’ : self.c