1 | |
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2 | char getchar(void); |
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3 | |
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4 | /* #define UART_BUFSIZE 16 */ |
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5 | /* #define UART_BUFSIZE_MASK 0x0f */ |
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6 | #define UART_BUFSIZE 128 |
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7 | #define UART_BUFSIZE_MASK 0x7f |
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8 | |
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9 | extern char uart_txbuf[UART_BUFSIZE]; |
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10 | extern unsigned char uart_txbuf_prod; |
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11 | extern volatile unsigned char uart_txbuf_cons; |
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12 | |
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13 | extern char uart_rxbuf[UART_BUFSIZE]; |
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14 | extern volatile unsigned char uart_rxbuf_prod; |
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15 | extern unsigned char uart_rxbuf_cons; |
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16 | |
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17 | char uart_getchar(void); |
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18 | void uart_putchar_raw(char); |
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19 | #if 0 |
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20 | #define UART_PUTCHAR_HARD(c) { \ |
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21 | while (PIR1bits.TX1IF == 0) \ |
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22 | ; \ |
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23 | TXREG1 = c; \ |
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24 | } |
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25 | #endif |
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26 | void uart_putchar_hard(char) __wparam; |
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27 | |
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28 | #define UART_FLUSH() { \ |
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29 | while (PIE1bits.TX1IE) \ |
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30 | ; \ |
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31 | } |
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32 | |
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33 | |
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34 | #define USART_INIT { \ |
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35 | uart_txbuf_prod = uart_txbuf_cons = 0; \ |
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36 | uart_rxbuf_prod = uart_rxbuf_cons = 0; \ |
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37 | (void)RCREG1; \ |
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38 | PIE1bits.RC1IE = 1; \ |
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39 | } |
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40 | |
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41 | #define USART_INTR {\ |
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42 | if (PIE1bits.TX1IE && PIR1bits.TX1IF) { \ |
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43 | if (uart_txbuf_prod == uart_txbuf_cons) { \ |
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44 | PIE1bits.TX1IE = 0; /* buffer empty */ \ |
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45 | } else { \ |
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46 | /* Place char in TXREG - this starts transmition */ \ |
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47 | TXREG1 = uart_txbuf[uart_txbuf_cons]; \ |
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48 | uart_txbuf_cons = (uart_txbuf_cons + 1) & UART_BUFSIZE_MASK;\ |
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49 | } \ |
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50 | } \ |
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51 | if (PIE1bits.RC1IE && PIR1bits.RC1IF) { \ |
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52 | register char c = RCREG1; \ |
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53 | if (RCSTA1bits.OERR) { \ |
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54 | RCSTA1bits.CREN = 0; \ |
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55 | RCSTA1bits.CREN = 1; \ |
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56 | } \ |
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57 | if (status & STAT_CONSOLE) { \ |
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58 | uart_rxbuf_prod = (uart_rxbuf_prod + 1) & UART_BUFSIZE_MASK;\ |
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59 | uart_rxbuf[uart_rxbuf_prod] = c; \ |
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60 | } else { \ |
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61 | if (c == '\r') c = '\n';\ |
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62 | if (c != '\n' || uart_rxbuf[uart_rxbuf_prod] != '\n') { \ |
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63 | uart_rxbuf_prod = (uart_rxbuf_prod + 1) & UART_BUFSIZE_MASK;\ |
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64 | uart_rxbuf[uart_rxbuf_prod] = c; \ |
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65 | if (c == '\n') { \ |
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66 | if (softintrs & INT_RX1) \ |
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67 | softintrs |= INT_RX1OF; \ |
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68 | softintrs |= INT_RX1; \ |
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69 | } \ |
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70 | } \ |
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71 | } \ |
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72 | }\ |
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73 | } |
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