Last change
on this file since 80 was
41,
checked in by rolagamo, 12 years ago
|
Ceci est la version stable avant optimisation
|
File size:
1.1 KB
|
Rev | Line | |
---|
[15] | 1 | ---------------------------------------------------------------------------------- |
---|
| 2 | -- Company: |
---|
| 3 | -- Engineer: |
---|
| 4 | -- |
---|
| 5 | -- Create Date: 09:35:09 06/13/2011 |
---|
| 6 | -- Design Name: |
---|
| 7 | -- Module Name: DEMUX1 - Behavioral |
---|
| 8 | -- Project Name: |
---|
| 9 | -- Target Devices: |
---|
| 10 | -- Tool versions: |
---|
| 11 | -- Description: |
---|
| 12 | -- |
---|
| 13 | -- Dependencies: |
---|
| 14 | -- |
---|
| 15 | -- Revision: |
---|
| 16 | -- Revision 0.01 - File Created |
---|
| 17 | -- Additional Comments: |
---|
| 18 | -- |
---|
| 19 | ---------------------------------------------------------------------------------- |
---|
| 20 | library IEEE; |
---|
| 21 | use IEEE.STD_LOGIC_1164.ALL; |
---|
| 22 | use IEEE.STD_LOGIC_ARITH.ALL; |
---|
| 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
---|
| 24 | |
---|
| 25 | ---- Uncomment the following library declaration if instantiating |
---|
| 26 | ---- any Xilinx primitives in this code. |
---|
| 27 | --library UNISIM; |
---|
| 28 | --use UNISIM.VComponents.all; |
---|
| 29 | |
---|
[41] | 30 | entity CDEMUX1 is |
---|
[15] | 31 | Port ( di : in STD_LOGIC; |
---|
| 32 | sel : in STD_LOGIC; |
---|
| 33 | do1 : out STD_LOGIC; |
---|
| 34 | do2 : out STD_LOGIC); |
---|
[41] | 35 | end CDEMUX1; |
---|
[15] | 36 | |
---|
[41] | 37 | architecture Behavioral of CDEMUX1 is |
---|
[15] | 38 | |
---|
| 39 | begin |
---|
| 40 | |
---|
| 41 | demux_process : process(di, sel) |
---|
| 42 | begin |
---|
| 43 | if sel = '0' then |
---|
| 44 | do1 <= di; |
---|
| 45 | do2 <= '0'; |
---|
| 46 | else |
---|
| 47 | do2 <= di; |
---|
| 48 | do1 <='0'; |
---|
| 49 | end if; |
---|
| 50 | end process; |
---|
| 51 | |
---|
| 52 | |
---|
| 53 | end Behavioral; |
---|
| 54 | |
---|
Note: See
TracBrowser
for help on using the repository browser.