Last change
on this file since 66 was
41,
checked in by rolagamo, 12 years ago
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Ceci est la version stable avant optimisation
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File size:
1.1 KB
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1 | ---------------------------------------------------------------------------------- |
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2 | -- Company: |
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3 | -- Engineer: |
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4 | -- |
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5 | -- Create Date: 09:30:26 06/13/2011 |
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6 | -- Design Name: |
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7 | -- Module Name: MUX8 - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: |
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12 | -- |
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13 | -- Dependencies: |
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14 | -- |
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15 | -- Revision: |
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16 | -- Revision 0.01 - File Created |
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17 | -- Additional Comments: |
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18 | -- |
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19 | ---------------------------------------------------------------------------------- |
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20 | library IEEE; |
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21 | use IEEE.STD_LOGIC_1164.ALL; |
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22 | use IEEE.STD_LOGIC_ARITH.ALL; |
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23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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24 | |
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25 | ---- Uncomment the following library declaration if instantiating |
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26 | ---- any Xilinx primitives in this code. |
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27 | --library UNISIM; |
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28 | --use UNISIM.VComponents.all; |
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29 | |
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30 | entity CMUX8 is |
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31 | Port ( di1 : in STD_LOGIC_VECTOR (7 downto 0); |
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32 | di2 : in STD_LOGIC_VECTOR (7 downto 0); |
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33 | sel : in STD_LOGIC; |
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34 | do : out STD_LOGIC_VECTOR (7 downto 0)); |
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35 | end CMUX8; |
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36 | |
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37 | architecture Behavioral of CMUX8 is |
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38 | |
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39 | begin |
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40 | with sel select |
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41 | do <= di1 when '0', |
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42 | di2 when '1', |
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43 | di1 when others; |
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44 | end Behavioral; |
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45 | |
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