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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE.vhd @ 39

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 21:20:54 07/16/2012
6	-- Design Name:
7	-- Module Name: PE - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	library NocLib ;
23	library Std;
24	--use IEEE.STD_LOGIC_ARITH.ALL;
25	--use IEEE.STD_LOGIC_UNSIGNED.ALL;
26	use NocLib.CoreTypes.all;
27	use work.Packet_type.all;
28	use work.MPI_RMA.all;
29	use std.textio.all;
30	use IEEE.NUMERIC_STD.ALL;
31
32
33	entity PE is
34	Generic (DestId : natural );
35	Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0);
36	Instruction_en : out STD_LOGIC;
37	Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0);
38	clk : in STD_LOGIC;
39	reset : in STD_LOGIC;
40	Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0);
41	Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0);
42	Core_RAM_WE : in STD_LOGIC;
43	Core_RAM_EN : in STD_LOGIC;
44	--Core_RAM_ENB : in STD_LOGIC;
45	Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
46	Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
47	Core_Hold_req : in STD_LOGIC;
48	Core_Hold_Ack : out STD_LOGIC);
49	end PE;
50
51	architecture Behavioral of PE is
52	COMPONENT RAM_v
53	generic (width : positive;size :positive);
54	PORT(
55	clka : IN std_logic;
56	clkb : IN std_logic;
57	wea : IN std_logic;
58	ena : IN std_logic;
59	enb : IN std_logic;
60	addra : IN std_logic_vector;
61	addrb : IN std_logic_vector;
62	dia : IN std_logic_vector;
63	dob : OUT std_logic_vector
64	);
65	END COMPONENT;
66	--données du programme PE
67	--signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0');
68	signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0';
69	signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic;
70	signal pe_instr_en,pe_hold_ack: std_logic:='0';
71	signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
72	signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
73	signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
74	signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
75	signal sram : typ_dpram;
76
77	signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0);
78	signal dpid,dpid_i : natural range 0 to 15:=DestId;
79	signal MyRank :std_logic_vector(3 downto 0);
80	signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque
81	signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée
82	signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO
83	signal Lib_Init : std_logic; -- l'initialisation est terminée
84	--signaux pour la gestion de la MAE
85	type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate, putdata,getdata,WinCompleted,finalize,st_timeout);
86	signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées
87	signal count,count_i : natural range 0 to 15:=0;
88
89
90	signal RunState : typ_mae;
91	signal Ram_busy :std_logic:='0';
92	begin
93	Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN)
94	PORT MAP(
95	clka =>clk,
96	clkb => clk,
97	wea => ram_we,
98	ena => ram_ena,
99	enb => ram_enb,
100	addra => ram_addra,
101	addrb =>ram_addrb,
102	dia => ram_din,
103	dob => ram_do
104	);
105	--================================================================
106	--MUX de la RAM
107
108	Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr,
109	Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do,
110	Pe_ram_din,Pe_ram_we )
111	begin
112	case ramsel is
113
114	when '1' =>
115	ram_addra <= Core_ram_address_wr ;
116	ram_addrb <= Core_ram_address_rd ;
117	ram_ena <= Core_ram_en;
118	ram_enb <= Core_ram_en;
119	ram_we<= Core_ram_we;
120	ram_din <= Core_ram_data_in;
121	pe_ram_do<=(others=>'Z');
122	Core_ram_data_out<=ram_do;
123
124	when others =>
125	ram_addra <= pe_ram_addra;
126	ram_addrb <= pe_ram_addrb;
127	ram_ena <= pe_ram_ena;
128	ram_enb <= pe_ram_enb;
129	ram_we<= pe_ram_we;
130	ram_din <=pe_ram_din;
131	Core_ram_data_out<=(others=>'Z');
132	pe_ram_do<=ram_do;
133	end case ;
134	end process ;
135
136
137
138	Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --******A changer ********
139	--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce
140	-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!!
141	instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8));
142
143	dpid<=dpid_i;
144
145	Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié
146	Lib_init<=Core_Pushout(4); -- Initialized
147	-- pe_hold_req<=Core_hold_req;
148	--Core_hold_ack<=pe_hold_ack;
149
150	hold:process (Core_Hold_Req,clk,reset)
151	begin
152	if rising_edge(clk) then
153	if reset='1' then
154	Core_Hold_Ack<='0';
155	else
156	if Core_Hold_Req='1' then
157
158	ramsel<=not(ram_busy);
159	Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération
160	Pe_hold_ack<=not(ram_busy);
161	else
162	Core_Hold_Ack<='0';
163	ramsel<='0';
164	Pe_hold_ack<='0';
165
166	end if;
167	end if;
168	end if;
169	end process hold;
170	--=======================================================================
171
172
173
174	--=======================================================================
175	--MAE du PE
176	--=======================================================================
177
178	pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do)
179
180	constant DATAPTR : natural :=256;
181	variable bfill,destrank,pid,mport : natural range 0 to 15;
182	variable fsrc,ret : natural range 0 to 15:=0;
183	variable timeout,ct,dlen : natural range 0 to 255;
184	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
185	variable mywin : Mpi_win;
186	variable iack : std_logic:='0';
187	variable adresse,adresse_rd :natural range 0 to 65536;
188	variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');
189	--=======================================================
190	--variables pour la création du fichier de résultats
191	type char_file is file of character;
192	file f: text;
193	variable status :file_open_status ;
194	variable char_count: integer range 0 to 65536 := 0;
195	variable str: string (1 to 79) ;
196	variable L: line;
197	variable fopened: std_logic:='0';
198	--======================================================
199	begin
200	--=== Partie combinatoire du process ===================================
201	Libr.Instr_ack<=Core_pushout(0);
202	Libr.InitOk<=Core_pushout(4);
203	Libr.Hold_Req<=Core_Hold_req;
204	Libr.Hold_Ack<=Pe_Hold_Ack;
205	Libr.RamSel<=RamSel;
206	sram.data_out<=PE_ram_do;
207	--=== Fin de la partie combinatoire du process ==========================
208
209
210
211	--end loop;
212
213	if (clk'event and clk='1') then
214	if reset='1' then
215	RunState<=start;
216
217	else
218
219	Libr.Instr_ack<=Core_pushout(0);
220	Libr.InitOk<=Core_pushout(4);
221	Libr.Hold_Req<=Core_Hold_req;
222	Libr.Hold_Ack<=Pe_Hold_Ack;
223	Libr.RamSel<=RamSel;
224	sram.data_out<=PE_ram_do;
225	case RunState is
226	when start =>
227	Dcount<=0;
228	if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
229	RunState<=Fillmem;
230	end if;
231	Ram_busy<='0';
232	PE_Instr_En<='0';
233	iack:='0';
234	adresse:=DATAPTR;
235
236	adresse_rd:=0;
237	timeout:=0;
238	dcount<=0;
239	if fopened='0' then
240	file_open(status,f, integer'image(destid) & "test_file0.txt", APPEND_MODE);
241	--while not endfile(c_file_handle) loop
242	--end if;
243
244	--write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));
245	--report l.all;
246	-- writeline (f, l) ;
247	fopened:='1';
248	end if;
249
250	when Fillmem =>
251	if Ramsel='0' then
252
253
254
255	PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
256	PE_Instr_En<='0';
257	dcount<=dcount+1;
258
259	if dcount=200 then
260	bfill:=bfill+1;
261
262	if bfill=4 then
263	RunState<=InitApp;
264	else
265	RunState<=nextfill;
266	end if;
267	else
268	adresse:=adresse+1;
269	RunState<=Fillmem;
270	end if;
271	else -- attente de la libéraion de la mémoire
272	timeout:=timeout+1;
273	if timeout=100 then
274	RunState<=st_timeout;
275	end if;
276
277	end if;
278	when nextfill => --prépare le prochain bloc mémoire qui sera rempli
279	adresse:=200*bfill;
280	dcount<=0;
281	ct:=0;
282	RunState<=Fillmem;
283	PE_Instr_En<='0';
284	when InitApp =>
285	--code pour Init
286	dlen:=1;
287	if ct=0 then
288	write (l,string'("Dlen; ;INIT of Process n°; " & image(MyRank) & "; started at ; " & time'image(now)));
289
290	report l.all;
291	writeline (f, l) ;
292	end if;
293	pMPI_Init(ct,Libr,Clk,SRam);
294	PE_Instr_EN<=Libr.instr_en;
295	adresse:=to_integer(unsigned(sram.addr_wr));
296	adresse_rd:=to_integer(unsigned(sram.addr_rd));
297	PE_ram_din<=sram.data_in;
298
299	--if Libr.InitOk='1' then
300	if ct=0 then
301	RunState<=GetRank;
302	write (l,string'("Dlen; ;INIT;" & "; ended at ; " & time'image(now)));
303	report l.all;
304	writeline (f, l) ;
305	end if;
306
307
308
309	when GetRank =>
310	if ct=0 then
311
312	write (l,string'("Dlen; ; Rank ; " & "; started ; " & time'image(now)));
313	report l.all;
314	writeline (f, l) ;
315	end if;
316	pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
317	adresse_rd:=to_integer(unsigned(sram.addr_rd));
318	if ct=0 then
319	RunState<=PutData;
320	write (l,string'("Dlen; ; Rank ; " & "; ended at ; " & time'image(now)));
321	report l.all;
322	writeline (f, l) ;
323	end if;
324
325
326	when Wincreate =>
327
328
329	when putdata => --construire le packet pour le Put
330
331	--dlen:=251; ---
332	if ct=0 then
333	write (l,string'("Dlen;" & integer'image(dlen) & ";Put of Pr n°; " & image(MyRank) & "; started at ; " & time'image(now)));
334	report l.all;
335	writeline (f, l) ;
336	end if;
337	if unsigned(MyRank) = 0 then
338	Destrank:=1;
339	else
340	DestRank:=0;
341	end if;
342
343	SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
344	DestAdr:=X"2000";
345
346	pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
347	adresse:=to_integer(unsigned(sram.addr_wr));
348	adresse_rd:=to_integer(unsigned(sram.addr_rd));
349	PE_Instr_EN<=Libr.instr_en;
350	PE_ram_din<=sram.data_in;
351	dcount<=ct;
352
353	if ct=0 then
354	RunState<=GetData;
355	report "Put of Process n°; " & image(MyRank) & "; ended at ; " & time'image(now);
356	write (l,string'("Dlen;" & integer'image(dlen) & ";Put of Pr n°; " & image(MyRank) & "; ended at time ; " & time'image(now)));
357	report l.all;
358	writeline (f, l) ;
359	end if;
360
361
362	when getdata => --positionnement du mot de longueur des données
363	--dlen:=251; ---
364	if ct=0 then
365	write (l,string'("Dlen;" & integer'image(dlen) & ";GET of Process n°; " & image(MyRank) & "; started at ; " & time'image(now)));
366	report l.all;
367	writeline (f, l) ;
368	end if;
369
370	SrcAdr:=X"0120";
371	DestAdr:=X"4000";
372
373	pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
374	adresse:=to_integer(unsigned(sram.addr_wr));
375	adresse_rd:=to_integer(unsigned(sram.addr_rd));
376	PE_Instr_EN<=Libr.instr_en;
377	PE_ram_din<=sram.data_in;
378	dcount<=ct;
379
380	if ct=0 then
381	RunState<=wincompleted;
382	assert ct/=0 report "GET_END " & integer'image(destrank)
383	severity Warning ;
384	write (l,string'("Dlen ;" & integer'image(dlen) & ";GET of Proc n°; " & image(MyRank) & "; ended at ; " & time'image(now)));
385	report l.all;
386
387	writeline (f, l) ;
388	end if;
389
390	when WinCompleted =>
391	if ct=0 then
392	write (l,string'("Dlen ;" & integer'image(dlen) & ";Wait of Proc n°; " & image(MyRank) & "; started at ; " & time'image(now)));
393	report l.all;
394	writeline (f, l) ;
395	end if;
396	pMPI_Win_wait(ct,Libr,sram,MyWin );
397	adresse:=to_integer(unsigned(sram.addr_wr));
398	adresse_rd:=to_integer(unsigned(sram.addr_rd));
399	if ct=0 then
400	RunState<=finalize;
401	write (l,string'("Dlen ;" & integer'image(dlen) & ";Wait of Proc n°; " & image(MyRank) & "; ended at ; " & time'image(now)));
402	report l.all;
403	writeline (f, l) ;
404
405	end if;
406
407
408	when finalize =>
409	if ct=0 then
410	write (l,string'("Dlen ;" & integer'image(dlen) & ";Finalize of Proc n°; " & image(MyRank) & "; started at ; " & time'image(now)));
411	report l.all;
412	writeline (f, l) ;
413	end if;
414
415	if ct=0 then
416	RunState<=start;
417	write (l,string'("Dlen ;" & integer'image(dlen) & ";Finalize of Proc n°; " & image(MyRank) & "; ended at ; " & time'image(now)));
418	report l.all;
419	writeline (f, l) ;
420	file_close(f);
421	end if;
422
423	when st_timeout =>
424
425	--if ram_busy='1' then
426	RunState<=start;
427	--end if
428
429	RunState<=start;
430	end case;
431	pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16));
432	pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16));
433	end if;
434	end if;
435
436	end process pPutGet;
437
438	majPutGet:process (RunState,pe_ram_do,sram,Lib_Init)
439
440	begin
441	case RunState is
442	when start =>
443
444	PE_Ram_we<='0';
445	PE_Ram_ena<='0';
446	PE_Ram_enb<='0';
447	--PE_Instr_En<='0';
448
449	when fillmem =>
450	PE_Ram_we<='1';
451	PE_Ram_ena<='1';
452
453	PE_Ram_enb<='0';
454	--PE_Instr_En<='0';
455	when nextfill =>
456	PE_Ram_we<='1';
457	PE_Ram_ena<='1';
458	PE_Ram_enb<='0';
459
460	when InitApp =>
461	-- PE_Ram_we<='1';
462	-- PE_Ram_ena<='1';
463	-- PE_Ram_enb<='0';
464	PE_Ram_we<=sram.we;
465	PE_Ram_ena<=sram.ena;
466	PE_Ram_enb<=sram.enb;
467
468
469	when GetRank =>
470
471	PE_Ram_we<=sram.we;
472	PE_Ram_ena<=sram.ena;
473	PE_Ram_enb<=sram.enb;
474	when WinCreate =>
475
476	PE_Ram_we<=sram.we;
477	PE_Ram_ena<=sram.ena;
478	PE_Ram_enb<=sram.enb;
479
480
481	--positionnement du mot de longueur des données
482
483
484	when putdata =>
485	srcadr0<=X"00";
486	srcadr1<=X"01";
487	destadr0<=X"00";
488	destadr1<=X"02";
489	PE_Ram_we<=sram.we;
490	PE_Ram_ena<=sram.ena;
491	PE_Ram_enb<=sram.enb;
492
493	when getdata =>
494	PE_Ram_we<=sram.we;
495	PE_Ram_ena<=sram.ena;
496	PE_Ram_enb<=sram.enb;
497
498	when Wincompleted =>
499	PE_Ram_we<=sram.we;
500	PE_Ram_ena<=sram.ena;
501	PE_Ram_enb<=sram.enb;
502
503	when finalize =>
504
505	PE_Ram_we<='0';
506	PE_Ram_ena<='0';
507	PE_Ram_enb<='0';
508
509
510	when st_timeout =>
511	PE_Ram_we<='0';
512	PE_Ram_ena<='0';
513	PE_Ram_enb<='0';
514
515
516	end case;
517
518	end process majPutGet ;
519	end Behavioral;
520

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