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load_instr.vhd @ 43

Last change on this file since 43 was 15, checked in by rolagamo, 12 years ago

File size: 9.4 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer: GAMOM NGOUNOU
4	--
5	-- Create Date: 04:57:14 07/15/2012
6	-- Design Name:
7	-- Module Name: load_instr - Behavioral
8	-- Project Name: MPI CORE
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: Ce mdule permet de charger une instruction dans le FIFO 1
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	library NocLib;
22	use IEEE.STD_LOGIC_1164.ALL;
23
24	-- Uncomment the following library declaration if using
25	-- arithmetic functions with Signed or Unsigned values
26	use IEEE.NUMERIC_STD.ALL;
27	use NocLib.CoreTypes.all;
28	-- Uncomment the following library declaration if instantiating
29	-- any Xilinx primitives in this code.
30	--library UNISIM;
31	--use UNISIM.VComponents.all;
32
33	entity load_instr is
34	Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
35	Instruction_en : in STD_LOGIC;
36
37	clk : in STD_LOGIC;
38	reset : in STD_LOGIC;
39	dma_rd_grant : in STD_LOGIC;
40	dma_rd_request : out STD_LOGIC:='0';
41	instruction_ack : out STD_LOGIC:='0';
42	fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0);
43	fifo_wr :out std_logic:='0';
44	copying :out std_logic:='0';
45	fifo_full : in STD_LOGIC;
46	ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
47	ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0);
48	Ram_rd_en : out std_logic);
49	end load_instr;
50
51	architecture Behavioral of load_instr is
52	--déclaration des types manipulés
53	type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout);
54	--déclaration des signaux
55	signal Ram_address_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
56	--signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM
57	signal Base_Adr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
58
59	signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée
60	signal fifo_din_i:std_logic_vector(WORD-1 downto 0):=(others=>'Z');
61	signal fifo_wr_i :std_logic:='0';
62	signal base_adrset_i : std_logic:='0';
63	signal instruction_ack_i :std_logic:='0';
64	signal Dma_rd_request_i :std_logic:='0';
65	signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE
66	signal etloadinst,next_loadinst : typ_loadinst;
67	begin
68	SYNC_PROC: process (clk)
69	begin
70	if rising_edge(clk) then
71	if (reset = '1') or instruction_en='0' then
72	etloadinst <= init;
73	Base_adrSet<= '0';
74	dma_rd_request<='0';
75	instruction_ack<='0';
76	else
77	etloadinst <= next_loadinst;
78	fifo_din <= fifo_din_i;
79	Base_AdrSet<=Base_adrSet_i;
80	ram_address_rd<=ram_address_i;
81	dma_rd_request<=dma_rd_request_i;
82	instruction_ack<=instruction_ack_i;
83	count<=count_i;
84
85
86	-- assign other outputs to internal signals
87	end if;
88	end if;
89	end process;
90
91	--
92	OUTPUT_DECODE: process (etloadinst,Count_i,Ram_data,Dma_rd_grant,fifo_wr_i,Ram_address_i)
93	variable Adr_inst1,adr_inst2 : natural;
94	begin
95	--insert statements to decode internal output signals
96	--below is simple example
97	case etloadinst is
98	when init =>
99	Dma_rd_request_i<='0';
100	fifo_wr<='0';
101	copying<='0';
102	Ram_rd_en<='0';
103	Instruction_ack_i<='0';
104	fifo_din_i<=(others=>'Z');
105
106	when SetAdr =>
107	Dma_rd_request_i<='0';
108	Instruction_ack_i<='0';
109	fifo_wr<='0';
110	copying<='0';
111	Ram_rd_en<='0';
112
113	fifo_din_i<=(others=>'Z');
114	Base_AdrSet_i<='1';
115
116	when getbus =>
117	fifo_wr<='0';
118	copying<='1';
119	Ram_rd_en<=Dma_rd_grant;
120	Dma_rd_request_i<='1';
121	Instruction_ack_i<='0';
122	fifo_din_i<=(others=>'Z');
123
124	when readptr =>
125	fifo_wr<='0';
126
127	copying<='1';
128	Ram_rd_en<='1';
129	Dma_rd_request_i<='1';
130	Instruction_ack_i<='0';
131	fifo_din_i<=(others=>'Z');
132
133	when readmem =>
134	Dma_rd_request_i<='1';
135	copying<='1';
136	Ram_rd_en<='1';
137	fifo_wr<=fifo_wr_i;
138	fifo_din_i<=Ram_data;
139	Instruction_ack_i<='0';
140
141	when freebus =>
142	Dma_rd_request_i<='0';
143	fifo_wr<='0';
144	copying<='0';
145	Ram_rd_en<='0';
146	Instruction_ack_i<='1';
147	fifo_din_i<=(others=>'Z');
148
149	when st_timeout =>
150	Dma_rd_request_i<='0';
151	fifo_wr<='0';
152	copying<='0';
153	Ram_rd_en<='0';
154	Instruction_ack_i<='0';
155	fifo_din_i<=(others=>'Z');
156	end case;
157	end process;
158
159	NEXT_STATE_DECODE: process (etloadinst, Base_AdrSet,Ram_data,Instruction,instruction_en, fifo_full,dma_rd_grant,count)
160	variable ptr : std_logic_vector(ADRLEN-1 downto 0);
161	variable timeout: natural range 0 to 255;
162	variable Base_AD,ADRtmp,iptr : natural range 0 to 65535;
163	begin
164	--declare default state for next_state to avoid latches
165	next_loadinst <= etloadinst; --default is to stay in current state
166	--insert statements to decode next_state
167	--below is a simple example
168	case (etloadinst) is
169	when init => if base_adrset='1' and Instruction_en='1' then
170
171	next_loadinst<=getbus;
172	elsif Instruction_en='1' then
173	next_loadinst<=Setadr;
174	else
175	next_loadinst<=init;
176	end if;
177	fifo_wr_i<='0';
178	count_i<=0;
179	When Setadr => if Base_adrSet='0' then
180	Base_Adr<=instruction & X"00"; --récupération des bits de poids forts de l'instruction
181	--
182	end if;
183	next_loadinst<=init;
184	Ram_address_i<=(others=>'Z');
185	count_i<=0;
186	when getbus =>
187	BASE_AD:=to_integer(unsigned(base_adr));
188	if dma_rd_grant = '1' then
189	next_loadinst <= readptr;
190	count_i<=0;
191	-- prépare la prochaine lecture
192
193
194	else
195
196	end if;
197	Ram_address_i<=(others=>'Z');
198
199	When readptr =>
200	if dma_rd_grant = '1' then --s'assurer que le bus est disponible
201
202
203
204	if count=0 then
205	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16));
206	count_i <=count+1;
207	elsif count=1 then-- attend que la donnée soit positionnée
208	count_i <=count+1;
209
210	elsif count=2 then
211	count_i <=count+1;
212
213	elsif count=3 then
214	ptr(Word-1 downto 0):=Ram_data;
215	Ram_address_i<=incr_vec(ram_address_i,'1');
216	count_i <=count+1;
217	elsif count=4 then
218	count_i <=count+1;
219	elsif count=5 then
220	ptr(15 downto 8):=Ram_data;
221	--count_i <=count+1;
222	--elsif count=6 then
223	--ptr(15 downto 8):=Ram_data;
224	count_i<=0;
225	timeout:=0;
226	next_loadinst <= readmem;
227	else
228
229	end if;
230
231	else
232	timeout:=timeout+1;
233	end if;
234	when readmem =>
235	if dma_rd_grant = '1' then --s'assurer que le bus est disponible
236	if fifo_full='0' then
237
238	if count=0 then
239	iptr:=to_integer(unsigned(ptr));
240	AdrTmp:=iptr;
241	count_i <=count+1;
242	fifo_wr_i<='0';
243	elsif count=1 then
244	count_i <=count+1;
245	fifo_wr_i<='0';
246	elsif count=2 then
247	count_i <=count+1;
248	AdrTmp:=iptr+1; --incrémentation de l'adresse
249	fifo_wr_i<='0';
250	elsif count=3 then
251	count_i <=count+1;
252	fifo_wr_i<='1'; --écriture de la donnée dans le fifo
253	elsif count=4 then
254	fifo_wr_i<='0';
255
256	count_i <=count+1;
257	elsif count=5 then
258	fifo_wr_i<='1'; --lecture de la donnée 2
259	count_i <=count+1;
260	AdrTmp:=iptr+2;
261	elsif count=6 then
262	count_i <=count+1;
263	fifo_wr_i<='0';
264	elsif count=7 then
265	count_i <=count+1;
266	fifo_wr_i<='0';
267	elsif count=8 then
268	fifo_wr_i<='1';--lecture de la donnée 3
269	count_i <=count+1;
270	AdrTmp:=iptr+3;
271	elsif count =9 then
272	count_i <=count+1;
273
274	fifo_wr_i<='0';
275	elsif count=10 then
276	count_i <=count+1;
277	fifo_wr_i<='0';
278
279	elsif count=11 then
280	fifo_wr_i<='1'; --lecture de la donnée 4
281	count_i <=count+1;
282	ADRTmp:=iptr+4;--incrémente l'adresse
283	elsif count =12 then
284	count_i <=count+1;
285
286	fifo_wr_i<='0';
287	elsif count=13 then
288	count_i <=count+1;
289	fifo_wr_i<='0';
290	elsif count=14 then
291	fifo_wr_i<='1';--lecture de la donnée 5
292	count_i <=count+1;
293	ADRtmp:=iptr+5;
294	elsif count =15 then
295	count_i <=count+1;
296	fifo_wr_i<='0';
297	elsif count=16 then
298	count_i <=count+1;
299	fifo_wr_i<='0';
300	elsif count=17 then
301	fifo_wr_i<='1';--lecture de la donnée 6
302	count_i <=count+1;
303	next_loadinst <= freebus;
304	end if;
305
306	Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16));
307	end if;
308
309	else
310	timeout:=timeout+1;
311	if timeout=50 then
312	next_loadinst<=st_timeout;
313	end if;
314	Ram_address_i<=(others=>'Z'); -- le bus n'est pas libre
315
316	end if;
317
318	when freebus =>
319	fifo_wr_i<='0';
320	count_i<=0;
321	Ram_address_i<=(others=>'Z');
322	if instruction_en='0' then
323	next_loadinst <= init;
324	end if;
325	when st_timeout =>
326	fifo_wr_i<='0';
327	Ram_address_i<=(others=>'Z');
328	next_loadinst<=init;
329	count_i<=0;
330	end case;
331	end process;
332
333	end Behavioral;
334

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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/load_instr.vhd @ 43

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