source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.02/EX2_FSM.vhi @ 37

-- VHDL Instantiation Created from source file EX2_FSM.vhd -- 05:55:35 06/21/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

        COMPONENT EX2_FSM
        PORT(
                dma_grant : IN std_logic;
                fifo_full : IN std_logic;
                switch_data_available : IN std_logic;
                switch_port_out_data : IN std_logic_vector(7 downto 0);
                packet_ack : IN std_logic;
                clk : IN std_logic;
                reset : IN std_logic;          
                dma_request : OUT std_logic;
                ram_address : OUT std_logic_vector(15 downto 0);
                fifo_data : OUT std_logic_vector(7 downto 0);
                fifo_wr_en : OUT std_logic;
                packet_received : OUT std_logic;
                barrier_completed : OUT std_logic;
                switch_port_out_rd_en : OUT std_logic
                );
        END COMPONENT;

        Inst_EX2_FSM: EX2_FSM PORT MAP(
                dma_grant => ,
                fifo_full => ,
                switch_data_available => ,
                switch_port_out_data => ,
                dma_request => ,
                ram_address => ,
                fifo_data => ,
                fifo_wr_en => ,
                packet_received => ,
                packet_ack => ,
                barrier_completed => ,
                clk => ,
                reset => ,
                switch_port_out_rd_en => 
        );