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PE.vhd @ 37

Last change on this file since 37 was 37, checked in by rolagamo, 12 years ago

File size: 13.1 KB

Line
1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 21:20:54 07/16/2012
6	-- Design Name:
7	-- Module Name: PE - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	library NocLib ;
23	--use IEEE.STD_LOGIC_ARITH.ALL;
24	--use IEEE.STD_LOGIC_UNSIGNED.ALL;
25	use NocLib.CoreTypes.all;
26	use work.Packet_type.all;
27	use work.MPI_RMA.all;
28	use IEEE.NUMERIC_STD.ALL;
29
30
31	entity PE is
32	Generic (DestId : natural );
33	Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0);
34	Instruction_en : out STD_LOGIC;
35	Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0);
36	clk : in STD_LOGIC;
37	reset : in STD_LOGIC;
38	Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0);
39	Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0);
40	Core_RAM_WE : in STD_LOGIC;
41	Core_RAM_EN : in STD_LOGIC;
42	--Core_RAM_ENB : in STD_LOGIC;
43	Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
44	Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
45	Core_Hold_req : in STD_LOGIC;
46	Core_Hold_Ack : out STD_LOGIC);
47	end PE;
48
49	architecture Behavioral of PE is
50	COMPONENT RAM_v
51	generic (width : positive;size :positive);
52	PORT(
53	clka : IN std_logic;
54	clkb : IN std_logic;
55	wea : IN std_logic;
56	ena : IN std_logic;
57	enb : IN std_logic;
58	addra : IN std_logic_vector;
59	addrb : IN std_logic_vector;
60	dia : IN std_logic_vector;
61	dob : OUT std_logic_vector
62	);
63	END COMPONENT;
64	--données du programme PE
65	--signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0');
66	signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0';
67	signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic;
68	signal pe_instr_en,pe_hold_ack: std_logic:='0';
69	signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
70	signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
71	signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
72	signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
73	signal sram : typ_dpram;
74
75	signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0);
76	signal dpid,dpid_i : natural range 0 to 15:=DestId;
77	signal MyRank :std_logic_vector(3 downto 0);
78	signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque
79	signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée
80	signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO
81	signal Lib_Init : std_logic; -- l'initialisation est terminée
82	--signaux pour la gestion de la MAE
83	type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,GetRank1,GetRank2,GetRank3,writeptr,InstrCopy,
84	putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout);
85	signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées
86	signal count,count_i : natural range 0 to 15:=0;
87
88
89	signal RunState : typ_mae;
90	signal Ram_busy :std_logic:='0';
91	begin
92	Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN)
93	PORT MAP(
94	clka =>clk,
95	clkb => clk,
96	wea => ram_we,
97	ena => ram_ena,
98	enb => ram_enb,
99	addra => ram_addra,
100	addrb =>ram_addrb,
101	dia => ram_din,
102	dob => ram_do
103	);
104	--================================================================
105	--MUX de la RAM
106
107	Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr,
108	Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do,
109	Pe_ram_din,Pe_ram_we )
110	begin
111	case ramsel is
112
113	when '1' =>
114	ram_addra <= Core_ram_address_wr ;
115	ram_addrb <= Core_ram_address_rd ;
116	ram_ena <= Core_ram_en;
117	ram_enb <= Core_ram_en;
118	ram_we<= Core_ram_we;
119	ram_din <= Core_ram_data_in;
120	pe_ram_do<=(others=>'Z');
121	Core_ram_data_out<=ram_do;
122
123	when others =>
124	ram_addra <= pe_ram_addra;
125	ram_addrb <= pe_ram_addrb;
126	ram_ena <= pe_ram_ena;
127	ram_enb <= pe_ram_enb;
128	ram_we<= pe_ram_we;
129	ram_din <=pe_ram_din;
130	Core_ram_data_out<=(others=>'Z');
131	pe_ram_do<=ram_do;
132	end case ;
133	end process ;
134
135
136
137	Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --******A changer ********
138	--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce
139	-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!!
140	instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8));
141
142	dpid<=dpid_i;
143
144	Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié
145	Lib_init<=Core_Pushout(4); -- Initialized
146	-- pe_hold_req<=Core_hold_req;
147	--Core_hold_ack<=pe_hold_ack;
148
149	hold:process (Core_Hold_Req,clk,reset)
150	begin
151	if rising_edge(clk) then
152	if reset='1' then
153	Core_Hold_Ack<='0';
154	else
155	if Core_Hold_Req='1' then
156
157	ramsel<=not(ram_busy);
158	Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération
159	Pe_hold_ack<=not(ram_busy);
160	else
161	Core_Hold_Ack<='0';
162	ramsel<='0';
163	Pe_hold_ack<='0';
164
165	end if;
166	end if;
167	end if;
168	end process hold;
169	--=======================================================================
170
171
172
173	--=======================================================================
174	--MAE du PE
175	--=======================================================================
176
177	pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do)
178
179	constant DATAPTR : natural :=256;
180	variable bfill,destrank,pid,mport : natural range 0 to 15;
181	variable fsrc,ret : natural range 0 to 15:=0;
182	variable timeout,ct,dlen : natural range 0 to 255;
183	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
184	variable iack : std_logic:='0';
185	variable adresse,adresse_rd :natural range 0 to 65536;
186	variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');
187	begin
188	--=== Partie combinatoire du process ===================================
189	Libr.Instr_ack<=Core_pushout(0);
190	Libr.InitOk<=Core_pushout(4);
191	Libr.Hold_Req<=Core_Hold_req;
192	Libr.Hold_Ack<=Pe_Hold_Ack;
193	Libr.RamSel<=RamSel;
194	sram.data_out<=PE_ram_do;
195	--=== Fin de la partie combinatoire du process ==========================
196	if (clk'event and clk='1') then
197	if reset='1' then
198	RunState<=start;
199
200	else
201
202	Libr.Instr_ack<=Core_pushout(0);
203	Libr.InitOk<=Core_pushout(4);
204	Libr.Hold_Req<=Core_Hold_req;
205	Libr.Hold_Ack<=Pe_Hold_Ack;
206	Libr.RamSel<=RamSel;
207	sram.data_out<=PE_ram_do;
208	case RunState is
209	when start =>
210	Dcount<=0;
211	if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
212	RunState<=Fillmem;
213	end if;
214	Ram_busy<='0';
215	PE_Instr_En<='0';
216	iack:='0';
217	adresse:=DATAPTR;
218
219	adresse_rd:=0;
220	timeout:=0;
221	dcount<=0;
222	when Fillmem =>
223	if Ramsel='0' then
224
225
226
227	PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
228	PE_Instr_En<='0';
229	dcount<=dcount+1;
230
231	if dcount=200 then
232	bfill:=bfill+1;
233
234	if bfill=4 then
235	RunState<=InitApp;
236	else
237	RunState<=nextfill;
238	end if;
239	else
240	adresse:=adresse+1;
241	RunState<=Fillmem;
242	end if;
243	else -- attente de la libéraion de la mémoire
244	timeout:=timeout+1;
245	if timeout=100 then
246	RunState<=st_timeout;
247	end if;
248
249	end if;
250	when nextfill => --prépare le prochain bloc mémoire qui sera rempli
251	adresse:=200*bfill;
252	dcount<=0;
253	ct:=0;
254	RunState<=Fillmem;
255	PE_Instr_En<='0';
256	when InitApp =>
257	--code pour Init
258
259	pMPI_Init(ct,Libr,Clk,SRam);
260	PE_Instr_EN<=Libr.instr_en;
261	adresse:=to_integer(unsigned(sram.addr_wr));
262	adresse_rd:=to_integer(unsigned(sram.addr_rd));
263	PE_ram_din<=sram.data_in;
264
265	--if Libr.InitOk='1' then
266	if ct=0 then
267	RunState<=GetRank1;
268	end if;
269
270
271	when writeptr =>
272
273	When InstrCopy =>
274
275
276	when InitCompleted =>
277
278	when GetRank1 =>
279
280	pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
281	if ct=0 then
282	RunState<=PutData2;
283	end if;
284	adresse_rd:=to_integer(unsigned(sram.addr_rd));
285
286	when GetRank2 =>
287	adresse_rd:=CORE_INIT_ADR+1;
288	if ramsel='0' then
289	RunState<=Getrank3;
290	end if;
291	when GetRank3=>
292	adresse_rd:=CORE_INIT_ADR+1;
293	if ramsel='0' then
294	RunState<=putdata2;
295	end if;
296	when putdata => --construire le packet pour le Put
297
298
299	when putdata2 =>
300
301	if unsigned(MyRank) = 0 then
302	Destrank:=1;
303	else
304	DestRank:=0;
305	end if;
306	dlen:=200; --- to_integer(unsigned(datalen));
307	SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
308	DestAdr:=X"2000";
309
310	pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win);
311	adresse:=to_integer(unsigned(sram.addr_wr));
312	adresse_rd:=to_integer(unsigned(sram.addr_rd));
313	PE_Instr_EN<=Libr.instr_en;
314	PE_ram_din<=sram.data_in;
315	dcount<=ct;
316
317	if ct=0 then
318	RunState<=GetData;
319	end if;
320
321
322	when putcompleted =>
323
324	when getdata => --positionnement du mot de longueur des données
325
326	dlen:=200; --- to_integer(unsigned(datalen));
327	SrcAdr:=X"0120";
328	DestAdr:=X"4000";
329
330	pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win);
331	adresse:=to_integer(unsigned(sram.addr_wr));
332	adresse_rd:=to_integer(unsigned(sram.addr_rd));
333	PE_Instr_EN<=Libr.instr_en;
334	PE_ram_din<=sram.data_in;
335	dcount<=ct;
336
337	if ct=0 then
338	RunState<=terminate;
339	end if;
340	when getdata2 =>
341
342
343
344
345	when getcompleted =>
346
347
348
349	when terminate =>
350
351
352	RunState<=start;
353
354	when st_timeout =>
355
356	--if ram_busy='1' then
357	RunState<=start;
358	--end if
359
360	RunState<=start;
361	end case;
362	pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16));
363	pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16));
364	end if;
365	end if;
366
367	end process pPutGet;
368
369	majPutGet:process (RunState,pe_ram_do,sram,Lib_Init)
370
371	begin
372	case RunState is
373	when start =>
374
375	PE_Ram_we<='0';
376	PE_Ram_ena<='0';
377	PE_Ram_enb<='0';
378	--PE_Instr_En<='0';
379
380	when fillmem =>
381	PE_Ram_we<='1';
382	PE_Ram_ena<='1';
383
384	PE_Ram_enb<='0';
385	--PE_Instr_En<='0';
386	when nextfill =>
387	PE_Ram_we<='1';
388	PE_Ram_ena<='1';
389	PE_Ram_enb<='0';
390
391	when InitApp =>
392	-- PE_Ram_we<='1';
393	-- PE_Ram_ena<='1';
394	-- PE_Ram_enb<='0';
395	PE_Ram_we<=sram.we;
396	PE_Ram_ena<=sram.ena;
397	PE_Ram_enb<=sram.enb;
398
399	when Initcompleted =>
400
401	PE_Ram_ena<=Lib_Init;
402	PE_Ram_we<='1';
403	PE_Ram_enb<='1';
404
405	when GetRank1 =>
406
407	PE_Ram_we<=sram.we;
408	PE_Ram_ena<=sram.ena;
409	PE_Ram_enb<=sram.enb;
410	when GetRank2 =>
411	PE_Ram_ena<='0';
412	--lecture effective du rang
413	PE_Ram_enb<='1';
414	--MyRank<=PE_ram_do(3 downto 0);
415	when GetRank3 =>
416	PE_Ram_ena<='0';
417	--lecture effective du rang
418	PE_Ram_enb<='1';
419	--MyRank<=PE_ram_do(3 downto 0);
420	when writeptr =>
421	PE_Ram_we <='1'; --écriture dans la RAM
422	PE_Ram_ena <='1';
423
424	PE_Ram_enb <='0';
425	-- dcount<=dcount+1;
426
427	--PE_Instr_En<='0';
428	when InstrCopy => --instruction copy
429	PE_Ram_we<='0';
430	PE_Ram_ena<='0';
431	PE_Ram_enb<='0';
432
433
434	when putdata => --positionnement du mot de longueur des données
435	--dcount<=0;
436	srcadr0<=X"00";
437	srcadr1<=X"01";
438	destadr0<=X"00";
439	destadr1<=X"02";
440	PE_Ram_we<='0';
441	PE_Ram_ena<='0';
442
443	PE_Ram_enb<='1';
444
445	when putdata2 =>
446	-- PE_Ram_we <='1'; --écriture dans la RAM
447	-- PE_Ram_ena <='1';
448	-- PE_Ram_enb <='0';
449	srcadr0<=X"00";
450	srcadr1<=X"01";
451	destadr0<=X"00";
452	destadr1<=X"02";
453	PE_Ram_we<=sram.we;
454	PE_Ram_ena<=sram.ena;
455	PE_Ram_enb<=sram.enb;
456
457	when putcompleted =>
458	PE_Ram_we <='1';
459	PE_Ram_ena <='1';
460	-- lecture du résultat
461	PE_Ram_enb <='1';
462	--PE_Instr_En<='1';
463	when getdata =>
464	PE_Ram_we<=sram.we;
465	PE_Ram_ena<=sram.ena;
466	PE_Ram_enb<=sram.enb;
467
468
469	when getdata2 =>
470	PE_Ram_we <='1'; --écriture dans la RAM
471	PE_Ram_ena <='1';
472
473	PE_Ram_enb <='0';
474
475	when getcompleted =>
476	PE_Ram_we <='1';
477	PE_Ram_ena <='1';
478
479	PE_Ram_enb <='1';
480
481	when terminate =>
482
483	PE_Ram_we<='0';
484	PE_Ram_ena<='0';
485	PE_Ram_enb<='0';
486
487
488	when st_timeout =>
489	PE_Ram_we<='0';
490	PE_Ram_ena<='0';
491	PE_Ram_enb<='0';
492
493
494	end case;
495
496	end process majPutGet ;
497	end Behavioral;
498

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