[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: KIEGAING EMMANUEL |
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| 4 | -- GAMOM ROLAND CHRISTIAN |
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| 5 | -- |
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| 6 | -- Create Date: 04:39:43 05/21/2011 |
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| 7 | -- Design Name: |
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| 8 | -- Module Name: DMA_ARBITER - Behavioral |
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| 9 | -- Project Name: |
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| 10 | -- Target Devices: |
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| 11 | -- Tool versions: |
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| 12 | -- Description: |
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| 13 | -- gestionnaire DMA pour le port secodaire de la RAM true dual port des mémoire |
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| 14 | -- privée de chaque noeud |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: 09/07/2012 |
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| 18 | -- Revision 1.01 - File Created |
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[64] | 19 | -- Revision 1.2 - 19/03/2013 |
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| 20 | -- Correction de bugs et optimisation du nombre de cycles |
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| 21 | -- Création d'un testbench |
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[15] | 22 | -- Additional Comments: Ce module pourra être optimisé pour générer les adresses automatiquement |
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| 23 | -- par le controleur DMA lorsqu'il est sollicité par la périphérie |
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| 24 | -- |
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| 25 | ---------------------------------------------------------------------------------- |
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| 26 | library IEEE; |
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| 27 | library NocLib; |
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| 28 | use IEEE.STD_LOGIC_1164.ALL; |
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| 29 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 30 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 31 | use IEEE.numeric_std.all; |
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| 32 | use NocLib.CoreTypes.all; |
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| 33 | ---- Uncomment the following library declaration if instantiating |
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| 34 | ---- any Xilinx primitives in this code. |
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| 35 | --library UNISIM; |
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| 36 | --use UNISIM.VComponents.all; |
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| 37 | |
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| 38 | entity DMA_ARBITER is |
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| 39 | Port ( dma_rd_request : in STD_LOGIC_VEctor (3 downto 0):=(others=>'0'); |
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| 40 | data_wr_in : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 41 | data_rd_out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 42 | address_rd : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); --adresse pour lecture |
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| 43 | address_wr : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse pour écriture |
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| 44 | address_out_wr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse de sortie du DMA Arbiter |
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| 45 | address_out_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 46 | ram_en : out STD_LOGIC; -- |
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| 47 | ram_we : out STD_LOGIC; |
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| 48 | data_wr_mem : out STD_LOGIC_VECTOR (Word-1 downto 0); -- donnée en sortie écriture |
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| 49 | data_rd_mem : in STD_LOGIC_VECTOR (Word-1 downto 0); -- données en sortie lecture |
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| 50 | dma_wr_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation d'écriture |
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| 51 | hold_req : out STD_Logic; --requete vers application |
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| 52 | hold_ack : in STD_Logic; --autorisation par l'application |
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| 53 | clk : in std_logic; |
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| 54 | reset : in std_logic; |
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| 55 | dma_rd_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation de lecture |
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| 56 | dma_wr_request : in STD_LOGIC_vector(3 downto 0):=(others=>'0')); -- demande de lecture |
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| 57 | end DMA_ARBITER; |
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| 58 | |
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| 59 | architecture Behavioral of DMA_ARBITER is |
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| 60 | type fsm_states is (idle,wait_ack,arbiter_ack, writing,ReadWrite,reading);-- definition du type etat pour le codage des etats des fsm |
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| 61 | signal dmac_state : fsm_states; |
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| 62 | |
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| 63 | signal prio_rd,prio_wr:std_logic_vector(3 downto 0);--vecteur de bits de priorité |
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| 64 | signal pri_rd,pri_wr : natural range 0 to 3; -- stocke le numéro du module qui a la priorité |
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| 65 | signal dma_rd_logic : std_logic_vector(3 downto 0):=(others=>'0'); |
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| 66 | signal dma_wr_logic : std_logic_vector(3 downto 0):=(others=>'0'); |
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[64] | 67 | signal dma_rd_latch,dma_wr_latch: std_logic_vector(3 downto 0):=(others=>'0'); |
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[15] | 68 | signal dma_req_wr, dma_req_rd : std_logic; |
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[64] | 69 | signal last_grant_rd,last_grant_wr : STD_LOGIC_vector(3 downto 0):=(others=>'0'); |
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[15] | 70 | signal tmp :std_logic_vector(3 downto 0):="0000"; |
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| 71 | |
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| 72 | begin |
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| 73 | --========================================================================== |
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| 74 | ---le MUX qui contrôle les adresses est géré à l'extérieur du contrôleur DMA |
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[64] | 75 | dma_sync: process (clk) |
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| 76 | begin |
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[15] | 77 | data_rd_out<=data_rd_mem ; |
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| 78 | data_wr_mem <= data_wr_in; |
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| 79 | address_out_rd <= address_rd; |
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| 80 | address_out_wr <= address_wr; |
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[64] | 81 | |
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| 82 | end process; |
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| 83 | --dma_rd_grant<= dma_rd_logic; |
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| 84 | --dma_wr_grant<= dma_wr_logic; |
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| 85 | dma_rd_grant<= dma_rd_latch; |
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| 86 | dma_wr_grant<= dma_wr_latch; |
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[15] | 87 | --========================================================================== |
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| 88 | |
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| 89 | --Déterminer si une requête HOLD doit être émise vers l'application pour la libération du |
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| 90 | --bus mémoire |
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| 91 | tmp<=(others =>'0'); |
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| 92 | |
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| 93 | --for i in 0 to 3 loop |
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| 94 | --dma_req_wr<=dma_req_wr or dma_wr_request(i); |
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| 95 | --loop; |
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| 96 | |
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| 97 | --for i in 0 to 3 loop |
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| 98 | -- dma_req_rd<=dma_req_rd or dma_rd_request(i); -- construire le signal request vers l'extérieur |
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| 99 | --loop; |
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[64] | 100 | hold_req<='1' when dma_req_rd='1' or dma_req_wr='1' else '0'; --envoyer un Hold vers l'application |
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[15] | 101 | |
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| 102 | |
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| 103 | -- machine à etat du DMAC |
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[64] | 104 | dmac_process : process(clk,reset) |
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[15] | 105 | --variable tmp : natural range 0 to 15; |
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| 106 | variable tmp_rd,tmp_wr: std_logic_vector(3 downto 0); |
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| 107 | variable req_rd,req_wr : std_logic:='0' ; |
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| 108 | |
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| 109 | begin |
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| 110 | if rising_edge(clk) then |
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| 111 | if reset = '1' then |
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| 112 | dmac_state<= idle; |
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| 113 | |
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| 114 | prio_rd <="0001"; -- au debut priorité lecture au premier module |
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| 115 | prio_wr <="0010"; -- au debut priorité ecriture au deuxième module |
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| 116 | pri_rd<=0;--index de la priorité |
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| 117 | pri_wr<=1; |
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| 118 | req_rd:='0'; |
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| 119 | req_wr:='0'; |
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| 120 | else |
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[64] | 121 | if req_wr='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité en écriture |
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[15] | 122 | case dma_wr_request is |
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| 123 | when "0001" => pri_wr<=0; |
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| 124 | prio_wr<="0001"; |
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| 125 | req_wr:='1'; |
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| 126 | dma_req_wr<= '1'; |
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| 127 | dma_wr_logic <="0001"; |
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| 128 | when "0010" => pri_wr<=1; |
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| 129 | prio_wr<="0010"; |
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| 130 | req_wr:='1'; |
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| 131 | dma_req_wr<= '1'; |
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| 132 | dma_wr_logic <="0010"; |
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| 133 | when "0100" => pri_wr<=2; |
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| 134 | prio_wr<="0100"; |
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| 135 | req_wr:='1'; |
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| 136 | dma_req_wr<= '1'; |
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| 137 | dma_wr_logic <="0100"; |
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| 138 | when "1000" => pri_wr<=3; |
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| 139 | prio_wr<="1000"; |
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| 140 | req_wr:='1'; |
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| 141 | dma_req_wr<= '1'; |
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| 142 | dma_wr_logic <="1000"; |
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| 143 | |
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[35] | 144 | when others => |
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[64] | 145 | if req_rd='1' then --demande simultané de lecture et d'écriture |
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[35] | 146 | |
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[39] | 147 | if dma_rd_request(pri_rd)='1' then |
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| 148 | pri_wr<=pri_rd; |
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| 149 | req_wr:='1'; |
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[41] | 150 | for i in 0 to 3 loop |
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| 151 | if i=pri_rd then |
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| 152 | prio_wr(i)<='1'; |
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| 153 | dma_wr_logic(i)<='1'; |
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| 154 | else |
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| 155 | prio_wr(i)<='0'; |
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| 156 | dma_wr_logic(i)<='0'; |
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| 157 | end if; |
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| 158 | end loop; |
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[39] | 159 | |
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[41] | 160 | |
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[39] | 161 | end if; |
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| 162 | |
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[64] | 163 | else --on affecte l'accè à la mémoire suivant le round robbin |
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[39] | 164 | tmp_wr:= (dma_wr_request and prio_wr) ; |
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| 165 | dma_wr_logic <=tmp_wr; |
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| 166 | |
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| 167 | req_wr:= not(All_zeros(tmp_wr)); |
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| 168 | dma_req_wr<= not(All_zeros(tmp_wr)); |
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| 169 | end if; |
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[15] | 170 | -- la priorité est circulaire et décale à chaque coup d'horloge |
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[35] | 171 | if req_wr='0' then |
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| 172 | prio_wr<=rol_vec(prio_wr); |
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| 173 | if pri_wr=3 then |
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| 174 | pri_wr<=0; |
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| 175 | Prio_wr<="0001"; |
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| 176 | else |
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| 177 | pri_wr<=pri_wr+1; |
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| 178 | end if; |
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| 179 | end if; |
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[15] | 180 | end case; |
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[64] | 181 | else --req_wr='1' |
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| 182 | |
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| 183 | --demande simultané de lecture et d'écriture |
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| 184 | |
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| 185 | if dma_rd_request(pri_wr)='1' then |
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| 186 | pri_rd<=pri_wr; |
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| 187 | req_rd:='1'; |
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| 188 | prio_rd<=prio_wr; |
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| 189 | -- for i in 0 to 3 loop |
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| 190 | -- if i=pri_rd then |
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| 191 | -- prio_wr(i)<='1'; |
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| 192 | -- dma_wr_logic(i)<='1'; |
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| 193 | -- else |
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| 194 | -- prio_wr(i)<='0'; |
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| 195 | -- dma_wr_logic(i)<='0'; |
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| 196 | -- end if; |
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| 197 | -- end loop; |
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| 198 | |
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| 199 | end if; |
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| 200 | |
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[15] | 201 | end if; |
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| 202 | |
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[64] | 203 | if req_rd='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité |
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[15] | 204 | case dma_rd_request is |
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| 205 | when "0001" => pri_rd<=0; |
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| 206 | prio_rd<="0001"; |
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| 207 | req_rd:='1'; |
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| 208 | dma_req_rd<= '1'; |
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| 209 | dma_rd_logic<="0001"; |
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| 210 | when "0010" => pri_rd<=1; |
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| 211 | prio_rd<="0010"; |
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| 212 | req_rd:='1'; |
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| 213 | dma_req_rd<= '1'; |
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| 214 | dma_rd_logic<="0010"; |
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| 215 | |
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| 216 | when "0100" => pri_rd<=2; |
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| 217 | prio_rd<="0100"; |
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| 218 | req_rd:='1'; |
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| 219 | dma_req_rd<= '1'; |
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| 220 | dma_rd_logic<="0100"; |
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| 221 | |
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| 222 | when "1000" => pri_rd<=3; |
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| 223 | prio_rd<="1000"; |
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| 224 | req_rd:='1'; |
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| 225 | dma_req_rd<= '1'; |
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| 226 | dma_rd_logic<="1000"; |
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| 227 | |
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| 228 | when others => |
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[39] | 229 | --si une demande survient de la part d'un composant déjà acquitté alors celui-ci est prioritaire |
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| 230 | if req_wr='1' then |
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[15] | 231 | |
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[39] | 232 | if dma_rd_request(pri_wr)='1' then |
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| 233 | pri_rd<=pri_wr; |
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| 234 | req_rd:='1'; |
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[41] | 235 | for i in 0 to 3 loop |
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| 236 | if i=pri_wr then |
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| 237 | prio_rd(i)<='1'; |
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| 238 | dma_rd_logic(i)<='1'; |
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| 239 | else |
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| 240 | prio_rd(i)<='0'; |
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| 241 | dma_rd_logic(i)<='0'; |
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| 242 | end if; |
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| 243 | end loop; |
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[39] | 244 | |
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[41] | 245 | |
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[39] | 246 | end if; |
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| 247 | |
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| 248 | else |
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| 249 | tmp_rd:= (dma_rd_request and prio_rd) ; |
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| 250 | dma_rd_logic<=tmp_rd; |
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| 251 | dma_req_rd<= not (All_Zeros(tmp_rd)); |
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| 252 | req_rd:= not (All_Zeros(tmp_rd)); |
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| 253 | end if; |
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[15] | 254 | -- la priorité est circulaire et décale à chaque coup d'horloge |
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[35] | 255 | if req_rd='0' then |
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| 256 | prio_rd<=rol_vec(prio_rd); |
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| 257 | if pri_rd =3 then |
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| 258 | pri_rd<=0; |
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| 259 | prio_rd<="0001"; |
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| 260 | else |
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| 261 | |
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| 262 | pri_rd<=pri_rd+1; |
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| 263 | end if; |
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[15] | 264 | end if; |
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| 265 | end case; |
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| 266 | |
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| 267 | end if; |
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| 268 | |
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| 269 | case dmac_state is |
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| 270 | when idle => if req_rd='1' or req_wr='1' then |
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| 271 | dmac_state<=wait_ack; |
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| 272 | else -- initialiser la priorité |
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| 273 | |
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| 274 | |
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| 275 | req_rd:='0'; |
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| 276 | dma_req_rd<= '0'; |
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| 277 | |
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| 278 | |
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[64] | 279 | |
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[15] | 280 | req_wr:='0'; |
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| 281 | dma_req_wr<= '0'; |
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[64] | 282 | |
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| 283 | dma_wr_logic <="0000"; --aucun accès mémoire n'est accrédité |
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| 284 | dma_rd_logic <="0000"; |
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[15] | 285 | |
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| 286 | end if; |
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[64] | 287 | |
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[15] | 288 | when wait_ack => -- l'application doit autoriser l'utilisation de la RAM par le Core |
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| 289 | if dma_wr_request(pri_wr) ='1' or dma_rd_request(pri_rd) ='1' then |
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| 290 | if hold_ack='1' then |
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[64] | 291 | --dmac_state<=arbiter_ack; |
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| 292 | if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- |
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| 293 | dmac_state <= Readwrite; |
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| 294 | elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then |
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| 295 | dmac_state <= Reading; |
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| 296 | elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then |
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| 297 | dmac_state <= Writing; |
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| 298 | else |
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| 299 | dmac_state<=Idle; |
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| 300 | end if; |
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[15] | 301 | end if; |
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| 302 | else |
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| 303 | |
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| 304 | if dma_wr_request(pri_wr) ='0' then |
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| 305 | req_wr:='0';-- forcer une nouvelle recherche de priorité |
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| 306 | end if; |
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| 307 | |
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| 308 | if dma_rd_request(pri_rd) ='0' then |
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| 309 | req_rd:='0'; |
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| 310 | end if; |
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| 311 | dmac_state<=Idle; |
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| 312 | end if; |
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| 313 | |
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| 314 | |
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[64] | 315 | when arbiter_ack => |
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| 316 | -- if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- |
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| 317 | -- dmac_state <= Readwrite; |
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| 318 | -- elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then |
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| 319 | -- dmac_state <= Reading; |
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| 320 | -- elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then |
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| 321 | -- dmac_state <= Writing; |
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| 322 | -- else |
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[15] | 323 | dmac_state<=Idle; |
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[64] | 324 | -- end if; |
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| 325 | -- cet état a été combiné au précédent pour gagner un cycle |
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[15] | 326 | when Writing => if dma_wr_request(pri_wr) ='1' then |
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| 327 | if hold_ack='1' then |
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| 328 | -- on reste dans cet état |
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| 329 | if dma_rd_request(pri_rd)='1' then |
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| 330 | dmac_state<=ReadWrite; |
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| 331 | else |
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| 332 | req_rd:='0'; |
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| 333 | end if; |
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| 334 | else |
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| 335 | dmac_state<=wait_ack; |
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| 336 | end if; |
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| 337 | elsif dma_rd_request(pri_rd) ='1' then |
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| 338 | dmac_state <= Reading; |
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[64] | 339 | req_wr:='0'; |
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[15] | 340 | else |
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| 341 | dmac_state <= idle; |
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[64] | 342 | req_wr:='0'; |
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[15] | 343 | end if; |
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| 344 | |
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| 345 | |
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| 346 | when ReadWrite => if hold_ack='1' then |
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| 347 | if dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='1' then |
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| 348 | dmac_state <= ReadWrite; |
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| 349 | elsif dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='0' then |
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| 350 | dmac_state <= Writing; |
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| 351 | req_rd:='0'; |
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| 352 | elsif dma_wr_request(pri_wr)='0' and dma_rd_request(pri_rd)='1' then |
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| 353 | dmac_state <= Reading; |
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| 354 | req_wr:='0'; |
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| 355 | else |
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| 356 | dmac_state <= Idle; |
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| 357 | req_rd:='0';req_wr:='0'; |
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| 358 | end if; |
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| 359 | else |
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| 360 | if (dma_wr_request(pri_wr)='1') or (dma_rd_request(pri_rd)='1') then |
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| 361 | dmac_state <= Wait_ack; |
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| 362 | else |
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| 363 | dmac_state <= Idle; |
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| 364 | end if; |
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| 365 | end if; |
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| 366 | when Reading => |
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| 367 | if dma_rd_request(pri_rd) ='1' then |
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| 368 | if hold_ack='1' then |
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| 369 | -- on reste dans cet état |
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| 370 | if dma_wr_request(pri_wr)='1' then |
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| 371 | dmac_state<=ReadWrite; |
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| 372 | else |
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| 373 | req_wr:='0'; |
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| 374 | end if; |
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| 375 | else |
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| 376 | dmac_state<=wait_ack; |
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| 377 | end if; |
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| 378 | elsif dma_wr_request(pri_wr) ='1' then |
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| 379 | dmac_state<=writing; |
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[64] | 380 | req_rd:='0'; |
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[15] | 381 | else |
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| 382 | dmac_state <= idle; |
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[64] | 383 | req_rd:='0'; |
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[15] | 384 | end if; |
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| 385 | when others => dmac_state <= idle; |
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| 386 | end case; |
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| 387 | end if; |
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| 388 | end if; |
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| 389 | end process; |
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| 390 | -- action_asociées |
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| 391 | ol: process(dmac_state, address_rd, address_wr,pri_wr,pri_rd,prio_wr,prio_rd,dma_wr_request,dma_rd_request) |
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| 392 | |
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| 393 | begin |
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| 394 | --tester les requêtes DMA en lecture ou en écriture |
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| 395 | |
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| 396 | case dmac_state is |
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| 397 | when idle => |
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| 398 | ram_en <='0'; |
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| 399 | ram_we <='0'; |
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[64] | 400 | dma_wr_latch <=(others=>'0'); |
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| 401 | dma_rd_latch <=(others=>'0'); |
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[15] | 402 | --address_out_rd <= address_rd; |
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| 403 | --hold_req<='0'; |
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| 404 | when wait_ack => |
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| 405 | ram_en <='0'; |
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| 406 | ram_we <='0'; |
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[64] | 407 | dma_wr_latch<=(others=>'0'); |
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| 408 | dma_rd_latch<=(others=>'0'); |
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[15] | 409 | --address_out_rd <= (others=>'Z'); |
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| 410 | --address_out_wr <= (others=>'Z'); |
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| 411 | --hold_req<='1'; |
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| 412 | when arbiter_ack => --à optimiser pour gagner un cycle |
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[64] | 413 | ram_en <='0'; |
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[15] | 414 | ram_we <='0'; |
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[64] | 415 | dma_wr_latch<=(others=>'0'); |
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| 416 | dma_rd_latch<=(others=>'0'); |
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[15] | 417 | --address_out_rd <= (others=>'Z'); |
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| 418 | --address_out_wr <= (others=>'Z'); |
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| 419 | when writing => -- ecriture dans la ram |
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| 420 | ram_en <='1'; |
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| 421 | ram_we <='1'; |
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[64] | 422 | dma_wr_latch<=(others=>'0'); |
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| 423 | dma_wr_latch(pri_wr) <='1'; |
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| 424 | dma_rd_latch <=(others=>'0'); |
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[15] | 425 | --address_out_rd <= (others=>'Z'); |
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| 426 | --address_out_wr <= address_wr; |
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| 427 | --hold_req<='1'; |
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| 428 | |
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| 429 | when ReadWrite => -- Lecture et écriture simultannée dans la Dual Port RAM |
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| 430 | ram_en <='1'; |
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| 431 | ram_we <='1'; |
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[64] | 432 | dma_wr_latch<=(others=>'0'); |
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| 433 | dma_wr_latch(pri_wr) <='1'; |
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| 434 | dma_rd_latch<=(others=>'0'); |
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| 435 | dma_rd_latch(pri_rd)<='1'; |
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[15] | 436 | |
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| 437 | --address_out_rd <= address_rd; |
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| 438 | --address_out_wr <= address_wr; |
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| 439 | --hold_req<='1'; |
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| 440 | when Reading => -- lecture dans la ram |
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| 441 | ram_en <='1'; |
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| 442 | ram_we <='0'; |
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[64] | 443 | dma_wr_latch<=(others=>'0'); |
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| 444 | dma_rd_latch<=(others=>'0'); |
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| 445 | dma_rd_latch(pri_rd)<='1'; |
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[15] | 446 | |
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| 447 | --address_out_rd <= address_rd; |
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| 448 | --address_out_wr <= (others=>'Z'); |
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| 449 | --hold_req<='1'; |
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| 450 | when others => |
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| 451 | ram_en <='0'; |
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| 452 | ram_we <='0'; |
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[64] | 453 | dma_wr_latch <=(others=>'0'); |
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| 454 | dma_rd_latch <=(others=>'0'); |
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[15] | 455 | --address_out_rd <= (others=>'Z'); |
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| 456 | --address_out_wr <= (others=>'Z'); |
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| 457 | --hold_req<='0'; |
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| 458 | end case; |
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| 459 | end process; |
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| 460 | |
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| 461 | |
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| 462 | end Behavioral; |
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| 463 | |
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