source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER.vhi

Last change on this file was 15, checked in by rolagamo, 12 years ago
File size: 1.3 KB
Line 
1
2-- VHDL Instantiation Created from source file DMA_ARBITER.vhd -- 05:54:04 06/21/2011
3--
4-- Notes:
5-- 1) This instantiation template has been automatically generated using types
6-- std_logic and std_logic_vector for the ports of the instantiated module
7-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
8
9        COMPONENT DMA_ARBITER
10        PORT(
11                dma_rd_request : IN std_logic;
12                data_wr_in : IN std_logic_vector(7 downto 0);
13                data_rd_in : IN std_logic_vector(7 downto 0);
14                address_rd : IN std_logic_vector(15 downto 0);
15                address_wr : IN std_logic_vector(15 downto 0);
16                clk : IN std_logic;
17                reset : IN std_logic;
18                dma_wr_request : IN std_logic;         
19                address_out : OUT std_logic_vector(15 downto 0);
20                ram_en : OUT std_logic;
21                ram_we : OUT std_logic;
22                data_wr_out : OUT std_logic_vector(7 downto 0);
23                data_rd_out : OUT std_logic_vector(7 downto 0);
24                dma_wr_grant : OUT std_logic;
25                dma_rd_grant : OUT std_logic
26                );
27        END COMPONENT;
28
29        Inst_DMA_ARBITER: DMA_ARBITER PORT MAP(
30                dma_rd_request => ,
31                data_wr_in => ,
32                data_rd_in => ,
33                address_rd => ,
34                address_wr => ,
35                address_out => ,
36                ram_en => ,
37                ram_we => ,
38                data_wr_out => ,
39                data_rd_out => ,
40                dma_wr_grant => ,
41                clk => ,
42                reset => ,
43                dma_rd_grant => ,
44                dma_wr_request =>
45        );
46
47
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