source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_CORE_COMPONENTS.gise @ 64

Last change on this file since 64 was 64, checked in by rolagamo, 11 years ago
File size: 44.5 KB
Line 
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4  <!--                                                          -->
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6  <!--             For tool use only. Do not edit.              -->
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8  <!--                                                          -->
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10  <!-- ProjectNavigator created generated project file.         -->
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14  <!-- allowing preservation of process status.                 -->
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16  <!--                                                          -->
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18  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
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179    <file xil_pn:fileType="FILE_NCD" xil_pn:name="PE_guide.ncd" xil_pn:origination="imported"/>
180    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="PE_isim_beh.exe"/>
181    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="PE_map.map" xil_pn:subbranch="Map"/>
182    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="PE_map.mrp" xil_pn:subbranch="Map"/>
183    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="PE_map.ncd" xil_pn:subbranch="Map"/>
184    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="PE_map.ngm" xil_pn:subbranch="Map"/>
185    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="PE_pad.csv" xil_pn:subbranch="Par"/>
186    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="PE_pad.txt" xil_pn:subbranch="Par"/>
187    <file xil_pn:fileType="FILE_HTML" xil_pn:name="PE_summary.html"/>
188    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="PE_xst.xrpt"/>
189    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="SWITCH_GEN.bld"/>
190    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SWITCH_GEN.cmd_log"/>
191    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SWITCH_GEN.lso"/>
192    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN.ncd" xil_pn:subbranch="Par"/>
193    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SWITCH_GEN.ngc"/>
194    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="SWITCH_GEN.ngd"/>
195    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SWITCH_GEN.ngr"/>
196    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="SWITCH_GEN.pad"/>
197    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="SWITCH_GEN.par" xil_pn:subbranch="Par"/>
198    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="SWITCH_GEN.pcf" xil_pn:subbranch="Map"/>
199    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SWITCH_GEN.prj"/>
200    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="SWITCH_GEN.ptwx"/>
201    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SWITCH_GEN.stx"/>
202    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SWITCH_GEN.syr"/>
203    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="SWITCH_GEN.twr" xil_pn:subbranch="Par"/>
204    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="SWITCH_GEN.twx" xil_pn:subbranch="Par"/>
205    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="SWITCH_GEN.unroutes" xil_pn:subbranch="Par"/>
206    <file xil_pn:fileType="FILE_XPI" xil_pn:name="SWITCH_GEN.xpi"/>
207    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SWITCH_GEN.xst"/>
208    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SWITCH_GENERIQUE.cmd_log"/>
209    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SWITCH_GENERIQUE.lso"/>
210    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SWITCH_GENERIQUE.prj"/>
211    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SWITCH_GENERIQUE.syr"/>
212    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SWITCH_GENERIQUE.xst"/>
213    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GENERIQUE_envsettings.html"/>
214    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GENERIQUE_summary.html"/>
215    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GENERIQUE_xst.xrpt"/>
216    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GEN_envsettings.html"/>
217    <file xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_guide.ncd" xil_pn:origination="imported"/>
218    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SWITCH_GEN_map.map" xil_pn:subbranch="Map"/>
219    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SWITCH_GEN_map.mrp" xil_pn:subbranch="Map"/>
220    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_map.ncd" xil_pn:subbranch="Map"/>
221    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="SWITCH_GEN_map.ngm" xil_pn:subbranch="Map"/>
222    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_map.xrpt"/>
223    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_ngdbuild.xrpt"/>
224    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="SWITCH_GEN_pad.csv" xil_pn:subbranch="Par"/>
225    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="SWITCH_GEN_pad.txt" xil_pn:subbranch="Par"/>
226    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_par.xrpt"/>
227    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GEN_summary.html"/>
228    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="SWITCH_GEN_summary.xml"/>
229    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="SWITCH_GEN_usage.xml"/>
230    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_xst.xrpt"/>
231    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
232    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
233    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
234    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
235    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
236    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
237    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
238    <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
239    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
240    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
241    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
242    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="load_instr.bld"/>
243    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="load_instr.cmd_log"/>
244    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="load_instr.lso"/>
245    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="load_instr.ncd" xil_pn:subbranch="Par"/>
246    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="load_instr.ngc"/>
247    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="load_instr.ngd"/>
248    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="load_instr.ngr"/>
249    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="load_instr.par" xil_pn:subbranch="Par"/>
250    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="load_instr.pcf" xil_pn:subbranch="Map"/>
251    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="load_instr.prj"/>
252    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="load_instr.stx"/>
253    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="load_instr.syr"/>
254    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="load_instr.twr" xil_pn:subbranch="Par"/>
255    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="load_instr.twx" xil_pn:subbranch="Par"/>
256    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="load_instr.unroutes" xil_pn:subbranch="Par"/>
257    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="load_instr.xst"/>
258    <file xil_pn:fileType="FILE_HTML" xil_pn:name="load_instr_envsettings.html"/>
259    <file xil_pn:fileType="FILE_NCD" xil_pn:name="load_instr_guide.ncd" xil_pn:origination="imported"/>
260    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="load_instr_map.map" xil_pn:subbranch="Map"/>
261    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="load_instr_map.mrp" xil_pn:subbranch="Map"/>
262    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="load_instr_map.ncd" xil_pn:subbranch="Map"/>
263    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="load_instr_map.ngm" xil_pn:subbranch="Map"/>
264    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="load_instr_pad.csv" xil_pn:subbranch="Par"/>
265    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="load_instr_pad.txt" xil_pn:subbranch="Par"/>
266    <file xil_pn:fileType="FILE_HTML" xil_pn:name="load_instr_summary.html"/>
267    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="load_instr_xst.xrpt"/>
268    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mpi_test_beh.prj"/>
269    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="mpi_test_isim_beh.exe"/>
270    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="mpi_test_isim_beh.wdb"/>
271    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mpi_test_stx_beh.prj"/>
272    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="multimpitest.bgn" xil_pn:subbranch="FPGAConfiguration"/>
273    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="multimpitest.bit" xil_pn:subbranch="FPGAConfiguration"/>
274    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="multimpitest.drc" xil_pn:subbranch="FPGAConfiguration"/>
275    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="pepExtractor.prj"/>
276    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
277    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_DMA_isim_beh.exe"/>
278    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_xbar_8x8_isim_beh.exe"/>
279    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/>
280    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
281    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
282    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
283    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
284    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
285    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
286  </files>
287
288  <transforms xmlns="http://www.xilinx.com/XMLSchema">
289    <transform xil_pn:end_ts="1356687406" xil_pn:name="TRANEXT_compLibraries_FPGA" xil_pn:prop_ck="5489153583840594524" xil_pn:start_ts="1356687405">
290      <status xil_pn:value="FailedRun"/>
291      <status xil_pn:value="ReadyToRun"/>
292    </transform>
293    <transform xil_pn:end_ts="1366390106" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1366390106">
294      <status xil_pn:value="SuccessfullyRun"/>
295      <status xil_pn:value="ReadyToRun"/>
296    </transform>
297    <transform xil_pn:end_ts="1366622930" xil_pn:in_ck="-6687518003772672403" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1366622930">
298      <status xil_pn:value="SuccessfullyRun"/>
299      <status xil_pn:value="ReadyToRun"/>
300      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
301      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
302      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/>
303      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/>
304      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/>
305      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/>
306      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/>
307      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/>
308      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/>
309      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD"/>
310      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD"/>
311      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/>
312      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/>
313      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/>
314      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/>
315      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/>
316      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/>
317      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/>
318      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/>
319      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/>
320      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/>
321      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/>
322      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/>
323      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD"/>
324      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/>
325      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/>
326      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/conv.vhd"/>
327      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/>
328      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/>
329      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/>
330      <outfile xil_pn:name="CORE_MPI.vhd"/>
331      <outfile xil_pn:name="DEMUX1.vhd"/>
332      <outfile xil_pn:name="DMA_ARBITER.vhd"/>
333      <outfile xil_pn:name="EX1_FSM.vhd"/>
334      <outfile xil_pn:name="EX2_FSM.vhd"/>
335      <outfile xil_pn:name="EX3_FSM.vhd"/>
336      <outfile xil_pn:name="EX4_FSM.vhd"/>
337      <outfile xil_pn:name="Ex0_Fsm.vhd"/>
338      <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
339      <outfile xil_pn:name="FIfo_mem.vhd"/>
340      <outfile xil_pn:name="FIfo_proc.vhd"/>
341      <outfile xil_pn:name="Hold_FSM.vhd"/>
342      <outfile xil_pn:name="MPICORETEST.vhd"/>
343      <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
344      <outfile xil_pn:name="MPI_NOC.vhd"/>
345      <outfile xil_pn:name="MPI_RMA.vhd"/>
346      <outfile xil_pn:name="MUX1.vhd"/>
347      <outfile xil_pn:name="MUX8.vhd"/>
348      <outfile xil_pn:name="MultiMPITest.vhd"/>
349      <outfile xil_pn:name="PE.vhd"/>
350      <outfile xil_pn:name="Packet_type.vhd"/>
351      <outfile xil_pn:name="RAM_32_32.vhd"/>
352      <outfile xil_pn:name="RAM_64.vhd"/>
353      <outfile xil_pn:name="image_pkg.vhd"/>
354      <outfile xil_pn:name="load_instr.vhd"/>
355      <outfile xil_pn:name="mpi_test.vhd"/>
356      <outfile xil_pn:name="round_robbin_machine.vhd"/>
357      <outfile xil_pn:name="sim_fifo.vhd"/>
358      <outfile xil_pn:name="test_DMA.vhd"/>
359    </transform>
360    <transform xil_pn:end_ts="1366610992" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1366610992">
361      <status xil_pn:value="SuccessfullyRun"/>
362      <status xil_pn:value="ReadyToRun"/>
363    </transform>
364    <transform xil_pn:end_ts="1366610993" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1366610992">
365      <status xil_pn:value="SuccessfullyRun"/>
366      <status xil_pn:value="ReadyToRun"/>
367    </transform>
368    <transform xil_pn:end_ts="1366390108" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1366390108">
369      <status xil_pn:value="SuccessfullyRun"/>
370      <status xil_pn:value="ReadyToRun"/>
371    </transform>
372    <transform xil_pn:end_ts="1366622930" xil_pn:in_ck="-6687518003772672403" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1366622930">
373      <status xil_pn:value="SuccessfullyRun"/>
374      <status xil_pn:value="ReadyToRun"/>
375      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
376      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
377      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/>
378      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/>
379      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/>
380      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/>
381      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/>
382      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/>
383      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/>
384      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD"/>
385      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD"/>
386      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/>
387      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/>
388      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/>
389      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/>
390      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/>
391      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/>
392      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/>
393      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/>
394      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/>
395      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/>
396      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/>
397      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/>
398      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD"/>
399      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/>
400      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/>
401      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/conv.vhd"/>
402      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/>
403      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/>
404      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/>
405      <outfile xil_pn:name="CORE_MPI.vhd"/>
406      <outfile xil_pn:name="DEMUX1.vhd"/>
407      <outfile xil_pn:name="DMA_ARBITER.vhd"/>
408      <outfile xil_pn:name="EX1_FSM.vhd"/>
409      <outfile xil_pn:name="EX2_FSM.vhd"/>
410      <outfile xil_pn:name="EX3_FSM.vhd"/>
411      <outfile xil_pn:name="EX4_FSM.vhd"/>
412      <outfile xil_pn:name="Ex0_Fsm.vhd"/>
413      <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
414      <outfile xil_pn:name="FIfo_mem.vhd"/>
415      <outfile xil_pn:name="FIfo_proc.vhd"/>
416      <outfile xil_pn:name="Hold_FSM.vhd"/>
417      <outfile xil_pn:name="MPICORETEST.vhd"/>
418      <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
419      <outfile xil_pn:name="MPI_NOC.vhd"/>
420      <outfile xil_pn:name="MPI_RMA.vhd"/>
421      <outfile xil_pn:name="MUX1.vhd"/>
422      <outfile xil_pn:name="MUX8.vhd"/>
423      <outfile xil_pn:name="MultiMPITest.vhd"/>
424      <outfile xil_pn:name="PE.vhd"/>
425      <outfile xil_pn:name="Packet_type.vhd"/>
426      <outfile xil_pn:name="RAM_32_32.vhd"/>
427      <outfile xil_pn:name="RAM_64.vhd"/>
428      <outfile xil_pn:name="image_pkg.vhd"/>
429      <outfile xil_pn:name="load_instr.vhd"/>
430      <outfile xil_pn:name="mpi_test.vhd"/>
431      <outfile xil_pn:name="round_robbin_machine.vhd"/>
432      <outfile xil_pn:name="sim_fifo.vhd"/>
433      <outfile xil_pn:name="test_DMA.vhd"/>
434    </transform>
435    <transform xil_pn:end_ts="1366622969" xil_pn:in_ck="-6687518003772672403" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-471607606114857674" xil_pn:start_ts="1366622930">
436      <status xil_pn:value="SuccessfullyRun"/>
437      <status xil_pn:value="ReadyToRun"/>
438      <status xil_pn:value="OutOfDateForOutputs"/>
439      <status xil_pn:value="OutputChanged"/>
440      <outfile xil_pn:name="fuse.log"/>
441      <outfile xil_pn:name="isim"/>
442      <outfile xil_pn:name="isim.log"/>
443      <outfile xil_pn:name="mpi_test_beh.prj"/>
444      <outfile xil_pn:name="mpi_test_isim_beh.exe"/>
445      <outfile xil_pn:name="xilinxsim.ini"/>
446    </transform>
447    <transform xil_pn:end_ts="1366622969" xil_pn:in_ck="2617743916491253678" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="810398370776000169" xil_pn:start_ts="1366622969">
448      <status xil_pn:value="SuccessfullyRun"/>
449      <status xil_pn:value="ReadyToRun"/>
450      <status xil_pn:value="OutOfDateForOutputs"/>
451      <status xil_pn:value="OutputChanged"/>
452      <outfile xil_pn:name="isim.cmd"/>
453      <outfile xil_pn:name="isim.log"/>
454      <outfile xil_pn:name="mpi_test_isim_beh.wdb"/>
455    </transform>
456    <transform xil_pn:end_ts="1354901662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1354901662">
457      <status xil_pn:value="SuccessfullyRun"/>
458      <status xil_pn:value="ReadyToRun"/>
459    </transform>
460    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1582102620978348987" xil_pn:start_ts="1364403007">
461      <status xil_pn:value="SuccessfullyRun"/>
462      <status xil_pn:value="ReadyToRun"/>
463      <status xil_pn:value="OutOfDateForInputs"/>
464      <status xil_pn:value="InputAdded"/>
465      <status xil_pn:value="InputChanged"/>
466    </transform>
467    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1364403007">
468      <status xil_pn:value="SuccessfullyRun"/>
469      <status xil_pn:value="ReadyToRun"/>
470    </transform>
471    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1364403007">
472      <status xil_pn:value="SuccessfullyRun"/>
473      <status xil_pn:value="ReadyToRun"/>
474    </transform>
475    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1364403007">
476      <status xil_pn:value="SuccessfullyRun"/>
477      <status xil_pn:value="ReadyToRun"/>
478    </transform>
479    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1364403007">
480      <status xil_pn:value="SuccessfullyRun"/>
481      <status xil_pn:value="ReadyToRun"/>
482      <status xil_pn:value="OutOfDateForPredecessor"/>
483    </transform>
484    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4624523187203829856" xil_pn:start_ts="1364403007">
485      <status xil_pn:value="SuccessfullyRun"/>
486      <status xil_pn:value="ReadyToRun"/>
487      <status xil_pn:value="OutOfDateForPredecessor"/>
488    </transform>
489    <transform xil_pn:end_ts="1365597033" xil_pn:in_ck="-7317970075764060686" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-1458878356683843968" xil_pn:start_ts="1365596908">
490      <status xil_pn:value="SuccessfullyRun"/>
491      <status xil_pn:value="WarningsGenerated"/>
492      <status xil_pn:value="ReadyToRun"/>
493      <status xil_pn:value="OutOfDateForInputs"/>
494      <status xil_pn:value="OutOfDateForPredecessor"/>
495      <status xil_pn:value="InputAdded"/>
496      <status xil_pn:value="InputChanged"/>
497      <outfile xil_pn:name="Crossbar.ngr"/>
498      <outfile xil_pn:name="DMA_ARBITER.ngr"/>
499      <outfile xil_pn:name="MPI_CORE_SCHEDULER.ngr"/>
500      <outfile xil_pn:name="MultiMPITest.lso"/>
501      <outfile xil_pn:name="MultiMPITest.ngc"/>
502      <outfile xil_pn:name="MultiMPITest.ngr"/>
503      <outfile xil_pn:name="MultiMPITest.prj"/>
504      <outfile xil_pn:name="MultiMPITest.stx"/>
505      <outfile xil_pn:name="MultiMPITest.syr"/>
506      <outfile xil_pn:name="MultiMPITest.xst"/>
507      <outfile xil_pn:name="MultiMPITest_stx_beh.prj"/>
508      <outfile xil_pn:name="MultiMPITest_vhdl.prj"/>
509      <outfile xil_pn:name="MultiMPITest_xst.xrpt"/>
510      <outfile xil_pn:name="PE.ngr"/>
511      <outfile xil_pn:name="SWITCH_GEN.ngr"/>
512      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
513      <outfile xil_pn:name="load_instr.ngr"/>
514      <outfile xil_pn:name="webtalk_pn.xml"/>
515      <outfile xil_pn:name="xst"/>
516    </transform>
517    <transform xil_pn:end_ts="1365008714" xil_pn:in_ck="6885079285025204965" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1365008714">
518      <status xil_pn:value="SuccessfullyRun"/>
519      <status xil_pn:value="ReadyToRun"/>
520      <status xil_pn:value="OutOfDateForPredecessor"/>
521    </transform>
522    <transform xil_pn:end_ts="1365597048" xil_pn:in_ck="3099115937148329492" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-5155457213437603231" xil_pn:start_ts="1365597033">
523      <status xil_pn:value="SuccessfullyRun"/>
524      <status xil_pn:value="WarningsGenerated"/>
525      <status xil_pn:value="ReadyToRun"/>
526      <status xil_pn:value="OutOfDateForPredecessor"/>
527      <outfile xil_pn:name="MultiMPITest.bld"/>
528      <outfile xil_pn:name="MultiMPITest.ngd"/>
529      <outfile xil_pn:name="MultiMPITest_ngdbuild.xrpt"/>
530      <outfile xil_pn:name="_ngo"/>
531      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
532    </transform>
533    <transform xil_pn:end_ts="1365597494" xil_pn:in_ck="4998795473985982555" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4079613270754646221" xil_pn:start_ts="1365597048">
534      <status xil_pn:value="SuccessfullyRun"/>
535      <status xil_pn:value="WarningsGenerated"/>
536      <status xil_pn:value="ReadyToRun"/>
537      <status xil_pn:value="OutOfDateForPredecessor"/>
538      <outfile xil_pn:name="MultiMPITest.pcf"/>
539      <outfile xil_pn:name="MultiMPITest_map.map"/>
540      <outfile xil_pn:name="MultiMPITest_map.mrp"/>
541      <outfile xil_pn:name="MultiMPITest_map.ncd"/>
542      <outfile xil_pn:name="MultiMPITest_map.ngm"/>
543      <outfile xil_pn:name="MultiMPITest_map.xrpt"/>
544      <outfile xil_pn:name="MultiMPITest_summary.xml"/>
545      <outfile xil_pn:name="MultiMPITest_usage.xml"/>
546      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
547    </transform>
548    <transform xil_pn:end_ts="1365598174" xil_pn:in_ck="-2175087184199880886" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1365597494">
549      <status xil_pn:value="SuccessfullyRun"/>
550      <status xil_pn:value="WarningsGenerated"/>
551      <status xil_pn:value="ReadyToRun"/>
552      <status xil_pn:value="OutOfDateForPredecessor"/>
553      <outfile xil_pn:name="MultiMPITest.ncd"/>
554      <outfile xil_pn:name="MultiMPITest.pad"/>
555      <outfile xil_pn:name="MultiMPITest.par"/>
556      <outfile xil_pn:name="MultiMPITest.ptwx"/>
557      <outfile xil_pn:name="MultiMPITest.unroutes"/>
558      <outfile xil_pn:name="MultiMPITest.xpi"/>
559      <outfile xil_pn:name="MultiMPITest_pad.csv"/>
560      <outfile xil_pn:name="MultiMPITest_pad.txt"/>
561      <outfile xil_pn:name="MultiMPITest_par.xrpt"/>
562      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
563    </transform>
564    <transform xil_pn:end_ts="1365598174" xil_pn:in_ck="-5951230430360050753" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1365598146">
565      <status xil_pn:value="SuccessfullyRun"/>
566      <status xil_pn:value="ReadyToRun"/>
567      <status xil_pn:value="OutOfDateForPredecessor"/>
568      <outfile xil_pn:name="MultiMPITest.twr"/>
569      <outfile xil_pn:name="MultiMPITest.twx"/>
570      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
571    </transform>
572  </transforms>
573
574</generated_project>
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