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1	<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
2	<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3	<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
4	<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
5	<TD ALIGN=CENTER COLSPAN='4'><B>SWITCH_GEN Project Status (12/17/2012 - 14:30:15)</B></TD></TR>
6	<TR ALIGN=LEFT>
7	<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8	<TD>MPI_CORE_COMPONENTS.xise</TD>
9	<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
10	<TD> No Errors </TD>
11	</TR>
12	<TR ALIGN=LEFT>
13	<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
14	<TD>MultiMPITest</TD>
15	<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
16	<TD>Placed and Routed</TD>
17	</TR>
18	<TR ALIGN=LEFT>
19	<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
20	<TD>xc6slx45-3csg324</TD>
21	<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
22	<TD>
23	No Errors</TD>
24	</TR>
25	<TR ALIGN=LEFT>
26	<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
27	<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
28	<TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/*.xmsgs?&DataKey=Warning'>3183 Warnings (2171 new)</A></TD>
29	</TR>
30	<TR ALIGN=LEFT>
31	<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
32	<TD>Balanced</TD>
33	<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
34	<TD>
35	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.unroutes'>All Signals Completely Routed</A></TD>
36	</TR>
37	<TR ALIGN=LEFT>
38	<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
39	<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
40	<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
41	<TD>
42	<font color="red"; face="Arial"><b>X </b></font>
43	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.ptwx?&DataKey=ConstraintsData'>10 Failing Constraints</A></TD>
44	</TR>
45	<TR ALIGN=LEFT>
46	<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
47	<TD>
48	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_envsettings.html'>
49	System Settings</A>
50	</TD>
51	<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
52	<TD>2511  <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
53	</TR>
54	</TABLE>
55
56
57
58	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
59	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
60	<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
61	<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
62	</TR>
63	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
64	<TD ALIGN=RIGHT>2,787</TD>
65	<TD ALIGN=RIGHT>54,576</TD>
66	<TD ALIGN=RIGHT>5%</TD>
67	<TD COLSPAN='2'> </TD>
68	</TR>
69	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Flip Flops</TD>
70	<TD ALIGN=RIGHT>2,177</TD>
71	<TD> </TD>
72	<TD> </TD>
73	<TD COLSPAN='2'> </TD>
74	</TR>
75	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latches</TD>
76	<TD ALIGN=RIGHT>610</TD>
77	<TD> </TD>
78	<TD> </TD>
79	<TD COLSPAN='2'> </TD>
80	</TR>
81	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latch-thrus</TD>
82	<TD ALIGN=RIGHT>0</TD>
83	<TD> </TD>
84	<TD> </TD>
85	<TD COLSPAN='2'> </TD>
86	</TR>
87	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as AND/OR logics</TD>
88	<TD ALIGN=RIGHT>0</TD>
89	<TD> </TD>
90	<TD> </TD>
91	<TD COLSPAN='2'> </TD>
92	</TR>
93	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
94	<TD ALIGN=RIGHT>12,107</TD>
95	<TD ALIGN=RIGHT>27,288</TD>
96	<TD ALIGN=RIGHT>44%</TD>
97	<TD COLSPAN='2'> </TD>
98	</TR>
99	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as logic</TD>
100	<TD ALIGN=RIGHT>6,962</TD>
101	<TD ALIGN=RIGHT>27,288</TD>
102	<TD ALIGN=RIGHT>25%</TD>
103	<TD COLSPAN='2'> </TD>
104	</TR>
105	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O6 output only</TD>
106	<TD ALIGN=RIGHT>5,563</TD>
107	<TD> </TD>
108	<TD> </TD>
109	<TD COLSPAN='2'> </TD>
110	</TR>
111	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 output only</TD>
112	<TD ALIGN=RIGHT>409</TD>
113	<TD> </TD>
114	<TD> </TD>
115	<TD COLSPAN='2'> </TD>
116	</TR>
117	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 and O6</TD>
118	<TD ALIGN=RIGHT>990</TD>
119	<TD> </TD>
120	<TD> </TD>
121	<TD COLSPAN='2'> </TD>
122	</TR>
123	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as ROM</TD>
124	<TD ALIGN=RIGHT>0</TD>
125	<TD> </TD>
126	<TD> </TD>
127	<TD COLSPAN='2'> </TD>
128	</TR>
129	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Memory</TD>
130	<TD ALIGN=RIGHT>5,088</TD>
131	<TD ALIGN=RIGHT>6,408</TD>
132	<TD ALIGN=RIGHT>79%</TD>
133	<TD COLSPAN='2'> </TD>
134	</TR>
135	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Dual Port RAM</TD>
136	<TD ALIGN=RIGHT>5,080</TD>
137	<TD> </TD>
138	<TD> </TD>
139	<TD COLSPAN='2'> </TD>
140	</TR>
141	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O6 output only</TD>
142	<TD ALIGN=RIGHT>5,080</TD>
143	<TD> </TD>
144	<TD> </TD>
145	<TD COLSPAN='2'> </TD>
146	</TR>
147	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 output only</TD>
148	<TD ALIGN=RIGHT>0</TD>
149	<TD> </TD>
150	<TD> </TD>
151	<TD COLSPAN='2'> </TD>
152	</TR>
153	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 and O6</TD>
154	<TD ALIGN=RIGHT>0</TD>
155	<TD> </TD>
156	<TD> </TD>
157	<TD COLSPAN='2'> </TD>
158	</TR>
159	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Single Port RAM</TD>
160	<TD ALIGN=RIGHT>8</TD>
161	<TD> </TD>
162	<TD> </TD>
163	<TD COLSPAN='2'> </TD>
164	</TR>
165	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O6 output only</TD>
166	<TD ALIGN=RIGHT>8</TD>
167	<TD> </TD>
168	<TD> </TD>
169	<TD COLSPAN='2'> </TD>
170	</TR>
171	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 output only</TD>
172	<TD ALIGN=RIGHT>0</TD>
173	<TD> </TD>
174	<TD> </TD>
175	<TD COLSPAN='2'> </TD>
176	</TR>
177	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 and O6</TD>
178	<TD ALIGN=RIGHT>0</TD>
179	<TD> </TD>
180	<TD> </TD>
181	<TD COLSPAN='2'> </TD>
182	</TR>
183	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Shift Register</TD>
184	<TD ALIGN=RIGHT>0</TD>
185	<TD> </TD>
186	<TD> </TD>
187	<TD COLSPAN='2'> </TD>
188	</TR>
189	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used exclusively as route-thrus</TD>
190	<TD ALIGN=RIGHT>57</TD>
191	<TD> </TD>
192	<TD> </TD>
193	<TD COLSPAN='2'> </TD>
194	</TR>
195	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice register load</TD>
196	<TD ALIGN=RIGHT>9</TD>
197	<TD> </TD>
198	<TD> </TD>
199	<TD COLSPAN='2'> </TD>
200	</TR>
201	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice carry load</TD>
202	<TD ALIGN=RIGHT>48</TD>
203	<TD> </TD>
204	<TD> </TD>
205	<TD COLSPAN='2'> </TD>
206	</TR>
207	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with other load</TD>
208	<TD ALIGN=RIGHT>0</TD>
209	<TD> </TD>
210	<TD> </TD>
211	<TD COLSPAN='2'> </TD>
212	</TR>
213	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
214	<TD ALIGN=RIGHT>3,948</TD>
215	<TD ALIGN=RIGHT>6,822</TD>
216	<TD ALIGN=RIGHT>57%</TD>
217	<TD COLSPAN='2'> </TD>
218	</TR>
219	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
220	<TD ALIGN=RIGHT>12,444</TD>
221	<TD> </TD>
222	<TD> </TD>
223	<TD COLSPAN='2'> </TD>
224	</TR>
225	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused Flip Flop</TD>
226	<TD ALIGN=RIGHT>9,820</TD>
227	<TD ALIGN=RIGHT>12,444</TD>
228	<TD ALIGN=RIGHT>78%</TD>
229	<TD COLSPAN='2'> </TD>
230	</TR>
231	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused LUT</TD>
232	<TD ALIGN=RIGHT>337</TD>
233	<TD ALIGN=RIGHT>12,444</TD>
234	<TD ALIGN=RIGHT>2%</TD>
235	<TD COLSPAN='2'> </TD>
236	</TR>
237	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of fully used LUT-FF pairs</TD>
238	<TD ALIGN=RIGHT>2,287</TD>
239	<TD ALIGN=RIGHT>12,444</TD>
240	<TD ALIGN=RIGHT>18%</TD>
241	<TD COLSPAN='2'> </TD>
242	</TR>
243	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of unique control sets</TD>
244	<TD ALIGN=RIGHT>858</TD>
245	<TD> </TD>
246	<TD> </TD>
247	<TD COLSPAN='2'> </TD>
248	</TR>
249	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of slice register sites lost<BR>        to control set restrictions</TD>
250	<TD ALIGN=RIGHT>3,341</TD>
251	<TD ALIGN=RIGHT>54,576</TD>
252	<TD ALIGN=RIGHT>6%</TD>
253	<TD COLSPAN='2'> </TD>
254	</TR>
255	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
256	<TD ALIGN=RIGHT>10</TD>
257	<TD ALIGN=RIGHT>218</TD>
258	<TD ALIGN=RIGHT>4%</TD>
259	<TD COLSPAN='2'> </TD>
260	</TR>
261	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
262	<TD ALIGN=RIGHT>0</TD>
263	<TD ALIGN=RIGHT>116</TD>
264	<TD ALIGN=RIGHT>0%</TD>
265	<TD COLSPAN='2'> </TD>
266	</TR>
267	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
268	<TD ALIGN=RIGHT>0</TD>
269	<TD ALIGN=RIGHT>232</TD>
270	<TD ALIGN=RIGHT>0%</TD>
271	<TD COLSPAN='2'> </TD>
272	</TR>
273	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
274	<TD ALIGN=RIGHT>0</TD>
275	<TD ALIGN=RIGHT>32</TD>
276	<TD ALIGN=RIGHT>0%</TD>
277	<TD COLSPAN='2'> </TD>
278	</TR>
279	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
280	<TD ALIGN=RIGHT>0</TD>
281	<TD ALIGN=RIGHT>32</TD>
282	<TD ALIGN=RIGHT>0%</TD>
283	<TD COLSPAN='2'> </TD>
284	</TR>
285	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
286	<TD ALIGN=RIGHT>4</TD>
287	<TD ALIGN=RIGHT>16</TD>
288	<TD ALIGN=RIGHT>25%</TD>
289	<TD COLSPAN='2'> </TD>
290	</TR>
291	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGs</TD>
292	<TD ALIGN=RIGHT>4</TD>
293	<TD> </TD>
294	<TD> </TD>
295	<TD COLSPAN='2'> </TD>
296	</TR>
297	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGMUX</TD>
298	<TD ALIGN=RIGHT>0</TD>
299	<TD> </TD>
300	<TD> </TD>
301	<TD COLSPAN='2'> </TD>
302	</TR>
303	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
304	<TD ALIGN=RIGHT>0</TD>
305	<TD ALIGN=RIGHT>8</TD>
306	<TD ALIGN=RIGHT>0%</TD>
307	<TD COLSPAN='2'> </TD>
308	</TR>
309	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
310	<TD ALIGN=RIGHT>0</TD>
311	<TD ALIGN=RIGHT>376</TD>
312	<TD ALIGN=RIGHT>0%</TD>
313	<TD COLSPAN='2'> </TD>
314	</TR>
315	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
316	<TD ALIGN=RIGHT>0</TD>
317	<TD ALIGN=RIGHT>376</TD>
318	<TD ALIGN=RIGHT>0%</TD>
319	<TD COLSPAN='2'> </TD>
320	</TR>
321	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
322	<TD ALIGN=RIGHT>0</TD>
323	<TD ALIGN=RIGHT>376</TD>
324	<TD ALIGN=RIGHT>0%</TD>
325	<TD COLSPAN='2'> </TD>
326	</TR>
327	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
328	<TD ALIGN=RIGHT>0</TD>
329	<TD ALIGN=RIGHT>4</TD>
330	<TD ALIGN=RIGHT>0%</TD>
331	<TD COLSPAN='2'> </TD>
332	</TR>
333	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
334	<TD ALIGN=RIGHT>0</TD>
335	<TD ALIGN=RIGHT>256</TD>
336	<TD ALIGN=RIGHT>0%</TD>
337	<TD COLSPAN='2'> </TD>
338	</TR>
339	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
340	<TD ALIGN=RIGHT>0</TD>
341	<TD ALIGN=RIGHT>8</TD>
342	<TD ALIGN=RIGHT>0%</TD>
343	<TD COLSPAN='2'> </TD>
344	</TR>
345	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
346	<TD ALIGN=RIGHT>0</TD>
347	<TD ALIGN=RIGHT>4</TD>
348	<TD ALIGN=RIGHT>0%</TD>
349	<TD COLSPAN='2'> </TD>
350	</TR>
351	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
352	<TD ALIGN=RIGHT>0</TD>
353	<TD ALIGN=RIGHT>58</TD>
354	<TD ALIGN=RIGHT>0%</TD>
355	<TD COLSPAN='2'> </TD>
356	</TR>
357	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
358	<TD ALIGN=RIGHT>0</TD>
359	<TD ALIGN=RIGHT>1</TD>
360	<TD ALIGN=RIGHT>0%</TD>
361	<TD COLSPAN='2'> </TD>
362	</TR>
363	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
364	<TD ALIGN=RIGHT>0</TD>
365	<TD ALIGN=RIGHT>2</TD>
366	<TD ALIGN=RIGHT>0%</TD>
367	<TD COLSPAN='2'> </TD>
368	</TR>
369	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
370	<TD ALIGN=RIGHT>0</TD>
371	<TD ALIGN=RIGHT>2</TD>
372	<TD ALIGN=RIGHT>0%</TD>
373	<TD COLSPAN='2'> </TD>
374	</TR>
375	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
376	<TD ALIGN=RIGHT>0</TD>
377	<TD ALIGN=RIGHT>4</TD>
378	<TD ALIGN=RIGHT>0%</TD>
379	<TD COLSPAN='2'> </TD>
380	</TR>
381	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
382	<TD ALIGN=RIGHT>0</TD>
383	<TD ALIGN=RIGHT>1</TD>
384	<TD ALIGN=RIGHT>0%</TD>
385	<TD COLSPAN='2'> </TD>
386	</TR>
387	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
388	<TD ALIGN=RIGHT>0</TD>
389	<TD ALIGN=RIGHT>1</TD>
390	<TD ALIGN=RIGHT>0%</TD>
391	<TD COLSPAN='2'> </TD>
392	</TR>
393	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
394	<TD ALIGN=RIGHT>0</TD>
395	<TD ALIGN=RIGHT>1</TD>
396	<TD ALIGN=RIGHT>0%</TD>
397	<TD COLSPAN='2'> </TD>
398	</TR>
399	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
400	<TD ALIGN=RIGHT>5.70</TD>
401	<TD> </TD>
402	<TD> </TD>
403	<TD COLSPAN='2'> </TD>
404	</TR>
405	</TABLE>
406
407
408
409	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
410	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
411	<TR ALIGN=LEFT>
412	<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
413	<TD>2511 (Setup: 2511, Hold: 0)</TD>
414	<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
415	<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
416	</TR>
417	<TR ALIGN=LEFT>
418	<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
419	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.unroutes'>All Signals Completely Routed</A></TD>
420	<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
421	<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
422	</TR>
423	<TR ALIGN=LEFT>
424	<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
425	<TD>
426	<font color="red"; face="Arial"><b>X </b></font>
427	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.ptwx?&DataKey=ConstraintsData'>10 Failing Constraints</A></TD>
428	<TD BGCOLOR='#FFFF99'><B> </B></TD>
429	<TD COLSPAN='2'> </TD>
430	</TABLE>
431
432
433
434	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
435	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
436	<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
437	<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
438	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon 17. Dec 14:18:41 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/xst.xmsgs?&DataKey=Warning'>1257 Warnings (277 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/xst.xmsgs?&DataKey=Info'>428 Infos (8 new)</A></TD></TR>
439	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon 17. Dec 14:18:50 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>102 Warnings (70 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
440	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon 17. Dec 14:26:12 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Warning'>974 Warnings (974 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (2 new)</A></TD></TR>
441	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon 17. Dec 14:29:38 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Warning'>850 Warnings (850 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
442	<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
443	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon 17. Dec 14:30:13 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
444	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bgn'>Bitgen Report</A></TD><TD>Out of Date</TD><TD>Sat 8. Dec 15:41:28 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>693 Warnings (693 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
445	</TABLE>
446	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
447	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
448	<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
449	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 7. Dec 14:52:37 2012</TD></TR>
450	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat 8. Dec 15:45:26 2012</TD></TR>
451	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat 8. Dec 15:45:32 2012</TD></TR>
452	</TABLE>
453
454
455	<br><center><b>Date Generated:</b> 12/17/2012 - 14:30:15</center>
456	</BODY></HTML>

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