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PE.vhd @ 100

Last change on this file since 100 was 64, checked in by rolagamo, 11 years ago

File size: 17.5 KB

Rev	Line
[15]	1	----------------------------------------------------------------------------------
	2	-- Company:
	3	-- Engineer:
	4	--
	5	-- Create Date: 21:20:54 07/16/2012
	6	-- Design Name:
	7	-- Module Name: PE - Behavioral
	8	-- Project Name:
	9	-- Target Devices:
	10	-- Tool versions:
	11	-- Description:
	12	--
	13	-- Dependencies:
	14	--
	15	-- Revision:
	16	-- Revision 0.01 - File Created
	17	-- Additional Comments:
	18	--
	19	----------------------------------------------------------------------------------
	20	library IEEE;
	21	use IEEE.STD_LOGIC_1164.ALL;
	22	library NocLib ;
[39]	23	library Std;
[15]	24	--use IEEE.STD_LOGIC_ARITH.ALL;
	25	--use IEEE.STD_LOGIC_UNSIGNED.ALL;
	26	use NocLib.CoreTypes.all;
	27	use work.Packet_type.all;
	28	use work.MPI_RMA.all;
[41]	29	-- synthesis translate_off
[39]	30	use std.textio.all;
[41]	31	-- synthesis translate_on
[15]	32	use IEEE.NUMERIC_STD.ALL;
	33
	34
	35	entity PE is
[41]	36	Generic (DestId : natural:=0 );
[15]	37	Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0);
	38	Instruction_en : out STD_LOGIC;
	39	Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0);
	40	clk : in STD_LOGIC;
	41	reset : in STD_LOGIC;
	42	Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0);
	43	Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0);
	44	Core_RAM_WE : in STD_LOGIC;
	45	Core_RAM_EN : in STD_LOGIC;
	46	--Core_RAM_ENB : in STD_LOGIC;
	47	Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
	48	Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
	49	Core_Hold_req : in STD_LOGIC;
	50	Core_Hold_Ack : out STD_LOGIC);
	51	end PE;
	52
	53	architecture Behavioral of PE is
	54	COMPONENT RAM_v
	55	generic (width : positive;size :positive);
	56	PORT(
	57	clka : IN std_logic;
	58	clkb : IN std_logic;
	59	wea : IN std_logic;
	60	ena : IN std_logic;
	61	enb : IN std_logic;
	62	addra : IN std_logic_vector;
	63	addrb : IN std_logic_vector;
	64	dia : IN std_logic_vector;
	65	dob : OUT std_logic_vector
	66	);
	67	END COMPONENT;
[64]	68	COMPONENT Hold_FSM is
	69	Port ( Hold_Req : in STD_LOGIC;
	70	Ram_busy : in STD_LOGIC;
	71	Clk : in STD_LOGIC;
	72	Reset : in STD_LOGIC;
	73	Ramsel : out STD_LOGIC;
	74	Hold_Ack : out STD_LOGIC);
	75	end COMPONENT Hold_FSM;
[15]	76	--données du programme PE
	77	--signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0');
	78	signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0';
	79	signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic;
	80	signal pe_instr_en,pe_hold_ack: std_logic:='0';
	81	signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
	82	signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
	83	signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
	84	signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
	85	signal sram : typ_dpram;
[64]	86	signal MyGroup:mpi_group;
	87	signal MyWin : mpi_win;
[15]	88	signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0);
	89	signal dpid,dpid_i : natural range 0 to 15:=DestId;
	90	signal MyRank :std_logic_vector(3 downto 0);
	91	signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque
	92	signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée
	93	signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO
	94	signal Lib_Init : std_logic; -- l'initialisation est terminée
[64]	95	signal Hold_Ack : std_logic;
[15]	96	--signaux pour la gestion de la MAE
[64]	97	type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinStart, putdata,getdata,WinCompleted,finalize,st_timeout);
	98	type typ_Hld is (Ht_Lock,Core_Lock,Ht_free);
[15]	99	signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées
	100	signal count,count_i : natural range 0 to 15:=0;
	101
	102
	103	signal RunState : typ_mae;
[64]	104	signal Hld_state :typ_hld;
[15]	105	signal Ram_busy :std_logic:='0';
	106	begin
	107	Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN)
	108	PORT MAP(
	109	clka =>clk,
	110	clkb => clk,
	111	wea => ram_we,
	112	ena => ram_ena,
	113	enb => ram_enb,
	114	addra => ram_addra,
	115	addrb =>ram_addrb,
	116	dia => ram_din,
	117	dob => ram_do
	118	);
	119	--================================================================
	120	--MUX de la RAM
	121
	122	Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr,
	123	Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do,
	124	Pe_ram_din,Pe_ram_we )
	125	begin
	126	case ramsel is
	127
	128	when '1' =>
	129	ram_addra <= Core_ram_address_wr ;
	130	ram_addrb <= Core_ram_address_rd ;
	131	ram_ena <= Core_ram_en;
	132	ram_enb <= Core_ram_en;
	133	ram_we<= Core_ram_we;
	134	ram_din <= Core_ram_data_in;
	135	pe_ram_do<=(others=>'Z');
	136	Core_ram_data_out<=ram_do;
	137
	138	when others =>
	139	ram_addra <= pe_ram_addra;
	140	ram_addrb <= pe_ram_addrb;
	141	ram_ena <= pe_ram_ena;
	142	ram_enb <= pe_ram_enb;
	143	ram_we<= pe_ram_we;
	144	ram_din <=pe_ram_din;
	145	Core_ram_data_out<=(others=>'Z');
	146	pe_ram_do<=ram_do;
	147	end case ;
	148	end process ;
	149
	150
	151
	152	Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --******A changer ********
	153	--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce
	154	-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!!
	155	instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8));
	156
	157	dpid<=dpid_i;
	158
	159	Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié
	160	Lib_init<=Core_Pushout(4); -- Initialized
	161
[64]	162	Hold1: Hold_fsm port map (
	163	clk=>clk,
	164	reset =>reset,
	165	Ram_Busy=>Libr.membusy,
	166	Hold_Ack=>Hold_Ack,
	167	Hold_req =>Core_Hold_Req,
	168	RamSel => RamSel);
	169	Core_Hold_Ack<=Hold_Ack;
[15]	170
	171
	172	--=======================================================================
	173	--MAE du PE
	174	--=======================================================================
	175
	176	pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do)
	177
	178	constant DATAPTR : natural :=256;
	179	variable bfill,destrank,pid,mport : natural range 0 to 15;
	180	variable fsrc,ret : natural range 0 to 15:=0;
	181	variable timeout,ct,dlen : natural range 0 to 255;
	182	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
[39]	183	variable mywin : Mpi_win;
[15]	184	variable iack : std_logic:='0';
	185	variable adresse,adresse_rd :natural range 0 to 65536;
	186	variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');
[39]	187	--=======================================================
	188	--variables pour la création du fichier de résultats
[41]	189	-- synthesis translate_off
[39]	190	type char_file is file of character;
	191	file f: text;
	192	variable status :file_open_status ;
	193	variable char_count: integer range 0 to 65536 := 0;
	194	variable str: string (1 to 79) ;
	195	variable L: line;
	196	variable fopened: std_logic:='0';
[41]	197	-- synthesis translate_on
[39]	198	--======================================================
[15]	199	begin
	200	--=== Partie combinatoire du process ===================================
[41]	201
[39]	202	--=== Fin de la partie combinatoire du process ==========================
	203
	204
	205
	206	--end loop;
	207
[15]	208	if (clk'event and clk='1') then
[41]	209	Libr.Instr_ack<=Core_pushout(0);
	210	Libr.InitOk<=Core_pushout(4);
	211	Libr.Hold_Req<=Core_Hold_req;
[64]	212	Libr.Hold_Ack<=Hold_Ack;
[41]	213	Libr.RamSel<=RamSel;
	214	sram.data_out<=PE_ram_do;
	215
[15]	216	if reset='1' then
	217	RunState<=start;
	218
	219	else
	220
	221	Libr.Instr_ack<=Core_pushout(0);
	222	Libr.InitOk<=Core_pushout(4);
	223	Libr.Hold_Req<=Core_Hold_req;
[64]	224	Libr.Hold_Ack<=Hold_Ack;
[15]	225	Libr.RamSel<=RamSel;
	226	sram.data_out<=PE_ram_do;
[64]	227
[15]	228	case RunState is
	229	when start =>
	230	Dcount<=0;
	231	if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
	232	RunState<=Fillmem;
	233	end if;
	234	Ram_busy<='0';
[64]	235	Libr.MemBusy<='0';
[15]	236	PE_Instr_En<='0';
	237	iack:='0';
	238	adresse:=DATAPTR;
	239
	240	adresse_rd:=0;
	241	timeout:=0;
	242	dcount<=0;
[41]	243	-- synthesis translate_off
[39]	244	if fopened='0' then
	245	file_open(status,f, integer'image(destid) & "test_file0.txt", APPEND_MODE);
	246	--while not endfile(c_file_handle) loop
	247	--end if;
	248
	249	--write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));
	250	--report l.all;
	251	-- writeline (f, l) ;
	252	fopened:='1';
	253	end if;
[41]	254	-- synthesis translate_on
[15]	255	when Fillmem =>
	256	if Ramsel='0' then
	257
	258
	259
	260	PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
	261	PE_Instr_En<='0';
	262	dcount<=dcount+1;
	263
[64]	264	if dcount=100 then
[15]	265	bfill:=bfill+1;
	266
	267	if bfill=4 then
	268	RunState<=InitApp;
	269	else
	270	RunState<=nextfill;
	271	end if;
	272	else
	273	adresse:=adresse+1;
	274	RunState<=Fillmem;
	275	end if;
	276	else -- attente de la libéraion de la mémoire
	277	timeout:=timeout+1;
	278	if timeout=100 then
	279	RunState<=st_timeout;
	280	end if;
	281
	282	end if;
	283	when nextfill => --prépare le prochain bloc mémoire qui sera rempli
[64]	284	adresse:=200*bfill+1;
[15]	285	dcount<=0;
	286	ct:=0;
	287	RunState<=Fillmem;
	288	PE_Instr_En<='0';
	289	when InitApp =>
	290	--code pour Init
[64]	291	dlen:=139;
[39]	292	if ct=0 then
[41]	293	-- synthesis translate_off
	294	write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & time'image(now)));
[39]	295
	296	report l.all;
	297	writeline (f, l) ;
[41]	298	-- synthesis translate_on
[39]	299	end if;
[15]	300	pMPI_Init(ct,Libr,Clk,SRam);
	301	PE_Instr_EN<=Libr.instr_en;
	302	adresse:=to_integer(unsigned(sram.addr_wr));
	303	adresse_rd:=to_integer(unsigned(sram.addr_rd));
	304	PE_ram_din<=sram.data_in;
[64]	305	Ram_busy<=Libr.membusy;
[15]	306	--if Libr.InitOk='1' then
	307	if ct=0 then
[39]	308	RunState<=GetRank;
[41]	309	-- synthesis translate_off
	310	write (l,string'("Dlen; ;INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
[39]	311	report l.all;
	312	writeline (f, l) ;
[41]	313	-- synthesis translate_on
[15]	314	end if;
	315
	316
	317
[39]	318	when GetRank =>
	319	if ct=0 then
[41]	320	-- synthesis translate_off
	321	write (l,string'("Dlen; ;Rank1 " & integer'image(Dlen) & "; ; started ; " & time'image(now)));
[39]	322	report l.all;
	323	writeline (f, l) ;
[41]	324	-- synthesis translate_on
[39]	325	end if;
[15]	326	pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
[39]	327	adresse_rd:=to_integer(unsigned(sram.addr_rd));
[64]	328	Ram_busy<=Libr.membusy;
	329
[15]	330	if ct=0 then
[64]	331	RunState<=WinStart;
[41]	332	-- synthesis translate_off
	333	write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
[39]	334	report l.all;
[41]	335	writeline (f, l) ;
	336	-- synthesis translate_on
[15]	337	end if;
[39]	338
[64]	339
[39]	340	when Wincreate =>
[64]	341
	342	when WinStart =>
	343	if ct=0 then
	344	-- synthesis translate_off
	345	write (l,string'("Dlen; ;WStart1 " & integer'image(Dlen) & "; ; started ; " & time'image(now)));
	346	report l.all;
	347	writeline (f, l) ;
	348	-- synthesis translate_on
	349	end if;
	350	pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin);
	351	adresse:=to_integer(unsigned(sram.addr_wr));
	352	adresse_rd:=to_integer(unsigned(sram.addr_rd));
	353	--PE_Instr_EN<=Libr.instr_en;
	354	PE_ram_din<=sram.data_in;
	355	Ram_busy<=Libr.membusy;
	356	dcount<=ct;
[39]	357
[64]	358	if ct=0 then
	359	RunState<=PutData;
	360	-- synthesis translate_off
	361	write (l,string'("Dlen; ;WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
	362	report l.all;
	363	writeline (f, l) ;
	364	-- synthesis translate_on
	365	end if;
	366
[39]	367
[15]	368	when putdata => --construire le packet pour le Put
	369
[39]	370	--dlen:=251; ---
	371	if ct=0 then
[41]	372	-- synthesis translate_off
	373	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now)));
[39]	374	report l.all;
	375	writeline (f, l) ;
[41]	376	-- synthesis translate_on
[39]	377	end if;
[15]	378	if unsigned(MyRank) = 0 then
[41]	379	Destrank:=2;
	380
	381	elsif unsigned(MyRank) = 1 then
	382	Destrank:=0;
	383	elsif unsigned(MyRank) = 2 then
	384	Destrank:=1;
	385	elsif unsigned(MyRank) = 3 then
	386	Destrank:=2;
[15]	387	else
	388	DestRank:=0;
	389	end if;
[39]	390
[15]	391	SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
[64]	392	DestAdr:=X"0340";
[41]	393	pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
[15]	394
	395	adresse:=to_integer(unsigned(sram.addr_wr));
	396	adresse_rd:=to_integer(unsigned(sram.addr_rd));
	397	PE_Instr_EN<=Libr.instr_en;
	398	PE_ram_din<=sram.data_in;
[64]	399	Ram_busy<=Libr.membusy;
[15]	400	dcount<=ct;
	401
	402	if ct=0 then
	403	RunState<=GetData;
[41]	404	-- synthesis translate_off
[39]	405	report "Put of Process n°; " & image(MyRank) & "; ended at ; " & time'image(now);
[41]	406	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & time'image(now)));
[39]	407	report l.all;
[41]	408	writeline (f, l) ;
	409	-- synthesis translate_on
[15]	410	end if;
[39]	411
[15]	412
	413	when getdata => --positionnement du mot de longueur des données
[39]	414	--dlen:=251; ---
	415	if ct=0 then
[41]	416	-- synthesis translate_off
	417	write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & time'image(now)));
[39]	418	report l.all;
	419	writeline (f, l) ;
[41]	420	-- synthesis translate_on
[39]	421	end if;
	422
[35]	423	SrcAdr:=X"0120";
[64]	424	DestAdr:=X"1400";
[41]	425	if unsigned(MyRank) /= 2 then
	426	pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
	427	else
	428	RunState<=wincompleted;
	429	end if;
[15]	430	adresse:=to_integer(unsigned(sram.addr_wr));
	431	adresse_rd:=to_integer(unsigned(sram.addr_rd));
	432	PE_Instr_EN<=Libr.instr_en;
	433	PE_ram_din<=sram.data_in;
[64]	434	Ram_busy<=Libr.membusy;
[15]	435	dcount<=ct;
	436
	437	if ct=0 then
[39]	438	RunState<=wincompleted;
[41]	439	-- synthesis translate_off
[39]	440	assert ct/=0 report "GET_END " & integer'image(destrank)
	441	severity Warning ;
[41]	442	write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
[39]	443	report l.all;
	444
[41]	445	writeline (f, l) ;
	446	-- synthesis translate_on
[15]	447	end if;
	448
[39]	449	when WinCompleted =>
	450	if ct=0 then
[41]	451	-- synthesis translate_off
	452	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now)));
[39]	453	report l.all;
	454	writeline (f, l) ;
[41]	455	-- synthesis translate_on
[39]	456	end if;
	457	pMPI_Win_wait(ct,Libr,sram,MyWin );
	458	adresse:=to_integer(unsigned(sram.addr_wr));
	459	adresse_rd:=to_integer(unsigned(sram.addr_rd));
[64]	460	Ram_busy<=Libr.membusy;
[39]	461	if ct=0 then
	462	RunState<=finalize;
[41]	463	-- synthesis translate_off
	464	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
[39]	465	report l.all;
	466	writeline (f, l) ;
[41]	467	-- synthesis translate_on
[39]	468
	469	end if;
[15]	470
	471
[39]	472	when finalize =>
	473	if ct=0 then
[41]	474	-- synthesis translate_off
	475	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now)));
[39]	476	report l.all;
	477	writeline (f, l) ;
[41]	478	-- synthesis translate_on
[39]	479	end if;
	480
	481	if ct=0 then
	482	RunState<=start;
[41]	483	-- synthesis translate_off
	484	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
[39]	485	report l.all;
	486	writeline (f, l) ;
	487	file_close(f);
[41]	488	-- synthesis translate_on
[39]	489	end if;
[15]	490
	491	when st_timeout =>
	492
	493	--if ram_busy='1' then
	494	RunState<=start;
	495	--end if
	496
	497	RunState<=start;
	498	end case;
	499	pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16));
	500	pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16));
	501	end if;
	502	end if;
	503
	504	end process pPutGet;
	505
	506	majPutGet:process (RunState,pe_ram_do,sram,Lib_Init)
	507
	508	begin
	509	case RunState is
	510	when start =>
	511
	512	PE_Ram_we<='0';
	513	PE_Ram_ena<='0';
	514	PE_Ram_enb<='0';
	515	--PE_Instr_En<='0';
	516
	517	when fillmem =>
	518	PE_Ram_we<='1';
	519	PE_Ram_ena<='1';
	520
	521	PE_Ram_enb<='0';
	522	--PE_Instr_En<='0';
	523	when nextfill =>
	524	PE_Ram_we<='1';
	525	PE_Ram_ena<='1';
	526	PE_Ram_enb<='0';
	527
	528	when InitApp =>
	529	-- PE_Ram_we<='1';
	530	-- PE_Ram_ena<='1';
	531	-- PE_Ram_enb<='0';
	532	PE_Ram_we<=sram.we;
	533	PE_Ram_ena<=sram.ena;
	534	PE_Ram_enb<=sram.enb;
	535
[39]	536
	537	when GetRank =>
[15]	538
	539	PE_Ram_we<=sram.we;
	540	PE_Ram_ena<=sram.ena;
	541	PE_Ram_enb<=sram.enb;
[39]	542	when WinCreate =>
[15]	543
[39]	544	PE_Ram_we<=sram.we;
	545	PE_Ram_ena<=sram.ena;
	546	PE_Ram_enb<=sram.enb;
[15]	547
[64]	548	when WinStart =>
	549
	550	PE_Ram_we<=sram.we;
	551	PE_Ram_ena<=sram.ena;
	552	PE_Ram_enb<=sram.enb;
[39]	553	--positionnement du mot de longueur des données
[15]	554
	555
[39]	556	when putdata =>
[15]	557	srcadr0<=X"00";
	558	srcadr1<=X"01";
	559	destadr0<=X"00";
	560	destadr1<=X"02";
	561	PE_Ram_we<=sram.we;
	562	PE_Ram_ena<=sram.ena;
	563	PE_Ram_enb<=sram.enb;
[39]	564
[15]	565	when getdata =>
	566	PE_Ram_we<=sram.we;
	567	PE_Ram_ena<=sram.ena;
	568	PE_Ram_enb<=sram.enb;
	569
[39]	570	when Wincompleted =>
	571	PE_Ram_we<=sram.we;
	572	PE_Ram_ena<=sram.ena;
	573	PE_Ram_enb<=sram.enb;
[15]	574
[39]	575	when finalize =>
[15]	576
	577	PE_Ram_we<='0';
	578	PE_Ram_ena<='0';
	579	PE_Ram_enb<='0';
	580
	581
	582	when st_timeout =>
	583	PE_Ram_we<='0';
	584	PE_Ram_ena<='0';
	585	PE_Ram_enb<='0';
	586
	587
	588	end case;
	589
	590	end process majPutGet ;
	591	end Behavioral;
	592

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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/PE.vhd @ 100

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