[66] | 1 | -------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 07:29:14 03/26/2013 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: C:/Core MPI/CORE_MPI/mpi_test.vhd |
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| 8 | -- Project Name: MPI_CORE_COMPONENTS |
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| 9 | -- Target Device: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- VHDL Test Bench Created by ISE for module: MultiMPITest |
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| 14 | -- |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | -- Notes: |
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| 22 | -- This testbench has been automatically generated using types std_logic and |
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| 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends |
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| 24 | -- that these types always be used for the top-level I/O of a design in order |
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| 25 | -- to guarantee that the testbench will bind correctly to the post-implementation |
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| 26 | -- simulation model. |
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| 27 | -------------------------------------------------------------------------------- |
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| 28 | LIBRARY ieee; |
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| 29 | USE ieee.std_logic_1164.ALL; |
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| 30 | |
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| 31 | -- Uncomment the following library declaration if using |
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| 32 | -- arithmetic functions with Signed or Unsigned values |
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| 33 | --USE ieee.numeric_std.ALL; |
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| 34 | |
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| 35 | ENTITY mpi_test IS |
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| 36 | END mpi_test; |
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| 37 | |
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| 38 | ARCHITECTURE behavior OF mpi_test IS |
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| 39 | signal clk,reset : std_logic:='0'; |
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| 40 | signal result : std_logic_vector(7 downto 0); |
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| 41 | -- Component Declaration for the Unit Under Test (UUT) |
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| 42 | |
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| 43 | COMPONENT MultiMPITest |
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| 44 | |
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| 45 | port (clkm : in std_logic; |
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| 46 | reset : in std_logic; |
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| 47 | result : out std_logic_vector(7 downto 0)); |
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| 48 | |
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| 49 | END COMPONENT; |
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| 50 | |
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| 51 | -- No clocks detected in port list. Replace <clock> below with |
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| 52 | -- appropriate port name |
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| 53 | |
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| 54 | constant clk_period : time := 10 ns; |
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| 55 | |
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| 56 | BEGIN |
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| 57 | |
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| 58 | -- Instantiate the Unit Under Test (UUT) |
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| 59 | uut: MultiMPITest PORT MAP ( |
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| 60 | clkm=>clk, |
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| 61 | reset=>reset, |
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| 62 | result=>result |
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| 63 | ); |
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| 64 | |
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| 65 | -- Clock process definitions |
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| 66 | clk_process :process |
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| 67 | begin |
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| 68 | clk <= '0'; |
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| 69 | wait for clk_period/2; |
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| 70 | clk <= '1'; |
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| 71 | wait for clk_period/2; |
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| 72 | end process; |
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| 73 | |
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| 74 | |
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| 75 | -- Stimulus process |
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| 76 | stim_proc: process |
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| 77 | begin |
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| 78 | -- hold reset state for 100 ns. |
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| 79 | reset<='1'; |
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| 80 | wait for clk_period*10; |
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| 81 | reset<='0'; |
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| 82 | wait ; |
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| 83 | |
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| 84 | -- insert stimulus here |
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| 85 | |
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| 86 | wait; |
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| 87 | end process; |
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| 88 | |
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| 89 | END; |
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