[66] | 1 | -------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 14:37:10 03/18/2013 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: C:/Core MPI/CORE_MPI/test_DMA.vhd |
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| 8 | -- Project Name: MPI_CORE_COMPONENTS |
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| 9 | -- Target Device: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- VHDL Test Bench Created by ISE for module: DMA_ARBITER |
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| 14 | -- |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | -- Notes: |
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| 22 | -- This testbench has been automatically generated using types std_logic and |
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| 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends |
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| 24 | -- that these types always be used for the top-level I/O of a design in order |
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| 25 | -- to guarantee that the testbench will bind correctly to the post-implementation |
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| 26 | -- simulation model. |
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| 27 | -------------------------------------------------------------------------------- |
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| 28 | LIBRARY ieee; |
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| 29 | USE ieee.std_logic_1164.ALL; |
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| 30 | |
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| 31 | -- Uncomment the following library declaration if using |
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| 32 | -- arithmetic functions with Signed or Unsigned values |
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| 33 | --USE ieee.numeric_std.ALL; |
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| 34 | |
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| 35 | ENTITY test_DMA IS |
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| 36 | END test_DMA; |
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| 37 | |
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| 38 | ARCHITECTURE behavior OF test_DMA IS |
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| 39 | |
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| 40 | -- Component Declaration for the Unit Under Test (UUT) |
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| 41 | |
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| 42 | COMPONENT DMA_ARBITER |
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| 43 | PORT( |
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| 44 | dma_rd_request : IN std_logic_vector(3 downto 0); |
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| 45 | data_wr_in : IN std_logic_vector(7 downto 0); |
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| 46 | data_rd_out : OUT std_logic_vector(7 downto 0); |
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| 47 | address_rd : IN std_logic_vector(15 downto 0); |
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| 48 | address_wr : IN std_logic_vector(15 downto 0); |
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| 49 | address_out_wr : OUT std_logic_vector(15 downto 0); |
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| 50 | address_out_rd : OUT std_logic_vector(15 downto 0); |
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| 51 | ram_en : OUT std_logic; |
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| 52 | ram_we : OUT std_logic; |
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| 53 | data_wr_mem : OUT std_logic_vector(7 downto 0); |
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| 54 | data_rd_mem : IN std_logic_vector(7 downto 0); |
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| 55 | dma_wr_grant : OUT std_logic_vector(3 downto 0); |
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| 56 | hold_req : OUT std_logic; |
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| 57 | hold_ack : IN std_logic; |
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| 58 | clk : IN std_logic; |
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| 59 | reset : IN std_logic; |
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| 60 | dma_rd_grant : OUT std_logic_vector(3 downto 0); |
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| 61 | dma_wr_request : IN std_logic_vector(3 downto 0) |
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| 62 | ); |
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| 63 | END COMPONENT; |
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| 64 | |
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| 65 | COMPONENT RAM_v |
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| 66 | generic (width : positive;size :positive); |
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| 67 | PORT( |
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| 68 | clka : IN std_logic; |
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| 69 | clkb : IN std_logic; |
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| 70 | wea : IN std_logic; |
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| 71 | ena : IN std_logic; |
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| 72 | enb : IN std_logic; |
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| 73 | addra : IN std_logic_vector; |
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| 74 | addrb : IN std_logic_vector; |
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| 75 | dia : IN std_logic_vector; |
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| 76 | dob : OUT std_logic_vector |
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| 77 | ); |
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| 78 | END COMPONENT; |
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| 79 | --Inputs |
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| 80 | signal dma_rd_request : std_logic_vector(3 downto 0) := (others => '0'); |
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| 81 | signal data_wr_in : std_logic_vector(7 downto 0) := (others => '0'); |
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| 82 | signal address_rd : std_logic_vector(15 downto 0) := (others => '0'); |
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| 83 | signal address_wr : std_logic_vector(15 downto 0) := (others => '0'); |
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| 84 | signal data_rd_mem : std_logic_vector(7 downto 0) := (others => '0'); |
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| 85 | signal hold_ack : std_logic := '0'; |
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| 86 | signal clk : std_logic := '0'; |
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| 87 | signal reset : std_logic := '0'; |
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| 88 | signal dma_wr_request : std_logic_vector(3 downto 0) := (others => '0'); |
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| 89 | |
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| 90 | --Outputs |
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| 91 | signal data_rd_out : std_logic_vector(7 downto 0); |
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| 92 | signal address_out_wr : std_logic_vector(15 downto 0); |
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| 93 | signal address_out_rd : std_logic_vector(15 downto 0); |
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| 94 | signal ram_en : std_logic; |
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| 95 | signal ram_we : std_logic; |
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| 96 | signal data_wr_mem : std_logic_vector(7 downto 0); |
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| 97 | signal dma_wr_grant : std_logic_vector(3 downto 0); |
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| 98 | signal hold_req : std_logic; |
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| 99 | signal dma_rd_grant : std_logic_vector(3 downto 0); |
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| 100 | |
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| 101 | -- Clock period definitions |
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| 102 | constant clk_period : time := 10 ns; |
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| 103 | |
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| 104 | BEGIN |
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| 105 | |
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| 106 | -- Instantiate the Unit Under Test (UUT) |
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| 107 | uut: DMA_ARBITER PORT MAP ( |
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| 108 | dma_rd_request => dma_rd_request, |
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| 109 | data_wr_in => data_wr_in, |
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| 110 | data_rd_out => data_rd_out, |
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| 111 | address_rd => address_rd, |
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| 112 | address_wr => address_wr, |
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| 113 | address_out_wr => address_out_wr, |
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| 114 | address_out_rd => address_out_rd, |
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| 115 | ram_en => ram_en, |
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| 116 | ram_we => ram_we, |
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| 117 | data_wr_mem => data_wr_mem, |
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| 118 | data_rd_mem => data_rd_mem, |
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| 119 | dma_wr_grant => dma_wr_grant, |
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| 120 | hold_req => hold_req, |
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| 121 | hold_ack => hold_ack, |
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| 122 | clk => clk, |
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| 123 | reset => reset, |
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| 124 | dma_rd_grant => dma_rd_grant, |
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| 125 | dma_wr_request => dma_wr_request |
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| 126 | ); |
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| 127 | |
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| 128 | Inst_RAM_v: RAM_v generic map(width=>8,size=>16) |
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| 129 | PORT MAP( |
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| 130 | clka =>clk, |
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| 131 | clkb => clk, |
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| 132 | wea => ram_we, |
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| 133 | ena => ram_en, |
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| 134 | enb => ram_en, |
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| 135 | addra => address_out_wr, |
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| 136 | addrb =>address_out_rd, |
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| 137 | dia => data_wr_mem, |
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| 138 | dob => data_rd_mem |
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| 139 | ); |
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| 140 | -- Clock process definitions |
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| 141 | clk_process :process |
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| 142 | begin |
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| 143 | clk <= '0'; |
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| 144 | wait for clk_period/2; |
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| 145 | clk <= '1'; |
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| 146 | wait for clk_period/2; |
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| 147 | end process; |
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| 148 | |
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| 149 | |
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| 150 | -- Stimulus process |
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| 151 | reset_proc: process |
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| 152 | begin |
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| 153 | -- hold reset state for 100 ns. |
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| 154 | reset <='1'; |
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| 155 | wait for 100 ns; |
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| 156 | reset<='0'; |
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| 157 | wait for clk_period*10; |
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| 158 | |
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| 159 | -- insert stimulus here |
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| 160 | |
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| 161 | wait; |
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| 162 | end process; |
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| 163 | |
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| 164 | stim_proc: process (clk,reset) |
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| 165 | variable i,j,k,l : std_logic_vector(15 downto 0); |
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| 166 | variable x: integer ; --indique le temps à partir duquel chaque |
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| 167 | --permet de faire des requêtes DMA et de les valider |
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| 168 | begin |
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| 169 | if rising_edge(clk) then |
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| 170 | if reset ='1' then |
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| 171 | x:=0; |
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| 172 | else |
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| 173 | x:=x+1; |
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| 174 | if x>=1 and x<=20 then |
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| 175 | dma_rd_request<="0001"; |
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| 176 | elsif x>=21 and x<=40 then |
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| 177 | dma_rd_request<="0011"; |
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| 178 | elsif x>=41 and x<=60 then |
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| 179 | dma_rd_request<="0010"; |
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| 180 | elsif x>=61 and x<=80 then |
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| 181 | dma_rd_request<="0110"; |
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| 182 | elsif x>=81 and x<=100 then |
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| 183 | dma_rd_request<="0100"; |
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| 184 | elsif x>=61 and x<=80 then |
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| 185 | dma_rd_request<="1100"; |
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| 186 | elsif x>=101 and x<=120 then |
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| 187 | dma_rd_request<="1101"; |
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| 188 | elsif x>=121 and x<=140 then |
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| 189 | dma_rd_request<="1001"; |
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| 190 | elsif x>=141 and x<=160 then |
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| 191 | dma_rd_request<="1000"; |
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| 192 | elsif x>=161 and x<=180 then |
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| 193 | dma_rd_request<="0000"; |
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| 194 | elsif x>=181 and x<=200 then |
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| 195 | dma_rd_request<="0111"; |
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| 196 | elsif x>=181 and x<=200 then |
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| 197 | dma_rd_request<="1111"; |
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| 198 | elsif x>=181 and x<=200 then |
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| 199 | dma_rd_request<="1110"; |
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| 200 | else |
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| 201 | x:=0; |
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| 202 | |
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| 203 | end if; |
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| 204 | |
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| 205 | end if; |
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| 206 | end if; |
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| 207 | end process; |
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| 208 | stim2_proc: process (clk,reset) |
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| 209 | variable i,j,k,l : std_logic_vector(15 downto 0); |
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| 210 | variable x: integer ; --indique le temps à partir duquel chaque |
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| 211 | --permet de faire des requêtes DMA et de les valider |
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| 212 | begin |
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| 213 | if rising_edge(clk) then |
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| 214 | if reset ='1' then |
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| 215 | x:=0; |
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| 216 | else |
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| 217 | x:=x+1; |
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| 218 | if x>=1 and x<=10 then |
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| 219 | dma_wr_request<="0001"; |
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| 220 | elsif x>=11 and x<=20 then |
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| 221 | dma_wr_request<="0011"; |
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| 222 | elsif x>=21 and x<=30 then |
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| 223 | dma_wr_request<="0010"; |
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| 224 | elsif x>=31 and x<=40 then |
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| 225 | dma_wr_request<="0110"; |
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| 226 | elsif x>=41 and x<=50 then |
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| 227 | dma_wr_request<="0100"; |
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| 228 | elsif x>=51 and x<=60 then |
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| 229 | dma_wr_request<="1100"; |
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| 230 | elsif x>=61 and x<=80 then |
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| 231 | dma_wr_request<="1101"; |
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| 232 | elsif x>=81 and x<=90 then |
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| 233 | dma_wr_request<="1001"; |
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| 234 | elsif x>=91 and x<=100 then |
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| 235 | dma_wr_request<="1000"; |
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| 236 | elsif x>=101 and x<=110 then |
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| 237 | dma_wr_request<="0000"; |
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| 238 | elsif x>=111 and x<=120 then |
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| 239 | dma_wr_request<="0111"; |
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| 240 | elsif x>=121 and x<=130 then |
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| 241 | dma_wr_request<="1111"; |
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| 242 | elsif x>=131 and x<=200 then |
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| 243 | dma_wr_request<="1110"; |
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| 244 | else |
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| 245 | x:=0; |
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| 246 | |
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| 247 | end if; |
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| 248 | |
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| 249 | end if; |
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| 250 | end if; |
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| 251 | end process; |
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| 252 | liredat:process (dma_rd_grant) |
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| 253 | begin |
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| 254 | |
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| 255 | |
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| 256 | if dma_rd_grant="0001" then |
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| 257 | address_rd<=x"0000"; |
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| 258 | elsif dma_rd_grant="0010" then |
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| 259 | address_rd<=x"0002"; |
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| 260 | elsif dma_rd_grant="0100" then |
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| 261 | address_rd<=x"0004"; |
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| 262 | elsif dma_rd_grant="1000" then |
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| 263 | address_rd<=x"0006"; |
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| 264 | else |
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| 265 | |
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| 266 | address_rd<=x"0000"; |
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| 267 | end if; |
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| 268 | |
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| 269 | end process; |
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| 270 | ecriredat:process (dma_wr_grant) |
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| 271 | begin |
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| 272 | |
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| 273 | |
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| 274 | if dma_wr_grant="0001" then |
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| 275 | address_wr<=x"0000"; |
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| 276 | data_wr_in<=x"0a"; |
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| 277 | elsif dma_rd_grant="0010" then |
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| 278 | address_wr<=x"0002"; |
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| 279 | data_wr_in<=x"20"; |
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| 280 | elsif dma_rd_grant="0100" then |
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| 281 | address_wr<=x"0004"; |
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| 282 | data_wr_in<=x"a0"; |
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| 283 | elsif dma_rd_grant="1000" then |
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| 284 | address_wr<=x"0006"; |
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| 285 | data_wr_in<=x"0F"; |
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| 286 | else |
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| 287 | |
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| 288 | address_wr<=x"0000"; |
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| 289 | |
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| 290 | end if; |
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| 291 | |
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| 292 | end process; |
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| 293 | Hold_ack<=Hold_req; -- toujours autoriser la gestion de la mémoire par le DMA |
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| 294 | |
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| 295 | END; |
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