source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.04/EX1_FSM.vhi

Last change on this file was 15, checked in by rolagamo, 12 years ago
File size: 1.2 KB
Line 
1
2-- VHDL Instantiation Created from source file EX1_FSM.vhd -- 05:54:42 06/21/2011
3--
4-- Notes:
5-- 1) This instantiation template has been automatically generated using types
6-- std_logic and std_logic_vector for the ports of the instantiated module
7-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
8
9        COMPONENT EX1_FSM
10        PORT(
11                clk : IN std_logic;
12                reset : IN std_logic;
13                fifo_empty : IN std_logic;
14                fifo_data_out : IN std_logic_vector(7 downto 0);
15                switch_port_in_full : IN std_logic;
16                ram_data : IN std_logic_vector(7 downto 0);
17                dma_grant : IN std_logic;         
18                ram_address : OUT std_logic_vector(15 downto 0);
19                priority_rotation : OUT std_logic;
20                fifo_rd_en : OUT std_logic;
21                switch_port_in_data : OUT std_logic_vector(7 downto 0);
22                switch_port_in_wr_en : OUT std_logic;
23                dma_request : OUT std_logic
24                );
25        END COMPONENT;
26
27        Inst_EX1_FSM: EX1_FSM PORT MAP(
28                clk => ,
29                reset => ,
30                fifo_empty => ,
31                fifo_data_out => ,
32                switch_port_in_full => ,
33                ram_data => ,
34                ram_address => ,
35                priority_rotation => ,
36                fifo_rd_en => ,
37                switch_port_in_data => ,
38                switch_port_in_wr_en => ,
39                dma_request => ,
40                dma_grant =>
41        );
42
43
Note: See TracBrowser for help on using the repository browser.