Context Navigation

← Previous Revision
Next Revision →
Blame
Revision Log

EX2_FSM.vhd

Last change on this file was 64, checked in by rolagamo, 13 years ago

File size: 25.0 KB

Line
1	----------------------------------------------------------------------------------
2	-- Company: GRIIA - ETIS
3	-- Engineer: GAMOM, KIEGAING
4	--
5	-- Create Date: 01:02:10 06/17/2011
6	-- Design Name:
7	-- Module Name: EX2_FSM - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	-- machine a etat qui execute la reception des packet dans le core mpi
13	-- Dependencies:
14	--ss
15	-- Revision: 26/01/2012
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	library NocLib ;
22	use IEEE.STD_LOGIC_1164.ALL;
23	use IEEE.Numeric_std.ALL;
24	use IEEE.STD_LOGIC_UNSIGNED.ALL;
25	use Work.Packet_type.ALL;
26	use NocLib.CoreTypes.all;
27	---- Uncomment the following library declaration if instantiating
28	---- any Xilinx primitives in this code.
29	--library UNISIM;
30	--use UNISIM.VComponents.all;
31
32	entity EX2_FSM is
33
34	generic (
35	pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur
36	nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1
37	);
38	Port ( clk : in STD_LOGIC;
39	reset : in STD_LOGIC;
40
41	Instruction_en : in std_logic;
42
43	dma_wr_grant : in STD_LOGIC;
44	dma_wr_request : out STD_LOGIC;
45	dma_rd_grant : in STD_LOGIC;
46	dma_rd_request : out STD_LOGIC;
47	ram_rd : out std_logic;
48	ram_wr : out std_logic;
49	ram_address : out std_logic_vector(ADRLEN-1 downto 0);
50	Ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
51	Ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
52
53	fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0);
54	fifo_wr_en : out STD_LOGIC;
55	fifo_full : in STD_LOGIC;
56
57	AppRank : in STD_LOGIC_VECTOR(3 downto 0);
58	AppSize : in STD_LOGIC_VECTOR(3 downto 0);
59	packet_received : out STD_LOGIC;
60	packet_ack : in STD_LOGIC;
61	barrier_completed : out STD_LOGIC;
62	Ready : Out std_logic;
63	AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application
64	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
65	Initialized:in std_logic ; -- état de la Lib
66
67	switch_data_available : in STD_LOGIC;
68	switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0);
69	switch_port_out_rd_en : out STD_LOGIC
70
71
72
73	);
74	end EX2_FSM;
75
76	architecture Behavioral of EX2_FSM is
77	-- définition du type etat de la machine à etat
78	type fsm_states is (fetch_packet_type, decode_packet_type, decode_packet_type2,
79	fetch_addresses,execute_spawn,execute_put1,execute_put2,execute_put3 ,execute_put4,
80	execute_put5,execute_get1, execute_get2,execute_get3,execute_get4,
81	execute_barrier1, execute_barrier2, execute_barrier3, execute_barrier4,
82	execute_barrier5, execute_barrier6, execute_barrier7,execute_init1,execute_init2);
83	signal ex2_state_mach :fsm_states;
84	-- machine a etat du module
85	signal packet_type : std_logic_vector(3 downto 0);
86	signal packet_length : std_logic_vector(Word-1 downto 0);
87	signal barrier_counter : std_logic_vector(3 downto 0);
88	signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0');
89	signal n : std_logic_vector(3 downto 0);
90	signal dest_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'Z');
91	signal data_to_write_fifo : std_logic_vector(Word-1 downto 0);
92	signal Ex2_on : std_logic:='0';
93	signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
94
95	begin
96	ram_address <= dest_address;
97	fifo_data <= data_to_write_fifo;
98
99	-- processus de transistion entre les etats
100	fsm_nst_logic : process(clk)
101	variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée
102	variable tempval : std_logic_vector(Word-1 downto 0);
103	begin
104	if rising_edge(clk) then
105	if reset = '1' then
106	ex2_state_mach <= fetch_packet_type;
107	Ex2_on<='0';
108	barrier_counter <= "0000";
109	else
110	Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non
111	case ex2_state_mach is
112	when fetch_packet_type => if switch_data_available ='1' and Ex2_on='1' then --and initialized ='1'
113	ex2_state_mach <= decode_packet_type;
114	packet_type<=switch_port_out_data(7 downto 4);
115	else
116	ex2_state_mach <= fetch_packet_type;
117	end if;
118	when decode_packet_type => if switch_data_available ='0' then
119	ex2_state_mach <= decode_packet_type;
120	else
121	if packet_type = MPI_PUT then
122	packet_length <= switch_port_out_data - 2;
123	n <="0000";
124	ex2_state_mach <= decode_packet_type2;
125	elsif packet_type = MPI_GET then
126	packet_length <=switch_port_out_data-2;
127	ex2_state_mach <= decode_packet_type2;
128	elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
129	packet_length <= switch_port_out_data;
130	n <= "0000";
131	ex2_state_mach <= execute_barrier1;
132	elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then
133	ex2_state_mach <= execute_init1;
134	else
135	ex2_state_mach <= decode_packet_type;
136	end if;
137	end if;
138	when decode_packet_type2 => if packet_type = MPI_PUT then
139	ex2_state_mach <= fetch_addresses;
140	else
141	ex2_state_mach <= execute_get1;
142	end if;
143	when fetch_addresses => if switch_data_available = '1' and n = 0 then
144	dest_address(15 downto 8) <= switch_port_out_data;
145	n <= n + 1;
146	ex2_state_mach <= fetch_addresses;
147	elsif switch_data_available = '1' and n = 1 then
148	dest_address(Word-1 downto 0) <= switch_port_out_data;
149	packet_length <= packet_length - 2;
150	ex2_state_mach <= execute_put1;
151	else
152	ex2_state_mach <= fetch_addresses;
153	end if;
154	-- execution du mpi Init
155	when execute_init1 =>if Initialized='1' then
156	ex2_state_mach<=execute_init2;
157	end if;
158	when execute_init2=> if AppInitAck='1' then
159	ex2_state_mach<=fetch_packet_type;
160	end if;
161	when execute_put1 => if dma_wr_grant = '1' then
162	ex2_state_mach <= execute_put2;
163	data_to_ram<=switch_port_out_data;
164	rd_ok<='1';
165	n<="0000";
166	delai:=0;
167	else
168	ex2_state_mach <= execute_put1;
169	end if;
170	when execute_put2 => if unsigned( packet_length) > 1 then
171
172	if switch_data_available = '1' and dma_wr_grant='1' then
173
174	packet_length <= packet_length - 1;
175	dest_address <= dest_address + 1;
176	ex2_state_mach <= execute_put2;
177	rd_ok<='1';
178	wr_ok<='1';
179	data_to_ram<=switch_port_out_data;
180	else
181	if switch_data_available = '1' and dma_wr_grant='0' then
182	if delai=0 then
183	data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
184	end if;
185	delai:=1;--indique qu'un temps supplémentaire est
186	--nécessaire pour écrire la donnée en RAM
187	end if;
188	ex2_state_mach <= execute_put2;
189	rd_ok<='0'; --bloaque la lecture du switch pour ne pas perdre les données
190	end if;
191	else
192	if switch_data_available = '1' then
193	--la dernière donnée à écrire en RAM
194	data_to_ram<=switch_port_out_data;
195	rd_ok<='0';
196	wr_ok<='1';
197	else
198	rd_ok<='1';
199	wr_ok<='0';
200	end if;
201	if dma_wr_grant='1' then
202
203	ex2_state_mach <= execute_put3;
204	Wr_ok<='0';
205
206	end if;
207	end if;
208
209	when execute_put3 => if dma_rd_grant='1' then
210	dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
211	ex2_state_mach <= execute_put4;
212	n<="0000";
213	rd_ok<='1';
214	wr_ok<='0';
215	end if;
216
217	when execute_put4 => if n <=4 then
218
219	dma_wr<='1'; --demander un accès exclusif au bus
220	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
221	else
222	dma_wr<='0';
223	dma_rd<='0';
224	end if;
225	if n=0 then
226	if dma_rd_grant='1' then
227	n<=n+1;
228	else
229	rd_ok<='1';
230	wr_ok<='0';
231	end if;
232	elsif n=1 then
233	if dma_rd_grant='1' then
234	n<=n+1;
235	else
236	rd_ok<='1';
237	wr_ok<='0';
238	end if;
239	elsif n=2 then
240	if dma_rd_grant='1' then
241	n<=n+1;
242	tempval:=Ram_data_in;
243	tempval(4):='1'; --SET du bit DReceived
244	tempval(1):='0'; --reset du bit DRING !!
245	data_to_ram<=tempval;
246	rd_ok<='0';
247	wr_ok<='1';
248	else
249	rd_ok<='1';
250	wr_ok<='0';
251	n<=n-1;
252	end if;
253	elsif n=3 then
254	if dma_wr_grant='1' then
255	rd_ok<='0';
256	wr_ok<='1';
257	n<=n+1;
258	end if;
259	elsif n=4 then
260	if dma_wr_grant='1' then
261	rd_ok<='0';
262	wr_ok<='1';
263	ex2_state_mach <= execute_put5;
264	n<="0000";
265	end if;
266	end if;
267
268
269
270	dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
271	when execute_put5 =>
272	ex2_state_mach <= fetch_packet_type; -- fin du mpi_put
273
274
275	when execute_get1 => if switch_data_available = '1' then -- conversion du get en put en empilement dans le fifo
276	data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);
277	packet_length <= packet_length - 1;
278	ex2_state_mach <= execute_get2;
279	wr_ok<='1';
280	end if;
281	when execute_get2 => if fifo_full = '0' and switch_data_available ='1' and packet_length > 0 then
282	data_to_write_fifo <= switch_port_out_data;
283	packet_length <= packet_length - 1;
284	ex2_state_mach <= execute_get2;
285	wr_ok<='1';
286	elsif packet_length = 0 and switch_data_available ='1' then--
287	ex2_state_mach <= fetch_packet_type;
288	wr_ok<='0';
289	else
290	ex2_state_mach <= execute_get3;
291	wr_ok<='0';
292	end if;
293	when execute_get3 => if dma_rd_grant='1' then -- fin du mpi_put
294	ex2_state_mach <= execute_get4;
295	n<="0000";
296	--activer le bit sending du registre de transfert
297	else
298	ex2_state_mach <= execute_get3;
299	end if;
300
301	dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
302	when execute_get4 => if n <4 then
303
304	dma_wr<='1'; --demander un accès exclusif au bus
305	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
306	else
307	dma_wr<='0';
308	dma_rd<='0';
309	end if;
310	if n=0 then
311	if dma_rd_grant='1' then
312	n<=n+1;
313
314	end if;
315	rd_ok<='1';
316	wr_ok<='0';
317	elsif n=1 then
318	if dma_rd_grant='1' then
319	n<=n+1;
320
321	end if;
322	rd_ok<='1';
323	wr_ok<='0';
324
325	elsif n=2 then
326	if dma_rd_grant='1' and dma_wr_grant='1' then
327	n<=n+1;
328	tempval:=Ram_data_in;
329	tempval(2):='1'; --mise à 1 du Bit Dreceiving
330	--tempval(5):='0'; --Mise à 0 du Bit Sent
331	data_to_ram<=tempval;
332	rd_ok<='0';
333	wr_ok<='1';
334	else
335	rd_ok<='1';
336	wr_ok<='0';
337	end if;
338
339	elsif n=3 then
340	if dma_wr_grant = '1' then
341	n<=n+1;
342	rd_ok<='0';
343	wr_ok<='1';
344	end if;
345	elsif n=4 then
346	if dma_wr_grant = '1' then
347	n<="0000";
348	ex2_state_mach <= fetch_packet_type; -- fin du mpi_get
349	else
350	rd_ok<='0';
351	wr_ok<='1';
352	--n<=n-1;
353	end if;
354	end if;
355
356
357	dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
358	-- execution du barrier
359	when execute_barrier1 => if switch_data_available = '1' then
360	pading_data <= switch_port_out_data;
361	ex2_state_mach <= execute_barrier2;
362	else
363	ex2_state_mach <= execute_barrier1;
364	end if;
365	when execute_barrier2 => if packet_type = MPI_BARRIER_REACHED then
366	barrier_counter <= barrier_counter + 1;
367	ex2_state_mach <= execute_barrier4;
368	else
369	ex2_state_mach <= execute_barrier3;
370	end if;
371	when execute_barrier3 => if n < 10 then
372	n <= n + 1;
373	ex2_state_mach <= execute_barrier3;
374	else
375	ex2_state_mach <= fetch_packet_type;
376	end if;
377	when execute_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED
378	data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000";
379	ex2_state_mach <= execute_barrier5;
380	else
381	ex2_state_mach <= fetch_packet_type;
382	end if;
383	when execute_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED
384	data_to_write_fifo <= "00000011";
385	ex2_state_mach <= execute_barrier6;
386	else
387	ex2_state_mach <= execute_barrier5;
388	end if;
389	when execute_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED
390	data_to_write_fifo <= "00000000";
391	ex2_state_mach <= execute_barrier7;
392	else
393	ex2_state_mach <= execute_barrier6;
394	end if;
395	when execute_barrier7 => if fifo_full = '0' then
396	barrier_counter <= "0000";
397	ex2_state_mach <= fetch_packet_type;
398	else
399	ex2_state_mach <= execute_barrier7;
400	end if;
401
402	when others => ex2_state_mach <= fetch_packet_type;
403	end case;
404	end if;
405	end if;
406	end process;
407
408	-- sortie de la machine à etat
409	--
410	ex2_fsm_action : process(ex2_state_mach, fifo_full, packet_length, data_to_write_fifo, packet_type,
411	switch_data_available,switch_port_out_data,Ram_data_in,rd_ok)
412	variable transact : std_logic_vector(Word-1 downto 0);
413	begin
414	-- code fonctionnel
415	case ex2_state_mach is
416
417	when fetch_packet_type => fifo_wr_en <= '0';
418	switch_port_out_rd_en <= switch_data_available;
419	packet_received <= '0';
420	dma_wr_request <= '0';
421	dma_rd_request <= '0';
422	barrier_completed <= '0';
423	Ram_data_out<=(others=>'Z');
424	Ram_rd<='0';
425	Ram_wr<='0';
426	Ready<='1';
427	AppInitReq<='0';
428
429
430	when decode_packet_type => fifo_wr_en <= '0';
431	switch_port_out_rd_en <= switch_data_available;
432	packet_received <= '0';
433	dma_wr_request <= '0';
434	dma_rd_request <= '0';
435	Ram_rd<='0';
436	Ram_wr<='0';
437	Ram_data_out<=(others=>'Z');
438	barrier_completed <= '0';
439	AppInitReq<='0';
440	Ready<='0';
441
442	when decode_packet_type2 => fifo_wr_en <= '0';
443	switch_port_out_rd_en <= '0';
444	packet_received <= '0';
445	dma_wr_request <= '0';
446	dma_rd_request <= '0';
447	Ram_rd<='0';
448	Ram_wr<='0';
449	Ram_data_out<=(others=>'Z');
450	barrier_completed <= '0';
451	AppInitReq<='0';
452	Ready<='0';
453	when fetch_addresses => fifo_wr_en <= '0';
454	switch_port_out_rd_en <= switch_data_available;
455	packet_received <= '0';
456	dma_wr_request <= '0';
457	dma_rd_request <= '0';
458	Ram_rd<='0';
459	Ram_wr<='0';
460	Ram_data_out<=(others=>'Z');
461	barrier_completed <= '0';
462	AppInitReq<='0';
463	Ready<='0';
464
465	when execute_put1 => fifo_wr_en <= '0';
466	switch_port_out_rd_en <= '0';
467	packet_received <= '0';
468	dma_wr_request <= '1';
469	dma_rd_request <= '0';
470	Ram_rd<='0';
471	Ram_wr<='0';
472	Ram_data_out<=(others=>'Z');
473	barrier_completed <= '0';
474	AppInitReq<='0';
475	Ready<='0';
476
477	when execute_put2 => Ready<='0';
478	fifo_wr_en <= '0';
479	switch_port_out_rd_en <=rd_ok;
480
481	if rd_ok = '1' then
482
483	Ram_data_out<=switch_port_out_data;
484	else
485	Ram_data_out<=data_to_ram;
486	end if;
487	Ram_wr<='1';
488	Ram_rd<='0';
489	packet_received <= '0';
490	dma_rd_request <= '0';
491	dma_wr_request <= '1';
492	AppInitReq<='0';
493	barrier_completed <= '0';
494	when execute_put3 => Ready<='0';
495	fifo_wr_en <= '0';
496	switch_port_out_rd_en <=rd_ok;
497	--ne pas corrompre le contenu de la RAM
498	--Ram_data_out<=data_to_ram;
499	Ram_wr<='0';
500	Ram_rd<='1';
501	packet_received <= '0';
502	dma_rd_request <= '1';
503	dma_wr_request <= '0';
504	AppInitReq<='0';
505	barrier_completed <= '0';
506
507
508	when execute_put4 => fifo_wr_en <= '0';
509	Ready<='0';
510	switch_port_out_rd_en <= '0';
511	packet_received <= '1';
512	dma_rd_request <= dma_rd;
513	dma_wr_request <=dma_wr;
514	Ram_wr<=wr_ok;
515	Ram_rd<=rd_ok;
516	AppInitReq<='0';
517	barrier_completed <= '0';
518	Ram_data_out<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution
519
520	when execute_put5 =>
521	Ready<='0';
522	switch_port_out_rd_en<='0';
523	fifo_wr_en <= '0';
524	packet_received <= '1';
525	AppInitReq<='0';
526	barrier_completed <= '0';
527	dma_rd_request <= dma_rd;
528	dma_wr_request <= dma_wr;
529	Ram_rd<=rd_ok;
530	Ram_wr<=wr_ok;
531	Ram_data_out<=data_to_ram;
532	--Result <=(1=>'1',others=>'0'); --put completed
533
534	when execute_get1=> fifo_wr_en <= '0';
535	switch_port_out_rd_en <= switch_data_available;
536	packet_received <= '0';
537	dma_wr_request <= '0';
538	dma_rd_request <= '0';
539	Ram_rd<='0';
540	Ram_wr<='0';
541	Ram_data_out<=(others=>'Z');
542	barrier_completed <= '0';
543	AppInitReq<='0';
544	Ready<='0';
545
546	when execute_get2 => if fifo_full = '0' and switch_data_available = '1' and packet_length > 0 then
547
548	switch_port_out_rd_en <='1';
549	else
550
551	switch_port_out_rd_en <='0';
552	end if;
553
554	fifo_wr_en <= Wr_ok;
555	Ready<='0';
556	packet_received <= '0';
557	dma_rd_request <= '0';
558	dma_wr_request <= '0';
559	Ram_rd<='0';
560	Ram_wr<='0';
561	Ram_data_out<=(others=>'Z');
562	barrier_completed <= '0';
563	AppInitReq<='0';
564
565	when execute_get3 => fifo_wr_en <= '0';
566	Ready<='0';
567	switch_port_out_rd_en <= '0';
568	packet_received <= '1';
569	dma_rd_request <= '1';
570	dma_wr_request <='0';
571	Ram_wr<='0';
572	Ram_rd<='1';
573	AppInitReq<='0';
574	barrier_completed <= '0';
575	--Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
576
577	when execute_get4 =>
578	Ready<='0';
579	barrier_completed <= '0';
580	switch_port_out_rd_en<='0';
581	fifo_wr_en <= '0';
582	packet_received <= '1';
583	AppInitReq<='0';
584	dma_rd_request <= dma_rd;
585	dma_wr_request <= dma_wr;
586	Ram_rd<=rd_ok;
587	Ram_wr<=wr_ok;
588	Ram_data_out<=data_to_ram; --activer le bit DSending
589
590
591	when execute_barrier1 => fifo_wr_en <= '0';
592	switch_port_out_rd_en <= switch_data_available;
593	packet_received <= '0';
594	dma_wr_request <= '0';
595	dma_rd_request <= '0';
596	Ram_rd<='0';
597	Ram_wr<='0';
598	Ram_data_out<=(others=>'Z');
599	barrier_completed <= '0';
600	Ready<='0';
601	AppInitReq<='0';
602
603	when execute_barrier2 => fifo_wr_en <= '0';
604	Ready<='0';
605	switch_port_out_rd_en <='0';
606	packet_received <= '0';
607	dma_wr_request <= '0';
608	dma_rd_request <= '0';
609	Ram_rd<='0';
610	Ram_wr<='0';
611	Ram_data_out<=(others=>'Z');
612	barrier_completed <= '0';
613	AppInitReq<='0';
614
615	when execute_barrier3 => fifo_wr_en <= '0';
616	switch_port_out_rd_en <='0';
617	Ready<='0';
618	packet_received <= '0';
619	dma_wr_request <= '0';
620	dma_rd_request <= '0';
621	Ram_rd<='0';
622	Ram_wr<='0';
623	Ram_data_out<=(others=>'Z');
624	barrier_completed <= '1';
625	AppInitReq<='0';
626
627	when execute_barrier4 => fifo_wr_en <= '0';
628	switch_port_out_rd_en <='0';
629	packet_received <= '0';
630	dma_wr_request <= '0';
631	dma_rd_request <= '0';
632	Ram_rd<='0';
633	Ram_wr<='0';
634	Ram_data_out<=(others=>'Z');
635	barrier_completed <= '0';
636	AppInitReq<='0';
637	Ready<='0';
638
639
640	when execute_barrier5 => fifo_wr_en <= not(fifo_full);
641	switch_port_out_rd_en <='0';
642	packet_received <= '0';
643	dma_wr_request <= '0';
644	dma_rd_request <= '0';
645	Ram_rd<='0';
646	Ram_wr<='0';
647	Ram_data_out<=(others=>'Z');
648	barrier_completed <= '0';
649	AppInitReq<='0';
650	Ready<='0';
651
652	when execute_barrier6 => fifo_wr_en <= not(fifo_full);
653	switch_port_out_rd_en <= '0';
654	packet_received <= '0';
655	dma_wr_request <= '0';
656	dma_rd_request <= '0';
657	Ram_rd<='0';
658	Ram_wr<='0';
659	Ram_data_out<=(others=>'Z');
660	barrier_completed <= '0';
661	AppInitReq<='0';
662	Ready<='0';
663
664	when execute_barrier7 => fifo_wr_en <= not(fifo_full);
665	switch_port_out_rd_en <= '0';
666	packet_received <= '0';
667	dma_wr_request <= '0';
668	dma_rd_request <= '0';
669	Ram_rd<='0';
670	Ram_wr<='0';
671	Ram_data_out<=(others=>'Z');
672	barrier_completed <= '0';
673	AppInitReq<='0';
674	Ready<='0';
675
676
677	when execute_init1 => fifo_wr_en <= not(fifo_full);
678	switch_port_out_rd_en <= '0';
679	packet_received <= '0';
680	dma_wr_request <= '0';
681	dma_rd_request <= '0';
682	Ram_rd<='0';
683	Ram_wr<='0';
684	barrier_completed <= '0';
685	Ready<='0';
686	Ram_data_out<=(others =>'Z');
687	AppInitReq<='1';
688
689
690	when execute_init2 => fifo_wr_en <= not(fifo_full);
691	switch_port_out_rd_en <= '0';
692	packet_received <= '0';
693	dma_wr_request <= '0';
694	dma_rd_request <= '0';
695	Ram_rd<='0';
696	Ram_wr<='0';
697	barrier_completed <= '0';
698	Ram_data_out<=(others =>'Z');
699	AppInitReq<='1';
700	Ready<='0';
701
702	when others => Ready<='1'; -- le module est à nouveau libre
703	fifo_wr_en <= '0';
704	switch_port_out_rd_en <= '0';
705	packet_received <= '0';
706	dma_wr_request <= '0';
707	dma_rd_request <= '0';
708	barrier_completed <= '0';
709	Ram_data_out<=(others=>'Z');
710	Ram_rd<='0';
711	Ram_wr<='0';
712	Ready<='1';
713	AppInitReq<='0';
714	end case;
715
716	end process;
717
718	end Behavioral;
719

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.04/EX2_FSM.vhd

Download in other formats: