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Processing_node.vhd

Last change on this file was 15, checked in by rolagamo, 13 years ago

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1	--------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 01:27:32 04/20/2012
6	-- Design Name:
7	-- Module Name: C:/Core MPI/CORE_MPI/MPICORETEST.vhd
8	-- Project Name: MPI_CORE_COMPONENTS
9	-- Target Device:
10	-- Tool versions:
11	-- Description:
12	--
13	-- VHDL Test Bench Created by ISE for module: MPI_NOC
14	--
15	-- Dependencies:
16	--
17	-- Revision: 11 Juillet 2012
18	-- Revision 0.01 - File Created
19	-- Additional Comments : entité de test de l'environement MPSOC il est constitué d'une
20	--MAE simulant le processeur
21	-- Notes:
22	--
23	--
24	--------------------------------------------------------------------------------
25	LIBRARY ieee;
26	USE ieee.std_logic_1164.ALL;
27	library NocLib ;
28	--use IEEE.STD_LOGIC_ARITH.ALL;
29	--use IEEE.STD_LOGIC_UNSIGNED.ALL;
30	use NocLib.CoreTypes.all;
31	use work.Packet_type.all;
32	-- Uncomment the following library declaration if using
33	-- arithmetic functions with Signed or Unsigned values
34	USE ieee.numeric_std.ALL;
35
36	ENTITY PROCESSING_ELEMENT IS
37	-- entité du processeur du MPI
38	port ( clk : in std_logic;
39	reset : in std_logic;
40	ram_we : in std_logic;
41	ram_ena : in std_logic;
42	ram_enb : in std_logic;
43	ram_do : out std_logic_vector( downto ); --word - 1 downto 0
44	ram_din : in std_logic_vector(word - 1 downto 0);--word - 1 downto 0
45	ram_addra : out std_logic_vector(ADRLEN - 1 downto 0);-- ADRLEN - 1 downto 0
46	ram_addrb : out std_logic_vector(ADRLEN - 1 downto 0);-- ADRLEN - 1 downto 0
47	instruction_en : out std_logic;
48	hold_request : in std_logic;
49	hold_ack : out std_logic;
50	ram_sel : out std_logic;
51	lib_ready : in std_logic;
52	lib_initialized : in std_logic;
53	);
54	END PROCESSING_ELEMENT;
55
56	ARCHITECTURE behavior OF PROCESSING_ELEMENT IS
57
58	--données du programme PE
59	signal SrcAdr0, SrcAdr1, destAdr0, destAdr1, Datalen : std_logic_vector(word - 1downto 0);--
60	signal dpid,dpid_i : natural range 0 to 15;
61	--signaux pour la gestion de la MAE
62	type typ_mae is (InitApp,InitCompleted,writeptr, putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout);
63	signal dcount : natural range 0 to 255:= 0; --permet de compter le packet de données envoyées
64	signal count,count_i : natural range 0 to 15:=0;
65	--signal adresse,adresse_rd :natural range 0 to 65536;
66	signal etPutGet : typ_mae;
67	signal Ram_busy :std_logic:='0';
68	--constant pour la construction du fichier
69	-- ces lignes devront être commentées lors de l'assemblage final
70	BEGIN
71
72
73	dpid<=dpid_i;
74	pPutGet : process(clk)
75
76	variable bfill,destrank,pid,mport : natural range 0 to 15;
77	variable fsrc,ret : natural range 0 to 15:=0;
78	variable timeout : natural range 0 to 255;
79	variable adrToset : std_logic_vector(15 downto 0);
80	variable adresse,adresse_rd :natural range 0 to 65536;
81	begin
82	if (clk'event and clk ='1') then
83	if reset='1' then
84	etputget<= InitApp;
85	adresse:=0;
86	adresse_rd:=0;
87	timeout:=0;
88	dcount<=0;
89	else
90	case etputget is
91
92	when InitApp =>
93	--code pour Init ici
94	--mettre mpi_init à l'adresse mpi
95	--initialisation du module mpi du pn
96	ram_do <=MPI_INIT & x"0" ;
97	fsrc:=1;
98	adrToSet:=std_logic_vector(to_unsigned(core_init_adr,16));
99	if ret/=fsrc then
100	dcount<=0;
101	etputget<=writeptr;
102	adresse:=core_base_adr+2;
103	else
104	adresse:=core_init_adr;
105	etputget<= InitCompleted;
106	end if;
107
108	when writeptr =>
109
110	if PE_Hold_req = '0' then --s'assurer que le bus est disponible
111	if dcount=0 then
112	ram_do <=AdrToSet(7 downto 0);
113	dcount <=dcount+1;
114	--adresse:=adresse+1; --prépare la prochaine écriture
115	elsif dcount=1 then
116	dcount <=dcount+1;
117	adresse:=adresse+1; --prépare la prochaine écriture
118	ram_do <=AdrToSet(15 downto 8);
119	elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
120	ret:=fsrc;
121	dcount<=0;
122	timeout:=0;
123	if fsrc=1 then
124	etputget <= InitApp;
125	elsif fsrc=2 then
126	etputget <= putdata;
127	elsif fsrc=3 then
128	etputget <= getdata;
129	else
130	etputget <= start;
131	end if;
132
133	end if;
134
135	end if;
136	when InitCompleted =>
137	if Lib_Init='1' then
138	etputget <= putdata;
139	end if;
140	when putdata => --construire le packet pour le Put
141	DestRank:=1;
142	adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank;
143	timeout:=0;
144	dcount<=0;
145	fsrc:=2;
146	adrToSet:=std_logic_vector(to_unsigned(core_put_adr,16));
147	if ret/=fsrc then
148	etputget<=writeptr;
149	ret:=0;
150	else
151	etputget<= putdata2;
152	end if;
153
154	when putdata2 =>
155	if dcount<5 then
156	dcount<=dcount+1;
157	if dcount=0 then
158	adresse:=core_put_adr;
159	ram_do <=MPI_PUT & std_logic_vector(to_unsigned(Dpid,4));
160	elsif dcount=1 then
161	adresse:=core_put_adr+dcount;
162	ram_do <=SrcAdr1 ;
163	elsif dcount=2 then
164	adresse:=core_put_adr+dcount;
165	ram_do <=SrcAdr0 ;
166	elsif dcount=3 then
167	adresse:=core_put_adr+dcount;
168	ram_do <=DestAdr1 ;
169	elsif dcount=4 then
170	adresse:=core_put_adr+dcount;
171	ram_do <=DestAdr0 ;
172	elsif dcount=5 then
173	adresse:=core_put_adr+dcount;
174	ram_do <=Datalen ;
175	end if;
176	else
177	adresse:=core_base_adr+1;
178	adresse_rd:=core_base_adr;
179	ram_do <=x"01"; --instruction pulse enable;
180	if ram_din(1)='1' then -- Instruction ack
181	if PE_Hold_Req='0' then
182	adresse:=core_base_adr+1;
183	ram_do <=x"00"; --ramener le IPulse à 0;
184	etPutGet<=putcompleted;
185	else
186
187	end if;
188	end if;
189	end if;
190
191	when putcompleted =>
192	adresse_rd:=core_put_adr+6;
193	if ram_din(0)='1' then --Put completed
194	etPutGet<=GetData;
195	end if;
196	when getdata => --positionnement du mot de longueur des données
197	adresse:=core_get_adr;
198	DestRank:=1;
199	timeout:=0;
200	dcount<=0;
201	fsrc:=3;
202	adrToSet:=std_logic_vector(to_unsigned(core_get_adr,16));
203	if ret/=fsrc then
204
205	etputget<=writeptr;
206	ret:=0;
207	else
208	etputget<= getdata2;
209	end if;
210
211	when getdata2 =>
212	if dcount<5 then
213	dcount<=dcount+1;
214	if dcount=0 then
215	adresse:=core_get_adr;
216	ram_do <=MPI_GET & std_logic_vector(to_unsigned(Dpid,4));
217	adresse:=core_get_adr+dcount;
218	ram_do <=SrcAdr1 ;
219	elsif dcount=2 then
220	adresse:=core_get_adr+dcount;
221	ram_do <=SrcAdr0 ;
222	elsif dcount=3 then
223	adresse:=core_get_adr+dcount;
224	ram_do <=DestAdr1 ;
225	elsif dcount=4 then
226	adresse:=core_get_adr+dcount;
227	ram_do <=DestAdr0 ;
228	elsif dcount=5 then
229	adresse:=core_get_adr+dcount;
230	ram_do <=Datalen;
231	end if;
232	else
233	adresse:=core_base_adr+1;
234	adresse_rd:=core_base_adr;
235	ram_do <=x"01"; --instruction pulse enable;
236	if ram_din(1)='1' then -- Instruction ack
237	etPutGet<=getcompleted;
238	else
239
240	end if;
241	end if;
242
243	when getcompleted =>
244	adresse_rd:=core_get_adr+6;
245	if ram_din(0)='1' then --Put completed
246	if PE_Hold_Req='0' then
247	adresse:=core_base_adr+1;
248	ram_do <=x"00"; --ramener le IPulse à 0;
249	etPutGet<=Terminate;
250	else
251	timeout:=timeout+1;
252	end if;
253	end if;
254
255
256	when terminate =>
257
258
259	etputget<=start;
260
261	when st_timeout =>
262
263	--if ram_busy='1' then
264	etputget<=start;
265	--end if
266	etputget<=start;
267	end case;
268	ram_addra <=STD_LOGIC_VECTOR(to_unsigned(adresse,16));
269	ram_addrb <=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16));
270	end if; --reset='1'
271	end if;
272	end process pPutGet;
273
274	majPutGet:process (etputget)
275
276	begin
277	case etputget is
278	when start =>
279	ram_we <='0';
280	ram_ena<='0';
281	ram_enb<='0';
282	instruction_en<='0';
283
284	when fillmem =>
285	ram_we <='1';
286	ram_ena<='1';
287
288	ram_enb<='0';
289	instruction_en<='0';
290	when nextfill =>
291	ram_we <='1';
292	ram_ena<='1';
293	ram_enb<='0';
294	instruction_en<='0';
295	when InitApp =>
296	ram_we <='1';
297	ram_ena<='1';
298	ram_enb<='0';
299	instruction_en<='0';
300	when Initcompleted =>
301	instruction_en<='1';
302	when writeptr =>
303	ram_we <='1'; --écriture dans la RAM
304	ram_ena <='1';
305
306	ram_enb <='0';
307	-- dcount<=dcount+1;
308
309	instruction_en<='0';
310
311	when putdata => --positionnement du mot de longueur des données
312	--dcount<=0;
313	srcadr0<=X"00";
314	srcadr1<=X"01";
315	destadr0<=X"00";
316	destadr1<=X"02";
317	ram_we <='0';
318	ram_ena<='0';
319	--lecture du n° de port de destination
320	ram_enb<='1';
321	datalen<=std_logic_vector(to_unsigned(50,8));
322	dpid_i<=to_integer(unsigned(ram_din(3 downto 0))); --le port est situé ur les 4 bits de poids faible
323	instruction_en<='0';
324	when putdata2 =>
325	ram_we <='1'; --écriture dans la RAM
326	ram_ena <='1';
327
328	ram_enb <='0';
329	-- dcount<=dcount+1;
330	if dcount=5 then
331	instruction_en<='1';
332	else
333	instruction_en<='0';
334	end if;
335	when putcompleted =>
336	ram_we <='1';
337	ram_ena <='1';
338	-- lecture du résultat
339	ram_enb <='1';
340	instruction_en<='1';
341	when getdata =>
342	--dcount<=0;
343	srcadr0<=X"00";
344	srcadr1<=X"02";
345	destadr0<=X"00";
346	destadr1<=X"03";
347	datalen<=std_logic_vector(to_unsigned(50,8));
348	instruction_en<='0';
349	when getdata2 =>
350	ram_we <='1'; --écriture dans la RAM
351	ram_ena <='1';
352
353	ram_enb <='0';
354	--dcount<=dcount+1;
355	if dcount=5 then
356	instruction_en<='1';
357	else
358	instruction_en<='0';
359	end if;
360	when getcompleted =>
361	ram_we <='1';
362	ram_ena <='1';
363	-- lecture du résultat
364	ram_enb <='1';
365	instruction_en<='1';
366	when terminate =>
367
368	ram_we <='0';
369	ram_ena<='0';
370	ram_enb<='0';
371	instruction_en<='0';
372
373	when st_timeout =>
374	ram_we <='0';
375	ram_ena<='0';
376	ram_enb<='0';
377	instruction_en <='0';
378	end case;
379	end process majPutGet ;
380
381	hold:process (clk)
382	begin
383	if rising_edge(clk) then
384	if reset='1' then
385	hold_ack<='0';
386	else
387	if hold_request ='1' then
388	ramsel<='1';
389	pe_hold_ack<= '1';--not(ram_busy); --si la mémoire est occupé, forcé une libération
390	else
391	pe_hold_ack<='0';
392	ramsel<='0';
393	end if;
394	end if;
395	end if;
396	end process hold;
397	END;

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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.04/Processing_node.vhd

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