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load_instr.vhd

Last change on this file was 64, checked in by rolagamo, 12 years ago

File size: 9.6 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer: GAMOM NGOUNOU
4	--
5	-- Create Date: 04:57:14 07/15/2012
6	-- Design Name:
7	-- Module Name: load_instr - Behavioral
8	-- Project Name: MPI CORE
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: Ce mdule permet de charger une instruction dans le FIFO 1
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	library NocLib;
22	use IEEE.STD_LOGIC_1164.ALL;
23
24	-- Uncomment the following library declaration if using
25	-- arithmetic functions with Signed or Unsigned values
26	use IEEE.NUMERIC_STD.ALL;
27	use NocLib.CoreTypes.all;
28	-- Uncomment the following library declaration if instantiating
29	-- any Xilinx primitives in this code.
30	--library UNISIM;
31	--use UNISIM.VComponents.all;
32
33	entity load_instr is
34	Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
35	Instruction_en : in STD_LOGIC;
36
37	clk : in STD_LOGIC;
38	reset : in STD_LOGIC;
39	dma_rd_grant : in STD_LOGIC;
40	dma_rd_request : out STD_LOGIC:='0';
41	instruction_ack : out STD_LOGIC:='0';
42	fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0);
43	fifo_wr :out std_logic:='0';
44	copying :out std_logic:='0';
45	fifo_full : in STD_LOGIC;
46	ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
47	ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0);
48	Ram_rd_en : out std_logic);
49	end load_instr;
50
51	architecture Behavioral of load_instr is
52	--déclaration des types manipulés
53	type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout);
54	--déclaration des signaux
55	signal Ram_address_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
56	--signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM
57	signal Base_Adr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
58
59	signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée
60	signal fifo_din_i:std_logic_vector(WORD-1 downto 0):=(others=>'Z');
61	signal fifo_wr_i :std_logic:='0';
62	signal base_adrset_i : std_logic:='0';
63	signal instruction_ack_i :std_logic:='0';
64	signal Dma_rd_request_i :std_logic:='0';
65	signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE
66	signal etloadinst,next_loadinst : typ_loadinst;
67	begin
68	SYNC_PROC: process (clk)
69	begin
70	if rising_edge(clk) then
71	if (reset = '1') or instruction_en='0' then
72	etloadinst <= init;
73	Base_adrSet<= '0';
74	dma_rd_request<='0';
75	instruction_ack<='0';
76	else
77	etloadinst <= next_loadinst;
78	fifo_din <= fifo_din_i;
79	Base_AdrSet<=Base_adrSet_i;
80	ram_address_rd<=ram_address_i;
81	dma_rd_request<=dma_rd_request_i;
82	instruction_ack<=instruction_ack_i;
83	count<=count_i;
84
85
86	-- assign other outputs to internal signals
87	end if;
88	end if;
89	end process;
90
91	--
92	OUTPUT_DECODE: process (etloadinst,Count_i,Ram_data,Dma_rd_grant,fifo_wr_i,Ram_address_i)
93	variable Adr_inst1,adr_inst2 : natural;
94	begin
95	--insert statements to decode internal output signals
96	--below is simple example
97	case etloadinst is
98	when init =>
99	Dma_rd_request_i<='0';
100	fifo_wr<='0';
101	copying<='0';
102	Ram_rd_en<='0';
103	Instruction_ack_i<='0';
104	fifo_din_i<=(others=>'Z');
105	Base_AdrSet_i<='0';
106
107	when SetAdr =>
108	Dma_rd_request_i<='0';
109	Instruction_ack_i<='0';
110	fifo_wr<='0';
111	copying<='0';
112	Ram_rd_en<='0';
113
114	fifo_din_i<=(others=>'Z');
115	Base_AdrSet_i<='1';
116
117	when getbus =>
118	fifo_wr<='0';
119	copying<='1';
120	Ram_rd_en<=Dma_rd_grant;
121	Dma_rd_request_i<='1';
122	Instruction_ack_i<='0';
123	fifo_din_i<=(others=>'Z');
124	Base_AdrSet_i<='1';
125	when readptr =>
126	fifo_wr<='0';
127
128	copying<='1';
129	Ram_rd_en<='1';
130	Dma_rd_request_i<='1';
131	Instruction_ack_i<='0';
132	fifo_din_i<=(others=>'Z');
133	Base_AdrSet_i<='1';
134	when readmem =>
135	Dma_rd_request_i<='1';
136	copying<='1';
137	Ram_rd_en<='1';
138	fifo_wr<=fifo_wr_i;
139	fifo_din_i<=Ram_data;
140	Base_AdrSet_i<='1';
141	Instruction_ack_i<='0';
142
143	when freebus =>
144	Dma_rd_request_i<='0';
145	fifo_wr<='0';
146	copying<='0';
147	Ram_rd_en<='0';
148	Instruction_ack_i<='1';
149	fifo_din_i<=(others=>'Z');
150	Base_AdrSet_i<='1';
151	when st_timeout =>
152	Dma_rd_request_i<='0';
153	fifo_wr<='0';
154	copying<='0';
155	Ram_rd_en<='0';
156	Instruction_ack_i<='0';
157	fifo_din_i<=(others=>'Z');
158	Base_AdrSet_i<='1';
159	end case;
160	end process;
161
162	NEXT_STATE_DECODE: process (etloadinst, Base_AdrSet,Ram_data,Instruction,instruction_en, fifo_full,dma_rd_grant,count)
163	variable ptr : std_logic_vector(ADRLEN-1 downto 0);
164	variable timeout: natural range 0 to 255;
165	variable Base_AD,ADRtmp,iptr : natural range 0 to 65535;
166	begin
167	--declare default state for next_state to avoid latches
168	next_loadinst <= etloadinst; --default is to stay in current state
169	--insert statements to decode next_state
170	--below is a simple example
171	case (etloadinst) is
172	when init => if base_adrset='1' and Instruction_en='1' then
173
174	next_loadinst<=getbus;
175	elsif Instruction_en='1' then
176	next_loadinst<=Setadr;
177	Base_Adr<=X"0000";
178	else
179	next_loadinst<=init;
180	Base_Adr<=X"0000";
181	end if;
182	fifo_wr_i<='0';
183	count_i<=0;
184	--
185	When Setadr => if Base_adrSet='0' then
186	Base_Adr<=instruction & X"00"; --récupération des bits de poids forts de l'instruction
187	--
188	end if;
189	next_loadinst<=init;
190	Ram_address_i<=(others=>'Z');
191	count_i<=0;
192	when getbus =>
193	BASE_AD:=to_integer(unsigned(base_adr));
194	if dma_rd_grant = '1' then
195	next_loadinst <= readptr;
196
197	-- prépare la prochaine lecture
198
199
200	else
201
202	end if;
203	Ram_address_i<=(others=>'Z');
204	count_i<=0;
205	When readptr =>
206	if dma_rd_grant = '1' then --s'assurer que le bus est disponible
207
208
209
210	if count=0 then
211	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16));
212	count_i <=count+1;
213	elsif count=1 then-- attend que la donnée soit positionnée
214	count_i <=count+1;
215
216	elsif count=2 then
217	count_i <=count+1;
218
219	elsif count=3 then
220	ptr(Word-1 downto 0):=Ram_data;
221	Ram_address_i<=incr_vec(ram_address_i,'1');
222	count_i <=count+1;
223	elsif count=4 then
224
225	count_i <=count+1;
226	elsif count=5 then
227	ptr(15 downto 8):=Ram_data;
228	--count_i <=count+1;
229	--elsif count=6 then
230	--ptr(15 downto 8):=Ram_data;
231	count_i<=0;
232	timeout:=0;
233	next_loadinst <= readmem;
234	else
235
236	end if;
237
238	else
239	timeout:=timeout+1;
240	end if;
241	when readmem =>
242	if dma_rd_grant = '1' then --s'assurer que le bus est disponible
243	if fifo_full='0' then
244
245	if count=0 then
246	iptr:=to_integer(unsigned(ptr));
247	AdrTmp:=iptr;
248	count_i <=count+1;
249	fifo_wr_i<='0';
250	elsif count=1 then
251	count_i <=count+1;
252	fifo_wr_i<='0';
253	elsif count=2 then
254	count_i <=count+1;
255	AdrTmp:=iptr+1; --incrémentation de l'adresse
256	fifo_wr_i<='0';
257	elsif count=3 then
258	count_i <=count+1;
259	fifo_wr_i<='1'; --écriture de la donnée dans le fifo
260	elsif count=4 then
261	fifo_wr_i<='0';
262
263	count_i <=count+1;
264	elsif count=5 then
265	fifo_wr_i<='1'; --lecture de la donnée 2
266	count_i <=count+1;
267	AdrTmp:=iptr+2;
268	elsif count=6 then
269	count_i <=count+1;
270	fifo_wr_i<='0';
271	elsif count=7 then
272	count_i <=count+1;
273	fifo_wr_i<='0';
274	elsif count=8 then
275	fifo_wr_i<='1';--lecture de la donnée 3
276	count_i <=count+1;
277	AdrTmp:=iptr+3;
278	elsif count =9 then
279	count_i <=count+1;
280
281	fifo_wr_i<='0';
282	elsif count=10 then
283	count_i <=count+1;
284	fifo_wr_i<='0';
285
286	elsif count=11 then
287	fifo_wr_i<='1'; --lecture de la donnée 4
288	count_i <=count+1;
289	ADRTmp:=iptr+4;--incrémente l'adresse
290	elsif count =12 then
291	count_i <=count+1;
292
293	fifo_wr_i<='0';
294	elsif count=13 then
295	count_i <=count+1;
296	fifo_wr_i<='0';
297	elsif count=14 then
298	fifo_wr_i<='1';--lecture de la donnée 5
299	count_i <=count+1;
300	ADRtmp:=iptr+5;
301	elsif count =15 then
302	count_i <=count+1;
303	fifo_wr_i<='0';
304	elsif count=16 then
305	count_i <=count+1;
306	fifo_wr_i<='0';
307	elsif count=17 then
308	fifo_wr_i<='1';--lecture de la donnée 6
309	count_i <=count+1;
310	next_loadinst <= freebus;
311	end if;
312
313	Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16));
314	end if;
315
316	else
317	timeout:=timeout+1;
318	if timeout=50 then
319	next_loadinst<=st_timeout;
320	end if;
321	Ram_address_i<=(others=>'Z'); -- le bus n'est pas libre
322
323	end if;
324
325	when freebus =>
326	fifo_wr_i<='0';
327	count_i<=0;
328	Ram_address_i<=(others=>'Z');
329	if instruction_en='0' then
330	next_loadinst <= init;
331	end if;
332	when st_timeout =>
333	fifo_wr_i<='0';
334	Ram_address_i<=(others=>'Z');
335	next_loadinst<=init;
336	count_i<=0;
337	end case;
338	end process;
339
340	end Behavioral;
341

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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.04/load_instr.vhd

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