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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/CORE_MPI.vhd @ 70

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer: GAMOM NGOUNOU
4	--
5	-- Create Date: 05:52:25 06/21/2011
6	-- Design Name:
7	-- Module Name: CORE_MPI - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	Library NocLib;
22	use IEEE.STD_LOGIC_1164.ALL;
23	use IEEE.STD_LOGIC_ARITH.ALL;
24	use IEEE.STD_LOGIC_UNSIGNED.ALL;
25	use NocLib.CoreTypes.all;
26	---- Uncomment the following library declaration if instantiating
27	---- any Xilinx primitives in this code.
28	--library UNISIM;
29	--use UNISIM.VComponents.all;
30
31	entity CORE_MPI is
32	Port (
33	clk : in STD_LOGIC;
34	reset : in STD_LOGIC;
35	clkout : out std_logic;
36	instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
37	instruction_en : in STD_LOGIC; --valide l'instruction
38	instruction_fifo_full : out STD_LOGIC;
39	ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
40	barrier_completed : out STD_LOGIC;
41	packet_received : out STD_LOGIC;
42	packet_ack : in std_logic;
43	PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); --le resultat de l'exécution
44	ram_we : out STD_LOGIC;
45	ram_en : out STD_LOGIC;
46	ram_address_rd : out STD_LOGIC_VECTOR (15 downto 0);
47	ram_address_wr : out STD_LOGIC_VECTOR (15 downto 0);
48	ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
49	hold_req : out STD_Logic; --requete vers application
50	hold_ack : in STD_Logic; --autorisation par l'application
51	switch_port_in_cmd_en : out std_logic;
52	switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0);
53	switch_port_in_wr_en : out STD_LOGIC;
54	switch_port_in_full : in STD_LOGIC;
55	switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0);
56	switch_port_out_rd_en : out STD_LOGIC;
57	switch_port_in_empty : in STD_LOGIC;
58	switch_port_out_data_vailaible : in STD_LOGIC
59	);
60
61	end CORE_MPI;
62
63	architecture Structural of CORE_MPI is
64	--déclaration des types
65	type Type_Noc is
66	record
67	port_in_cmd_en : std_logic;
68	port_out_data : STD_LOGIC_VECTOR (Word-1 downto 0);
69	port_in_wr_en : STD_LOGIC;
70	port_in_empty : STD_LOGIC;
71	port_in_full : STD_LOGIC;
72	port_in_data : STD_LOGIC_VECTOR (Word-1 downto 0);
73	port_out_rd_en : STD_LOGIC;
74	port_out_data_available : STD_LOGIC;
75	end record;
76	-- déclaration des composants MPI
77
78	COMPONENT FIFO_64_FWFT
79	PORT(
80	clk : IN std_logic;
81	din : IN std_logic_vector(Word-1 downto 0);
82	rd_en : IN std_logic;
83	srst : IN std_logic;
84	wr_en : IN std_logic;
85	dout : OUT std_logic_vector(Word-1 downto 0);
86	empty : OUT std_logic;
87	full : OUT std_logic
88	);
89	END COMPONENT;
90	COMPONENT load_instr
91	Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
92	Instruction_en : in STD_LOGIC;
93	clk : in STD_LOGIC;
94	reset : in STD_LOGIC;
95	dma_rd_grant : in STD_LOGIC;
96	dma_rd_request : out STD_LOGIC;
97	instruction_ack : out STD_LOGIC;
98	fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0);
99	fifo_wr :out std_logic;
100	fifo_full : in STD_LOGIC;
101	copying : out std_logic;
102	Ram_rd_en : out STD_LOGIC;
103	ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
104	ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0));
105	end component;
106	COMPONENT DMA_ARBITER
107	PORT(
108
109	clk : IN std_logic;
110	reset : IN std_logic;
111	dma_rd_request : IN std_logic_vector(3 downto 0);
112	data_wr_in : IN std_logic_vector(Word-1 downto 0);
113	data_rd_out : out std_logic_vector(Word-1 downto 0);
114	address_rd : IN std_logic_vector(15 downto 0);
115	address_wr : IN std_logic_vector(15 downto 0);
116
117	dma_wr_request : IN std_logic_vector(3 downto 0);
118	address_out_rd : OUT std_logic_vector(15 downto 0);
119	address_out_wr : OUT std_logic_vector(15 downto 0);
120	ram_en : OUT std_logic;
121	ram_we : OUT std_logic;
122	hold_req : out STD_Logic; --requete vers application
123	hold_ack : in STD_Logic; --autorisation par l'application
124	data_wr_mem : OUT std_logic_vector(Word-1 downto 0);
125	data_rd_mem : IN std_logic_vector(Word-1 downto 0);
126	dma_wr_grant : OUT std_logic_vector(3 downto 0);
127	dma_rd_grant : OUT std_logic_vector(3 downto 0)
128	);
129	END COMPONENT;
130
131	COMPONENT EX1_FSM
132	PORT(
133	clk : IN std_logic;
134	reset : IN std_logic;
135
136	pid : in std_logic_vector (3 downto 0); --port id
137	nprocs : in std_logic_vector (3 downto 0); -- la taille du Noc
138	instruction : in std_logic_vector(Word-1 downto 0);
139	instruction_en : in std_logic;
140	fifo_empty : IN std_logic;
141	fifo_data_out : IN std_logic_vector(Word-1 downto 0);
142	fifo_rd_en : OUT std_logic;
143	fifo_src : IN STD_LOGIC;
144	ram_data_in : IN std_logic_vector(Word-1 downto 0);
145	ram_data_out : out std_logic_vector(Word-1 downto 0);
146	dma_rd_grant : IN std_logic;
147	dma_wr_grant : IN std_logic;
148	dma_wr_request : OUT std_logic;
149	dma_rd_request : OUT std_logic;
150	ram_address : OUT std_logic_vector(15 downto 0);
151	ram_rd,ram_wr : out std_logic;
152	Snd_Data : IN Typ_PortIO(0 to 3);
153	Snd_Start : IN std_logic;
154	Snd_Ack : OUT std_logic;
155	priority_rotation : OUT std_logic;
156
157	switch_port_in_data : OUT std_logic_vector(Word-1 downto 0);
158	switch_port_in_wr_en : OUT std_logic;
159	switch_port_in_full : IN std_logic;
160	Result :out std_logic_vector(Word-1 downto 0);
161	Ready : out std_logic;
162	AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application
163	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
164	Initialized:in std_logic -- état de la Lib
165	);
166	END COMPONENT;
167
168	COMPONENT EX2_FSM
169	PORT(
170	clk : IN std_logic;
171	reset : IN std_logic;
172
173	instruction_en: in std_logic;
174	Initialized : in std_logic;
175
176	switch_port_out_rd_en : OUT std_logic ;
177	switch_data_available : IN std_logic;
178	switch_port_out_data : IN std_logic_vector(Word-1 downto 0);
179	AppRank : in STD_LOGIC_VECTOR;
180	AppSize : in STD_LOGIC_VECTOR;
181	dma_wr_grant : IN std_logic;
182	dma_wr_request : OUT std_logic;
183	dma_rd_grant : IN std_logic;
184	dma_rd_request : OUT std_logic;
185	ram_address : OUT std_logic_vector(15 downto 0);
186	ram_rd,ram_wr : out std_logic;
187	Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
188	Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
189	fifo_full : IN std_logic;
190	Rec_Rdy : OUT std_logic;
191	Rec_Data : OUT Typ_PortIO(0 to 3);
192	Rec_Ack : IN std_logic;
193	fifo_data : OUT std_logic_vector(Word-1 downto 0);
194	fifo_wr_en : OUT std_logic;
195	--fifo_out : out std_logic_vector;
196	Result : out STD_LOGIC_VECTOR (Word-1 downto 0);
197	packet_received : OUT std_logic;
198	packet_ack : IN std_logic;
199	barrier_completed : OUT std_logic;
200	Ready : Out std_logic;
201	AppInitAck : in std_logic;
202	AppInitReq : out std_logic
203	);
204	END COMPONENT;
205
206
207	COMPONENT EX3_FSM
208	PORT(
209	instruction : IN std_logic_vector(Word-1 downto 0);
210	clk : IN std_logic;
211	reset : IN std_logic;
212	Ismain :in std_logic;
213	ResOut : OUT std_logic_vector(Word-1 downto 0)
214
215	);
216	END COMPONENT;
217
218	COMPONENT EX4_FSM
219	PORT(
220	Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); --permet de lire le FIFO
221	Instruction_En : in STD_LOGIC;
222	clk : in STD_LOGIC;
223	reset : in STD_LOGIC;
224	ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0);
225	Result_En : out STD_LOGIC;
226	Ready : out STD_LOGIC;
227	NocSize : out STD_LOGIC_VECTOR;
228	AppRank : out STD_LOGIC_VECTOR;
229	AppSize : out STD_LOGIC_VECTOR;
230	IsMain : out STD_LOGIC;
231	I_fifo_full :in STD_LOGIC;
232	Snd_Ack : IN std_logic;
233	Rec_Rdy : IN std_logic;
234	Rec_Data : IN Typ_PortIO(0 to 3);
235	Snd_data : OUT Typ_PortIO(0 to 3);
236	Snd_Start : OUT std_logic;
237	Rec_Ack : OUT std_logic;
238	I_fifo_wr_en: out STD_LOGIC;
239	I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0);
240	Initialized : out STD_LOGIC;
241	dma_wr_request : out std_logic;
242	dma_rd_request : out std_logic;
243	dma_wr_grant : in std_logic;
244	dma_rd_grant : in std_logic;
245	Ram_address : out STD_LOGIC_VECTOR (15 downto 0); --accès au stockage
246	Ram_wr : out STD_LOGIC; --activation de l'écriture en RAM
247	Ram_Data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);--données des ports
248	Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
249	AppAck : in STD_LOGIC;
250	AppReq : in STD_LOGIC;
251	PortId : out STD_LOGIC_VECTOR(3 downto 0);
252	port_in_cmd_en : out STD_LOGIC;
253	port_in_wr_en : out STD_LOGIC;
254	port_in_empty : in STD_LOGIC;
255	port_in_full : in STD_LOGIC;
256	port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0);
257	port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0);
258	port_out_rd_en : out STD_LOGIC;
259	port_out_data_available : in STD_LOGIC);
260	END COMPONENT;
261
262	COMPONENT EX0_FSM
263	PORT(
264	clk : in STD_LOGIC;
265	reset : in STD_LOGIC;
266
267	Initialized : in STD_LOGIC;
268	Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
269	instruction_en: in STD_LOGIC;
270
271	ClkRate : in STD_LOGIC_VECTOR ;
272	uTimeResult : out STD_LOGIC_VECTOR;
273	TickResult : out STD_LOGIC_VECTOR
274	);
275	END COMPONENT;
276
277
278	COMPONENT MPI_CORE_SCHEDULER
279	PORT(
280	clk : IN std_logic;
281	reset : IN std_logic;
282	priority_rotation : IN std_logic;
283	instruction_fifo_empty : IN std_logic;
284	instruction_fifo_rd_en : OUT std_logic;
285	instruction_fifo_data : IN std_logic_vector(Word-1 downto 0);
286	instruction_available : OUT std_logic;
287
288	get_request_fifo_empty : IN std_logic;
289	get_request_fifo_rd_en : OUT std_logic;
290	get_request_fifo_data : IN std_logic_vector(Word-1 downto 0);
291
292	fifo_rd_en : IN std_logic;
293	fifo_empty : OUT std_logic;
294	fifo_selected : OUT std_logic;
295
296	data_out : OUT std_logic_vector(Word-1 downto 0)
297
298
299	);
300	END COMPONENT;
301
302	-- declaration des signaux d'interconnexion entre les modules du coresignal fifo_sel: std_logic; -- indique l'un des deux fifos d'instructions qui sont prêts
303	signal fifo_instr : std_logic; -- une instruction est prête dans les fifos d'instruction
304
305
306	signal scheduler_fifo_empty : std_logic;
307	signal scheduler_data_out : std_logic_vector(Word-1 downto 0);
308	signal dma_arbiter_data_rd_out : std_logic_vector(Word-1 downto 0);
309
310	signal scheduler_priority_rotation : std_logic;
311	signal scheduler_rd_en : std_logic;
312
313	signal dma_data_rd,dma_data_wr : std_logic_vector(Word-1 downto 0); -- bus à 3 états
314	signal dma_rd_address,dma_rd_address1,dma_rd_address2 : std_logic_vector(15 downto 0); -- ces bus doivent être gérés en logique 3 états!
315	signal dma_rd_address3 : std_logic_vector(15 downto 0);
316	signal dma_wr_address1,dma_wr_address3 : std_logic_vector(15 downto 0);
317	signal dma_wr_address2,dma_wr_address4 : std_logic_vector(15 downto 0);
318	signal dma_wr_address : std_logic_vector(15 downto 0);
319	signal switch_port_in_data_signal : std_logic_vector(Word-1 downto 0);
320	signal ram_data_out_signal : std_logic_vector(Word-1 downto 0);
321	signal weram,rdram,ram_wev,ram_env :std_logic:='0';
322
323	signal i_fifo2_signal : std_logic_vector(Word-1 downto 0);
324	signal Ex_EN : std_logic_vector(4 downto 1):=(others=>'0'); --active les sous MAE permettant de décoder les instructions MPI
325	signal Res4_en:std_logic;--acquittement du réusltat du module n°4
326	signal Ex4_en,Ex1_RDY,Ex2_RDY,EX3_RDY,EX4_RDY : std_logic:='0'; -- indique la fin de l'exécution de la MAE
327	signal ex1_ram_rd,ex2_ram_rd,ex4_ram_rd ,Exi_ram_rd: std_logic:='0' ; -- validation lecture des données en RAM
328	signal ex1_ram_wr,ex2_ram_wr,ex4_ram_wr,Exi_ram_wr : std_logic :='0'; -- validation écriture des données en RAM
329	signal Exi_busy : std_logic:='0';
330	signal Ex1_Result,Ex2_Result,Ex4_result : std_logic_vector(Word-1 downto 0);
331	signal Instr_in : STD_LOGIC_VECTOR (Word-1 downto 0);
332	--================interface DMA avec les modules ======================================
333	signal dma_data_in,Dma_data_in1,dma_data_in2,dma_data_in4 : std_logic_vector(Word-1 downto 0);
334	signal dma_data_out : std_logic_vector(Word-1 downto 0);
335	signal dma_rd_request :std_logic_vector(4 downto 1):=(others=>'0');
336	signal dma_wr_request :std_logic_vector(4 downto 1):=(others=>'0');
337	signal dma_wr_grant,dma_rd_grant:std_logic_vector(4 downto 1);
338	--
339	--======================================================================================
340	--connexion au switch
341
342	signal Noc1,NOC2,NOC3 : Type_Noc; -- regroupement des signaux qui vont au Noc
343
344	--================================================================
345	--déclaration des signaux d'état du Core
346	signal IsMain,SizeSet,RankSet,Initialized,AppReq,AppAck:std_logic;
347	signal InitReq,InitReq1,InitReq2 :std_logic:='0'; -- demande d'initialisation
348	signal InitAck,IAck,Ilatch : std_logic:='0';
349	signal MPISize,MyRank : std_logic_vector(3 downto 0);
350	signal LibState: std_logic_vector(Word-1 downto 0):=(others=>'0'); --ready,receiving,sending,spawning,rwaiting,swaiting,...
351	signal NocSize :std_logic_vector(3 downto 0):=(others=>'0');
352	Signal PortId : std_logic_vector(3 downto 0);
353	Signal uClkRate : std_logic_vector(Word-1 downto 0):="00011010"; --50 Mhz
354	signal uTimeCount :std_logic_vector(31 downto 0):=(others=>'0');
355	signal TickCount : std_logic_vector(31 downto 0):=(others=>'0');
356	signal RankSize: std_logic_vector(Word-1 downto 0):=(others=>'0');
357	--========================================================
358	--déclaration des signaux permettant d'activer le module
359	signal AdrSelect : std_logic_vector(ADRLEN-1 downto 0);
360	--========================================================
361	--signal PushOut_d,RankSize,TickUsOut:std_logic_vector; --résultat de l'execution des commandes mpi
362	--========================================================
363	--connexion avec les FIFO instructions
364	signal fifo1_wr : std_logic;
365	signal fifo1_din : std_logic_vector (Word-1 downto 0);
366	signal fifo_sel : std_logic; --permet d'arbitrer la priorité de lecture entre les deux fifos
367	signal i_fifo1_rd_en : std_logic;
368	signal fifo1_full : std_logic;
369	signal i_fifo1_empty : std_logic;
370	signal i_fifo1_data_out : std_logic_vector(Word-1 downto 0);
371	signal i_fifo2_rd_en : std_logic;
372	signal i_fifo2_data_out : std_logic_vector(Word-1 downto 0);
373	signal i_fifo2_data_in : std_logic_vector(Word-1 downto 0);
374	signal i_fifo2_wr_en : std_logic;
375	signal i_fifo2_empty : std_logic;
376	signal i_fifo2_full : std_logic;
377	signal Ex2_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0');
378	signal Ex2_i_fifo2_wr_en : std_logic:='0';
379	--signaux pour les données entre modules
380	signal Snd_Ack :std_logic;
381	signal Rec_Rdy : std_logic;
382	signal Rec_Data : Typ_PortIO(0 to 3);
383	signal Snd_data : Typ_PortIO(0 to 3);
384	signal Snd_Start : std_logic;
385	signal Rec_Ack : std_logic;
386	--signal i_fifo2_empty : std_logic;
387	--signal i_fifo2_full : std_logic;
388	signal Ex4_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0');
389	signal Ex4_i_fifo2_wr_en : std_logic:='0';
390	--signal i_fifo2_empty : std_logic;
391	--signal i_fifo2_full : std_logic;
392	-- signaux pour la gestion des MAE
393	signal n,n_i :natural range 0 to 7:=0;
394	signal St_Ex1,St_Ex2,St_Ex4:natural range 0 to 7:=0;
395	signal Next_St_Ex1,Next_St_Ex2,Next_St_Ex4:natural range 0 to 7:=0;
396	--===========================================================
397
398	begin
399	--switch_port_in_data_signal <= ;
400	--switch_port_out_data_signal <= ;
401	-- istanciation des composants du core MPI
402	Instruction_Fifo1: FIFO_64_FWFT PORT MAP(
403	clk =>clk,
404	din =>fifo1_din,
405	rd_en => i_fifo1_rd_en,
406	srst => reset,
407	wr_en => fifo1_wr,
408	dout =>i_fifo1_data_out,
409	empty => i_fifo1_empty,
410	full => fifo1_full
411	);
412
413	Instruction_Fifo2: FIFO_64_FWFT PORT MAP(
414	clk =>clk,
415	din => i_fifo2_data_in ,
416	rd_en =>i_fifo2_rd_en,
417	srst =>reset,
418	wr_en =>i_fifo2_wr_en,
419	dout =>i_fifo2_data_out,
420	empty =>i_fifo2_empty,
421	full => i_fifo2_full
422	);
423	LD_instr:load_instr PORT MAP (
424
425	Instruction =>Instruction,
426	Instruction_en =>Instruction_en,
427	clk =>clk,
428	reset =>reset,
429	dma_rd_grant =>dma_rd_grant(3),
430	dma_rd_request =>dma_rd_request(3),
431	copying=> Exi_busy,
432	instruction_ack =>iack, --indique la fin de la copie d'une instruction dans le FIFO
433	fifo_din => fifo1_din,
434	fifo_wr => fifo1_wr,
435	fifo_full =>fifo1_full,
436	Ram_rd_en=> Exi_ram_rd,
437	ram_address_rd => dma_rd_address3,
438	ram_data =>dma_data_out --sortie DMA
439	);
440
441	pushout(0)<=ILatch;
442	pushout(1)<=IsMain;
443	pushout(2)<=SizeSet;
444	pushout(3)<=RankSet;
445	pushout(4)<=Initialized;
446	pushout(5)<=Ex1_result(1); --
447	pushout(6)<=LibState(3); --Spawn
448
449	MPI_CORE_EX0_FSM: EX0_FSM PORT MAP(
450	instruction => i_fifo1_data_out,
451	instruction_en=> '1',
452	uTimeResult => uTimeCount,
453	TickResult => TickCount,
454	Initialized => Initialized, -- indique si la l'appel à init a été concluant
455	ClkRate => uClkRate,
456	clk =>clk ,
457	reset => reset
458	);
459	MPI_CORE_EX1_FSM: EX1_FSM PORT MAP(
460	clk =>clk ,
461	reset =>reset,
462	pid => MyRank, --port Id
463	nprocs=>MPISize, -- à revoir dans certains cas ou tous les PEs ne sont pas connectés
464	fifo_empty => scheduler_fifo_empty ,
465	fifo_data_out =>scheduler_data_out,
466	fifo_rd_en =>scheduler_rd_en,
467	fifo_src =>fifo_sel,
468	priority_rotation => scheduler_priority_rotation,
469
470	instruction_en=>Ex_en(1), --active le module
471	Instruction => Instruction,
472	switch_port_in_full =>Noc1.port_in_full, --ces signaux doivent être contrôlés en 3 state logic
473	switch_port_in_data =>Noc1.port_in_data,
474	switch_port_in_wr_en =>Noc1.Port_in_wr_en ,
475
476	Snd_Data =>Snd_Data,
477	Snd_Start =>Snd_start,
478	Snd_Ack =>Snd_ack,
479	Ram_rd => ex1_ram_rd,
480	Ram_wr =>ex1_ram_wr,
481	ram_data_in =>dma_data_out,
482	Ram_data_out =>dma_data_in1,
483	ram_address=>dma_wr_address1,
484	--ram_address =>dma_rd_address2, --la même adresse sert pour la lecture ou l'écriture
485	dma_rd_request =>dma_rd_request(1),
486	dma_wr_request =>dma_wr_request(1),
487	dma_rd_grant =>dma_rd_grant(1) ,
488	dma_wr_grant =>dma_wr_grant(1) ,
489
490	AppInitReq => InitReq1, -- requête d'initialisation de l'application
491	AppInitAck =>Res4_En , -- Acquitement d'initialisation
492	Initialized=>Initialized, -- état de la Lib
493	Result => Ex1_Result, -- le résultat de l'exécution
494	Ready=> Ex1_Rdy
495	);
496	instruction_fifo_full<=fifo1_full;
497	dma_rd_address1<=dma_wr_address1; --la même adresse sert pour la lecture ou l'écriture en RAM
498	Exi_sync :process(reset,clk)
499
500	begin
501	if rising_edge(clk) then
502	if reset='1' then
503	St_Ex2<=0;
504	St_Ex1<=0;
505	St_Ex4<=0;
506	Ilatch<='0';
507	n<=0;
508	else
509	St_Ex2<=Next_St_Ex2;
510	St_Ex1<=Next_St_Ex1;
511	St_Ex4<=Next_St_Ex4;
512	ILatch<=Iack;
513	n<=n_i;
514	end if;
515	end if;
516	End process Exi_sync;
517	-- détermination de l'activation des module
518	--scheduler_priority_rotation<=not(Ex1_rdy);
519	Ex1_Act:process(ST_Ex1,Initialized,fifo_instr,n,InitReq,Ex4_rdy,Ex1_rdy,Ex2_rdy)--A qoui sert encore ce processus (26/10/12) ????
520	variable c_cyl:natural range 0 to 15:=0;
521	begin
522	if reset='1' then
523	Next_St_ex1<=0;
524	c_cyl:=0;
525	else -- cette machie à état permet de distinguer les activations de Ex4 et Ex1
526	case St_ex1 is
527	when 0 => if InitReq='1' and Initialized='0' then
528	Next_St_ex1<=1;
529	elsif InitReq='1' and Initialized='1' then
530	Next_St_ex1 <=2;
531	elsif fifo_instr='1' then --cas d'une instruction directe qui est présente
532	--if fifo_sel='0' then
533	Next_St_ex1 <=2;
534	--end if;
535	end if;
536
537	when 1 => if Ex4_Rdy='1' then
538	Next_St_ex1<=4;
539	end if;
540	when 2 => if Ex1_rdy='0' then
541	Next_St_ex1<=3;
542	end if;
543
544	when 3 => if Ex1_rdy='1' then
545	Next_St_ex1<=0;
546	end if;
547	if initreq='1' then
548	Next_St_ex1<=1;
549	end if;
550	when 4 => if Ex2_rdy='0' then --s'il y a un message du réseau
551	--compter quelques cycles d'horloges pour attendre initreq2
552	if n=4 then
553	Next_St_ex1<=0;
554	n_i<=0;
555	else
556	n_i<=n+1;
557	end if;
558	else
559	Next_St_ex1<=0;
560	end if;
561
562	when others =>
563	Next_St_ex1<=0;
564	end case;
565	end if;
566	end process ex1_Act;
567
568	ex1_v:process(St_Ex1)
569	begin
570	case St_Ex1 is
571	when 0 =>
572	Ex_en(1)<='0';
573	when 1 =>
574	Ex_en(1)<='0';
575	when 2\|3 =>
576	Ex_en(1)<='1';
577	when others =>
578	Ex_en(1)<='0';
579	end case;
580
581	end process ex1_v;
582
583	Ex2_nextState:Process(reset,st_Ex2, Ex4_rdy,Initialized,Ex2_Result,Ex2_rdy) --active la réception lorsqu' Put ou un Get ou un Init a été effectué
584	begin
585	Next_St_Ex2<=st_Ex2;
586	Case st_Ex2 is
587
588	when 0 =>
589	if Initialized='1' and Ex4_rdy='1' then --- Ex1_result(0)='1' or Ex1_result(1)='1' or Ex1_result(2)='1' then
590	Next_St_Ex2<=1; --active la réception des mesages sur le noeud.
591
592	else
593	Next_St_Ex2<=0;
594	end if;
595	When 1 =>
596	if Ex2_rdy='0' then
597	Next_St_Ex2<=2;
598	end if;
599	When 2 =>
600	if Ex2_rdy='1' then
601	Next_St_Ex2<=0;
602	end if;
603	when others =>
604	Next_St_Ex2<=0;
605	end case;
606	end process;
607	Ex2_val:Process(st_Ex2,Ex4_result) --
608
609	begin
610	Case st_Ex2 is
611
612	when 0 =>
613	Ex_en(2)<='0';
614	LibState(3)<='0';
615	when 1\|2 =>
616	Ex_en(2) <='1';
617	when 3\|4\|5\|6\|7 =>
618	Ex_en(2)<='0';
619	when others=>
620	Ex_en(2)<='0';
621	end case;
622	if rising_edge(Ex4_result(1)) then
623	LibState(3)<='1'; --spawn a été détecté.
624	end if;
625	end process;
626
627	Ex_en_proc:process (clk,reset)
628	begin
629	if rising_edge(clk) then
630	if reset='1' then
631	Ex4_en<='0';
632	else
633
634	if Ex_en(4)='1' then
635	Ex4_en<='1'; --synchro
636	else
637	Ex4_en<='0'; --synchro
638	end if;
639	end if;
640	end if;
641	end process;
642	Ex4_Active:process (St_Ex4,initreq1,initreq2,Ex1_rdy,Initialized,Res4_en)
643	begin
644
645	case St_Ex4 is
646	when 0 =>
647	if (InitReq1='1') then
648	Next_St_Ex4<=1;
649	elsif InitReq2='1' then --le module 1 n'est pas actif
650	Next_St_Ex4<=2;
651	else
652	Next_St_Ex4<=0;
653	end if;
654	when 1 =>
655	If Res4_en='1' then --fin de l'exécution du module
656	Next_St_Ex4<=3;
657	end if;
658	when 2 =>
659	if Res4_en='1' then --Ex2_result(0)='1'
660	Next_St_Ex4<=4;
661	end if;
662	when 3 =>
663	if initreq1='0' then
664	Next_St_Ex4<=5;
665	end if;
666	when 4 =>
667	if initreq2='0' then
668	Next_St_Ex4<=5;
669	end if;
670	when 5 =>
671	Next_St_Ex4<=0;
672	when others =>
673	Next_St_Ex4<=0;
674	end case;
675
676	end process Ex4_active;
677
678	Ex4_active_val:process (st_Ex4)
679	begin
680	case St_Ex4 is
681	when 0 =>
682	AppReq<='0';
683	InitReq<='0';Ex_en(4)<='0';
684	AppAck<='0';
685	when 1 =>
686	AppReq<='1';
687	InitReq<='1';
688	Ex_en(4)<='1';
689	AppAck<='0';
690	when 2 =>
691	AppReq<='1';
692	InitReq<='1';
693	Ex_en(4)<='1';
694	AppAck<='0';
695	when 3 =>
696	AppReq<='0';
697	InitReq<='0';
698	Ex_en(4)<='0';
699	AppAck<='1';
700	when 4 =>
701	AppReq<='0';
702	InitReq<='0';
703	Ex_en(4)<='0';
704	AppAck<='1';
705	when 5 =>
706	AppReq<='0';
707	InitReq<='0';Ex_en(4)<='0';
708	AppAck<='1';
709	when others =>
710	AppReq<='0';
711	InitReq<='0';
712	AppAck<='0';
713	Ex_en(4)<='0';
714	end case ;
715	-- Appreq<=Ex_en(4); --signal d'activation de la MAE Init
716	--InitReq<=(not(Initialized) and InitReq1) or InitReq2; -- deux cas permettent d'activer l'initialisation
717	--AppAck<=Ex1_result(0) or Ex2_result(0); -- signal init completed
718	end process Ex4_active_val;
719	--Ex_en(2)<=Initialized; --- Me pose des soucis en ce moment ???
720	Ex_en(3)<='0';
721	--Ex_en(4)<= '1' when InitReq='1' else '0';
722
723	-- soit une requête du PE soit une requête du Core
724
725
726	MPI_CORE_EX2_FSM: EX2_FSM PORT MAP(
727
728	clk =>clk,
729	reset =>reset,
730	instruction_en=>Ex_en(2),
731	Ready =>Ex2_rdy, --signale que le module est disponible
732	fifo_full =>i_fifo2_full,
733
734	fifo_wr_en => Ex2_i_fifo2_wr_en,
735	fifo_data => Ex2_i_fifo2_data_in,
736
737	switch_port_out_rd_en => Noc2.port_out_rd_en,
738	switch_data_available =>Noc2.port_out_data_available,
739	switch_port_out_data =>Noc2.port_out_data ,
740
741	Rec_Rdy => Rec_Rdy,
742	Rec_Data =>Rec_Data,
743	Rec_Ack =>Rec_Ack,
744	-- il manque un signal pour valider l'accès à la RAM
745	dma_wr_request =>dma_wr_request(2),
746	dma_wr_grant =>dma_wr_grant(2),
747	dma_rd_request =>dma_rd_request(2),
748	dma_rd_grant =>dma_rd_grant(2),
749	ram_address =>dma_wr_address2,
750	Ram_rd => ex2_ram_rd,
751	Ram_wr =>ex2_ram_wr,
752	Ram_data_out=> Dma_data_out,
753	Ram_data_in => Dma_data_in2,
754	packet_received =>packet_received,
755	packet_ack => packet_ack,
756	barrier_completed =>barrier_completed,
757	AppRank =>MyRank,
758	AppSize =>MPISize,
759	AppInitReq => InitReq2, -- requête d'initialisation de l'application
760	AppInitAck =>Res4_En , -- Acquitement d'initialisation
761	Initialized=>Initialized,
762	Result => Ex2_Result -- le résultat de l'exécution
763	);
764	Dma_rd_address2<=Dma_wr_address2;
765	ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP(
766	instruction => instruction,
767	ResOut => RankSize,
768	clk =>clk ,
769	IsMain=>IsMain,
770	reset => reset
771	);
772	MPI_CORE_EX4_FSM :EX4_FSM PORT MAP (
773	Instruction => Instr_in, --STD_LOGIC_VECTOR (Word-1 downto 0);
774	Instruction_En =>Ex4_en, -- ='1' lorsque ce module est sollicité
775	clk =>clk,
776	reset =>reset,
777	ResultOut =>Ex4_Result, --STD_LOGIC_VECTOR (Word-1 downto 0);
778	Result_En =>Res4_En, -- ='1' lorsque fin de l'exécution du module
779	Ready => Ex4_Rdy,
780	NocSize =>NocSize,
781	AppRank =>MyRank,
782	AppSize =>MPISize,
783	IsMain =>IsMain,
784	Rec_Rdy => Rec_Rdy,
785	Rec_Data =>Rec_Data,
786	Rec_Ack =>Rec_Ack,
787	Snd_Ack =>Snd_ack,
788	Snd_data =>Snd_data,
789	Snd_Start =>Snd_Start,
790
791	I_fifo_full =>i_fifo2_full,
792
793	I_fifo_wr_en => Ex4_i_fifo2_wr_en,
794	I_fifo_data_in => Ex4_i_fifo2_data_in,
795	Initialized =>Initialized,
796	Ram_data_out => Dma_data_out,
797	Ram_address =>dma_wr_Address4, --accès au stockage
798	Ram_wr =>Ex4_Ram_wr, --activation de l'écriture en RAM
799	Ram_data_in =>Dma_data_in4, --données à écrire en RAM
800	DMA_rd_Request => dma_rd_request(4),
801	DMA_rd_grant => dma_rd_grant(4),
802	DMA_wr_Request => dma_wr_request(4),
803	DMA_wr_grant => dma_wr_grant(4),
804	AppAck =>AppAck,
805	AppReq =>InitReq,
806	PortId=>PortId,
807	port_in_cmd_en => Noc3.port_in_cmd_en,
808	port_in_wr_en =>Noc3.port_in_wr_en,
809	port_in_empty =>Noc3.port_in_empty,
810	port_in_full =>Noc3.port_in_full,
811	port_in_data =>Noc3.port_in_data,
812	port_out_data =>Noc3.port_out_data,
813	port_out_rd_en =>Noc3.port_out_rd_en,
814	port_out_data_available =>Noc3.port_out_data_available
815
816
817	);
818	--=============Mux des signaux d'accès à la RAM=========
819	ram_we<='1' when (weram='1' and ram_wev ='1') else '0'; -- le contrôleur DMA contrôle directement
820	Ram_en<= '1' when (rdram ='1' or weram='1') else '0'; -- les signaux qui vont vers la RAM
821
822	--dma_data_in <=dma_data_in1 or dma_data_in2;
823	--dma_data_out <=dma_data_out1 or dma_data_out2;
824	mux_ad_ram_rd:process (dma_rd_grant,dma_rd_address1,dma_rd_address2,dma_rd_address3,
825	ex1_ram_rd, Ex2_ram_rd, Exi_ram_rd )
826	begin
827	case dma_rd_grant is
828	when "0001" => dma_rd_address <= dma_rd_address1;
829	rdram<= ex1_ram_rd;
830	when "0010" => dma_rd_address <= dma_rd_address2;
831	rdram<= ex2_ram_rd;
832	when "0100" => dma_rd_address <= dma_rd_address3;
833	rdram<= exi_ram_rd;
834	-- when "1000" => dma_rd_address <= <input4>;
835	when others => dma_rd_address <= (others =>'-');
836	rdram<='0';
837	end case;
838	end process;
839	mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4,ex2_ram_wr,ex4_ram_wr)
840	begin
841	case dma_wr_grant is
842
843	when "0001" => dma_wr_address <= dma_wr_address1;
844	weram<=ex1_ram_wr ;
845	Dma_data_in<=Dma_data_in1;
846	when "0010" => dma_wr_address <= dma_wr_address2;
847	weram<=ex2_ram_wr ;
848	Dma_data_in<=Dma_data_in2;
849	when "1000" => dma_wr_address <= dma_wr_address4;
850	weram<=ex4_ram_wr;
851	Dma_data_in<=Dma_data_in4;
852	when others => dma_wr_address <= (others =>'-');
853	weram<='0';
854	end case;
855	end process;
856	--======================================================
857
858	--=================Mux des signaux qui vont au switch============
859	clkout<=clk; -- permettra le lien avec le module du switch
860
861	NOC1.port_out_data<=switch_port_out_data;
862	NOC1.port_out_data_available<=switch_port_out_data_vailaible;
863	NOC1.port_in_empty<=switch_port_in_empty;
864	NOC1.port_in_full<=switch_port_in_full;
865
866	NOC2.port_out_data<=switch_port_out_data;
867	NOC2.port_out_data_available<=switch_port_out_data_vailaible;
868	NOC2.port_in_empty<=switch_port_in_empty;
869	NOC2.port_in_full<=switch_port_in_full;
870
871	NOC3.port_out_data<=switch_port_out_data;
872	NOC3.port_out_data_available<=switch_port_out_data_vailaible;
873	NOC3.port_in_empty<=switch_port_in_empty;
874	NOC3.port_in_full<=switch_port_in_full;
875	mux_Noc:process (Ex_en,Noc1,Noc2,Noc3,switch_port_out_data_vailaible,Initialized,Initreq2,
876	ex2_i_fifo2_wr_en,ex2_i_fifo2_data_in)
877
878	begin
879	case Ex_en is
880
881	when"0001" =>
882	switch_port_in_data <=Noc1.port_in_data;
883	switch_port_out_rd_en<=NOC2.port_out_rd_en;
884	switch_port_in_wr_en <=NOC1.port_in_wr_en;
885	switch_port_in_cmd_en <='0';
886	when "0010"\|"0011" =>
887	switch_port_in_data <=Noc1.port_in_data;
888	switch_port_out_rd_en<=NOC2.port_out_rd_en;
889	switch_port_in_wr_en <=NOC1.port_in_wr_en;
890	switch_port_in_cmd_en <='0';
891	i_fifo2_wr_en<=ex2_i_fifo2_wr_en;
892	i_fifo2_data_in<=ex2_i_fifo2_data_in;
893	when"1011" => --ce cas pose problème car on ne sait ce qui se passe !!!
894	if initreq2='1' then
895	switch_port_in_data <=Noc1.port_in_data;
896	switch_port_out_rd_en<=NOC3.port_out_rd_en;
897	switch_port_in_wr_en <=NOC1.port_in_wr_en;
898	switch_port_in_cmd_en <='0';
899	else
900	switch_port_in_data <=Noc1.port_in_data;
901	switch_port_out_rd_en<=NOC2.port_out_rd_en;
902	switch_port_in_wr_en <=NOC1.port_in_wr_en;
903	switch_port_in_cmd_en <='0';
904	end if;
905	i_fifo2_wr_en<=ex2_i_fifo2_wr_en;
906	i_fifo2_data_in<=ex2_i_fifo2_data_in;
907	when "1001" => --ca où un appel à init est effectué
908	if initialized='0' then
909	switch_port_in_data <=Noc3.port_in_data;
910	switch_port_out_rd_en<=NOC3.port_out_rd_en;
911	switch_port_in_wr_en <=NOC3.port_in_wr_en;
912	switch_port_in_cmd_en <=NOC3.port_in_cmd_en;
913	else
914	switch_port_in_data <=Noc1.port_in_data;
915	switch_port_out_rd_en<=NOC3.port_out_rd_en;
916	switch_port_in_wr_en <=NOC1.port_in_wr_en;
917	end if;
918	i_fifo2_wr_en<=ex4_i_fifo2_wr_en;
919	i_fifo2_data_in<=ex4_i_fifo2_data_in;
920	when "1010" => --ca où un appel à init est effectué
921	--switch_port_in_data <=Noc3.port_in_data;
922	-- switch_port_out_rd_en<=NOC3.port_out_rd_en;
923	-- switch_port_in_wr_en <=NOC3.port_in_wr_en;
924	-- switch_port_in_cmd_en <=NOC3.port_in_cmd_en;
925	switch_port_in_data <=Noc1.port_in_data;
926	switch_port_out_rd_en<=NOC3.port_out_rd_en;
927	switch_port_in_wr_en <=NOC1.port_in_wr_en;
928	i_fifo2_wr_en<=ex4_i_fifo2_wr_en;
929	i_fifo2_data_in<=ex4_i_fifo2_data_in;
930	when others => --permet de gérer le cas où un spawn arrive par le réseau
931	switch_port_in_data <=Noc3.port_in_data;
932	switch_port_out_rd_en<=NOC3.port_out_rd_en;
933	switch_port_in_wr_en <=NOC3.port_in_wr_en;
934	switch_port_in_cmd_en <=NOC3.port_in_cmd_en;
935
936	i_fifo2_wr_en<=ex4_i_fifo2_wr_en;
937	i_fifo2_data_in<=ex4_i_fifo2_data_in;
938	end case;
939	Instr_in <=Instruction ;
940	if initreq2='1' and Ex_en(4)='1' then
941	Instr_in <=Ex2_Result ;
942	else
943	Instr_in <=Instruction ;
944	end if;
945	i_fifo2_wr_en<=ex2_i_fifo2_wr_en;
946	i_fifo2_data_in<=ex2_i_fifo2_data_in;
947	end process;
948
949
950	--===============================================================
951	MPI_CORE_DMA_ARBITER: DMA_ARBITER PORT MAP(
952	clk =>clk,
953	reset =>reset,
954
955	data_wr_mem => ram_data_in, --vers RAM
956
957	data_rd_mem => Ram_data_out, --- Vers RAM
958	address_rd =>dma_rd_address,
959	address_wr =>dma_wr_address,
960	address_out_rd =>ram_address_rd,
961	address_out_wr =>ram_address_wr,
962	ram_en => ram_env, --validation lecture
963	ram_we =>ram_wev, --validation écriture
964	hold_req=>hold_req,--demande de bus à l'application
965	hold_ack=>hold_ack, -- libération du bus RAM par l'application
966
967	data_rd_out => Dma_data_out, --vers périphérique
968	data_wr_in =>Dma_data_in, --vers périphérique
969	dma_wr_grant =>dma_wr_grant,
970	dma_rd_request => dma_rd_request,
971	dma_rd_grant => dma_rd_grant,
972	dma_wr_request => dma_wr_request
973	);
974
975
976	CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( -- permet de sélectionner la source de l'instruction
977	-- qui sera exécutée par la MAE EX1
978	clk => clk,
979	reset => reset,
980	priority_rotation =>scheduler_priority_rotation,
981	instruction_fifo_empty =>i_fifo1_empty,
982	get_request_fifo_empty => i_fifo2_empty,
983	instruction_fifo_rd_en =>i_fifo1_rd_en,
984	get_request_fifo_rd_en =>i_fifo2_rd_en ,
985	instruction_fifo_data =>i_fifo1_data_out,
986	get_request_fifo_data =>i_fifo2_data_out,
987	fifo_selected =>fifo_sel,
988	instruction_available => fifo_instr,
989	fifo_empty => scheduler_fifo_empty,
990	fifo_rd_en =>scheduler_rd_en,
991	data_out => scheduler_data_out
992	);
993
994	end structural;
995

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