Context Navigation

source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX1_FSM.vhd @ 72

Last change on this file since 72 was 72, checked in by rolagamo, 10 years ago

File size: 44.4 KB

Line
1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:GAMOM /KIEGAING
4	--
5	-- Create Date: 08:12:29 06/16/2011
6	-- Design Name:
7	-- Module Name: EX1_FSM - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: Ce module est chargé de recevoir les instructions du programme MPI et
12	-- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC
13	-- (GET)
14	--
15	-- Dependencies:
16	--
17	-- Revision: 09/07/2012
18	-- Revision 0.03 - File updated
19	-- Additional Comments:
20	--
21	----------------------------------------------------------------------------------
22	library IEEE;
23	use IEEE.STD_LOGIC_1164.ALL;
24	--use IEEE.STD_LOGIC_ARITH.ALL;
25	use IEEE.STD_LOGIC_UNSIGNED.ALL;
26	library NocLib ;
27	use Work.Packet_type.ALL;
28	USE ieee.numeric_std.ALL;
29
30
31	use NocLib.CoreTypes.all;
32	---- Uncomment the following library declaration if instantiating
33	---- any Xilinx primitives in this code.
34	--library UNISIM;
35	--use UNISIM.VComponents.all;
36
37	entity EX1_FSM is
38	-- parametres generiques du module :
39
40
41	Port (
42	--instruction_available : in STD_LOGIC;
43	clk : in STD_LOGIC;
44	reset : in STD_LOGIC;
45	instruction : in std_logic_vector(Word-1 downto 0);
46	instruction_en : in std_logic:='0'; -- active le module instruction
47	pid : in std_logic_vector(3 downto 0) ; -- id du processeur
48	nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1
49	Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
50	Ready : out std_logic; --indique la fin de l'éxécution d'une instruction
51	AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application
52	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
53	Initialized:in std_logic ; -- état de la Lib
54	-- Accès au Fifo d'instructions
55	priority_rotation : out STD_LOGIC:='0';
56	fifo_rd_en : out STD_LOGIC:='0';
57	fifo_empty : in STD_LOGIC;
58	fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0);
59	fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service
60
61
62	Snd_Data : IN Typ_PortIO(0 to 3);
63	Snd_Start : IN std_logic;
64	Snd_Ack : OUT std_logic;
65
66	-- Accès au réseau sur puce
67	switch_port_in_full : in std_logic;
68	switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
69	switch_port_in_wr_en : out STD_LOGIC:='0';
70	-- Accès à la mémoire RAM du PE
71	ram_data_in : in std_logic_vector(7 downto 0);
72	ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0');
73	ram_rd,ram_wr : out std_logic:='0';
74	ram_address : out std_logic_vector(15 downto 0):=(others=>'0');
75
76	dma_wr_request : OUT std_logic:='0';
77	dma_rd_request : OUT std_logic:='0';
78	dma_wr_grant : in STD_LOGIC;
79	dma_rd_grant : in STD_LOGIC);
80	end EX1_FSM;
81
82	architecture Behavioral of EX1_FSM is
83
84	component proto_send is
85	generic (sizemem : natural := 64);
86	port (
87	clk,reset : in std_logic;
88	fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée
89	fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie
90	fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie
91	fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée
92	fifo_in_data_out : in std_logic_vector(Word-1 downto 0);
93	fifo_out_data_in : out std_logic_vector(Word-1 downto 0);
94	packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet
95	copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo
96	snd_start : in std_logic; --début de la réception
97	snd_ack :in std_logic; -- acquittement de la réception
98	snd_comp : out std_logic; -- fin de la réception
99	mem :in memory(0 to sizemem-1)); --données à copier vers le fifo
100
101
102	end component proto_send;
103	-- definition du type etat pour le codage des etats des fsm
104	type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses,
105	decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4,
106	ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5,
107	ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync);
108	-- machine a etat du module
109	signal ex1_state,Next_Ex1_state : fsm_states;
110
111	-- les variables utilisées dans la fsm
112	signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0';
113	signal mem : memory(0 to 3);
114	signal data_to_send,noc_fifo_in : std_logic_vector(Word-1 downto 0);
115	signal packet_type : std_logic_vector(3 downto 0);
116	--signal dpid : std_logic_vector(3 downto 0);
117	signal pid_counter : std_logic_vector(3 downto 0);
118	signal p_len,p_len_i: std_logic_vector(Word-1 downto 0);
119	signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0);
120	signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0';
121	--signal res_address : std_logic_vector(15 downto 0);
122	signal dest_address : std_logic_vector(ADRLEN-1 downto 0);
123	signal n,n_i : natural range 0 to 15;
124	signal len,len_i : natural range 0 to 255;
125	signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0';
126	signal fifo_sel:std_logic:='0';
127	signal run_init:std_logic:='0';
128	begin
129	-- connection des signaux avec les ports
130	ram_address <= src_address;
131	sw_send: proto_send generic map (sizemem=>4)
132	port map (
133	clk=>clk,
134	reset=>reset,
135	fifo_in_empty=>fifo_empty,
136	fifo_in_full=>'0',--pas utilisé
137	fifo_out_empty=>'0',
138	packet_len=>p_len,
139	copy_mode=>fifo_copy,
140	fifo_out_full => switch_port_in_full,
141	fifo_in_rd_en=>fifo_rd,
142	fifo_in_data_out=>fifo_data_out,
143	fifo_out_wr_en =>fifo_wr,
144
145	fifo_out_data_in =>noc_fifo_in,
146	snd_start =>snd_start_sync,
147	snd_ack =>snd_ack1,
148	snd_comp=>snd_comp,
149	mem =>mem
150	);
151	ex1_fsm_sync:process(clk)
152
153	begin
154	if rising_edge(clk) then
155	if reset = '1' then
156	ex1_state <= fifo_select;
157	n<=0;
158	len<=0;
159	p_len<=(others=>'0');
160	snd_ack<='0';
161	src_address<=(others=>'0');
162	else
163	ex1_state<=next_ex1_state;
164	n<=n_i;
165	len<=len_i;
166	p_len<=p_len_i;
167	src_address <= src_address_i;
168	snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4
169	snd_start_sync<=snd_start1;
170	end if;
171	end if;
172	end process ex1_fsm_sync;
173	-- processus de transistion entre les etats
174	fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid,
175	pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address)
176	variable tempval : std_logic_vector(Word-1 downto 0);
177	variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé
178	begin
179	n_i<=n; --valeur par défaut
180	Next_ex1_state <=Ex1_state;
181	case ex1_state is
182	when fifo_select => if instruction_en='1' and fifo_empty ='0' then
183	Next_ex1_state <= fetch_packet_type;
184	else
185	Next_ex1_state <= fifo_select;
186	end if;
187	rd_ok<='0';
188	wr_ok<='0';
189	if instruction_en='1' and snd_start='1' then
190	run_init<='1';
191	Next_ex1_state<=ex1_init_run;
192	end if;
193	--lecture du registre status de la mib MPI
194	when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put
195	Next_ex1_state <= read_status2;
196	else
197	Next_ex1_state <= read_status1;
198	end if;
199	src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
200	when read_status2 =>
201	Next_ex1_state <= fifo_select;
202	when fetch_packet_type => rd_ok<='0';
203	if fifo_empty ='1' then
204	Next_ex1_state <= fifo_select;
205	else
206	packet_type <= fifo_data_out(7 downto 4);
207	data_to_send <= fifo_data_out;
208	Next_ex1_state <= decode_packet_type;
209	rd_ok<='1';
210	end if;
211	when decode_packet_type => rd_ok<='0';
212	if fifo_empty='0' then
213	if packet_type = MPI_PUT then
214	p_len_i <= fifo_data_out + 4;
215	n_i <= 0;rd_ok<='1';
216	Next_ex1_state <= fetch_addresses;
217	elsif packet_type = MPI_GET then
218	len_i <= to_integer(unsigned(fifo_data_out));
219	p_len_i <= fifo_data_out;
220	n_i <= 0; rd_ok<='1';
221	Next_ex1_state <= fetch_addresses;
222	elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
223	p_len_i <= "00000011"; -- = 3
224	pid_counter <= "0000";
225	rd_ok<='1';
226	Next_ex1_state <= ex1_barrier1;
227	elsif packet_type = MPI_INIT then
228	Next_ex1_state<=ex1_init1;
229	len_i <= to_integer(unsigned(fifo_data_out));
230	p_len_i<=fifo_data_out;
231	n_i<=0;rd_ok<='1';
232	elsif packet_type = MPI_ACK then
233	len_i <= to_integer(unsigned(fifo_data_out));
234	p_len_i<=fifo_data_out;
235	n_i <= 0; rd_ok<='0';
236	Next_ex1_state <= ex1_send_Ack;
237	elsif packet_type = MPI_WIN_SYNC then
238	len_i <= to_integer(unsigned(fifo_data_out));
239	p_len_i<=fifo_data_out;
240	n_i <= 0; rd_ok<='0';
241	Next_ex1_state <= ex1_WSynC;
242	elsif packet_type = MPI_SPAWN then
243	Next_ex1_state<=ex1_SPAWN;
244	len_i <= to_integer(unsigned(fifo_data_out));
245	p_len_i<=fifo_data_out;
246	onepop:='1';--il y a une donnée lue
247	src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16));
248	rd_ok<='0';
249	else -- packet non reconnu
250	--synthesis translate_off
251	report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ;
252	--synthesis translate_on
253	if fifo_empty = '1' then
254	Next_ex1_state <= fifo_select;
255
256	else
257	rd_ok<='1';
258	packet_type <= fifo_data_out(7 downto 4); --lire le prochain paquet
259	data_to_send <= fifo_data_out;
260	Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure
261	end if;
262	end if;
263	end if;
264	when fetch_addresses => n_i<=n;rd_ok<='1';
265	if fifo_empty = '0' and n = 0 then
266	src_address_i(15 downto 8) <= fifo_data_out;
267	n_i <= n + 1;
268	Next_ex1_state <= fetch_addresses;
269	elsif fifo_empty = '0' and n = 1 then
270	src_address_i(7 downto 0) <= fifo_data_out;
271	n_i <= n + 1;
272	Next_ex1_state <= fetch_addresses;
273	elsif fifo_empty = '0' and n = 2 then
274	dest_address(15 downto 8) <= fifo_data_out;
275	n_i <= n + 1;
276	Next_ex1_state <= fetch_addresses;
277	elsif fifo_empty = '0' and n = 3 then
278	dest_address(7 downto 0) <= fifo_data_out;
279	n_i <= n+1;
280	elsif n=4 then
281	rd_ok<='0';
282	n_i<=0;
283	Next_ex1_state <= decode_packet_type2;
284	elsif fifo_empty='1' then
285	rd_ok<='0';
286	Next_ex1_state <= fetch_addresses; --attendre les données manquantes
287	else
288	Next_ex1_state <= fifo_select;
289	end if;
290	when decode_packet_type2 => if packet_type = MPI_PUT then
291	Next_ex1_state <= ex1_put1;
292	elsif packet_type = MPI_GET then
293	Next_ex1_state <= ex1_get1;
294	end if;
295	-- execution du mpi put
296	when ex1_put1 => if dma_rd_grant = '1' then
297	Next_ex1_state <= ex1_put2;
298	else
299	Next_ex1_state <= ex1_put1;
300	end if;
301	Wr_ok<='0';
302	when ex1_put2 =>Wr_ok<='0';
303	if switch_port_in_full = '0' and n = 0 then
304	--envoie du code MPI_PUT
305	n_i<= n + 1;
306	wr_ok<='1';
307	Next_ex1_state <= ex1_put2;
308	elsif switch_port_in_full = '0' and n = 1 then
309	data_to_send <= p_len;
310	n_i<= n + 1;
311	wr_ok<='1';
312	Next_ex1_state <= ex1_put2;
313	elsif switch_port_in_full = '0' and n = 2 then
314	data_to_send <= dest_address(15 downto 8);
315	n_i<= n + 1;
316	wr_ok<='1';
317	Next_ex1_state <= ex1_put2;
318	elsif switch_port_in_full = '0' and n = 3 then
319	data_to_send <= dest_address(7 downto 0);
320	n_i<= n +1;
321	wr_ok<='1';
322	Next_ex1_state <= ex1_put2;
323	elsif switch_port_in_full = '0' and n = 4 then
324	p_len_i <= p_len - 4;
325	Next_ex1_state <= ex1_put3;
326	Wr_ok<='0';
327	n_i<=0;
328	else
329	Next_ex1_state <= ex1_put2;
330	end if;
331	when ex1_put3 => wr_ok<='0';
332	if unsigned(p_len)>0 then
333	--if n=0 then
334	-- n_i<=1; --cycle d'attente pour la RAM
335	-- Wr_ok<='0';
336	-- elsif n=1 then
337	if switch_port_in_full = '0' then
338	if n=1 then --creer un délai sur ces signaux par rapport à src_adress
339	p_len_i <= p_len - 1;
340	Wr_Ok<='1';
341	end if;
342	n_i<=1;
343	src_address_i <= src_address+1;
344	Next_ex1_state <= ex1_put3;
345
346
347	else
348	Wr_Ok<='0';
349	src_address_i <= src_address;
350	n_i<=0;
351	end if;
352	--elsif n=2 then
353	-- n_i<=0; --cycle d'attente pour la RAM
354	-- Wr_ok<='0';
355	-- src_address_i <= src_address ; --prochaine lecture
356	--
357	-- end if;
358	else
359	Wr_Ok<='0';
360	Next_ex1_state <= ex1_put4;
361	end if;
362	when ex1_put4 =>rd_ok<='1';
363	wr_ok<='0';
364	if dma_rd_grant = '1' then -- fin du mpi_put
365	Next_ex1_state <= ex1_put5;
366	rd_ok<='0';
367	n_i<=0;
368	data_to_send<="00000001";
369	else
370	Next_ex1_state <= ex1_put4;
371	end if;
372
373	if fifo_src='0' then --détection Put ou Get
374	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
375	else
376	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
377	end if;
378	when ex1_put5 => if n >0 then
379
380	dma_wr<='1'; --demander un accès exclusif au bus
381	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
382	else
383	dma_wr<='0';
384	dma_rd<='0';
385	end if;
386
387	if n=0 then
388
389	n_i<=n+1;
390	elsif n=1 then
391	if dma_rd_grant='1' then
392	n_i<=n+1;
393
394	end if;
395	rd_ok<='1';
396	wr_ok<='0';
397	dma_wr<='1';
398	dma_rd<='1';
399	elsif n=2 then
400	if dma_rd_grant='1' then
401	n_i<=n+1;
402	dma_wr<='1';
403	tempval:=Ram_data_in;
404	end if;
405	rd_ok<='1';
406	wr_ok<='0';
407
408	dma_rd<='1';
409	elsif n=3 then
410	if dma_rd_grant='1' and dma_wr_grant='1' then
411	n_i<=n+1;
412	tempval:=Ram_data_in;
413	--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
414	if fifo_src='0' then -- c'est un put qui est exécuté
415	tempval(5):='1'; -- SET du bit DSENT
416	else -- c'est un Get qui est exécuté
417	tempval(2):='1'; -- ne pas annuler le sending après un GET
418	end if;
419	data_to_send<=tempval;
420	rd_ok<='0';
421	wr_ok<='1';
422	dma_wr<='1';
423	dma_rd<='1';
424	else
425	rd_ok<='1';
426	wr_ok<='0';
427	dma_rd<='0'; --libérer le bus et revenir en arrière
428	dma_wr<='0';
429	n_i<=0;
430	end if;
431	elsif n=3 then
432	if dma_wr_grant = '1' and dma_rd_grant='1' then
433	n_i<=n+1;
434
435	--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
436	end if;
437	rd_ok<='0';
438	wr_ok<='1';
439	dma_wr<='1';
440	dma_rd<='1';
441	elsif n=4 then
442	if dma_wr_grant = '1' and dma_rd_grant='1' then
443	n_i<=n+1;
444
445	src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16));
446
447	end if;
448	rd_ok<='0';
449	wr_ok<='1';
450	dma_wr<='1';
451	dma_rd<='0';
452	elsif n=5 then
453	if dma_wr_grant = '1' then
454	n_i<=n+1;
455
456	-- SET du bit DSENT
457	data_to_send<="00000001";
458	end if;
459	rd_ok<='0';
460	wr_ok<='1';
461	dma_wr<='1';
462	dma_rd<='0';
463	elsif n=6 then
464	n_i<=0;
465	Next_ex1_state <= fifo_select;
466	rd_ok<='0';
467	wr_ok<='0';
468	dma_wr<='0';
469	dma_rd<='0';
470	end if;
471
472
473	when ex1_get1 => wr_ok<='0';
474	if switch_port_in_full = '0' and n = 0 then -- execution du mpi get
475	--écrire l'entête de la fonction
476	n_i<= n + 1;
477	Wr_ok<='1';
478	Next_ex1_state <= ex1_get1;
479	elsif switch_port_in_full = '0' and n = 1 then -- execution du mpi get
480	data_to_send <= "00001000"; -- longueur du paquet sur le réseau ?
481	n_i<= n + 1;
482	Wr_ok<='1';
483	Next_ex1_state <= ex1_get1;
484	elsif switch_port_in_full = '0' and n = 2 then
485	data_to_send <= "0000"&pid; -- Rang source
486	n_i<= n + 1;
487	Wr_ok<='1';
488	Next_ex1_state <= ex1_get1;
489	elsif switch_port_in_full = '0' and n = 3 then
490	data_to_send <= p_len;
491	n_i<= n + 1;
492	Wr_ok<='1';
493	Next_ex1_state <= ex1_get1;
494	elsif switch_port_in_full = '0' and n = 4 then
495	data_to_send <= src_address(15 downto 8);
496	n_i<= n + 1;
497	Wr_ok<='1';
498	Next_ex1_state <= ex1_get1;
499	elsif switch_port_in_full = '0' and n = 5 then
500	data_to_send <= src_address(7 downto 0);
501	n_i<= n + 1;
502	Wr_ok<='1';
503	Next_ex1_state <= ex1_get1;
504	elsif switch_port_in_full = '0' and n = 6 then
505	data_to_send <= dest_address(15 downto 8);
506	n_i<= n + 1;
507	Wr_ok<='1';
508	Next_ex1_state <= ex1_get1;
509	elsif switch_port_in_full = '0' and n = 7 then
510	data_to_send <= dest_address(7 downto 0);
511	n_i<= n + 1;
512	Wr_ok<='1';
513	Next_ex1_state <= ex1_get1;
514	elsif switch_port_in_full = '0' and n = 8 then
515	Next_ex1_state <= ex1_get2;
516	n_i<=0;
517	else
518	Next_ex1_state <= ex1_get1;
519	end if;
520	when ex1_get2 => if dma_wr_grant = '1' then
521	Next_ex1_state <= ex1_get3;
522	src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
523	data_to_send<="00000001";
524	else
525	Next_ex1_state <= ex1_get2;
526	end if;
527	dma_wr<='1';
528	when ex1_send_ack \|ex1_Wsync=> rd_ok<='0';
529	if n = 0 then -- execution du mpi ack /ou Mpi_Win_sync
530	if switch_port_in_full = '0' then
531
532	wr_Ok<='1'; --envoie de la première donnée(code ack)
533	n_i<= n + 1;
534	onepop:='0';
535
536	end if;
537	elsif n = 1 then
538	if fifo_empty='0' and onepop='0' then
539	data_to_send <=p_len ;
540
541	rd_Ok<='1'; --passe la longueur
542	onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
543
544	else
545	rd_Ok<='0';
546	end if;
547
548	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
549	onepop:=not onepop;
550	n_i<= n + 1;
551	wr_ok<='1';
552	elsif (switch_port_in_full = '1') then
553	wr_Ok<='0';
554
555	end if;
556
557	elsif (n= 2) then
558	if fifo_empty='0' and onepop='0' then
559
560	data_to_send <=fifo_data_out;
561	rd_Ok<='1';
562	onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
563
564	else
565	rd_Ok<='0';
566	end if;
567
568	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
569	onepop:=not onepop;
570	n_i<= n + 1;
571	wr_ok<='1';
572	else
573	wr_Ok<='0';
574
575	end if;
576	elsif (n= 3) then
577	if fifo_empty='0' and onepop='0' then
578
579	data_to_send <=fifo_data_out;
580	rd_Ok<='1';
581	onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
582
583	else
584	rd_Ok<='0';
585	end if;
586
587	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
588	onepop:=not onepop;
589	n_i<= n + 1;
590	wr_ok<='1';
591
592	else
593	wr_Ok<='0';
594
595	end if;
596	elsif n = 4 then
597	n_i<=0;
598	Wr_Ok<='0';
599	rd_ok<='0';--vider le tampon
600	Next_ex1_state <= fifo_select;
601
602	end if;
603
604	when ex1_get3 =>if n<3 then --ecriture de la fin d'envoie
605	if dma_wr_grant = '1' then -- fin du post de mpi_get
606
607	n_i<=n+1;
608	data_to_send<="00000001";
609	wr_ok<='1';
610	rd_ok<='0';
611	end if;
612
613	elsif n=3 then
614	n_i<=0;
615	Next_ex1_state <= ex1_get4;
616	end if;
617	src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
618	when ex1_get4 => wr_ok<='0';
619	rd_ok<='0';
620	dma_wr<='1';
621	dma_rd<='1';
622	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
623
624	if n=0 then
625
626	if dma_rd_grant='1' then
627	n_i<=n+1;
628
629	end if;
630	rd_ok<='1';
631	wr_ok<='0';
632
633	elsif n=1 then
634	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
635	if dma_rd_grant='1' then
636	n_i<=n+1;
637
638	end if;
639	rd_ok<='1';
640	wr_ok<='0';
641
642	elsif n=2 then
643	if dma_rd_grant='1' then
644	n_i<=n+1;
645	rd_ok<='1';
646	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
647	end if;
648
649	elsif n=3 then
650	if dma_rd_grant='1' and dma_wr_grant='1' then
651	n_i<=n+1;
652	tempval:=Ram_data_in;
653	rd_ok<='1';
654	wr_ok<='0';
655	dma_wr<='1';
656	dma_rd<='1';
657	else
658	dma_wr<='0';
659	dma_rd<='0';
660	n_i<=n-1;
661	end if;
662	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
663	elsif n=4 then
664	if dma_wr_grant = '1' and dma_rd_grant='1' then
665	n_i<=n+1;
666
667	tempval(6):='1'; --SET du bit Windows Busy --car réception Get
668	tempval(1):='1'; -- SET du bit DReceiving
669	data_to_send<=tempval;
670	else
671	rd_ok<='0';
672	wr_ok<='1';
673	end if;
674	dma_wr<='1';
675	dma_rd<='1';
676	elsif n=5 then
677	n_i<=0;
678	Next_ex1_state <= fifo_select;
679	dma_wr<='0';
680	dma_rd<='0';
681	end if;
682
683	when ex1_spawn => rd_ok<='0';
684	if n = 0 then -- execution du mpi spawn
685	if switch_port_in_full = '0' then
686
687	wr_Ok<='1';
688	n_i<= n + 1;
689	onepop:='0';
690	--data_to_send<=len;
691	end if;
692	elsif n = 1 then
693	if fifo_empty='0' and onepop='0' then
694	data_to_send <=p_len ;
695
696	rd_Ok<='1';
697	onepop:='1'; --une donnée lue il faut arrêter de dépiler
698
699	end if;
700
701	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
702	onepop:='0';
703	n_i<= n + 1;
704	wr_ok<='1';
705	else
706	wr_Ok<='0';
707
708	end if;
709
710	elsif (n= 2) or (n=3) then
711	if fifo_empty='0' and onepop='0' then
712
713	data_to_send <=fifo_data_out;
714	rd_Ok<='1';
715	onepop:='1'; --une donnée lue il faut arrêter de dépiler
716
717	end if;
718
719	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
720	onepop:='0';
721	n_i<= n + 1;
722	wr_ok<='1';
723	else
724	wr_Ok<='0';
725
726	end if;
727	elsif n=4 then
728	n_i<=0;
729	Wr_Ok<='0';
730	rd_ok<='0';
731	Next_ex1_state <= fifo_select;
732	end if;
733	-- execution du barrier
734	when ex1_barrier1 => if switch_port_in_full = '0' then
735	Next_ex1_state <= ex1_barrier2;
736	else
737	Next_ex1_state <= ex1_barrier1;
738	end if;
739	when ex1_barrier2 => if switch_port_in_full = '0' then
740	Next_ex1_state <= ex1_barrier3;
741	else
742	Next_ex1_state <= ex1_barrier2;
743	end if;
744	when ex1_barrier3 => if switch_port_in_full = '0' then
745	Next_ex1_state <= ex1_barrier4;
746	else
747	Next_ex1_state <= ex1_barrier3;
748	end if;
749	when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then
750	pid_counter <= pid_counter + 1;
751	Next_ex1_state <= ex1_barrier1;
752	else
753	Next_ex1_state <= fifo_select;
754	end if;
755	when ex1_init1 => rd_ok<='0';
756	if n=0 then
757	n_i<=n+1;
758	Len_i<=len-2; --deux données a été dépilée
759	elsif n=1 then --vider le fifo instruction
760	if len>0 then
761	if fifo_empty='0' then
762	rd_ok<='1';
763	Len_i<=len-1;
764
765	else
766	rd_ok<='0';
767	Len_i<=Len;
768	end if;
769	else
770	n_i<=n+1;
771	end if;
772	elsif n=2 then --
773	n_i<=0;
774	rd_ok<='0';
775	Next_ex1_state<=ex1_init_run;
776
777	end if;
778
779	when ex1_init_run=> if n=0 then
780	if snd_start='1' then --le module ex4 veut envoyer des données
781	if snd_data(0)(7 downto 4)=MPI_INIT or snd_data(0)(7 downto 4)=MPI_SPAWN then
782	n_i<=n+1;
783
784	for i in 0 to 3 loop
785	mem(i)<=snd_data(i);
786	end loop;
787	end if;
788	P_len_i<=x"04";
789	fifo_copy<='0';
790	snd_ack1<='0';
791
792	end if;
793	if AppInitAck='1' then
794	Next_ex1_state<=ex1_init2;
795	end if;
796	elsif n=1 then
797	fifo_sel<='0';--pas de rotation du fifo instruction
798	snd_start1<='1';
799	P_len_i<=x"04";
800	fifo_copy<='0';
801	snd_ack1<='0';
802
803	n_i<=n+1;
804	elsif n=2 then
805	if snd_comp='1' then
806	snd_ack1<='1';
807
808	snd_start1<='0';
809	n_i<=n+1;
810	end if;
811	elsif n=3 then
812	snd_start1<='0';
813	snd_ack1<='1';
814	fifo_sel<='0';
815	if snd_start='0' then --attente l'annulation de l'envoie
816	n_i<=0;
817	snd_ack1<='0';
818	if run_init='1' then
819	Next_EX1_state<=fifo_select;
820	run_init<='0';
821	end if;
822	end if;
823	end if;
824
825
826	when ex1_init2 =>
827	if n=0 then --envoie du message Spawn Ack sur le réseau
828	if instruction(6)='1' then --Spawned=1 ?
829	n_i<=1;
830	else
831	n_i<=4; --écrire le résultat de la fn
832	end if;
833
834	elsif n=1 then
835	n_i<=n+1;
836	mem(0)<=MPI_INIT & x"0"; --répondre au premier
837	mem(1)<=x"04";
838	mem(2)<=x"00";
839	mem(3)<=INIT_SPAWN & pid;-- indiquer qui répond au
840	elsif n=2 then
841	snd_start1<='1';
842	n_i<=n+1;
843	elsif n=3 then
844	if snd_comp='1' then
845	snd_ack1<='1';
846	snd_start1<='0';
847	n_i<=n+1;
848	end if;
849	elsif n=4 then
850	wr_ok<='1';
851	if dma_wr_grant = '1' then -- fin du mpi_init
852	n_i<=n+1;
853	end if;
854	elsif n=5 then
855	Next_ex1_state <= ex1_init3;
856	n_i<=0;
857	wr_ok<='0';
858	end if;
859
860	-- écriture dans le registre status reg.
861	src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
862	when ex1_init3 =>--if AppInitAck='1' then
863	Next_ex1_state <= fifo_select;
864	--end if;
865	when ex1_ready => Next_ex1_state <= fifo_select;
866	when others => Next_ex1_state <= fifo_select;
867	end case;
868
869	end process;
870
871	-- sortie de la machine à etat
872	ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid,
873	pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok)
874	variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0');
875	begin
876	-- code fonctionnel
877	case Next_ex1_state is
878	when fifo_select => priority_rotation <='1'; -- on peut changer la priorité
879	fifo_rd_en <= '0';
880	switch_port_in_data <= (others =>'0');
881	switch_port_in_wr_en <= '0';
882	dma_rd_request <= '0';
883	dma_wr_request <= '0';
884	Ram_rd<='0';
885	Ram_wr<='0';
886	Ram_data_out<=(others=>'0');
887	AppInitReq<='0';
888	Result <=(others=>'0');
889	Ready<='1';
890	when read_status1 => priority_rotation <='0';
891	fifo_rd_en <= '0';
892	switch_port_in_data <= (others =>'0');
893	switch_port_in_wr_en <= '0';
894	dma_rd_request <= '1';
895	dma_wr_request <= '0';
896	Ram_rd<='0';
897	Ram_wr<='0';
898	Ram_data_out<=(others=>'0');
899	AppInitReq<='0';
900	Result <=(others=>'0');
901	Ready<='0';
902	when read_status2 => priority_rotation <='0';
903	fifo_rd_en <= '0';
904	switch_port_in_data <= (others =>'0');
905	switch_port_in_wr_en <= '0';
906	dma_rd_request <= '1';
907	dma_wr_request <= '0';
908	Ram_rd<='1';
909	Ram_wr<='0';
910	Ram_data_out<=(others=>'0');
911	AppInitReq<='0';
912	status_reg:=Ram_data_in;
913	Result <=(others=>'0');
914	Ready<='0';
915	when fetch_packet_type => priority_rotation <='0';
916	fifo_rd_en <= rd_ok;
917	switch_port_in_data <= (others =>'0');
918	AppInitReq<='0';
919	switch_port_in_wr_en <= '0';
920	Ram_rd<='0';
921	Ram_wr<='0';
922	dma_rd_request <= '0';
923	dma_wr_request <= '0';
924	Ram_data_out<=(others=>'0');
925	Result <=(others=>'0');
926	Ready<='0';
927
928	when decode_packet_type => priority_rotation <='0';
929	fifo_rd_en <= rd_ok;
930	switch_port_in_data <= (others =>'0');
931	switch_port_in_wr_en <= '0';
932	AppInitReq<='0';
933	Ram_rd<='0';
934	Ram_wr<='0';
935	dma_rd_request <= '0';
936	dma_wr_request <= '0';
937	Ram_data_out<=(others=>'0');
938	Result <=(others=>'0');
939	Ready<='0';
940	when fetch_addresses => priority_rotation <='0';
941	fifo_rd_en <= rd_ok;
942	switch_port_in_data <= (others =>'0');
943	switch_port_in_wr_en <= '0';
944	AppInitReq<='0';
945	Ram_rd<='0';
946	Ram_wr<='0';
947	dma_rd_request <= '0';
948	dma_wr_request <= '0';
949	Ram_data_out<=(others=>'0');
950	Result <=(others=>'0');
951	Ready<='0';
952	when decode_packet_type2 =>priority_rotation <='0';
953	fifo_rd_en <= '0';
954	switch_port_in_data <= data_to_send;
955	switch_port_in_wr_en <= '0';
956	AppInitReq<='0';
957	Ram_rd<='0';
958	Ram_wr<='0';
959	dma_rd_request <= '0';
960	dma_wr_request <= '0';
961	Ram_data_out<=(others=>'0');
962	Result <=(others=>'0');
963	Ready<='0'; -- fin du module
964
965	when ex1_barrier1 => priority_rotation <='0';
966	fifo_rd_en <= '0';
967	switch_port_in_data <= packet_type & pid_counter;
968	switch_port_in_wr_en <= not(switch_port_in_full);
969	AppInitReq<='0';
970	Ram_rd<='0';
971	Ram_wr<='0';
972	dma_rd_request <= '0';
973	dma_wr_request <= '0';
974	Ram_data_out<=(others=>'0');
975	Result <=(others=>'0');
976	Ready<='0'; -- fin du module
977
978	when ex1_barrier2 => priority_rotation <='0';
979	fifo_rd_en <= '0';
980	switch_port_in_data <= p_len;
981	switch_port_in_wr_en <= not(switch_port_in_full);
982	AppInitReq<='0';
983	Ram_rd<='0';
984	Ram_wr<='0';
985	dma_rd_request <= '0';
986	dma_wr_request <= '0';
987	Ram_data_out<=(others=>'0');
988	Result <=(others=>'0');
989	Ready<='0'; -- fin du module
990
991	when ex1_barrier3 => priority_rotation <='0';
992	fifo_rd_en <= '0';
993	switch_port_in_data <= "0000" & pid;
994	switch_port_in_wr_en <= not(switch_port_in_full);
995	AppInitReq<='0';
996	Ram_rd<='0';
997	Ram_wr<='0';
998	dma_rd_request <= '0';
999	dma_wr_request <= '0';
1000	Ram_data_out<=(others=>'0');
1001	Result <=(others=>'0');
1002	Ready<='0'; -- fin du module
1003
1004	when ex1_barrier4 => priority_rotation <='0';
1005	fifo_rd_en <= '0';
1006	switch_port_in_data <= "0000" & pid;
1007	switch_port_in_wr_en <= '0';
1008	AppInitReq<='0';
1009	dma_rd_request <= '0';
1010	Ram_rd<='0';
1011	Ram_wr<='0';
1012	dma_wr_request <= '0';
1013	Ram_data_out<=(others=>'0');
1014	Result <=(others=>'0');
1015	Ready<='0'; -- fin du module
1016
1017	when ex1_get1 => priority_rotation <='0';
1018	fifo_rd_en <= '0';
1019	switch_port_in_data <= data_to_send;
1020	switch_port_in_wr_en <= Wr_ok;
1021	AppInitReq<='0';
1022	Ram_rd<='0';
1023	Ram_wr<='0';
1024	dma_rd_request <= '0';
1025	dma_wr_request <= '0';
1026	Ram_data_out<=(others=>'0');
1027	Result <=(others=>'0');
1028	Ready<='0'; -- fin du module
1029	when ex1_get2 => priority_rotation <='0';
1030	fifo_rd_en <= '0';
1031	switch_port_in_data <= data_to_send;
1032	switch_port_in_wr_en <='0';
1033	AppInitReq<='0';
1034	Ram_rd<='0';
1035	Ram_wr<='0';
1036	dma_rd_request <= '0';
1037	dma_wr_request <= dma_Wr;
1038	Ram_rd<='0';
1039	Ram_wr<='0';
1040	Ram_data_out<=(others=>'0');
1041	Result <=(others=>'0');
1042	Ready<='0'; -- fin du module
1043
1044	when ex1_get3 => priority_rotation <='0';
1045	fifo_rd_en <= '0';
1046	switch_port_in_data <= (others=>'0');---???
1047	switch_port_in_wr_en <= '0';
1048	AppInitReq<='0';
1049	dma_rd_request <= '0';
1050	dma_wr_request <= '1';
1051	Ram_rd<='0';
1052	Ram_wr<=wr_ok;
1053	Ram_data_out<=data_to_send; -- le résultat de l'exécution
1054	Ready<='0'; -- fin du module
1055	Result <=(2=>'1',others=>'0');--Get completed
1056	when ex1_get4 => priority_rotation <='0';
1057	fifo_rd_en <= '0';
1058	switch_port_in_data <= ram_Data_in;
1059	switch_port_in_wr_en <= '0';
1060	AppInitReq<='0';
1061	dma_rd_request <= dma_rd;
1062	dma_wr_request <= dma_wr;
1063	Ram_rd<=rd_ok;
1064	Ram_wr<=wr_ok;
1065	Ram_data_out<=data_to_send; --"00000001";
1066	Result <=(2=>'1',others=>'0'); --get completed
1067	Ready<='0'; -- fin du module
1068	when ex1_put1 => priority_rotation <='0';
1069	fifo_rd_en <= '0';
1070	switch_port_in_data <= data_to_send;
1071	switch_port_in_wr_en <= '0';
1072	AppInitReq<='0';
1073	dma_rd_request <= '1';
1074	dma_wr_request <= '0';
1075	Ram_rd<='0';
1076	Ram_wr<='0';
1077	Ram_data_out<=(others=>'0');
1078	Result <=(others=>'0');
1079	Ready<='0'; -- fin du module
1080
1081	when ex1_put2 => priority_rotation <='0';
1082	fifo_rd_en <= '0';
1083	switch_port_in_data <= data_to_send;
1084	switch_port_in_wr_en <= wr_ok;
1085	AppInitReq<='0';
1086	Ram_rd<='1';
1087	Ram_wr<='0';
1088	dma_rd_request <= '1';
1089	dma_wr_request <= '0';
1090	Ram_data_out<=(others=>'0');
1091	Result <=(others=>'0');
1092	Ready<='0'; -- fin du module
1093
1094	when ex1_put3 => priority_rotation <='0';
1095	fifo_rd_en <= '0';
1096	switch_port_in_data <= ram_data_in;
1097	switch_port_in_wr_en <= wr_ok;
1098	AppInitReq<='0';
1099	dma_rd_request <= '1';
1100	dma_wr_request <= '0';
1101	Ram_rd<='1';
1102	Ram_wr<='0';
1103	Ram_data_out<=(others=>'0');
1104	Result <=(others=>'0');
1105	Ready<='0'; -- fin du module
1106
1107	when ex1_put4 => priority_rotation <='0';
1108	fifo_rd_en <= '0';
1109	switch_port_in_data <= ram_data_in;---???
1110	switch_port_in_wr_en <= '0';
1111	AppInitReq<='0';
1112	dma_rd_request <= rd_ok;
1113	dma_wr_request <= wr_ok;
1114	Ram_rd<=rd_ok;
1115	Ram_wr<=wr_ok;
1116	Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution
1117	--result(1)<='1';
1118	Result <=(1=>'1',others=>'0');--put completed
1119	Ready<='0'; -- fin du module
1120	when ex1_put5 => priority_rotation <='0';
1121	fifo_rd_en <= '0';
1122	switch_port_in_data <= ram_Data_in;
1123	switch_port_in_wr_en <= '0';
1124	AppInitReq<='0';
1125	dma_rd_request <= dma_rd;
1126	dma_wr_request <= dma_wr;
1127	Ram_rd<=rd_ok;
1128	Ram_wr<=wr_ok;
1129	Ram_data_out<=data_to_send; --"00000001";
1130	Result <=(1=>'1',others=>'0'); --put completed
1131	Ready<='0'; -- fin du module
1132	when ex1_init1 => priority_rotation <='0';
1133	if fifo_empty='0' then
1134	fifo_rd_en <= rd_ok;
1135	else
1136	fifo_rd_en<='0';
1137	end if;
1138	switch_port_in_data <= data_to_send;
1139	switch_port_in_wr_en <= wr_ok;
1140	dma_rd_request <= '0';
1141	dma_wr_request <= '0';
1142	Ram_rd<='0';
1143	Ram_wr<='0';
1144	Ram_data_out<=(others=>'0');
1145	AppInitReq<='1';
1146	Result <=(others=>'0');
1147	when ex1_init_run => priority_rotation <='0';
1148
1149	fifo_rd_en <= fifo_rd;
1150
1151	switch_port_in_data <= noc_fifo_in;
1152	switch_port_in_wr_en <= fifo_wr;
1153	dma_rd_request <= '0';
1154	dma_wr_request <= '0';
1155	Ram_rd<='0';
1156	Ram_wr<='0';
1157	Ram_data_out<=(others=>'0');
1158	AppInitReq<='1';
1159	Result <=(others=>'0');
1160
1161
1162	when ex1_init2=> priority_rotation <='0';
1163	fifo_rd_en <= '0';
1164	switch_port_in_data <= noc_fifo_in;
1165	switch_port_in_wr_en <= push;
1166	AppInitReq<='1';
1167	dma_rd_request <= '0';
1168	dma_wr_request <= '1';
1169	Ram_rd<='0';
1170	Ram_wr<=wr_ok;
1171	Ram_data_out<="00010000"; -- le résultat de l'exécution
1172	-- dans le registre status
1173	Result <=(others=>'0');--
1174	when ex1_init3=> priority_rotation <='0';
1175	fifo_rd_en <= '0';
1176	switch_port_in_data <= ram_Data_in;
1177	switch_port_in_wr_en <= '0';
1178	AppInitReq<='0';
1179	dma_rd_request <= '0';
1180	dma_wr_request <= '1';
1181	Ram_rd<='0';
1182	Ram_wr<='1';
1183	Ram_data_out<="00010000";
1184	Ready<='0'; -- fin du module
1185	Result<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit
1186
1187	when ex1_spawn => priority_rotation <='0';
1188	fifo_rd_en <= rd_ok;
1189	switch_port_in_data <= Data_to_send;
1190	switch_port_in_wr_en <= wr_ok;
1191	AppInitReq<='0';
1192	dma_rd_request <= '0';
1193	dma_wr_request <= '0';
1194	Ram_rd<='0';
1195	Ram_wr<='0';
1196	Ram_data_out<=(others=>'0');
1197	Result <=(others=>'0');
1198	when ex1_send_ack\|ex1_Wsync => priority_rotation <='0';
1199	fifo_rd_en <= rd_ok;
1200	switch_port_in_data <= Data_to_send;
1201	switch_port_in_wr_en <= wr_ok;
1202	AppInitReq<='0';
1203	dma_rd_request <= '0';
1204	dma_wr_request <= '0';
1205	Ram_rd<='0';
1206	Ram_wr<='0';
1207	Ram_data_out<=(others=>'0');
1208	Result <=(others=>'0');
1209	when ex1_ready =>
1210	Ready<='1'; -- fin du module
1211	priority_rotation <='0';
1212	fifo_rd_en <= '0';
1213	switch_port_in_data <= (others =>'0');
1214	switch_port_in_wr_en <= '0';
1215	dma_rd_request <= '0';
1216	dma_wr_request <= '0';
1217	Ram_rd<='0';
1218	Ram_wr<='0';
1219	Ram_data_out<=(others=>'0');
1220	AppInitReq<='0';
1221	--Result <=Result;
1222
1223	when others => priority_rotation <='0';
1224	fifo_rd_en <= '0';
1225	switch_port_in_data <= (others =>'0');
1226	switch_port_in_wr_en <= '0';
1227	dma_rd_request <= '0';
1228	dma_wr_request <= '0';
1229	Ram_rd<='0';
1230	Ram_wr<='0';
1231	Ram_data_out<=(others=>'0');
1232	AppInitReq<='0';
1233	Result <=(others=>'0');
1234	end case;
1235
1236	end process;
1237
1238	end Behavioral;
1239

Note: See TracBrowser for help on using the repository browser.

Download in other formats: