source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/FIFO_64_FWFT.vhi @ 72

-- VHDL Instantiation Created from source file FIFO_64_FWFT.vhd -- 05:59:41 06/21/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

        COMPONENT FIFO_64_FWFT
        PORT(
                clk : IN std_logic;
                din : IN std_logic_vector(7 downto 0);
                rd_en : IN std_logic;
                srst : IN std_logic;
                wr_en : IN std_logic;          
                dout : OUT std_logic_vector(7 downto 0);
                empty : OUT std_logic;
                full : OUT std_logic
                );
        END COMPONENT;

        Inst_FIFO_64_FWFT: FIFO_64_FWFT PORT MAP(
                clk => ,
                din => ,
                rd_en => ,
                srst => ,
                wr_en => ,
                dout => ,
                empty => ,
                full => 
        );