source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/Hold_FSM.vhd

Last change on this file was 74, checked in by rolagamo, 11 years ago
File size: 2.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer: GAMOM Roland Christian
4--
5-- Create Date:    17:38:35 04/20/2013
6-- Design Name:
7-- Module Name:    Hold_FSM - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22
23-- Uncomment the following library declaration if using
24-- arithmetic functions with Signed or Unsigned values
25--use IEEE.NUMERIC_STD.ALL;
26
27-- Uncomment the following library declaration if instantiating
28-- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32entity Hold_FSM is
33    Port ( Hold_Req : in  STD_LOGIC;
34           ram_busy : in  STD_LOGIC;
35           Clk : in  STD_LOGIC;
36           Reset : in  STD_LOGIC;
37           Ramsel : out  STD_LOGIC;
38           Hold_Ack : out  STD_LOGIC);
39end Hold_FSM;
40
41architecture Behavioral of Hold_FSM is
42type typ_Hld is (Ht_Lock,Core_Lock,Ht_free);
43signal Holdstate,Hold_st :typ_hld;
44                signal Ram_sel :std_logic:='0';
45                signal front_Rbusy,front_hReq:std_logic:='0';
46begin
47
48hold_sync:process (clk,reset)
49 begin
50 if rising_edge(clk) then
51       
52               
53 end if;
54 end process hold_sync;
55 Ramsel_state:process(clk)--,HoldState,Hold_Req,ram_Busy,Front_HReq,Front_RBusy)
56 
57 begin
58 
59 if rising_edge(clk) then
60 if reset='1' then
61                HolDState<=Ht_free;
62        else
63--              HolDState<=Hold_St;
64--       Hold_St<=HoldState;
65 case HoldState is
66 when Ht_free =>
67        if Hold_Req='1' and ram_busy='0'   then
68                HolDState <=Core_lock;
69        elsif Hold_Req='0' and ram_busy='1' then
70                HoldState <=HT_lock;
71        elsif Hold_Req='1' and ram_busy='1' then
72                HoldState <=HT_lock;
73        else
74                HoldState <=HT_free;
75        end if;
76 when Ht_lock =>
77        if Hold_Req='0' and ram_busy='0'  then
78                HoldState <=HT_free;
79        elsif Hold_Req='1' and Ram_busy='0' then
80                HoldState <=Core_lock;
81        else
82                HoldState <=HT_lock;
83        end if;
84 
85 When Core_lock =>
86        If Hold_Req='0' and Ram_busy='0' then
87                HoldState <=HT_free;
88        elsif Hold_Req='0' and Ram_busy='1' then
89                HoldState <=HT_lock;
90        else
91                HoldState <=Core_lock;
92        end if;
93 end case ;
94 end if;
95 end if;
96
97 end process;
98 
99  Ramsel_val:process(HoldState,Hold_Req,Ram_Busy)
100 
101 begin
102 case HoldState is
103 when Ht_free =>
104 ram_sel<='0';
105 Hold_Ack<='0';
106 when Ht_Lock =>
107 ram_sel<='0';
108 Hold_Ack<='0';
109 when Core_lock =>
110 Ram_sel <='1';
111 Hold_Ack<='1';
112 end case;
113 if Hold_Req= not(front_HReq) then
114        front_HReq<= not front_HReq;
115end if;
116
117if Ram_busy= not (front_RBusy) then
118        front_RBusy<= not front_RBusy;
119end if;
120 end process ramsel_val;
121 Ramsel<=Ram_sel;
122--=======================================================================
123end Behavioral;
124
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