source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise @ 78

Last change on this file since 78 was 78, checked in by rolagamo, 10 years ago
File size: 42.3 KB
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181    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="MultiMPITest_map.ngm" xil_pn:subbranch="Map"/>
182    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_map.xrpt"/>
183    <file xil_pn:fileType="FILE_LOG" xil_pn:name="MultiMPITest_map_fpga_editor.log"/>
184    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_ngdbuild.xrpt"/>
185    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="MultiMPITest_pad.csv" xil_pn:subbranch="Par"/>
186    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="MultiMPITest_pad.txt" xil_pn:subbranch="Par"/>
187    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_par.xrpt"/>
188    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MultiMPITest_preroute.twr" xil_pn:subbranch="Map"/>
189    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MultiMPITest_preroute.twx" xil_pn:subbranch="Map"/>
190    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest_stx_beh.prj"/>
191    <file xil_pn:fileType="FILE_HTML" xil_pn:name="MultiMPITest_summary.html"/>
192    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest_vhdl.prj"/>
193    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_xst.xrpt"/>
194    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="PE.bld"/>
195    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="PE.cmd_log"/>
196    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="PE.fdo"/>
197    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="PE.lso"/>
198    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="PE.ncd" xil_pn:subbranch="Par"/>
199    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="PE.ngc"/>
200    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="PE.ngd"/>
201    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="PE.ngr"/>
202    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="PE.par" xil_pn:subbranch="Par"/>
203    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="PE.pcf" xil_pn:subbranch="Map"/>
204    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="PE.prj"/>
205    <file xil_pn:fileType="FILE_SPL" xil_pn:name="PE.spl"/>
206    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="PE.stx"/>
207    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="PE.sym" xil_pn:origination="imported"/>
208    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="PE.syr"/>
209    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="PE.twr" xil_pn:subbranch="Par"/>
210    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="PE.twx" xil_pn:subbranch="Par"/>
211    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="PE.unroutes" xil_pn:subbranch="Par"/>
212    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="PE.xst"/>
213    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="PE_beh.prj"/>
214    <file xil_pn:fileType="FILE_HTML" xil_pn:name="PE_envsettings.html"/>
215    <file xil_pn:fileType="FILE_NCD" xil_pn:name="PE_guide.ncd" xil_pn:origination="imported"/>
216    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="PE_isim_beh.exe"/>
217    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="PE_map.map" xil_pn:subbranch="Map"/>
218    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="PE_map.mrp" xil_pn:subbranch="Map"/>
219    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="PE_map.ncd" xil_pn:subbranch="Map"/>
220    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="PE_map.ngm" xil_pn:subbranch="Map"/>
221    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="PE_pad.csv" xil_pn:subbranch="Par"/>
222    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="PE_pad.txt" xil_pn:subbranch="Par"/>
223    <file xil_pn:fileType="FILE_HTML" xil_pn:name="PE_summary.html"/>
224    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="PE_xst.xrpt"/>
225    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="SWITCH_GEN.bld"/>
226    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SWITCH_GEN.cmd_log"/>
227    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SWITCH_GEN.lso"/>
228    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN.ncd" xil_pn:subbranch="Par"/>
229    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SWITCH_GEN.ngc"/>
230    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="SWITCH_GEN.ngd"/>
231    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SWITCH_GEN.ngr"/>
232    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="SWITCH_GEN.pad"/>
233    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="SWITCH_GEN.par" xil_pn:subbranch="Par"/>
234    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="SWITCH_GEN.pcf" xil_pn:subbranch="Map"/>
235    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SWITCH_GEN.prj"/>
236    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="SWITCH_GEN.ptwx"/>
237    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SWITCH_GEN.stx"/>
238    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SWITCH_GEN.syr"/>
239    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="SWITCH_GEN.twr" xil_pn:subbranch="Par"/>
240    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="SWITCH_GEN.twx" xil_pn:subbranch="Par"/>
241    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="SWITCH_GEN.unroutes" xil_pn:subbranch="Par"/>
242    <file xil_pn:fileType="FILE_XPI" xil_pn:name="SWITCH_GEN.xpi"/>
243    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SWITCH_GEN.xst"/>
244    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SWITCH_GENERIQUE.cmd_log"/>
245    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SWITCH_GENERIQUE.lso"/>
246    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SWITCH_GENERIQUE.prj"/>
247    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SWITCH_GENERIQUE.syr"/>
248    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SWITCH_GENERIQUE.xst"/>
249    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GENERIQUE_envsettings.html"/>
250    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GENERIQUE_summary.html"/>
251    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GENERIQUE_xst.xrpt"/>
252    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GEN_envsettings.html"/>
253    <file xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_guide.ncd" xil_pn:origination="imported"/>
254    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SWITCH_GEN_map.map" xil_pn:subbranch="Map"/>
255    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SWITCH_GEN_map.mrp" xil_pn:subbranch="Map"/>
256    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_map.ncd" xil_pn:subbranch="Map"/>
257    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="SWITCH_GEN_map.ngm" xil_pn:subbranch="Map"/>
258    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="SWITCH_GEN_pad.csv" xil_pn:subbranch="Par"/>
259    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="SWITCH_GEN_pad.txt" xil_pn:subbranch="Par"/>
260    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_par.xrpt"/>
261    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GEN_summary.html"/>
262    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_xst.xrpt"/>
263    <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="SetBit.vhi"/>
264    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
265    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
266    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
267    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
268    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
269    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
270    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
271    <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
272    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
273    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
274    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
275    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="load_instr.bld"/>
276    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="load_instr.cmd_log"/>
277    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="load_instr.lso"/>
278    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="load_instr.ncd" xil_pn:subbranch="Par"/>
279    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="load_instr.ngc"/>
280    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="load_instr.ngd"/>
281    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="load_instr.ngr"/>
282    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="load_instr.par" xil_pn:subbranch="Par"/>
283    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="load_instr.pcf" xil_pn:subbranch="Map"/>
284    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="load_instr.prj"/>
285    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="load_instr.stx"/>
286    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="load_instr.syr"/>
287    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="load_instr.twr" xil_pn:subbranch="Par"/>
288    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="load_instr.twx" xil_pn:subbranch="Par"/>
289    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="load_instr.unroutes" xil_pn:subbranch="Par"/>
290    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="load_instr.xst"/>
291    <file xil_pn:fileType="FILE_HTML" xil_pn:name="load_instr_envsettings.html"/>
292    <file xil_pn:fileType="FILE_NCD" xil_pn:name="load_instr_guide.ncd" xil_pn:origination="imported"/>
293    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="load_instr_map.map" xil_pn:subbranch="Map"/>
294    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="load_instr_map.mrp" xil_pn:subbranch="Map"/>
295    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="load_instr_map.ncd" xil_pn:subbranch="Map"/>
296    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="load_instr_map.ngm" xil_pn:subbranch="Map"/>
297    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="load_instr_pad.csv" xil_pn:subbranch="Par"/>
298    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="load_instr_pad.txt" xil_pn:subbranch="Par"/>
299    <file xil_pn:fileType="FILE_HTML" xil_pn:name="load_instr_summary.html"/>
300    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="load_instr_xst.xrpt"/>
301    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="mpi_test.fdo"/>
302    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mpi_test_beh.prj"/>
303    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="mpi_test_isim_beh.exe"/>
304    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="mpi_test_isim_beh.wdb"/>
305    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mpi_test_stx_beh.prj"/>
306    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="multimpitest.bgn" xil_pn:subbranch="FPGAConfiguration"/>
307    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="multimpitest.bit" xil_pn:subbranch="FPGAConfiguration"/>
308    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="multimpitest.drc" xil_pn:subbranch="FPGAConfiguration"/>
309    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="pepExtractor.prj"/>
310    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
311    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_DMA_isim_beh.exe"/>
312    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="test_xbar_8x8.fdo"/>
313    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_xbar_8x8_isim_beh.exe"/>
314    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/>
315    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
316    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
317    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
318    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
319    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
320    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
321    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
322    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
323  </files>
324
325  <transforms xmlns="http://www.xilinx.com/XMLSchema">
326    <transform xil_pn:end_ts="1389780673" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1389780673">
327      <status xil_pn:value="SuccessfullyRun"/>
328      <status xil_pn:value="ReadyToRun"/>
329    </transform>
330    <transform xil_pn:end_ts="1389973516" xil_pn:in_ck="-5178871848763058326" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1389973515">
331      <status xil_pn:value="SuccessfullyRun"/>
332      <status xil_pn:value="ReadyToRun"/>
333      <status xil_pn:value="OutOfDateForInputs"/>
334      <status xil_pn:value="OutOfDateForOutputs"/>
335      <status xil_pn:value="InputChanged"/>
336      <status xil_pn:value="OutputChanged"/>
337      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
338      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
339      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/>
340      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/>
341      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/>
342      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/>
343      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/>
344      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/>
345      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/>
346      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD"/>
347      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD"/>
348      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/>
349      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/>
350      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/>
351      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/>
352      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/>
353      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/>
354      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/>
355      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/>
356      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/>
357      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/>
358      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/>
359      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/>
360      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD"/>
361      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/>
362      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/>
363      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/conv.vhd"/>
364      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/>
365      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/>
366      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/>
367      <outfile xil_pn:name="CORE_MPI.vhd"/>
368      <outfile xil_pn:name="DEMUX1.vhd"/>
369      <outfile xil_pn:name="DMA_ARBITER.vhd"/>
370      <outfile xil_pn:name="EX1_FSM.vhd"/>
371      <outfile xil_pn:name="EX2_FSM.vhd"/>
372      <outfile xil_pn:name="EX3_FSM.vhd"/>
373      <outfile xil_pn:name="EX4_FSM.vhd"/>
374      <outfile xil_pn:name="Ex0_Fsm.vhd"/>
375      <outfile xil_pn:name="Ex5_FSM.vhd"/>
376      <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
377      <outfile xil_pn:name="FIfo_mem.vhd"/>
378      <outfile xil_pn:name="FIfo_proc.vhd"/>
379      <outfile xil_pn:name="HCL_Arch_conf.vhd"/>
380      <outfile xil_pn:name="HT_4.vhd"/>
381      <outfile xil_pn:name="HT_process.vhd"/>
382      <outfile xil_pn:name="Hold_FSM.vhd"/>
383      <outfile xil_pn:name="IP_Timer.vhd"/>
384      <outfile xil_pn:name="MPICORETEST.vhd"/>
385      <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
386      <outfile xil_pn:name="MPI_NOC.vhd"/>
387      <outfile xil_pn:name="MPI_RMA.vhd"/>
388      <outfile xil_pn:name="MUX1.vhd"/>
389      <outfile xil_pn:name="MUX8.vhd"/>
390      <outfile xil_pn:name="MultiMPITest.vhd"/>
391      <outfile xil_pn:name="PE.vhd"/>
392      <outfile xil_pn:name="Packet_type.vhd"/>
393      <outfile xil_pn:name="RAM_32_32.vhd"/>
394      <outfile xil_pn:name="RAM_64.vhd"/>
395      <outfile xil_pn:name="SetBit.vhd"/>
396      <outfile xil_pn:name="image_pkg.vhd"/>
397      <outfile xil_pn:name="load_instr.vhd"/>
398      <outfile xil_pn:name="mpi_test.vhd"/>
399      <outfile xil_pn:name="round_robbin_machine.vhd"/>
400      <outfile xil_pn:name="sim_fifo.vhd"/>
401      <outfile xil_pn:name="test_DMA.vhd"/>
402    </transform>
403    <transform xil_pn:end_ts="1389973586" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1389973586">
404      <status xil_pn:value="SuccessfullyRun"/>
405      <status xil_pn:value="ReadyToRun"/>
406    </transform>
407    <transform xil_pn:end_ts="1389973589" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1389973586">
408      <status xil_pn:value="SuccessfullyRun"/>
409      <status xil_pn:value="ReadyToRun"/>
410    </transform>
411    <transform xil_pn:end_ts="1389797219" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1389797219">
412      <status xil_pn:value="SuccessfullyRun"/>
413      <status xil_pn:value="ReadyToRun"/>
414    </transform>
415    <transform xil_pn:end_ts="1389973521" xil_pn:in_ck="-5178871848763058326" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1389973521">
416      <status xil_pn:value="SuccessfullyRun"/>
417      <status xil_pn:value="ReadyToRun"/>
418      <status xil_pn:value="OutOfDateForInputs"/>
419      <status xil_pn:value="OutOfDateForPredecessor"/>
420      <status xil_pn:value="OutOfDateForOutputs"/>
421      <status xil_pn:value="InputChanged"/>
422      <status xil_pn:value="OutputChanged"/>
423      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
424      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
425      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/>
426      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/>
427      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/>
428      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/>
429      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/>
430      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/>
431      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/>
432      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD"/>
433      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD"/>
434      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/>
435      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/>
436      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/>
437      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/>
438      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/>
439      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/>
440      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/>
441      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/>
442      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/>
443      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/>
444      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/>
445      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/>
446      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD"/>
447      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/>
448      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/>
449      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/conv.vhd"/>
450      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/>
451      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/>
452      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/>
453      <outfile xil_pn:name="CORE_MPI.vhd"/>
454      <outfile xil_pn:name="DEMUX1.vhd"/>
455      <outfile xil_pn:name="DMA_ARBITER.vhd"/>
456      <outfile xil_pn:name="EX1_FSM.vhd"/>
457      <outfile xil_pn:name="EX2_FSM.vhd"/>
458      <outfile xil_pn:name="EX3_FSM.vhd"/>
459      <outfile xil_pn:name="EX4_FSM.vhd"/>
460      <outfile xil_pn:name="Ex0_Fsm.vhd"/>
461      <outfile xil_pn:name="Ex5_FSM.vhd"/>
462      <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
463      <outfile xil_pn:name="FIfo_mem.vhd"/>
464      <outfile xil_pn:name="FIfo_proc.vhd"/>
465      <outfile xil_pn:name="HCL_Arch_conf.vhd"/>
466      <outfile xil_pn:name="HT_4.vhd"/>
467      <outfile xil_pn:name="HT_process.vhd"/>
468      <outfile xil_pn:name="Hold_FSM.vhd"/>
469      <outfile xil_pn:name="IP_Timer.vhd"/>
470      <outfile xil_pn:name="MPICORETEST.vhd"/>
471      <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
472      <outfile xil_pn:name="MPI_NOC.vhd"/>
473      <outfile xil_pn:name="MPI_RMA.vhd"/>
474      <outfile xil_pn:name="MUX1.vhd"/>
475      <outfile xil_pn:name="MUX8.vhd"/>
476      <outfile xil_pn:name="MultiMPITest.vhd"/>
477      <outfile xil_pn:name="PE.vhd"/>
478      <outfile xil_pn:name="Packet_type.vhd"/>
479      <outfile xil_pn:name="RAM_32_32.vhd"/>
480      <outfile xil_pn:name="RAM_64.vhd"/>
481      <outfile xil_pn:name="SetBit.vhd"/>
482      <outfile xil_pn:name="image_pkg.vhd"/>
483      <outfile xil_pn:name="load_instr.vhd"/>
484      <outfile xil_pn:name="mpi_test.vhd"/>
485      <outfile xil_pn:name="round_robbin_machine.vhd"/>
486      <outfile xil_pn:name="sim_fifo.vhd"/>
487      <outfile xil_pn:name="test_DMA.vhd"/>
488    </transform>
489    <transform xil_pn:end_ts="1389973619" xil_pn:in_ck="-5178871848763058326" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-6667380628693525942" xil_pn:start_ts="1389973589">
490      <status xil_pn:value="SuccessfullyRun"/>
491      <status xil_pn:value="ReadyToRun"/>
492      <status xil_pn:value="OutOfDateForInputs"/>
493      <status xil_pn:value="OutOfDateForPredecessor"/>
494      <status xil_pn:value="OutOfDateForOutputs"/>
495      <status xil_pn:value="InputChanged"/>
496      <status xil_pn:value="OutputChanged"/>
497      <outfile xil_pn:name="mpi_test.fdo"/>
498      <outfile xil_pn:name="vsim.wlf"/>
499      <outfile xil_pn:name="work"/>
500    </transform>
501    <transform xil_pn:end_ts="1389786150" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1389786150">
502      <status xil_pn:value="SuccessfullyRun"/>
503      <status xil_pn:value="ReadyToRun"/>
504    </transform>
505    <transform xil_pn:end_ts="1389882619" xil_pn:in_ck="6885079285025204965" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-2338681308976167439" xil_pn:start_ts="1389882619">
506      <status xil_pn:value="SuccessfullyRun"/>
507      <status xil_pn:value="ReadyToRun"/>
508      <status xil_pn:value="OutOfDateForProperties"/>
509    </transform>
510  </transforms>
511
512</generated_project>
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