| FIFO Project Status (01/16/2014 - 15:56:56) | |||
| Project File: | MPI_CORE_COMPONENTS.xise | Parser Errors: | No Errors |
| Module Name: | MultiMPITest | Implementation State: | Mapped |
| Target Device: | xc6slx45-3csg324 |
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| Product Version: | ISE 12.3 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary | [-] | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Wed 15. Jan 15:00:16 2014 | ||||
| Translation Report | Current | Wed 15. Jan 15:06:05 2014 | 0 | 36 Warnings (0 new) | 0 | |
| Map Report | Current | Wed 15. Jan 15:07:45 2014 | X 3 Errors (2 new) | 0 | 8 Infos (3 new) | |
| Place and Route Report | Out of Date | Mon 13. Jan 19:36:05 2014 | 0 | 1659 Warnings (0 new) | 0 | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Out of Date | Mon 13. Jan 19:37:30 2014 | 0 | 0 | 2 Infos (0 new) | |
| Bitgen Report | Out of Date | Tue 14. Jan 07:39:01 2014 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Thu 8. Aug 16:31:11 2013 | |
| Post-Map Static Timing Report | Out of Date | Wed 19. Dec 17:30:44 2012 | |
| Post-Place and Route Simulation Model Report | Out of Date | Tue 14. Jan 07:44:23 2014 | |
| WebTalk Report | Out of Date | Fri 7. Jun 23:56:05 2013 | |
| WebTalk Log File | Out of Date | Fri 7. Jun 23:56:14 2013 | |