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1	<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
2	<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3	<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
4	<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
5	<TD ALIGN=CENTER COLSPAN='4'><B>SWITCH_GEN Project Status (08/05/2013 - 19:22:45)</B></TD></TR>
6	<TR ALIGN=LEFT>
7	<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8	<TD>MPI_CORE_COMPONENTS.xise</TD>
9	<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
10	<TD> No Errors </TD>
11	</TR>
12	<TR ALIGN=LEFT>
13	<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
14	<TD>MultiMPITest</TD>
15	<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
16	<TD>Placed and Routed (Stopped)</TD>
17	</TR>
18	<TR ALIGN=LEFT>
19	<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
20	<TD>xc6slx75-3csg484</TD>
21	<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
22	<TD> </TD>
23	</TR>
24	<TR ALIGN=LEFT>
25	<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
26	<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
27	<TD> </TD>
28	</TR>
29	<TR ALIGN=LEFT>
30	<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
31	<TD>Balanced</TD>
32	<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
33	<TD>
34	</TD>
35	</TR>
36	<TR ALIGN=LEFT>
37	<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
38	<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
39	<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
40	<TD> </TD>
41	</TR>
42	<TR ALIGN=LEFT>
43	<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
44	<TD>
45	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_envsettings.html'>
46	System Settings</A>
47	</TD>
48	<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
49	<TD> </TD>
50	</TR>
51	</TABLE>
52
53
54
55	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
56	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
57	<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
58	<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
59	</TR>
60	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
61	<TD ALIGN=RIGHT>5,736</TD>
62	<TD ALIGN=RIGHT>93,296</TD>
63	<TD ALIGN=RIGHT>6%</TD>
64	<TD COLSPAN='2'> </TD>
65	</TR>
66	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Flip Flops</TD>
67	<TD ALIGN=RIGHT>4,343</TD>
68	<TD> </TD>
69	<TD> </TD>
70	<TD COLSPAN='2'> </TD>
71	</TR>
72	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latches</TD>
73	<TD ALIGN=RIGHT>1,393</TD>
74	<TD> </TD>
75	<TD> </TD>
76	<TD COLSPAN='2'> </TD>
77	</TR>
78	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latch-thrus</TD>
79	<TD ALIGN=RIGHT>0</TD>
80	<TD> </TD>
81	<TD> </TD>
82	<TD COLSPAN='2'> </TD>
83	</TR>
84	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as AND/OR logics</TD>
85	<TD ALIGN=RIGHT>0</TD>
86	<TD> </TD>
87	<TD> </TD>
88	<TD COLSPAN='2'> </TD>
89	</TR>
90	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
91	<TD ALIGN=RIGHT>24,021</TD>
92	<TD ALIGN=RIGHT>46,648</TD>
93	<TD ALIGN=RIGHT>51%</TD>
94	<TD COLSPAN='2'> </TD>
95	</TR>
96	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as logic</TD>
97	<TD ALIGN=RIGHT>13,765</TD>
98	<TD ALIGN=RIGHT>46,648</TD>
99	<TD ALIGN=RIGHT>29%</TD>
100	<TD COLSPAN='2'> </TD>
101	</TR>
102	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O6 output only</TD>
103	<TD ALIGN=RIGHT>10,469</TD>
104	<TD> </TD>
105	<TD> </TD>
106	<TD COLSPAN='2'> </TD>
107	</TR>
108	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 output only</TD>
109	<TD ALIGN=RIGHT>570</TD>
110	<TD> </TD>
111	<TD> </TD>
112	<TD COLSPAN='2'> </TD>
113	</TR>
114	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 and O6</TD>
115	<TD ALIGN=RIGHT>2,726</TD>
116	<TD> </TD>
117	<TD> </TD>
118	<TD COLSPAN='2'> </TD>
119	</TR>
120	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as ROM</TD>
121	<TD ALIGN=RIGHT>0</TD>
122	<TD> </TD>
123	<TD> </TD>
124	<TD COLSPAN='2'> </TD>
125	</TR>
126	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Memory</TD>
127	<TD ALIGN=RIGHT>10,176</TD>
128	<TD ALIGN=RIGHT>11,072</TD>
129	<TD ALIGN=RIGHT>91%</TD>
130	<TD COLSPAN='2'> </TD>
131	</TR>
132	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Dual Port RAM</TD>
133	<TD ALIGN=RIGHT>10,144</TD>
134	<TD> </TD>
135	<TD> </TD>
136	<TD COLSPAN='2'> </TD>
137	</TR>
138	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O6 output only</TD>
139	<TD ALIGN=RIGHT>10,144</TD>
140	<TD> </TD>
141	<TD> </TD>
142	<TD COLSPAN='2'> </TD>
143	</TR>
144	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 output only</TD>
145	<TD ALIGN=RIGHT>0</TD>
146	<TD> </TD>
147	<TD> </TD>
148	<TD COLSPAN='2'> </TD>
149	</TR>
150	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 and O6</TD>
151	<TD ALIGN=RIGHT>0</TD>
152	<TD> </TD>
153	<TD> </TD>
154	<TD COLSPAN='2'> </TD>
155	</TR>
156	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Single Port RAM</TD>
157	<TD ALIGN=RIGHT>32</TD>
158	<TD> </TD>
159	<TD> </TD>
160	<TD COLSPAN='2'> </TD>
161	</TR>
162	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O6 output only</TD>
163	<TD ALIGN=RIGHT>32</TD>
164	<TD> </TD>
165	<TD> </TD>
166	<TD COLSPAN='2'> </TD>
167	</TR>
168	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 output only</TD>
169	<TD ALIGN=RIGHT>0</TD>
170	<TD> </TD>
171	<TD> </TD>
172	<TD COLSPAN='2'> </TD>
173	</TR>
174	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 and O6</TD>
175	<TD ALIGN=RIGHT>0</TD>
176	<TD> </TD>
177	<TD> </TD>
178	<TD COLSPAN='2'> </TD>
179	</TR>
180	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Shift Register</TD>
181	<TD ALIGN=RIGHT>0</TD>
182	<TD> </TD>
183	<TD> </TD>
184	<TD COLSPAN='2'> </TD>
185	</TR>
186	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used exclusively as route-thrus</TD>
187	<TD ALIGN=RIGHT>80</TD>
188	<TD> </TD>
189	<TD> </TD>
190	<TD COLSPAN='2'> </TD>
191	</TR>
192	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice register load</TD>
193	<TD ALIGN=RIGHT>6</TD>
194	<TD> </TD>
195	<TD> </TD>
196	<TD COLSPAN='2'> </TD>
197	</TR>
198	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice carry load</TD>
199	<TD ALIGN=RIGHT>66</TD>
200	<TD> </TD>
201	<TD> </TD>
202	<TD COLSPAN='2'> </TD>
203	</TR>
204	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with other load</TD>
205	<TD ALIGN=RIGHT>8</TD>
206	<TD> </TD>
207	<TD> </TD>
208	<TD COLSPAN='2'> </TD>
209	</TR>
210	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
211	<TD ALIGN=RIGHT>7,515</TD>
212	<TD ALIGN=RIGHT>11,662</TD>
213	<TD ALIGN=RIGHT>64%</TD>
214	<TD COLSPAN='2'> </TD>
215	</TR>
216	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
217	<TD ALIGN=RIGHT>24,661</TD>
218	<TD> </TD>
219	<TD> </TD>
220	<TD COLSPAN='2'> </TD>
221	</TR>
222	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused Flip Flop</TD>
223	<TD ALIGN=RIGHT>19,198</TD>
224	<TD ALIGN=RIGHT>24,661</TD>
225	<TD ALIGN=RIGHT>77%</TD>
226	<TD COLSPAN='2'> </TD>
227	</TR>
228	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused LUT</TD>
229	<TD ALIGN=RIGHT>640</TD>
230	<TD ALIGN=RIGHT>24,661</TD>
231	<TD ALIGN=RIGHT>2%</TD>
232	<TD COLSPAN='2'> </TD>
233	</TR>
234	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of fully used LUT-FF pairs</TD>
235	<TD ALIGN=RIGHT>4,823</TD>
236	<TD ALIGN=RIGHT>24,661</TD>
237	<TD ALIGN=RIGHT>19%</TD>
238	<TD COLSPAN='2'> </TD>
239	</TR>
240	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of unique control sets</TD>
241	<TD ALIGN=RIGHT>1,854</TD>
242	<TD> </TD>
243	<TD> </TD>
244	<TD COLSPAN='2'> </TD>
245	</TR>
246	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of slice register sites lost<BR>        to control set restrictions</TD>
247	<TD ALIGN=RIGHT>7,688</TD>
248	<TD ALIGN=RIGHT>93,296</TD>
249	<TD ALIGN=RIGHT>8%</TD>
250	<TD COLSPAN='2'> </TD>
251	</TR>
252	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
253	<TD ALIGN=RIGHT>10</TD>
254	<TD ALIGN=RIGHT>328</TD>
255	<TD ALIGN=RIGHT>3%</TD>
256	<TD COLSPAN='2'> </TD>
257	</TR>
258	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
259	<TD ALIGN=RIGHT>0</TD>
260	<TD ALIGN=RIGHT>172</TD>
261	<TD ALIGN=RIGHT>0%</TD>
262	<TD COLSPAN='2'> </TD>
263	</TR>
264	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
265	<TD ALIGN=RIGHT>4</TD>
266	<TD ALIGN=RIGHT>344</TD>
267	<TD ALIGN=RIGHT>1%</TD>
268	<TD COLSPAN='2'> </TD>
269	</TR>
270	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
271	<TD ALIGN=RIGHT>0</TD>
272	<TD ALIGN=RIGHT>32</TD>
273	<TD ALIGN=RIGHT>0%</TD>
274	<TD COLSPAN='2'> </TD>
275	</TR>
276	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
277	<TD ALIGN=RIGHT>0</TD>
278	<TD ALIGN=RIGHT>32</TD>
279	<TD ALIGN=RIGHT>0%</TD>
280	<TD COLSPAN='2'> </TD>
281	</TR>
282	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
283	<TD ALIGN=RIGHT>1</TD>
284	<TD ALIGN=RIGHT>16</TD>
285	<TD ALIGN=RIGHT>6%</TD>
286	<TD COLSPAN='2'> </TD>
287	</TR>
288	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGs</TD>
289	<TD ALIGN=RIGHT>1</TD>
290	<TD> </TD>
291	<TD> </TD>
292	<TD COLSPAN='2'> </TD>
293	</TR>
294	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGMUX</TD>
295	<TD ALIGN=RIGHT>0</TD>
296	<TD> </TD>
297	<TD> </TD>
298	<TD COLSPAN='2'> </TD>
299	</TR>
300	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
301	<TD ALIGN=RIGHT>0</TD>
302	<TD ALIGN=RIGHT>12</TD>
303	<TD ALIGN=RIGHT>0%</TD>
304	<TD COLSPAN='2'> </TD>
305	</TR>
306	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
307	<TD ALIGN=RIGHT>0</TD>
308	<TD ALIGN=RIGHT>442</TD>
309	<TD ALIGN=RIGHT>0%</TD>
310	<TD COLSPAN='2'> </TD>
311	</TR>
312	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
313	<TD ALIGN=RIGHT>0</TD>
314	<TD ALIGN=RIGHT>442</TD>
315	<TD ALIGN=RIGHT>0%</TD>
316	<TD COLSPAN='2'> </TD>
317	</TR>
318	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
319	<TD ALIGN=RIGHT>0</TD>
320	<TD ALIGN=RIGHT>442</TD>
321	<TD ALIGN=RIGHT>0%</TD>
322	<TD COLSPAN='2'> </TD>
323	</TR>
324	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
325	<TD ALIGN=RIGHT>0</TD>
326	<TD ALIGN=RIGHT>4</TD>
327	<TD ALIGN=RIGHT>0%</TD>
328	<TD COLSPAN='2'> </TD>
329	</TR>
330	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
331	<TD ALIGN=RIGHT>0</TD>
332	<TD ALIGN=RIGHT>384</TD>
333	<TD ALIGN=RIGHT>0%</TD>
334	<TD COLSPAN='2'> </TD>
335	</TR>
336	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
337	<TD ALIGN=RIGHT>0</TD>
338	<TD ALIGN=RIGHT>8</TD>
339	<TD ALIGN=RIGHT>0%</TD>
340	<TD COLSPAN='2'> </TD>
341	</TR>
342	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
343	<TD ALIGN=RIGHT>0</TD>
344	<TD ALIGN=RIGHT>4</TD>
345	<TD ALIGN=RIGHT>0%</TD>
346	<TD COLSPAN='2'> </TD>
347	</TR>
348	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
349	<TD ALIGN=RIGHT>0</TD>
350	<TD ALIGN=RIGHT>132</TD>
351	<TD ALIGN=RIGHT>0%</TD>
352	<TD COLSPAN='2'> </TD>
353	</TR>
354	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
355	<TD ALIGN=RIGHT>0</TD>
356	<TD ALIGN=RIGHT>1</TD>
357	<TD ALIGN=RIGHT>0%</TD>
358	<TD COLSPAN='2'> </TD>
359	</TR>
360	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
361	<TD ALIGN=RIGHT>0</TD>
362	<TD ALIGN=RIGHT>4</TD>
363	<TD ALIGN=RIGHT>0%</TD>
364	<TD COLSPAN='2'> </TD>
365	</TR>
366	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
367	<TD ALIGN=RIGHT>0</TD>
368	<TD ALIGN=RIGHT>2</TD>
369	<TD ALIGN=RIGHT>0%</TD>
370	<TD COLSPAN='2'> </TD>
371	</TR>
372	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
373	<TD ALIGN=RIGHT>0</TD>
374	<TD ALIGN=RIGHT>6</TD>
375	<TD ALIGN=RIGHT>0%</TD>
376	<TD COLSPAN='2'> </TD>
377	</TR>
378	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
379	<TD ALIGN=RIGHT>0</TD>
380	<TD ALIGN=RIGHT>1</TD>
381	<TD ALIGN=RIGHT>0%</TD>
382	<TD COLSPAN='2'> </TD>
383	</TR>
384	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
385	<TD ALIGN=RIGHT>0</TD>
386	<TD ALIGN=RIGHT>1</TD>
387	<TD ALIGN=RIGHT>0%</TD>
388	<TD COLSPAN='2'> </TD>
389	</TR>
390	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
391	<TD ALIGN=RIGHT>0</TD>
392	<TD ALIGN=RIGHT>1</TD>
393	<TD ALIGN=RIGHT>0%</TD>
394	<TD COLSPAN='2'> </TD>
395	</TR>
396	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
397	<TD ALIGN=RIGHT>5.62</TD>
398	<TD> </TD>
399	<TD> </TD>
400	<TD COLSPAN='2'> </TD>
401	</TR>
402	</TABLE>
403
404
405
406	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
407	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
408	<TR ALIGN=LEFT>
409	<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
410	<TD> </TD>
411	<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
412	<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
413	</TR>
414	<TR ALIGN=LEFT>
415	<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
416	</TD>
417	<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
418	<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
419	</TR>
420	<TR ALIGN=LEFT>
421	<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
422	<TD> </TD>
423	<TD BGCOLOR='#FFFF99'><B> </B></TD>
424	<TD COLSPAN='2'> </TD>
425	</TABLE>
426
427
428
429	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
430	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
431	<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
432	<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
433	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon 5. Aug 19:05:19 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/xst.xmsgs?&DataKey=Warning'>3217 Warnings (3094 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/xst.xmsgs?&DataKey=Info'>383 Infos (383 new)</A></TD></TR>
434	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon 5. Aug 19:05:51 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>323 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
435	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon 5. Aug 19:21:47 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Warning'>2114 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR>
436	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon 5. Aug 19:22:37 2013</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
437	<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
438	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>Sat 3. Aug 11:21:28 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
439	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bgn'>Bitgen Report</A></TD><TD>Out of Date</TD><TD>Wed 19. Dec 13:42:44 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>1106 Warnings (565 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
440	</TABLE>
441	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
442	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
443	<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
444	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun 5. May 14:45:47 2013</TD></TR>
445	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 19. Dec 17:30:44 2012</TD></TR>
446	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 7. Jun 23:56:05 2013</TD></TR>
447	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 7. Jun 23:56:14 2013</TD></TR>
448	</TABLE>
449
450
451	<br><center><b>Date Generated:</b> 08/05/2013 - 19:22:46</center>
452	</BODY></HTML>

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