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PE_100.vhd

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 21:20:54 07/16/2012
6	-- Design Name:
7	-- Module Name: PE - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	library NocLib ;
23	--use IEEE.STD_LOGIC_ARITH.ALL;
24	--use IEEE.STD_LOGIC_UNSIGNED.ALL;
25	use NocLib.CoreTypes.all;
26	use work.Packet_type.all;
27	use work.MPI_RMA.all;
28	use IEEE.NUMERIC_STD.ALL;
29
30
31	entity PE is
32	Generic (DestId : natural );
33	Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0);
34	Instruction_en : out STD_LOGIC;
35	Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0);
36	clk : in STD_LOGIC;
37	reset : in STD_LOGIC;
38	Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0);
39	Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0);
40	Core_RAM_WE : in STD_LOGIC;
41	Core_RAM_EN : in STD_LOGIC;
42	--Core_RAM_ENB : in STD_LOGIC;
43	Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
44	Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
45	Core_Hold_req : in STD_LOGIC;
46	Core_Hold_Ack : out STD_LOGIC);
47	end PE;
48
49	architecture Behavioral of PE is
50	COMPONENT RAM_v
51	generic (width : positive;size :positive);
52	PORT(
53	clka : IN std_logic;
54	clkb : IN std_logic;
55	wea : IN std_logic;
56	ena : IN std_logic;
57	enb : IN std_logic;
58	addra : IN std_logic_vector;
59	addrb : IN std_logic_vector;
60	dia : IN std_logic_vector;
61	dob : OUT std_logic_vector
62	);
63	END COMPONENT;
64	--données du programme PE
65	--signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0');
66	signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0';
67	signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic;
68	signal pe_instr_en,pe_hold_ack: std_logic:='0';
69	signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
70	signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
71	signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
72	signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
73	signal sram : typ_dpram;
74
75	signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0);
76	signal dpid,dpid_i : natural range 0 to 15:=DestId;
77	signal MyRank :std_logic_vector(3 downto 0);
78	signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque
79	signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée
80	signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO
81	signal Lib_Init : std_logic; -- l'initialisation est terminée
82	--signaux pour la gestion de la MAE
83	type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,GetRank1,GetRank2,GetRank3,writeptr,InstrCopy,
84	putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout);
85	signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées
86	signal count,count_i : natural range 0 to 15:=0;
87
88
89	signal RunState : typ_mae;
90	signal Ram_busy :std_logic:='0';
91	begin
92	Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN)
93	PORT MAP(
94	clka =>clk,
95	clkb => clk,
96	wea => ram_we,
97	ena => ram_ena,
98	enb => ram_enb,
99	addra => ram_addra,
100	addrb =>ram_addrb,
101	dia => ram_din,
102	dob => ram_do
103	);
104	--================================================================
105	--MUX de la RAM
106
107	Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr,
108	Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do,
109	Pe_ram_din,Pe_ram_we )
110	begin
111	case ramsel is
112
113	when '1' =>
114	ram_addra <= Core_ram_address_wr ;
115	ram_addrb <= Core_ram_address_rd ;
116	ram_ena <= Core_ram_en;
117	ram_enb <= Core_ram_en;
118	ram_we<= Core_ram_we;
119	ram_din <= Core_ram_data_in;
120	pe_ram_do<=(others=>'Z');
121	Core_ram_data_out<=ram_do;
122
123	when others =>
124	ram_addra <= pe_ram_addra;
125	ram_addrb <= pe_ram_addrb;
126	ram_ena <= pe_ram_ena;
127	ram_enb <= pe_ram_enb;
128	ram_we<= pe_ram_we;
129	ram_din <=pe_ram_din;
130	Core_ram_data_out<=(others=>'Z');
131	pe_ram_do<=ram_do;
132	end case ;
133	end process ;
134
135
136
137	Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --******A changer ********
138	--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce
139	-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!!
140	instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8));
141
142	dpid<=dpid_i;
143
144	Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié
145	Lib_init<=Core_Pushout(4); -- Initialized
146	-- pe_hold_req<=Core_hold_req;
147	--Core_hold_ack<=pe_hold_ack;
148
149	hold:process (Core_Hold_Req,clk,reset)
150	begin
151	if rising_edge(clk) then
152	if reset='1' then
153	Core_Hold_Ack<='0';
154	else
155	if Core_Hold_Req='1' then
156
157	ramsel<=not(ram_busy);
158	Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération
159	Pe_hold_ack<=not(ram_busy);
160	else
161	Core_Hold_Ack<='0';
162	ramsel<='0';
163	Pe_hold_ack<='0';
164
165	end if;
166	end if;
167	end if;
168	end process hold;
169	--=======================================================================
170
171
172
173	--=======================================================================
174	--MAE du PE
175	--=======================================================================
176
177	pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do)
178
179	constant DATAPTR : natural :=256;
180	variable bfill,destrank,pid,mport : natural range 0 to 15;
181	variable fsrc,ret : natural range 0 to 15:=0;
182	variable timeout,ct,dlen : natural range 0 to 255;
183	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
184	variable iack : std_logic:='0';
185	variable adresse,adresse_rd :natural range 0 to 65536;
186	variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');
187	begin
188	--=== Partie combinatoire du process ===================================
189	Libr.Instr_ack<=Core_pushout(0);
190	Libr.InitOk<=Core_pushout(4);
191	Libr.Hold_Req<=Core_Hold_req;
192	Libr.Hold_Ack<=Pe_Hold_Ack;
193	Libr.RamSel<=RamSel;
194	sram.data_out<=PE_ram_do;
195	--=== Fin de la partie combinatoire du process ==========================
196	if (clk'event and clk='1') then
197	if reset='1' then
198	RunState<=start;
199
200	else
201
202	Libr.Instr_ack<=Core_pushout(0);
203	Libr.InitOk<=Core_pushout(4);
204	Libr.Hold_Req<=Core_Hold_req;
205	Libr.Hold_Ack<=Pe_Hold_Ack;
206	Libr.RamSel<=RamSel;
207	sram.data_out<=PE_ram_do;
208	case RunState is
209	when start =>
210	Dcount<=0;
211	if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
212	RunState<=Fillmem;
213	end if;
214	Ram_busy<='0';
215	PE_Instr_En<='0';
216	iack:='0';
217	adresse:=DATAPTR;
218
219	adresse_rd:=0;
220	timeout:=0;
221	dcount<=0;
222	when Fillmem =>
223	if Ramsel='0' then
224
225
226
227	PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
228	PE_Instr_En<='0';
229	dcount<=dcount+1;
230
231	if dcount=50 then
232	bfill:=bfill+1;
233
234	if bfill=4 then
235	RunState<=InitApp;
236	else
237	RunState<=nextfill;
238	end if;
239	else
240	adresse:=adresse+1;
241	RunState<=Fillmem;
242	end if;
243	else -- attente de la libéraion de la mémoire
244	timeout:=timeout+1;
245	if timeout=100 then
246	RunState<=st_timeout;
247	end if;
248
249	end if;
250	when nextfill => --prépare le prochain bloc mémoire qui sera rempli
251	adresse:=100*bfill;
252	dcount<=0;
253	ct:=0;
254	RunState<=Fillmem;
255	PE_Instr_En<='0';
256	when InitApp =>
257	--code pour Init
258
259	pMPI_Init(ct,Libr,Clk,SRam);
260	PE_Instr_EN<=Libr.instr_en;
261	adresse:=to_integer(unsigned(sram.addr_wr));
262	adresse_rd:=to_integer(unsigned(sram.addr_rd));
263	PE_ram_din<=sram.data_in;
264
265	--if Libr.InitOk='1' then
266	if ct=0 then
267	RunState<=GetRank1;
268	end if;
269
270
271	when writeptr =>
272	PE_Instr_En<='0';
273	if Ramsel= '0' then --s'assurer que le bus est disponible
274
275	if dcount=0 then
276	PE_RAM_Din<=AdrToSet(Word-1 downto 0);
277	dcount <=dcount+1;
278	--adresse:=adresse+1; --prépare la prochaine écriture
279	elsif dcount=1 then
280	dcount <=dcount+1;
281	adresse:=adresse+1; --prépare la prochaine écriture
282	PE_RAM_Din<=AdrToSet(15 downto 8);
283	elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
284	ret:=fsrc;
285	dcount<=0;
286	timeout:=0;
287
288	if fsrc=1 then
289	RunState <= InitApp;
290	elsif fsrc=2 then
291	RunState <= putdata;
292	elsif fsrc=3 then
293	RunState <= getdata;
294	else
295	RunState <= start;
296	end if;
297
298	end if;
299
300	end if;
301	When InstrCopy =>
302	if Lib_instr_ack='1' then
303	RunState<=Writeptr;
304	PE_instr_en<='0';
305	iack:='1';
306
307	else
308	PE_Instr_en<='1';
309	end if;
310
311	when InitCompleted =>
312	adresse:=CORE_BASE_ADR;
313
314	status_reg:=status_reg or x"10";
315	PE_Ram_din<=status_reg ;
316	if Lib_Init='1' then
317	RunState<=GetRank1;
318	PE_Instr_En<='0';
319	--instruction(5)<='1';
320	else
321	PE_Instr_En<='0';
322	end if;
323	when GetRank1 =>
324
325	pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
326	if ct=0 then
327	RunState<=PutData2;
328	end if;
329	adresse_rd:=to_integer(unsigned(sram.addr_rd));
330	-- adresse_rd:=CORE_INIT_ADR+1;
331	-- if ramsel='0' then
332	-- RunState<=getrank2;
333	-- end if;
334	when GetRank2 =>
335	adresse_rd:=CORE_INIT_ADR+1;
336	if ramsel='0' then
337	RunState<=Getrank3;
338	end if;
339	when GetRank3=>
340	adresse_rd:=CORE_INIT_ADR+1;
341	if ramsel='0' then
342	RunState<=putdata2;
343	end if;
344	when putdata => --construire le packet pour le Put
345	if unsigned(MyRank) = 0 then
346	Destrank:=1;
347	else
348	DestRank:=0;
349	end if;
350	adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank;
351
352	PE_Instr_En<='0';
353	timeout:=0;
354	dcount<=0;
355	fsrc:=2;
356	adrToSet:=std_logic_vector(to_unsigned(core_put_adr,16));
357	if ret/=fsrc then
358	adresse:=core_base_adr+2;
359	RunState<=writeptr;
360	ret:=0;
361	else
362	if Lib_instr_ack/='1' then
363	RunState<= putdata2;
364	end if;
365	end if;
366
367	when putdata2 =>
368
369	if unsigned(MyRank) = 0 then
370	Destrank:=1;
371	else
372	DestRank:=0;
373	end if;
374	dlen:=10; --- to_integer(unsigned(datalen));
375	SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
376	DestAdr:=X"2000";
377
378	pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win);
379	adresse:=to_integer(unsigned(sram.addr_wr));
380	adresse_rd:=to_integer(unsigned(sram.addr_rd));
381	PE_Instr_EN<=Libr.instr_en;
382	PE_ram_din<=sram.data_in;
383	dcount<=ct;
384
385	if ct=0 then
386	RunState<=GetData;
387	end if;
388
389	-- if dcount<=6 then
390	--
391	-- elsif dcount=7 then
392	--
393	-- PE_Instr_En<='1';
394	--
395	-- end if;
396
397	-- elsif PE_instr_En='0' then
398	-- timeout:=timeout+1;
399	-- if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire
400	-- ram_busy<='1';
401	-- timeout:=0;
402	-- PE_Instr_En<='0';
403	-- end if;
404	-- end if;
405	-- if dcount >=6 then
406	-- Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI
407	-- if Lib_instr_ack='1' then -- Instruction ack
408	-- PE_Instr_En<='0';
409	-- if Ramsel='0' then
410	-- adresse:=core_base_adr+1;
411	-- config_reg:=config_reg and x"f6";
412	-- PE_Ram_din<=config_reg ; --ramener le IPulse à 0;
413	-- Ram_busy<='0';
414	-- RunState<=putcompleted;
415	-- else
416	--
417	-- Ram_busy<='1'; --force la prise du bus
418	-- end if;
419	-- else
420	--
421	-- timeout:=timeout+1;
422	-- if timeout=150 then
423	-- RunState<=st_timeout;
424	-- end if;
425	-- end if;
426	-- end if;
427
428
429	when putcompleted =>
430	adresse_rd:=core_put_adr+6;
431	if PE_Ram_do(0)='1' then --Put completed
432	RunState<=GetData;
433	end if;
434	PE_Instr_En<='0';
435	when getdata => --positionnement du mot de longueur des données
436
437	--DestRank:=1;
438	timeout:=0;
439	dcount<=0;
440	fsrc:=3;
441	adrToSet:=std_logic_vector(to_unsigned(core_get_adr,16));
442	if ret/=fsrc then
443	adresse:=core_base_adr+2;
444	RunState<=writeptr;
445	ret:=0;
446	else
447	adresse:=core_get_adr;
448	RunState<= getdata2;
449	end if;
450	PE_Instr_En<='0';
451	when getdata2 =>
452
453	if ramsel='0' then
454	if dcount<=6 then
455
456	if dcount=0 then
457	adresse:=core_get_adr;
458	PE_Ram_din<=MPI_GET & std_logic_vector(to_unsigned(DestRank,4));
459	elsif dcount=1 then
460	adresse:=core_get_adr+dcount;
461	PE_Ram_din<=Datalen ;
462	elsif dcount=2 then
463	adresse:=core_get_adr+dcount;
464	PE_Ram_din<=SrcAdr1 ;
465	elsif dcount=3 then
466	adresse:=core_get_adr+dcount;
467	PE_Ram_din<=SrcAdr0 ;
468	elsif dcount=4 then
469	adresse:=core_get_adr+dcount;
470	PE_Ram_din<=DestAdr1 ;
471	elsif dcount=5 then
472	adresse:=core_get_adr+dcount;
473	PE_Ram_din<=DestAdr0 ;
474
475	elsif dcount=6 then
476	adresse:=core_base_adr+1;
477	adresse_rd:=core_base_adr;
478	PE_Instr_En<='1';
479	config_reg:=config_reg or x"01";
480	PE_Ram_din<=config_reg ; --instruction pulse enable;
481
482	timeout:=0;
483	end if;
484	dcount<=dcount+1;
485	end if;
486	elsif PE_Instr_En='0'then
487	timeout:=timeout+1;
488	if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire
489	ram_busy<='1';
490	timeout:=0;
491	PE_Instr_En<='0';
492	end if;
493	end if;
494
495	if dcount >=6 then
496	Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI
497	if Lib_instr_ack='1' then -- Instruction ack
498	PE_Instr_En<='0';
499	if Ramsel='0' then
500	adresse:=core_base_adr+1;
501	config_reg:=config_reg and x"f6";
502	PE_Ram_din<=config_reg ; --ramener le IPulse à 0;
503
504	Ram_busy<='0';
505	RunState<=getcompleted;
506	else
507
508	Ram_busy<='1'; --force la prise du bus
509	end if;
510	else
511
512	timeout:=timeout+1;
513	if timeout=150 then
514	RunState<=st_timeout;
515	end if;
516	end if;
517
518
519	end if;
520
521
522
523	when getcompleted =>
524	adresse_rd:=core_get_adr+6;
525	PE_Instr_En<='0';
526	if PE_Ram_do(0)='1' then --get completed
527	if Ramsel='0' then
528	adresse:=core_base_adr+1;
529	config_reg:=config_reg and x"f6";
530	PE_Ram_din<=config_reg ; --ramener le IPulse à 0;
531
532	RunState<=Terminate;
533	else
534	timeout:=timeout+1;
535	end if;
536	end if;
537
538
539	when terminate =>
540
541
542	RunState<=start;
543
544	when st_timeout =>
545
546	--if ram_busy='1' then
547	RunState<=start;
548	--end if
549
550	RunState<=start;
551	end case;
552	pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16));
553	pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16));
554	end if;
555	end if;
556
557	end process pPutGet;
558
559	majPutGet:process (RunState,pe_ram_do,sram,Lib_Init)
560
561	begin
562	case RunState is
563	when start =>
564
565	PE_Ram_we<='0';
566	PE_Ram_ena<='0';
567	PE_Ram_enb<='0';
568	--PE_Instr_En<='0';
569
570	when fillmem =>
571	PE_Ram_we<='1';
572	PE_Ram_ena<='1';
573
574	PE_Ram_enb<='0';
575	--PE_Instr_En<='0';
576	when nextfill =>
577	PE_Ram_we<='1';
578	PE_Ram_ena<='1';
579	PE_Ram_enb<='0';
580
581	when InitApp =>
582	-- PE_Ram_we<='1';
583	-- PE_Ram_ena<='1';
584	-- PE_Ram_enb<='0';
585	PE_Ram_we<=sram.we;
586	PE_Ram_ena<=sram.ena;
587	PE_Ram_enb<=sram.enb;
588
589	when Initcompleted =>
590
591	PE_Ram_ena<=Lib_Init;
592	PE_Ram_we<='1';
593	PE_Ram_enb<='1';
594
595	when GetRank1 =>
596	-- PE_Ram_ena<='0';
597	-- --lecture du rang positionnement de l'adresse
598	-- PE_Ram_enb<='1';
599	-- --MyRank<=PE_ram_do(3 downto 0);
600	PE_Ram_we<=sram.we;
601	PE_Ram_ena<=sram.ena;
602	PE_Ram_enb<=sram.enb;
603	when GetRank2 =>
604	PE_Ram_ena<='0';
605	--lecture effective du rang
606	PE_Ram_enb<='1';
607	--MyRank<=PE_ram_do(3 downto 0);
608	when GetRank3 =>
609	PE_Ram_ena<='0';
610	--lecture effective du rang
611	PE_Ram_enb<='1';
612	--MyRank<=PE_ram_do(3 downto 0);
613	when writeptr =>
614	PE_Ram_we <='1'; --écriture dans la RAM
615	PE_Ram_ena <='1';
616
617	PE_Ram_enb <='0';
618	-- dcount<=dcount+1;
619
620	--PE_Instr_En<='0';
621	when InstrCopy => --instruction copy
622	PE_Ram_we<='0';
623	PE_Ram_ena<='0';
624	PE_Ram_enb<='0';
625
626
627	when putdata => --positionnement du mot de longueur des données
628	--dcount<=0;
629	srcadr0<=X"00";
630	srcadr1<=X"01";
631	destadr0<=X"00";
632	destadr1<=X"02";
633	PE_Ram_we<='0';
634	PE_Ram_ena<='0';
635	--lecture du n° de port de destination
636	PE_Ram_enb<='1';
637	datalen<=std_logic_vector(to_unsigned(10,8));
638	dpid_i<=to_integer(unsigned(PE_ram_do(3 downto 0))); --le port est situé ur les 4 bits de poids faible
639	--PE_Instr_En<='0';
640	when putdata2 =>
641	-- PE_Ram_we <='1'; --écriture dans la RAM
642	-- PE_Ram_ena <='1';
643	-- PE_Ram_enb <='0';
644	srcadr0<=X"00";
645	srcadr1<=X"01";
646	destadr0<=X"00";
647	destadr1<=X"02";
648	PE_Ram_we<=sram.we;
649	PE_Ram_ena<=sram.ena;
650	PE_Ram_enb<=sram.enb;
651
652	when putcompleted =>
653	PE_Ram_we <='1';
654	PE_Ram_ena <='1';
655	-- lecture du résultat
656	PE_Ram_enb <='1';
657	--PE_Instr_En<='1';
658	when getdata =>
659	--dcount<=0;
660	PE_Ram_we<='1';
661	PE_Ram_ena<='1';
662	PE_Ram_enb<='0';
663
664	srcadr0<=X"50";
665	srcadr1<=X"01";
666	destadr0<=X"00";
667	destadr1<=X"03";
668	datalen<=std_logic_vector(to_unsigned(10,8));
669	--PE_Instr_En<='0';
670	when getdata2 =>
671	PE_Ram_we <='1'; --écriture dans la RAM
672	PE_Ram_ena <='1';
673
674	PE_Ram_enb <='0';
675	--dcount<=dcount+1;
676	if dcount=5 then
677	--PE_Instr_En<='1';
678	else
679	--PE_Instr_En<='0';
680	end if;
681	when getcompleted =>
682	PE_Ram_we <='1';
683	PE_Ram_ena <='1';
684	-- lecture du résultat
685	PE_Ram_enb <='1';
686	--PE_Instr_En<='1';
687	when terminate =>
688
689	PE_Ram_we<='0';
690	PE_Ram_ena<='0';
691	PE_Ram_enb<='0';
692	--PE_Instr_En<='0';
693
694	when st_timeout =>
695	PE_Ram_we<='0';
696	PE_Ram_ena<='0';
697	PE_Ram_enb<='0';
698	--PE_Instr_En<='0';
699
700	end case;
701
702	end process majPutGet ;
703	end Behavioral;
704

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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE_100.vhd

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