source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/ipcore_dir/coregen.cgc @ 68

Last change on this file since 68 was 15, checked in by rolagamo, 12 years ago
File size: 2.0 KB
Line 
1<?xml version="1.0" encoding="UTF-8"?>
2<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
3   <spirit:vendor>xilinx.com</spirit:vendor>
4   <spirit:library>project</spirit:library>
5   <spirit:name>coregen</spirit:name>
6   <spirit:version>1.0</spirit:version>
7   <spirit:description></spirit:description>
8   <spirit:vendorExtensions>
9      <xilinx:instanceProperties>
10       <xilinx:projectOptions>
11         <xilinx:projectName>coregen</xilinx:projectName>
12         <xilinx:outputDirectory>./</xilinx:outputDirectory>
13         <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
14         <xilinx:subWorkingDirectory>./tmp/_cg</xilinx:subWorkingDirectory>
15       </xilinx:projectOptions>
16       <xilinx:part>
17         <xilinx:device>xc5vlx50t</xilinx:device>
18         <xilinx:deviceFamily>virtex5</xilinx:deviceFamily>
19         <xilinx:package>ff1136</xilinx:package>
20         <xilinx:speedGrade>-3</xilinx:speedGrade>
21       </xilinx:part>
22       <xilinx:flowOptions>
23         <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
24         <xilinx:designEntry>VHDL</xilinx:designEntry>
25         <xilinx:asySymbol>true</xilinx:asySymbol>
26         <xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
27         <xilinx:addPads>false</xilinx:addPads>
28         <xilinx:removeRPMs>false</xilinx:removeRPMs>
29         <xilinx:createNDF>false</xilinx:createNDF>
30         <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
31         <xilinx:formalVerification>false</xilinx:formalVerification>
32       </xilinx:flowOptions>
33       <xilinx:simulationOptions>
34         <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
35         <xilinx:simulationLanguage>VHDL_and_Verilog</xilinx:simulationLanguage>
36         <xilinx:foundationSym>false</xilinx:foundationSym>
37       </xilinx:simulationOptions>
38     </xilinx:instanceProperties>
39   </spirit:vendorExtensions>
40</spirit:design>
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