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source:
PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/ipcore_dir/coregen.cgp
@
122
| Last change on this file since 122 was 74, checked in by , 11 years ago | |
|---|---|
| File size: 243 bytes | |
| Line | |
|---|---|
| 1 | SET designentry = VHDL |
| 2 | SET BusFormat = BusFormatAngleBracketNotRipped |
| 3 | SET devicefamily = spartan6 |
| 4 | SET device = xc6slx75 |
| 5 | SET package = csg484 |
| 6 | SET speedgrade = -3 |
| 7 | SET FlowVendor = Foundation_ISE |
| 8 | SET VerilogSim = True |
| 9 | SET VHDLSim = True |
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