[70] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 09:53:00 06/13/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: round_robbin_machine - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 24 | |
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| 25 | ---- Uncomment the following library declaration if instantiating |
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| 26 | ---- any Xilinx primitives in this code. |
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| 27 | --library UNISIM; |
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| 28 | --use UNISIM.VComponents.all; |
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| 29 | |
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| 30 | entity round_robbin_machine is |
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| 31 | Port ( get_request_fifo_empty : in STD_LOGIC; |
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| 32 | instruction_fifo_empty : in STD_LOGIC; |
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| 33 | priority_rotation : in STD_LOGIC; |
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| 34 | clk : in STD_LOGIC; |
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| 35 | fifo_selected : out STD_LOGIC; |
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| 36 | instruction_available : out STD_LOGIC; |
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| 37 | reset : in STD_LOGIC; |
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| 38 | mux_sel : out STD_LOGIC); |
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| 39 | end round_robbin_machine; |
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| 40 | |
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| 41 | architecture Behavioral of round_robbin_machine is |
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| 42 | signal priority : std_logic; |
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| 43 | signal fifo_selected_signal : std_logic; |
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| 44 | |
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| 45 | begin |
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| 46 | -- instruction disponible si au moins un fifo n'est pas vide |
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| 47 | instruction_available <= '1' when instruction_fifo_empty = '0' or get_request_fifo_empty = '0' else |
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| 48 | '0'; |
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| 49 | --signal indiquant a EX1_FSM le fifo selectionne |
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| 50 | fifo_selected <= fifo_selected_signal; |
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| 51 | mux_sel <= fifo_selected_signal; |
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| 52 | |
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| 53 | rr_machine_process : process(clk) |
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| 54 | begin |
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| 55 | if rising_edge(clk) then |
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| 56 | if reset = '1' then |
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| 57 | priority <= '0'; |
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| 58 | fifo_selected_signal <= '0'; |
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| 59 | elsif priority_rotation = '1' then |
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| 60 | if priority = '0' then |
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| 61 | if instruction_fifo_empty = '0' then |
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| 62 | fifo_selected_signal <= '0'; |
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| 63 | elsif get_request_fifo_empty = '0' then |
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| 64 | fifo_selected_signal <= '1'; |
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| 65 | end if; |
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| 66 | priority <= '1'; |
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| 67 | else |
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| 68 | if get_request_fifo_empty = '0' then |
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| 69 | fifo_selected_signal <= '1'; |
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| 70 | elsif instruction_fifo_empty = '0' then |
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| 71 | fifo_selected_signal <= '0'; |
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| 72 | end if; |
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| 73 | priority <= '0'; |
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| 74 | end if; |
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| 75 | end if; |
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| 76 | end if; |
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| 77 | end process; |
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| 78 | end Behavioral; |
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| 79 | |
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