source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/simulations command.tcl.txt @ 72

Last change on this file since 72 was 70, checked in by rolagamo, 11 years ago
File size: 1.2 KB
Line 
1isim condition add { /mpicoretest/uut/connect_core(1)/hardmpi/instruction_en == '1' } { stop }
2isim set radix hex
3show value Base_ad
4show value Base_adr
5 bp add dma_arbiter.vhd 209
6 bp add load_instr.vhd 254
7bp add load_instr.vhd 195
8bp add mpicoretest.vhd 291
9bp add ram_32_32.vhd 54
10bp add fifo_64_fwft.vhd 113
11isim condition add { mpicoretest/uut/\connect_core(1)\/hardmpi/MPI_CORE_EX4_FSM/port_in_wr_en } stop
12 bp add core_mpi.vhd  577
13 bp add core_mpi.vhd  445
14bp add ex4_fsm.vhd  605
15bp add ex4_fsm.vhd  555
16bp add ex4_fsm.vhd  570
17bp add ex4_fsm.vhd  549
18bp add ex4_fsm.vhd  637
19bp add ex4_fsm.vhd  1038
20 bp add "C:/Core MPI/SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" 510
21 bp add "C:/Core MPI/SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" 769
22 bp add "C:/Core MPI/SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" 750
23isim condition add { /mpicoretest/uut/socsyst/switch_gen1/switch4x4_7x7/\switch_4x4_7x7(1)\/PORTx4_INPUT_PORT_MODULE/port_granted } { stop }
24bp add pe.vhd 128
25bp add pe.vhd 330
26bp add pe.vhd 353
27bp add mpicoretest.vhd 420
28bp add ex1_fsm.vhd 111
29bp add ex1_fsm.vhd 423
30bp add fifo_64_fwft.vhd 113
31bp add ex1_fsm.vhd 160
32bp add ex1_fsm.vhd 423
33bp add core_mpi.vhd 569
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